AT25DL161-SSHN-B_技术文档

AT25DL161

16-Mbit, 1.65V Minimum SPI Serial Flash Memory

with Dual-I/O Support

DATASHEET

Features

 Single 1.65V – 1.95V supply

 Serial Peripheral Interface (SPI) compatible

 Supports SPI Modes 0 and 3

 Supports RapidS^™operation

 Supports Dual-Input Program and Dual-Output Read

 Very high operating frequencies

 100MHz for RapidS

 85MHz for SPI

 Clock-to-output time (t_V) of 5ns maximum

 Flexible, optimized erase architecture for code + data storage applications

 Uniform 4KB, 32KB, and 64KB Block Erase

 Full Chip Erase

 Individual sector protection with Global Protect/Unprotect feature

 32 sectors of 64KB each

 Hardware controlled locking of protected sectors via WP pin

 Sector Lockdown with permanent freeze option

 Make any combination of 64KB sectors permanently read-only

 128-byte, One-Time Programmable (OTP) Security Register

 64 bytes factory preprogrammed, 64 bytes user programmable

 Flexible programming

 Byte/Page Program (1 to 256 bytes)

 Fast program and erase times

 1.0ms typical Page Program (256 bytes) time

 50ms typical 4KB Block Erase time

 250ms typical 32KB Block Erase time

 550ms typical 64KB Block Erase time

 Program and Erase Suspend/Resume

 Automatic checking and reporting of erase/program failures

 Software controlled reset

 JEDEC Standard Manufacturer and Device ID Read Methodology

 Low power dissipation

 10mA Active Read current (typical at 20MHz)

 8μA Deep Power-Down current (typical)

 Endurance: 100,000 program/erase cycles

 Data retention: 20 years

 Complies with full industrial temperature range

 Industry standard green (Pb/halide-free/RoHS-compliant) package options

 8-lead SOIC (0.150" wide)

 8-pad Ultra-thin DFN (5 x 6 x 0.6mm)

 8-ball dBGA (WLCSP)

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1.

Description

The AT25DL161 is a serial interface Flash memory device designed for use in a wide variety of high-volume, consumer-

based applications in which program code is shadowed from Flash memory into embedded or external RAM for

execution. The flexible erase architecture of the AT25DL161, with its erase granularity as small as 4KB, makes it ideal for

data storage as well, eliminating the need for additional data storage EEPROM devices.

The physical sectoring and the erase block sizes of the AT25DL161 have been optimized to meet the needs of today's

code and data storage applications. By optimizing the size of the physical sectors and erase blocks, the memory space

can be used much more efficiently. Because certain code modules and data storage segments must reside by

themselves in their own protected sectors, the wasted and unused memory space that occurs with large sectored and

large Block Erase Flash memory devices can be greatly reduced. This increased memory space efficiency allows

additional code routines and data storage segments to be added, while still maintaining the same overall device density.

The AT25DL161 also offers a sophisticated method for protecting individual sectors against erroneous or malicious

program and erase operations. By providing the ability to individually protect and unprotect sectors, a system can

unprotect a specific sector to modify its contents while keeping the remaining sectors of the memory array securely

protected. This is useful in applications where program code is patched, updated on a subroutine or module basis, or in

applications where data storage segments need to be modified without running the risk of errant modifications to the

program code segments. In addition to individual sector protection capabilities, the AT25DL161 incorporates Global

Protect and Global Unprotect features that allow the entire memory array to be either protected or unprotected all at

once. This reduces overhead during the manufacturing process because sectors do not have to be unprotected one by

one prior to initial programming.

To take code and data protection to the next level, the AT25DL161 incorporates a sector lockdown mechanism that

allows any combination of individual 64KB sectors to be locked down and become permanently read-only. This

addresses the need of certain secure applications that require portions of the Flash memory array to be permanently

protected against malicious attempts at altering program code, data modules, security information or

encryption/decryption algorithms, keys, and routines. The device also contains a specialized, OTP (One-Time

Programmable) security register, which can be used for unique device serialization, system-level Electronic Serial

Number (ESN) storage, locked key storage, or other purposes.

Specifically designed for use in 1.8V systems, the AT25DL161 supports read, program, and erase operations with a

supply voltage range of 1.65V to 1.95V. No separate voltage is required for programming and erasing.

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2.

Pin Descriptions and Pinouts

Table 2-1. Pin Descriptions

Asserted

State

Symbol

Name and Function

Type

Chip Select: Asserting the CS pin selects the device. When the CS pin is

deasserted, the device will be deselected and normally be placed in standby

mode (not deep Power-Down mode) and the SO pin will be in a high-impedance

state. When the device is deselected, data will not be accepted on the SI pin.

CS

Low

Input

A high-to-low transition on the CS pin is required to start an operation and a

low-to-high transition is required to end an operation. When ending an internally

self-timed operation, such as a program or erase cycle, the device will not enter

the standby mode until the completion of the operation.

Serial Clock: This pin is used to provide a clock to the device and is used to

control the flow of data to and from the device. Command, address, and input

data present on the SI pin is always latched in on the rising edge of SCK, while

output data on the SO pin is always clocked out on the falling edge of SCK.

SCK

—

Input

Serial Input (Serial Input/Output): The SI pin is used to shift data into the

device. The SI pin is used for all data input including command and address

sequences. Data on the SI pin is always latched in on the rising edge of SCK.

With the Dual-Output Read Array command, the SI pin becomes an output pin

(SIO) to allow two bits (on the SO and SIO pins) of data to be clocked out on

every falling edge of SCK. To maintain consistency with SPI nomenclature, the

SIO pin will be referenced as SI throughout this document except for those

sections dealing with the Dual-Output Read Array command, in which it will be

referenced as SIO.

SI (SIO)

—

Input/Output

Data present on the SI pin will be ignored whenever the device is deselected

(CS is deasserted).

Serial Output (Serial Output/Input): The SO pin is used to shift data out from

the device. Data on the SO pin is always clocked out on the falling edge of

SCK.

With the Dual-Input Byte/Page Program command, the SO pin becomes an

input pin (SOI) to allow two bits (on the SOI and SI pins) of data to be clocked in

on every rising edge of SCK. To maintain consistency with nomenclature, the

SOI pin will be referenced as SO throughout this document except for those

sections dealing with the Dual-Input Byte/Page Program command in which it

will be referenced as SOI.

SO (SOI)

—

Input/Output

The SO pin will be in a high-impedance state whenever the device is deselected

(CS is deasserted).

Write Protect: The WP pin controls the hardware locking feature of the device.

See “Protection Commands and Features” on page 21 for more details on

protection features and the WP pin.

WP

Low

Input

The WP pin is internally pulled-high and may be left floating if hardware

controlled protection will not be used. However, it is recommended that the WP

pin also be externally connected to V_CCwhenever possible.

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Table 2-1. Pin Descriptions (Continued)

Asserted

State

Symbol

Name and Function

Type

Hold: The HOLD pin is used to temporarily pause serial communication without

deselecting or resetting the device. While the HOLD pin is asserted, transitions

on the SCK pin and data on the SI pin will be ignored and the SO pin will be in a

high-impedance state.

The CS pin must be asserted and the SCK pin must be in the low state in order

for a Hold condition to start. A Hold condition pauses serial communication only

and does not have an affect on internally self-timed operations, such as a

program or erase cycle. See “Hold” on page 46 for additional details on the Hold

operation.

HOLD

Low

Input

The HOLD pin is internally pulled-high and may be left floating if the Hold

function will not be used. However, it is recommended that the HOLD pin also

be externally connected to the V_CCwhenever possible.

Device Power Supply: The V_CCpin is used to supply the source voltage to the

device.

V_CC

—

Power

Operations at invalid V_CCvoltages may produce spurious results and should not

be attempted.

Ground: The ground reference for the power supply. GND should be

connected to the system ground.

GND

Figure 2-1. 8-lead SOIC

Figure 2-2. 8-pad UDFN

Figure 2-3. 8-ball dBGA (WLSCP)

1

2

1

2

3

4

8

7

6

5

CS

SO (SOI)

WP

V

CC

A

B

C

D

E

F

CS

SO (SOI)

WP

1

2

3

4

8

7

6

5

V

CC

HOLD

SCK

HOLD

SCK

VCC CS

HOLD SO (SOI)

SCK WP

GND

SI (SIO)

GND

SI (SIO)

SI (SIO) GND

Top View

through back of Die

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3.

Block Diagram

Figure 3-1. Block Diagram

Control and

Protection Logic

I/O Buffers

and Latches

CS

SRAM

Data Buffer

SCK

Interface

Control

and

SI (SIO)

Y-Decoder

Y-Gating

Logic

SO (SOI)

Flash

Memory

Array

WP

X-Decoder

HOLD

Note: SIO and SOI pin naming convention is used for Dual-I/O commands.

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4.

Memory Array

To provide the greatest flexibility, the AT25DL161 memory array can be erased in four levels of granularity, including a

full Chip Erase. In addition, the array has been divided into physical sectors of uniform size, which can be individually

protected from program and erase operations. The size of the physical sectors is optimized for both code and data

storage applications, allowing both code and data segments to reside in their own isolated regions. The memory

architecture diagram illustrates the breakdown of each erase level, as well as the breakdown of each physical sector.

Figure 4-1. Memory Architecture Diagram

1-256 byte

Page Program

(02h Command)

256 bytes

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5.

Device Operation

The AT25DL161 is controlled by a set of instructions that are sent from a host controller, commonly referred to as the SPI

master. The SPI master communicates with the AT25DL161 via the SPI bus, which is comprised of four signal lines:

Chip Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO).

The SPI protocol defines a total of four modes of operation (Mode 0, 1, 2, or 3), with each mode differing in respect to the

SCK polarity and phase and how the polarity and phase control the flow of data on the SPI bus. The AT25DL161

supports the two most common modes, SPI Modes 0 and 3. The only difference between SPI Modes 0 and 3 is the

polarity of the SCK signal when in the inactive state (when the SPI master is in standby mode and not transferring any

data). With SPI Modes 0 and 3, data is always latched in on the rising edge of SCK and always output on the falling edge

of SCK.

Figure 5-1. SPI Mode 0 and 3

CS

SCK

MSB

LSB

SI

MSB

LSB

SO

5.1

Dual-I/O Operation

The AT25DL161 features a Dual-Input Program mode and a Dual-Output Read mode that allow two bits of data to be

clocked into or out of the device every clock cycle to improve throughput. To accomplish this, both the SI and SO pins

are utilized as inputs/outputs for the transfer of data bytes. With the Dual-Input Byte/page Program command, the SO

pin becomes an input along with the SI pin. Alternatively, with the Dual-Output Read Array command, the SI pin

becomes an output along with the SO pin. For both Dual-I/O commands, the SO pin will be referred to as the

SOI (Serial Output/Input) pin and the SI pin will be referred to as the SIO (Serial Input/Output) pin.

6.

Commands and Addressing

A valid instruction or operation must always be started by first asserting the CS pin. After the CS pin has been asserted,

the host controller must then clock out a valid 8-bit opcode on the SPI bus. Following the opcode, instruction-dependent

information, such as address and data bytes, would then be clocked out by the host controller. All opcode, address, and

data bytes are transferred with the Most-Significant Bit (MSB) first. An operation is ended by deasserting the CS pin.

Opcodes not supported by the AT25DL161 will be ignored by the device and no operation will be started. The device will

continue to ignore any data presented on the SI pin until the start of the next operation (CS pin being deasserted and

then reasserted). In addition, if the CS pin is deasserted before complete opcode and address information is sent to the

device, then no operation will be performed, and the device will simply return to the idle state and wait for the next

operation.

Addressing of the device requires a total of three bytes of information to be sent, representing address bits A23-A0.

Since the upper address limit of the AT25DL161 memory array is 1FFFFFh, address bits A23-A21 are always ignored by

the device.

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Table 6-1. Command Listing

Clock

Frequency

Address

Bytes

Dummy

Bytes

Data

Bytes

Command

Read Commands

1Bh

0Bh

03h

3Bh

0001 1011

0000 1011

0000 0011

0011 1011

Up to 100MHz

Up to 85MHz

Up to 40MHz

Up to 66MHz

3

2

1

0

1

1+

Read Array

Dual-Output Read Array

Program and Erase Commands

Block Erase (4KB)

20h

52h

D8h

60h

C7h

02h

A2h

B0h

D0h

0010 0000

0101 0010

1101 1000

0110 0000

1100 0111

0000 0010

1010 0010

1011 0000

1101 0000

Up to 100MHz

3

0

3

0

Block Erase (32KB)

Block Erase (64KB)

0

Chip Erase

0

Byte/Page Program (1 to 256 bytes)

Dual-Input Byte/Page Program (1 to 256 bytes)

Program/Erase Suspend

Program/Erase Resume

Protection Commands

Write Enable

1+

0

06h

04h

36h

39h

0000 0110

0000 0100

0011 0110

0011 1001

Up to 100MHz

0

3

0

Write Disable

Protect Sector

Unprotect Sector

Global Protect/Unprotect

Read Sector Protection Registers

Security Commands

Use Write Status Register Byte 1 Command

3Ch

0011 1100

Up to 100MHz

3

0

1+

Sector Lockdown

33h

34h

35h

9Bh

77h

0011 0011

0011 0100

0011 0101

1001 1011

0111 0111

Up to 100MHz

3

0

2

1

Freeze Sector Lockdown State

Read Sector Lockdown Registers

Program OTP Security Register

Read OTP Security Register

Status Register Commands

Read Status Register

1

1+

05h

01h

31h

0000 0101

0000 0001

0011 0001

Up to 100MHz

0

1+

1

Write Status Register Byte 1

Write Status Register Byte 2

Miscellaneous Commands

Reset

1

F0h

9Fh

B9h

ABh

1111 0000

1001 1111

1011 1001

1010 1011

Up to 100MHz

Up to 85MHz

Up to 100MHz

0

1

1 to 5

0

Read Manufacturer and Device ID

Deep Power-Down

Resume from Deep Power-Down

0

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7.

Read Commands

7.1

Read Array

The Read Array command can be used to sequentially read a continuous stream of data from the device by simply

providing the clock signal once the initial starting address has been specified. The device incorporates an internal

address counter that automatically increments on every clock cycle.

Three opcodes (1Bh, 0Bh, and 03h) can be used for the Read Array command. The use of each opcode depends on the

maximum clock frequency that will be used to read data from the device. The 0Bh opcode can be used at any clock

frequency up to the maximum specified by f_CLK, and the 03h opcode can be used for lower frequency read operations, up

to the maximum specified by f_RDLF. The 1Bh opcode allows the highest read performance possible and can be used at

any clock frequency up to the maximum specified by f_MAX; however, use of the 1Bh opcode at clock frequencies above

f_CLKshould be reserved for systems employing the RapidS protocol.

To perform the Read Array operation, the CS pin must first be asserted and then the appropriate opcode (1Bh, 0Bh, or

03h) must be clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in

to specify the location of the first byte to read within the memory array. Following the three address bytes, additional

dummy bytes may need to be clocked into the device, depending on which opcode is used for the Read Array operation.

If the 1Bh opcode is used, then two dummy bytes must be clocked into the device after the three address bytes. If the

0Bh opcode is used, then a single dummy byte must be clocked in after the address bytes.

After the three address bytes (and any dummy bytes) have been clocked in, additional clock cycles will result in data

being output on the SO pin. The data is always output with the MSB of a byte first. When the last byte (1FFFFFh) of the

memory array has been read, the device will continue reading from the beginning of the array (000000h). No delays will

be incurred when wrapping around from the end of the array to the beginning of the array.

Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS pin can

be deasserted at any time and does not require that a full byte of data be read.

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Figure 7-1. Read Array – 1Bh Opcode

CS

0

1

2

3

4

5

6

7

8

9

10 11 12

29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

SCK

SI

Opcode

Address Bits A23-A0

Don't Care

0

MSB

0

1

0

1

A

MSB

A

X

MSB

X

MSB

X

Data Byte 1

High-impedance

D

MSB

D

MSB

D

SO

Figure 7-2. Read Array – 0Bh Opcode

CS

0

1

2

3

4

5

6

7

8

9

10 11 12

29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

SCK

SI

Opcode

Address Bits A23-A0

Don't Care

0

MSB

0

1

0

1

A

MSB

A

X

MSB

X

Data Byte 1

High-impedance

D

MSB

D

MSB

D

SO

Figure 7-3. Read Array – 03h Opcode

CS

0

1

2

3

4

5

6

7

8

9

10 11 12

29 30 31 32 33 34 35 36 37 38 39 40

SCK

SI

Opcode

Address Bits A23-A0

0

MSB

0

1

A

MSB

A

Data Byte 1

High-impedance

D

MSB

D

MSB

D

SO

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7.2

Dual-Output Read Array

The Dual-Output Read Array command is similar to the standard Read Array command and can be used to sequentially

read a continuous stream of data from the device by simply providing the clock signal once the initial starting address has

been specified. Unlike the standard Read Array command, however, the Dual-Output Read Array command allows two

bits of data to be clocked out of the device on every clock cycle, rather than just one.

The Dual-Output Read Array command can be used at any clock frequency, up to the maximum specified by f_RDDO. To

perform the Dual-Output Read Array operation, the CS pin must first be asserted and then the opcode 3Bh must be

clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the

location of the first byte to read within the memory array. Following the three address bytes, a single dummy byte must

also be clocked into the device.

After the three address bytes and the dummy byte have been clocked in, additional clock cycles will result in data being

output on both the SO and SIO pins. The data is always output with the MSB of a byte first and the MSB is always output

on the SO pin. During the first clock cycle, bit 7 of the first data byte is output on the SO pin, while bit 6 of the same data

byte is output on the SIO pin. During the next clock cycle, bits 5 and 4 of the first data byte are output on the SO and SIO

pins, respectively. The sequence continues with each byte of data being output after every four clock cycles. When the

last byte (1FFFFFh) of the memory array has been read, the device will continue reading from the beginning of the array

(000000h). No delays will be incurred when wrapping around from the end of the array to the beginning of the array.

Deasserting the CS pin will terminate the read operation and put the SO and SIO pins into a high-impedance state. The

CS pin can be deasserted at any time and does not require that a full byte of data be read.

Figure 7-4. Dual-Output Read Array

CS

0

1

2

3

4

5

6

7

8

9

10 11 12

29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

SCK

SI (SIO)

SO (SOI)

Output

Opcode

Address Bits A23-A0

Don't Care

Data Byte 1

Data Byte 2

D

0

MSB

0

1

0

1

A

MSB

A

X

MSB

X

6

4

2

0

1

6

4

2

0

1

6

7

4

5

High-impedance

D

7

5

3

7

5

3

MSB

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8.

Program and Erase Commands

8.1

Byte/Page Program

The Byte/Page program command allows anywhere from a single byte of data to 256 bytes of data to be programmed

into previously erased memory locations. An erased memory location is one that has all eight bits set to the Logical 1

state (a byte value of FFh). Before a byte/page program command can be started, the Write Enable command must have

been previously issued to the device (see “Write Enable” on page 21) to set the Write Enable Latch (WEL) bit of the

Status Register to a Logical 1 state.

To perform a Byte/Page Program command, a 02h opcode must be clocked into the device followed by the three address

bytes denoting the first location of the memory array to begin programming at. After the address bytes have been clocked

in, data can then be clocked into the device and be stored in an internal buffer.

If the starting memory address denoted by A23-A0 does not fall on an even 256-byte page boundary (A7-A0 are not

all 0), then special circumstances regarding which memory locations are to be programmed will apply. In this situation,

any data that are sent to the device that go beyond the end of the page will wrap around to the beginning of the same

page. In addition, if more than 256 bytes of data are sent to the device, then only the last 256 bytes sent will be latched

into the internal buffer.

Example: If the starting address denoted by A23-A0 is 0000FEh and three bytes of data are sent to the device, then

the first two bytes of data will be programmed at addresses 0000FEh and 0000FFh, while the last byte of

data will be programmed at address 000000h. The remaining bytes in the page (addresses 000001h

through 0000FDh) will not be programmed and will remain in the erased state (FFh).

When the CS pin is deasserted, the device will program the data stored in the internal buffer into the appropriate memory

array locations based on the starting address specified by A23-A0 and the number of data bytes sent to the device. If

fewer than 256 bytes of data are sent to the device, then the remaining bytes within the page will not be programmed and

will remain in the erased state (FFh). The programming of the data bytes is internally self-timed and should take place in

a time of t_PPor t_BPif only programming a single byte.

The three address bytes and at least one complete byte of data must be clocked into the device before the CS pin is

deasserted, and the CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device

will abort the operation and no data will be programmed into the memory array. In addition, if the address specified by

A23-A0 points to a memory location within a sector that is in the protected state (see “Protect Sector” on page 23) or

locked down (see “Sector Lockdown” on page 29), then the Byte/Page Program command will not be executed and the

device will return to the idle state once the CS pin has been deasserted. The WEL bit in the Status Register will be reset

back to the Logical 0 state if the program cycle aborts due to an incomplete address being sent, an incomplete byte of

data being sent, the CS pin being deasserted on uneven byte boundaries, or because the memory location to be

programmed is protected or locked down.

While the device is programming, the Status Register can be read and will indicate that the device is busy. For faster

throughput, it is recommended that the Status Register be polled rather than waiting the t_BPor t_PPtime to determine if the

data bytes have finished programming. At some point before the program cycle completes, the WEL bit in the Status

Register will be reset back to the Logical 0 state.

The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program

properly. If a programming error arises, it will be indicated by the EPE bit in the Status Register.

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Figure 8-1. Byte Program

CS

0

1

2

3

4

5

6

7

8

9

10 11 12

29 30 31 32 33 34 35 36 37 38 39

SCK

SI

Opcode

Address Bits A23-A0

Data In

0

MSB

0

1

0

A

MSB

A

D

MSB

D

High-impedance

SO

Figure 8-2. Page Program

CS

0

1

2

3

4

5

6

7

8

9

29 30 31 32 33 34 35 36 37 38 39

SCK

SI

Opcode

Address Bits A23-A0

Data In Byte 1

Data In Byte n

0

MSB

0

1

0

A

D

MSB

D

MSB

D

MSB

High-impedance

SO

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8.2

Dual-Input Byte/Page Program

The Dual-Input Byte/Page Program command is similar to the standard Byte/Page Program command and can be used

to program anywhere from a single byte of data up to 256 bytes of data into previously erased memory locations. Unlike

the standard byte/page program command, however, the Dual-Input Byte/Page Program command allows two bits of

data to be clocked into the device on every clock cycle rather than just one.

Before the Dual-Input Byte/Page Program command can be started, the Write Enable command must have been

previously issued to the device (see “Write Enable” on page 21) to set the Write Enable Latch (WEL) bit of the Status

Register to a Logical 1 state. To perform a Dual-Input Byte/Page Program command, an A2h opcode must be clocked

into the device followed by the three address bytes denoting the first location of the memory array to begin programming

at. After the address bytes have been clocked in, data can then be clocked into the device two bits at a time on both the

SOI and SI pins.

The data is always input with the MSB of a byte first, and the MSB is always input on the SOI pin. During the first clock

cycle, bit 7 of the first data byte is input on the SOI pin while bit 6 of the same data byte is input on the SI pin. During the

next clock cycle, bits 5 and 4 of the first data byte are input on the SOI and SI pins, respectively. The sequence continues

with each byte of data being input after every four clock cycles. Like the standard Byte/Page Program command, all data

clocked into the device are stored in an internal buffer.

If the starting memory address denoted by A23-A0 does not fall on an even 256-byte page boundary (A7-A0 are

not all 0), then special circumstances regarding which memory locations are to be programmed will apply. In this

situation, any data that are sent to the device that go beyond the end of the page will wrap around to the beginning of the

same page. In addition, if more than 256 bytes of data are sent to the device, then only the last 256 bytes sent will be

latched into the internal buffer.