AW24MUFL-H2_技术文档

2.4GHz DSSS Micro Radio Module with Integrated Antenna

AW24MxxL

Data Sheet

1

Features

3

Applications

The AW24MxxL is a 2.4ꢀGHz Direct Sequence Spread Spectrum

(DSSS) complete radio module which includes the Cypress radio

integrated circuit CyFi™ CYRF7936, integrated Antenna, and all

external components

PC Human Interface Devices (HID)

Wireless Keyboards and Mice

VOIP and Wireless Headsets

Wireless Gamepads

Remote Control

Operates in the unlicensed worldwide Industrial, Scientific and

Medical (ISM) band (2.400 GHz–2.483 GHz)

White Goods (Smart Appliances)

Window unit air conditioners

Kitchen compactors

Dishwashers

21mA operating current (Transmit @ –5 dBm)

Transmit power up to +4 dBm

Receive sensitivity up to –97 dBm

Sleep Current <1 µA

Operating range of up to 20m indoor or 40m LOS.

DSSS data rates up to 250 kbps, GFSK data rate of 1 Mbps

Washers

Dryers

Consumer

Auto Transaction Sequencer (ATS) ꢀ no micro controller

intervention

Sports and Leisure Equipment

Remote Controls

Framing, Length, CRC16, and Auto ACK

Fast Startup and Fast Channel Changes

Separate 16ꢀbyte Transmit and Receive FIFOs

AutoRate™ ꢀ dynamic data rate reception

Receive Signal Strength Indication (RSSI)

4ꢀMHz SPI microcontroller interface

No proprietary software required

Audio Subwoofer

Presenter Tools

Locator Alarms

Toys

Building/Home Automation

Automatic Meter Readers (AMR)

OnꢀSite Paging Systems

Garage door opener

Alarm and Security

Serial Peripheral Interface (SPI) control while in sleep mode

Vertical or horizontal mounting

Operating voltage from 2.4 to 3.6 volts

Operating temperature from ꢀ20°C to 70°C

Size: 16 mm x 13.5 mm (~0.6” x 0.5”)

Weight: 2 grams

Lighting Control

Climate Control

Fan Control

Industrial Control

FCC Modular Approval Grant to meet FCC Part 15, EN 300 328ꢀ

1, EN 301 489ꢀ1, EN 301 489ꢀ7 and Industry Canada RSSꢀ210

standards In Progress.

An FCC Module Approval (MA) Grant provides customers

significant cost savings, by allowing customers to adopt the

AW24MXXL FCC ID into their own products

Active RFID and asset tracking systems

Inventory Management

Pointꢀofꢀsale systems

Factory Automation

Data Acquisition

Transportation

2

Functional Description

Remote Keyless Entry with acknowledgement (RKE)

Airline Baggage Tracking

Diagnostics

The Artaflex AW24MXXL Wireless Radio Module offers a

complete radio module solution for integration into existing or

new 2.4ꢀGHz products.

The AW24MXXL is tested for functional operation and is

FCC/ETSI (EU)/Industry Canada certified. The module is

supplied with integrated or external antenna options.

The AW24MxxL is available in a small PCB design and can be

mounted horizontally or vertically to the device PCB via a 12ꢀ

pin header. The pinꢀout of the header is shown in the

Connector Footprint section.

Artaflex Inc.

215 Konrad Crescent

Markham, Ontario, Canada

DSꢀ102ꢀ0006ꢀR1.5

Revised 04 Jan 2013

L3R8T9

Page 1 of 13

http://www.artaflexmodules.com

905ꢀ479ꢀ0148

2.4GHz DSSS SPI Radio with Integrated Antenna

AW24MxxL

Data Sheet

*Figure 1 – Module Schematic (Header version)

*Figure 2– Module Schematic (SMT Version)

Artaflex Inc.

DSꢀ102ꢀ0006ꢀR1.5

215 Konrad Crescent

Markham, Ontario, Canada

L3R8T9

Revised 04 Jan 2013

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905ꢀ479ꢀ0148

2.4GHz DSSS SPI Radio with Integrated Antenna

AW24MxxL

Data Sheet

3.1

Reference Documentation

For information on technical details of the Cypress Semiconductor, CYRF7936 CyFi^TM, 2.4ꢀGHz DSSS Radio system on chip such

as register settings, timing, application interfaces, and clocking, refer to the device data sheet CYFI7936 available on the Cypress

Web Site at:ꢀ

The following is the link , known at the time of publication that accompany this data sheet:

http://download.cypress.com.edgesuite.net/design_resources/datasheets/contents/cyrf7936_8.pdf?key=1229340511568

www.cypress.com

•

Artaflex Inc.

DSꢀ102ꢀ0006ꢀR1.5

Revised 04 Jan 2013

215 Konrad Crescent

Markham, Ontario, Canada

L3R8T9

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905ꢀ479ꢀ0148

2.4GHz DSSS SPI Radio with Integrated Antenna

AW24MxxL

Data Sheet

4

Functional Overview

The AW24MXXL Module provides a complete SPI to RF antenna wireless MODEM. The module is designed to implement wireless

device links operating in the worldwide 2.4ꢀGHz ISM frequency band. It is intended for systems compliant with worldꢀwide

regulations covered by Europe ETSI EN 301 489ꢀ1, ETSI EN 301 489ꢀ7, & ETSI EN 300 328ꢀ1, USA FCC Part 15 and Industry

Canada RSSꢀ210 standards.

The module contains a 2.4ꢀGHz 1ꢀMbps GFSK radio transceiver, packet data buffering, packet framer, DSSS baseband controller,

Received Signal Strength Indication (RSSI), and SPI interface for data transfer and device configuration.

The radio supports 80 discrete 1ꢀMHz channels (regulations may limit the use of some of these channels in certain jurisdictions). In

DSSS modes the baseband performs DSSS spreading/deꢀspreading, while in GFSK Mode (1 Mb/s ꢀ GFSK) the baseband

performs Start of Frame (SOF), End of Frame (EOF) detection and CRC16 generation and checking. The baseband may also be

configured to automatically transmit Acknowledge (ACK) handshake packets whenever a valid packet is received.

When in receive mode, with packet framing enabled, the device is always ready to receive data transmitted at any of the supported

bit rates, except SDR, enabling the implementation of mixedꢀrate systems in which different devices use different data rates. This

also enables the implementation of dynamic data rate systems, which use high data rates at shorter distances and/or in a lowꢀ

moderate interference environment, and change to lower data rates at longer distances and/or in high interference environments.

4.1

Link Layer Modes

The AW24MXXL module supports the following data packet framing features:

SOP – Packets begin with a 2ꢀsymbol Start of Packet (SOP) marker. This is required in GFSK and 8DR modes, but is optional in

DDR mode and is not supported in SDR mode; if framing is disabled then an SOP event is inferred whenever two successive

correlations are detected. The SOP_CODE_ADR code used for the SOP is different from that used for the “body” of the packet and

if desired may be a different length. SOP must be configured to be the same length on both sides of the link.

EOP – There are two options for detecting the end of a packet. If SOP is enabled, then a packet length field may be enabled.

GFSK and 8DR must enable the length field. This is the first 8ꢀbits after the SOP symbol, and is transmitted at the payload data

rate. If the length field is enabled, an End of Packet (EOP) condition is inferred after reception of the number of bytes defined in the

length field, plus two bytes for the CRC16 (if enabled—see below). The alternative to using the length field is to infer an EOP

condition from a configurable number of successive nonꢀcorrelations; this option is not available in GFSK mode and is only

recommended to enable when using SDR mode.

CRC16 – The device may be configured to append a 16ꢀbit CRC16 to each packet. The CRC16 uses the USB CRC polynomial

with the added programmability of the seed. If enabled, the receiver will verify the calculated CRC16 for the payload data against

the received value in the CRC16 field. The starting value for the CRC16 calculation is configurable, and the CRC16 transmitted

may be calculated using either the loaded seed value or a zero seed; the received data CRC16 will be checked against both the

configured and zero CRC16 seeds.

CRC16 detects the following errors:

Any one bit in error

Any two bits in error (no matter how far apart, which column, and so on)

Any odd number of bits in error (no matter where they are)

An error burst as wide as the checksum itself

4.2

Packet Buffers

All data transmission and reception utilizes the 16ꢀbyte packet buffers—one for transmission and one for reception.

The transmit buffer allows a complete packet of up to 16ꢀbytes of payload data to be loaded in one burst SPI transaction, and then

transmitted with no further micro controller intervention. Similarly, the receive buffer allows an entire packet of payload data up to

16 bytes to be received with no firmware intervention required until packet reception is complete.

The AW24MXXL module supports packet length of up to 40 bytes; interrupts are provided to allow a micro controller to use the

transmit and receive buffers as FIFOs. When transmitting a packet longer than 16 bytes, the micro controller can load 16ꢀbytes

initially, and add further bytes to the transmit buffer as transmission of data creates space in the buffer. Similarly, when receiving

packets longer than 16 bytes, the micro controller must fetch received data from the FIFO periodically during packet reception to

prevent it from overflowing.

Artaflex Inc.

DSꢀ102ꢀ0006ꢀR1.5

Revised 04 Jan 2013

215 Konrad Crescent

Markham, Ontario, Canada

L3R8T9

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905ꢀ479ꢀ0148

2.4GHz DSSS SPI Radio with Integrated Antenna

AW24MxxL

Data Sheet

4.3

AutoTransaction Sequencer (ATS)

The AW24MXXL module provides automated support for transmission and reception of acknowledged data packets.

When transmitting a data packet, the device automatically starts the crystal and synthesizer, enters transmit mode, transmits the

packet in the transmit buffer, and then automatically switches to receive mode and waits for a handshake packet and then

automatically reverts to sleep mode or idle mode when either an ACK packet is received, or a timeout period expires.

Similarly, when receiving in transaction mode, the device waits in receive mode for a valid packet to be received, and then

automatically transitions to transmit mode, transmits an ACK packet, and then switches back to receive mode to await the next

packet. The contents of the packet buffers are not affected by the transmission or reception of ACK packets.

In each case, the entire packet transaction takes place without any need for micro controller firmware action; to transmit data the

micro controller simply needs to load the data packet to be transmitted, set the length, and set the TX GO bit. Similarly, when

receiving packets in transaction mode, firmware simply needs to retrieve the fully received packet in response to an interrupt

request indicating reception of a packet.

4.4

Data Rates

By combining the DATA_CODE_ADR code lengths and data transmission modes described above, the AW24MXXL supports the

following modes and data rates.

Table 1 - Data Rates

RF Transmission Mode

GFSK

Raw Data Rate kbps

1,000.00

250.00

125.00

62.50

32ꢀChip 8DR

64ꢀchip 8DR^[2]

32ꢀchip DDR^[3]

64ꢀchip DDR^[3]

64ꢀchip SDR^[2,3]

31.25

15.63

5

SPI Communication

The AW24MXXL has an SPI interface supporting communications between an application MCU and one or more slave

devices (including the AW24MXXL). The SPI interface supports singleꢀbyte and multiꢀbyte serial transfers using either 4ꢀpin

or 3ꢀpin interfacing. The SPI communications interface consists of Slave Select (

Slave In (MOSI), Master InꢀSlave Out (MISO), or Serial Data (SDAT).

₎, Serial Clock (SCK), and Master Outꢀ

The SPI communications is as follows:

ꢀ

Command Direction (bit 7) = “1” enables SPI write transaction. A “0” enables SPI read transactions.

Command Increment (bit 6) = “1” enables SPI auto address increment. When set, the address field automatically

increments at the end of each data byte in a burst access, otherwise the same address is accessed.

ꢀ

Six bits of address.

Eight bits of data.

The device receives SCK from an application MCU on the SCK pin. Data from the application MCU is shifted in on the MOSI

pin. Data to the application MCU is shifted out on the MISO pin. The activeꢀlow Slave Select (

initiate an SPI transfer.

) pin must be asserted to

The application MCU can initiate SPI data transfers via a multi byte transaction. The first byte is the Command/Address byte,

and the following bytes are the data bytes as shown in Figure 2 through Figure 5.

Artaflex Inc.

DSꢀ102ꢀ0006ꢀR1.5

Revised 04 Jan 2013

215 Konrad Crescent

Markham, Ontario, Canada

L3R8T9

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2.4GHz DSSS SPI Radio with Integrated Antenna

AW24MxxL

Data Sheet

The SPI communications interface has a burst mechanism, where the first byte can be followed by as many data bytes as

desired. A burst transaction is terminated by deasserting the slave select ( = 1).

The SPI communications interface single read and burst read sequences are shown in Figure 3 and Figure 4, respectively.

The SPI communications interface single write and burst write sequences are shown in Figure 5 and Figure 6, respectively.

This interface may optionally be operated in a 3ꢀpin mode with the MISO and MOSI functions combined in a single

bidirectional data pin (SDAT). When using 3ꢀpin mode, user firmware should ensure that the MOSI pin on the MCU is in a

high impedance state except when MOSI is actively transmitting data.

The device registers may be written to or read from 1 byte at a time, or several sequential register locations may be

written/read in a single SPI transaction using incrementing burst mode. In addition to single byte configuration registers, the

device includes register files; register files are FIFOs written to and read from using nonꢀincrementing burst SPI transactions.

The IRQ pin function may optionally be multiplexed onto the MOSI pin; when this option is enabled the IRQ function is not

available while the

AW24MXXL is in a high impedance state whenever the

pin is low. When using this configuration, user firmware should ensure that the MOSI pin on the

pin is high.

The SPI interface is not dependent on the internal 12ꢀMHz clock, and registers may therefore be read from or written to while

the device is in sleep mode, and the 12ꢀMHz oscillator disabled.

Figure 2 – SPI Transaction Format

Figure 3 - SPI Single Read Sequence

Figure 4 - SPI Incrementing Burst Read

Sequence

Artaflex Inc.

DSꢀ102ꢀ0006ꢀR1.5

Revised 04 Jan 2013

215 Konrad Crescent

Markham, Ontario, Canada

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2.4GHz DSSS SPI Radio with Integrated Antenna

AW24MxxL

Data Sheet

Figure 5 - SPI Single Write Sequence

Figure 6 - SPI Incrementing Burst Write Sequence

6

Power Management

The operating voltage of the module is 2.4V to 3.6V DC, which is applied to the V_ccpin 2 of the connector. The device can be

shutdown to a fully static sleep mode by writing to the FRC END = 1 and END STATE = 000 bits in the XACT_CFG_ADR

register over the SPI interface. The module will enter sleep mode within 35ꢀꢁs after the last SCK positive edge at the end of

this SPI transaction. Alternatively, the module may be configured to automatically enter sleep mode after completing packet

transmission or reception. When in sleep mode, the onꢀchip oscillator is stopped, but the SPI interface remains functional.

The module will wake from sleep mode automatically when the module is commanded to enter transmit or receive mode.

When resuming from sleep mode, there is a short delay while the oscillator restarts. The module may be configured to assert

the IRQ pin when the oscillator has stabilized.

7

Low NoiseAmplifier (LNA) and Received Signal Strength Indication (RSSI)

The gain of the receiver may be controlled directly by clearing the AGC EN bit and writing to the Low Noise Amplifier (LNA) bit of

the RX_CFG_ADR register. When the LNA bit is cleared, the receiver gain is reduced by approximately 20 dB, allowing accurate

reception of very strong received signals (for example when operating a receiver very close to the transmitter). Approximately 30

dB of receiver attenuation can be added by setting the Attenuation (ATT) bit; this allows data reception to be limited to devices at

very short ranges. Disabling AGC and enabling LNA is recommended unless receiving from a device using external PA.

When the module is in receive mode the RSSI_ADR register returns the relative signal strength of the onꢀchannel signal power.

When receiving, the module will automatically measure and store the relative strength of the signal being received as a 5ꢀ bit value.

An RSSI reading is taken automatically when the SOP is detected. In addition, a new RSSI reading is taken every time the

previous reading is read from the RSSI_ADR register, allowing the background RF energy level on any given channel to be easily

measured when RSSI is read when no signal is being received. A new reading can occur as fast as once every 12 ꢁs.

Artaflex Inc.

DSꢀ102ꢀ0006ꢀR1.5

Revised 04 Jan 2013

215 Konrad Crescent

Markham, Ontario, Canada

L3R8T9

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2.4GHz DSSS SPI Radio with Integrated Antenna

AW24MxxL

Data Sheet

8

Absolute Maximum Ratings

9

Operating Conditions

Storage Temperature ............................................................ –65°C to +150°C

Ambient Temperature with Power Applied............................. –55°C to +125°C

Supply Voltage on any power supply pin relative to............ V_SS–0.3V to +3.9V

DC Voltage to Logic Inputs^[3]............................................... –0.3V to V_IO+0.3V

DC Voltage applied to Outputs in HighꢀZ State.................... –0.3V to V_IO+0.3V

Static Discharge Voltage (Digital)^[4]...................................................... >2000V

Static Discharge Voltage (RF)^[4]............................................................. 1100V

Latchꢀup Current ................................................................+200 mA, –200 mA

V_CCꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂ.ꢂ2.4V to 3.6V

T_A(Ambient Temperature under Bias)ꢂꢂꢂꢂ.0°C to +70°C

Ground Voltageꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂ.0V

F_OSC(Crystal Frequency)ꢂꢂꢂꢂꢂꢂꢂꢂ.12 MHz ±30 ppm

Notes

[1]. Typically data modes with high chip encoding which provides a higher process gain and lower data rates provide longer range and / or a more

robust wireless link.

[2]. This mode is compatible with Cypress Generation 1 RF CyFi transceiver devices, CYWUSB6934 and CYWUSB6935.

[3]. It is permissible to connect voltages above V_IOto inputs through a series resistor limiting input current to 1 mA. AC timing not guaranteed.

[4]. Human Body Model (HBM).

10 DC Characteristics (T = 25°C, V_cc= 2.4V, f_OSC= 12.000 MHz)

Table 2 - DC Characteristics

Parameter

V_CC

V_IO

I_synth

TX I_CC5

TX I_CC6

TX I_CC7

RX I_CCoff

RX I_CCon

I_SB

Description

Conditions

0 to 70ºC

Min.

2.4

Typ.

Max.

3.6

V_CC+0.7

Unit

V

mA

µA

Power Supply Voltage

Voltage applied to I/O

I_CCduring Synth Start

I_CCduring Transmit

I_CCduring Receive

8.4

20.8

26.2

34.1

18.4

21.2

0.8

PA = 5 (ꢀ5dBm)

PA = 6 (0dBm)

PA = 7 (+4dBm)

LNA off, ATT on

LNA on, ATT off

I_CCduring Receive

Sleep Mode Current I_cc

10.0

Artaflex Inc.

215 Konrad Crescent

DSꢀ102ꢀ0006ꢀR1.5

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Markham, Ontario, Canada

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2.4GHz DSSS SPI Radio with Integrated Antenna

AW24MxxL

Data Sheet

11 AC Characteristics^[5]

Table 3 – SPI Interface^[6]

Parameter

Description

Min.

238.1

100

25

Typ.

Max.

Unit

nS

SPI Clock Period

t

SCK_CYC

SPI Clock High Time

SCK_HI

SPI Clock Low Time

SCK_LO

DAT_SU

DAT_HLD

DAT_VAL

DAT_VAL_TRI

SS_SU

SPI Input Data Setꢀup Time

SPI Input Data Hold Time

SPI Output Data Valid Time

10

0

50

20

SPI Output Data Triꢀstate (MOSI from Slave Select Deassert)

SPI Slave Select Setꢀup Time before first positive edge of SCK^[7]

SPI Slave Select Hold Time after last negative edge of SCK

SPI Slave Select Minimum Pulse Width

10

20

10

SS_HLD

SS_PW

SPI Slave Select Setꢀup Time

SCK_SU

SCK_HLD

RESET

SPI SCK Hold Time

Minimum RST pin pulse width

Figure 7 - SPI Timing

Notes

[5] AC values are not guaranteed if voltage on any pin exceeds V_IO.

[6] C_LOAD= 30 pF.

[7] SCK must start low at the time

goes low, otherwise the success of SPI transactions are not guaranteed.

Artaflex Inc.

DSꢀ102ꢀ0006ꢀR1.5

Revised 04 Jan 2013

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2.4GHz DSSS SPI Radio with Integrated Antenna

AW24MxxL

Data Sheet

12 RF Characteristics

Table 4 – Radio Parameters

Parameter Description

Conditions

Min.

Typ.

Max.

Unit

RF Frequency Range

2.400

2.483

GHz

Receiver (T=25°C, VCC = 3.0V, f_OSC= 12.000000MHz, BER < 1Eꢀ3)

Sensitivity 125kbps 64ꢀ8DR

Sensitivity 250ꢀkbps 32ꢀ8DR

Sensitivity

Sensitivity GFSK

LNA gain

BER 1Eꢀ3

CER 1Eꢀ3

–97

–93

–87

–84

22.8

–31.7

–6

dBm

dB

dBm

Count

dB/Count

–80

–15

BER 1Eꢀ3, ALL SLOW = 1

ATT gain

Maximum Received Signal

RSSI value for PWR_in–60 dBm

RSSI slope

LNA On

21

1.9

Interference Performance (CER 1Eꢀ3)

Coꢀchannel Interference rejection

CarrierꢀtoꢀInterference (C/I)

Adjacent (±1 MHz) channel selectivity C/I 1 MHz

Adjacent (±2 MHz) channel selectivity C/I 2 MHz

Adjacent (> 3 MHz) channel selectivity C/I > 3 MHz

OutꢀofꢀBand Blocking 30 MHz–12.75 MHz[

Intermodulation

C = –60dBm

9

dB

C = –60dBm

C = –67dBm

3

dB

dBm

–30

–38

–30

–36

C = –64dBm, ∆f = 5, 10 MHz

Receive Spurious Emission

800 MHz

1.6GHz

100ꢀkHz ResBW

–79

–71

–65

dBm

3.2 GHz

Transmitter (T = 25°C, VCC = 3.0V)

Maximum RF Transmit Power

RF Power Control Range

RF Power Control Range Step Size

Frequency Deviation Min

Frequency Deviation Max

Error Vector Magnitude (FSK error)

Occupied Bandwidth

PA = 7

PA = 6

PA = 5

PA = 4

PA = 3

PA = 2

PA = 1

PA = 0

+2

–2

–7

–15

–20

–26

–32

–37

+4

0

–5

+6

+2

–3

–11

–16

–22

–28

–33

dBm

dB

kHz

%rms

kHz

–13

–18

–24

–30

–35

39

5.6

270

323

10

seven steps, monotonic

PN Code Pattern 10101010

PN Code Pattern 11110000

>0 dBm

–6 dBc, 100ꢀkHz ResBW

500

876

Artaflex Inc.

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2.4GHz DSSS SPI Radio with Integrated Antenna

Table 4 – Radio Parameters (continued)

AW24MxxL

Data Sheet

Parameter Description

Conditions

Min.

Typ.

Max.

Unit

Transmit Spurious Emission (PA = 7)

Inꢀband Spurious Second Channel Power (±2 MHz)

Inꢀband Spurious Third Channel Power (>3 MHz)

NonꢀHarmonically Related Spurs (800MHz)

NonꢀHarmonically Related Spurs (1.6GHz)

NonꢀHarmonically Related Spurs (3.2GHz)

Harmonic Spurs (Second Harmonic)

Harmonic Spurs (Third Harmonic)

Fourth and Greater Harmonics

Power Management (with 30ppm crystal)

Crystal start to 10ppm

–38

–44

–38

–34

–47

–43

–48

–59

dBm

0.7

0.6

1.3

ms

ꢁs

Crystal start to IRQ

Synth Settle

XSIRQ EN = 1

Slow channels

Medium channels

Fast channels

GFSK

270

180

100

30

Link turnꢀaround time

ꢁs

Link turnꢀaround time

250 kbps

62

ꢁs

Link turnꢀaround time

125 kbps

94

ꢁs

Link turnꢀaround time

<125 kbps

31

ꢁs

Max. packet length

<60ppm crystalꢀtoꢀcrystal

all modes except 64ꢀDDR

<60ppm crystalꢀtoꢀcrystal

64ꢀDDR

40

bytes

Max. packet length

16

bytes

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2.4GHz DSSS SPI Radio with Integrated Antenna

AW24MxxL

Data Sheet

13 Mechanical Package Description

Size:

16mm x 13.5mm (0.63” x 0.53”) with Chip Antenna (AW24MCHLꢀH2)

16mm x 13.5mm (0.63” x 0.53”) with Chip Antenna (AW24MCHLꢀHR)

15mm x 13.5mm (0.63” x 0.53”) with Chip Antenna (AW24MUFLꢀH2)

15mm x 13.5mm (0.6” x 0.53”) with Chip Antenna (AW24MCHLꢀSM)

Weight: ~2 grams

* Check http://www.artaflexmodules.com/products.html for detailed mechanical info.

14 Connector

Table 5 – Connector Pin out Information For both Header and SMT Modules

SMT

Pin No

Header

Pin No

Name

Type

Default

Description

12

11

1

2

GND

VCC

Power

GND

VCC

Ground

Main Supply 2.4 to 3.6 volts

Interrupt output (configurable active high or

low), or GPIO

5

9

3

4

IRQ

I/O

ꢀ

Module Reset. Internal on Chip 10kꢀohm

pullꢀdown resistor. Active HIGH

*RST

Input

3

4

2

5

6

7

MOSI

SS

I/O

Input

Pull Up

Input

SPI data input, or SDAT

SPI Interface enable, Active LOW

SPI Clock

Input

SCK

SPI data output pin or GPIO in 3ꢀpin SPI

mode.

6

8

9

MISO

GND

I/O

Power

NC

Hi Z

GND

NC

13

Ground

1,14,15,

16,10

10

No Connect – Leave Open Circuit^[8]

11

12

TXPA

RXPA

I

No Connect – Leave Open Circuit^[8]

Buffered 0.75, 1.5, 3, 6, or 12 MHz clock, PACTL, or

GPIO. Triꢀstates in sleep mode (configure as GPIO

drive LOW).

7

8

XOUT

I/O

O

CYRF7936 control signal for external PA,

T/R switch, or GPIO.

PACTL

Note

[8]. Pins not connected internally. Reserved for power amplifier control signals, on the AWA24S,AW24RUH Artaflex module.

*There is an onboard 0.1uF capacitor placed on the reset line for POR. If the VCC power ON ramp is slower than 1mSec then it is recommended to

add an additional 0.47uF capacitor externally. When powered ON, module’s V_reset should reach 0.7xVCC at least.

Artaflex Inc.

DSꢀ102ꢀ0006ꢀR1.5

Revised 04 Jan 2013

215 Konrad Crescent

Markham, Ontario, Canada

L3R8T9

Page 12 of 13

http://www.artaflexmodules.com

905ꢀ479ꢀ0148

2.4GHz DSSS SPI Radio with Integrated Antenna

AW24MxxL

Data Sheet

14.1 Standard Part Numbers

Table 6 – Standard Part Numbers

Part Number

Description

Temperature

ꢀ20 to 70ºC

Integrated Chip Antenna Radio with Open 12 Pin Header in Commercial Temperature

Integrated Chip Antenna Radio with 12 Pin Right Angle Header in Commercial Temperature

U.FL connector External Antenna Radio with 12 Pin Header in Commercial Temperature

Integrated Chip Antenna Radio in SMT Package, Commercial Temperature

AW24MCHLꢀH2

AW24MCHLꢀHR

AW24MUFLꢀ H2

AW24MCHLꢀSM

The information contained herein is subject to change without notice and may be found to contain errors of omission or changes in parameters. For

feedback or technical support regarding Artaflex CyFi Radio Modem products please contact Artaflex at www.artaflex.com.

Artaflex Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in an Artaflex product.

Nor does it convey or imply any license under patent or other rights. Artaflex products are not warranted nor intended to be used for medical, life

support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Artaflex Inc. Furthermore, Artaflex

does not authorize its products for use as critical components in lifeꢀsupport systems where a malfunction or failure may reasonably be expected to

result in significant injury to the user. The inclusion of Artaflex products in lifeꢀsupport systems application implies that the manufacturer assumes all

risk of such use and in doing so indemnifies Artaflex Inc. against all charges.

CyFi and AutoRate are trademarks™ of Cypress Semiconductor.

All products and company names mentioned in this document are the trademarks of their respective holders.

Artaflex Inc.

DSꢀ102ꢀ0006ꢀR1.5

Revised 04 Jan 2013

215 Konrad Crescent

Markham, Ontario, Canada

L3R8T9

Page 13 of 13

http://www.artaflexmodules.com

905ꢀ479ꢀ0148


型号：	AW24MUFL-H2
厂家：	ETC
描述：	2.4GHz DSSS Micro Radio Module with Integrated Antenna
文件：	总13页 (文件大小：504K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AW24MUFL-H2 [ETC]

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