BQ4024MA-120 [ETC]
128Kx16 Nonvolatile SRAM; 128Kx16非易失SRAM
| 型号： | BQ4024MA-120 |
| 厂家： | 
ETC |
| 描述： | 128Kx16 Nonvolatile SRAM |
| 文件： | 总12页 (文件大小：433K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
bq4024/bq4024Y
128Kx16 Nonvolatile SRAM
At t h is t im e t h e in t egr a l en er gy
source is switched on to sustain the
memory until after VCC returns valid.
Features
➤ Data retention in the absence of
General Description
The CMOS bq4024 is a nonvolatile
2,097,152-bit static RAM organized
as 131,072 words by 16 bits. The
integral control circuitry and lith-
ium energy source provide reliable
nonvolatility coupled with the un-
lim it ed wr it e cycles of st a n da r d
SRAM.
power
Th e bq4024 u ses ext r em ely low
standby current CMOS SRAMs, cou-
pled with small lithium coin cells to
provide nonvolatility without long
write-cycle times and the write-cycle
limitations associated with EEPROM.
➤ Automatic write-protection dur-
ing power-up/power-down cycles
➤ Industry-standard 40-pin 128K x
16 pinout
➤ Conventional SRAM operation;
The bq4024 requires no external cir-
cuitry and is compatible with the
industry-standard 2Mb SRAM pin-
out.
Th e con t r ol cir cu it r y con st a n t ly
monitors the single 5V supply for
a n ou t -of-t ole r a n ce con d it ion .
When VCC falls out of tolerance, the
SRAM is u n con dit ion a lly wr it e-
protected to prevent an inadvertent
write operation.
unlimited write cycles
➤ 10-year minimum data retention
in absence of power
➤ Battery internally isolated until
power is applied
Pin Connections
Pin Names
Block Diagram
A0–A16
Address inputs
V
NC
CE
40
1
2
3
4
5
6
7
8
CC
DQ0–DQ15 Data input/output
39
38
37
36
35
34
33
32
31
30
WE
A
A
A
A
A
A
A
DQ
15
14
13
12
11
10
16
15
14
13
12
11
10
9
SS
8
DQ
DQ
DQ
DQ
DQ
CE
Chip enable input
Output enable input
Write enable input
No connect
OE
9
DQ
DQ
9
8
A
WE
NC
VCC
VSS
10
11
12
13
14
15
16
17
18
19
20
V
A
V
SS
DQ
DQ
DQ
DQ
DQ
29
28
27
26
25
24
23
22
21
7
6
5
4
3
A
7
A
A
5
A
6
+5 volt supply input
Ground
4
DQ
DQ
DQ
A
3
A
2
1
0
2
A
1
A
OE
0
40-Pin DIP Module
PN402401.eps
Selection Guide
Maximum
Access
Negative
Supply
Maximum
Access
Negative
Supply
Part
Part
Number
Time (ns)
Tolerance
Number
Time (ns)
Tolerance
bq4024MA -85
bq4024MA -120
85
-5%
-5%
bq4024YMA -85
bq4024YMA -120
85
-10%
-10%
120
120
Sept. 1992
1
bq4024/bq4024Y
As VCC falls past VPFD and approaches 3V, the control
circuitry switches to the internal lithium backup supply,
which provides data retention until valid VCC is applied.
Functional Description
When power is valid, the bq4024 operates as a standard
CMOS SRAM. During power-down and power-up cycles,
the bq4024 acts as a nonvolatile memory, automatically
protecting and preserving the memory contents.
When VCC returns to a level above the internal backup
cell voltage, the supply is switched back to VCC
. After
VCC ramps above the VPFD threshold, write-protection
continues for a time tCER (120ms maximum) to allow for
processor stabilization. Normal memory operation may
resume after this time.
Power-down/power-up control circuitry constantly moni-
tors the VCC supply for a power-fail-detect threshold
VPFD. The bq4024 monitors for VPFD = 4.62V typical for
use in systems with 5% supply tolerance. The bq4024Y
monitors for VPFD = 4.37V typical for use in systems
with 10% supply tolerance.
The internal coin cells used by the bq4024 have an ex-
tremely long shelf life and provide data retention for
more than 10 years in the absence of system power.
When VCC falls below the VPFD threshold, the SRAM
automatically write-protects the data. All outputs be-
come high impedance, and all inputs are treated as
“don’t care.” If a valid access is in process at the time of
power-fail detection, the memory cycle continues to com-
pletion. If the memory cycle fails to terminate within
time tWPT, write-protection takes place.
As shipped from Benchmarq, the integral lithium cells
a r e elect r ica lly isola t ed fr om t h e m em or y. (Self-
discharge in this condition is approximately 0.5% per
year.) Following the first application of VCC, this isola-
tion is broken, and the lithium backup provides data re-
tention on subsequent power-downs.
Truth Table
Mode
Not selected
Output disable
Read
CE
H
L
WE
X
OE
X
I/O Operation
High Z
High Z
DOUT
Power
Standby
Active
H
H
L
H
L
Active
Write
L
L
X
DIN
Active
Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
Conditions
VCC
DC voltage applied on VCC relative to VSS
-0.3 to 7.0
V
DC voltage applied on any pin excluding VCC
relative to VSS
VT
-0.3 to 7.0
V
V
T ≤ VCC + 0.3
TOPR
TSTG
TBIAS
Operating temperature
Storage temperature
Temperature under bias
0 to +70
-40 to +70
-10 to +70
+260
°C
°C
°C
°C
TSOLDER Soldering temperature
For 10 seconds
Note:
Permanent device damage may occur if Absolu te Maxim u m Ratin gs are exceeded. Functional operation
should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to con-
ditions beyond the operational limits for extended periods of time may affect device reliability.
Sept. 1992
2
bq4024/bq4024Y
Recommended DC Operating Conditions (T = 0 to 70°C)
A
Symbol
Parameter
Minimum
Typical
Maximum
Unit
Notes
bq4024Y
4.5
4.75
0
5.0
5.0
0
5.5
V
V
V
V
V
VCC
Supply voltage
5.5
0
bq4024
VSS
VIL
VIH
Supply voltage
Input low voltage
Input high voltage
-0.3
2.2
-
0.8
-
VCC + 0.3
Note:
Typical values indicate operation at TA = 25°C.
DC Electrical Characteristics (T = 0 to 70°C, V
≤ V
≤ V
CC CCmax)
A
CCmin
Symbol
Parameter
Minimum
Typical
Maximum
Unit
Conditions/Notes
ILI
Input leakage current
-
-
± 2
± 1
µA
VIN = VSS to VCC
CE = VIH or OE = VIH or
WE = VIL
ILO
Output leakage current
-
-
µA
VOH
VOL
ISB1
Output high voltage
Output low voltage
Standby supply current
2.4
-
-
-
V
V
IOH = -1.0 mA
IOL = 2.1 mA
CE = VIH
-
-
0.4
11
5
mA
CE ≥ VCC - 0.2V,
0V ≤ VIN ≤ 0.2V,
or VIN ≥ VCC - 0.2V
ISB2
Standby supply current
Operating supply current
-
2.5
5
mA
Min. cycle, duty = 100%,
CE = VIL, II/O = 0mA
ICC
-
95
200
mA
4.55
4.30
-
4.62
4.37
3
4.75
4.50
-
V
V
V
bq4024
VPFD
Power-fail-detect voltage
Supply switch-over voltage
bq4024Y
VSO
Note:
Typical values indicate operation at TA = 25°C, VCC = 5V.
Capacitance (T = 25°C, F = 1MHz, V
)
A
CC = 5.0V
Symbol
CI/O
Parameter
Minimum
Typical
Maximum
Unit
Conditions
Output voltage = 0V
Input voltage = 0V
Input/output capacitance
Input capacitance
-
-
-
-
10
20
pF
pF
CIN
Note:
This parameter is sampled and not 100% tested.
Sept. 1992
3
bq4024/bq4024Y
AC Test Conditions
Parameter
Test Conditions
0V to 3.0V
Input pulse levels
Input rise and fall times
5 ns
Input and output timing reference levels
Output load (including scope and jig)
1.5 V (unless otherwise specified)
See Figures 1 and 2
Figure 1. Output Load A
Figure 2. Output Load B
Read Cycle (T = 0 to 70°C, V
≤ V
≤ V
CC
A
CCmin
CCmax)
-85
-120
Min. Max. Min. Max.
Symbol
tRC
Parameter
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions
Read cycle time
85
-
-
85
85
45
-
120
-
-
120
120
60
-
tAA
Address access time
Chip enable access time
Output load A
tACE
tOE
-
-
Output load A
Output load A
Output load B
Output load B
Output load B
Output load B
Output load A
Output enable to output valid
Chip enable to output in low Z
-
-
tCLZ
tOLZ
tCHZ
tOHZ
tOH
5
5
Output enable to output in low Z
Chip disable to output in high Z
Output disable to output in high Z
Output hold from address change
0
-
0
-
0
35
25
-
0
45
35
-
0
0
10
10
Sept. 1992
4
bq4024/bq4024Y
1,2
Read Cycle No. 1 (Address Access)
1,3,4
Read Cycle No. 2 (CE Access)
1,5
Read Cycle No. 3 (OE Access)
Notes:
1. WE is held high for a read cycle.
2. Device is continuously selected: CE = OE = VIL
3. Address is valid prior to or coincident with CE transition low.
4. OE = VIL
5. Device is continuously selected: CE = VIL
.
.
.
Sept. 1992
5
bq4024/bq4024Y
Write Cycle (T = 0 to 70°C, V
≤ V
≤ V
A
CCmin
CC
CCmax)
-120
-85
Min. Max. Min. Max.
Symbol
tWC
Parameter
Write cycle time
Units
ns
Conditions/Notes
85
75
75
-
-
-
120
100
100
-
-
-
tCW
Chip enable to end of write
Address valid to end of write
ns
(1)
(1)
tAW
ns
Measured from address valid to be-
ginning of write. (2)
tAS
Address setup time
Write pulse width
0
65
5
-
-
0
85
5
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
Measured from beginning of write to
end of write. (1)
tWP
Write recovery time
(write cycle 1)
Measured from WE going high to end
of write cycle. (3)
tWR1
tWR2
tDW
tDH1
tDH2
tWZ
-
-
Write recovery time
(write cycle 2)
Measured from CE going high to end
of write cycle. (3)
15
35
0
-
15
45
0
-
Measured to first low-to-high transi-
tion of either CE or WE.
Data valid to end of write
-
-
Data hold time
(write cycle 1)
Measured from WE going high to end
of write cycle.(4)]
-
-
Data hold time
(write cycle 2)
Measured from CE going high to end
of write cycle. (4)
10
0
-
10
0
-
Write enabled to output in
high-Z
30
-
40
-
I/O pins are in output state. (5)
I/O pins are in output state. (5)
Output active from end of
write
tOW
0
0
Notes:
1. A write ends at the earlier transition of CE going high and WE going high.
2. A write occurs during the overlap of a low CE and a low WE. A write begins at the later
transition of CE going low and WE going low.
3. Either tWR1 or tWR2 must be met.
4. Either tDH1 or tDH2 must be met.
5. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in
high-impedance state.
Sept. 1992
6
bq4024/bq4024Y
1,2,3
Write Cycle No. 1 (WE-Controlled)
1,2,3,4,5
Write Cycle No. 2 (CE-Controlled)
Notes:
1. CE or WE must be high during address transition.
2. Because I/O may be active (OE low) during this period, data input signals of opposite polarity to the
outputs must not be applied.
3. If OE is high, the I/O pins remain in a state of high impedance.
4. Either tWR1 or tWR2 must be met.
5. Either tDH1 or tDH2 must be met.
Sept. 1992
7
bq4024/bq4024Y
Power-Down/Power-Up Cycle (T = 0 to 70°C)
A
Symbol
tPF
Parameter
Minimum
Typical
Maximum
Unit
µs
Conditions
VCC slew, 4.75 to 4.25 V
VCC slew, 4.25 to VSO
300
10
0
-
-
-
-
-
-
tFS
µs
tPU
VCC slew, VSO to VPFD (max.)
µs
Time during which
SRAM is write-pro-
tected after VCC passes
VPFD on power-up.
tCER
Chip enable recovery time
40
10
40
80
-
120
-
ms
years
µs
Data-retention time in
absence of VCC
tDR
TA =25°C. (2)
Delay after VCC slews
down past VPFD before
SRAM is write-
tWPT
Write-protect time
100
150
protected.
Notes:
1. Typical values indicate operation at TA = 25°C, VCC = 5V.
2. Batteries are disconnected from circuit until after VCC is applied for the first time. tDR is the
accumulated time in absence of power beginning when power is first applied to the device.
Ca u tion : Nega tive u n d er sh oots below th e a bsolu te m a xim u m r a tin g of -0.3V in ba tter y-ba ck u p m od e
m a y a ffect d a ta in tegr ity.
Power-Down/Power-Up Timing
Sept. 1992
8
bq4024/bq4024Y
MA: 40-Pin A-Type Module
(
)
40-Pin MA A-Type Module
Dimension
Minimum
0.365
0.015
0.017
0.008
2.070
0.710
0.590
0.090
0.120
0.075
Maximum
0.375
-
A
A1
B
C
D
E
0.023
0.013
2.100
0.740
0.630
0.110
0.150
0.110
e
G
L
S
All dimensions are in inches.
Sept. 1992
9
bq4024/bq4024Y
Ordering Information
bq4024 MA -
Tem p er a tu r e:
blank = Commercial (0 to +70°C)
Sp eed Op tion s:
85 = 85 ns
120 = 120 ns
Pa ck a ge Op tion :
MA = A-type module
Su p p ly Toler a n ce:
no mark = 5% negative supply tolerance
Y = 10% negative supply tolerance
Device:
bq4024 128K x 16 NVSRAM
Sept. 1992
10
Notes
11
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明