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bq4050

ZHCSEW9B –MARCH 2016–REVISED OCTOBER 2017

用于 1-4 节串联锂离子电池组的

bq4050 CEDV 电量测量仪表和保护解决方案

1 特性

bq4050 器件提供一个基于电池组的完全集成式解决方

1

案，该解决方案具备闪存可编程的定制精简指令集

CPU (RISC)、安全保护以及身份验证，适用于锂离子

和锂聚合物电池组。

•

高侧保护 N 通道 FET 驱动器可在故障期间实现串

行总线通信

•

采用内部旁路的电池均衡功能可优化电池健康状况

用于故障分析的诊断使用寿命数据监控器和黑盒记

录器

bq4050 电量测量仪表通过一个与 SMBus 兼容的接口

进行通信，并将超低功耗的高速 TI bqBMP 处理器、

高精度模拟测量功能、集成式闪存存储器、一组外设和

通信端口、N 通道 FET 驱动以及 SHA-1 身份验证变

换响应器，融合为一个完整的高性能电池管理解决方

案。

•

全面的可编程保护特性：电压、电流和温度

JEITA 充电算法支持智能充电

具有双路独立模数转换器 (ADC) 的模拟前端

–

同步电流和电压采样

高精度库伦计数器，输入偏移误差 < 1µV（典型

值）

器件信息⁽¹⁾

•

支持电池跳变点 (BTP) 功能，用于 Windows^®集成

器件型号

bq4050

封装

VQFN (32)

封装尺寸（标称值）

LED 显示屏用于充电状态和电池状态指示

4.00mm x 4.00mm

适用于编程和数据访问的 100KHz SMBus 1.1 版通

信接口，具有 400KHz 交替模式

(1) 如需了解所有可用封装，请见产品说明书末尾的可订购产品附

录。

•

SHA-1 认证响应器，用于提高电池组安全性

紧凑型 32 引脚 VQFN 封装 (RSM)

简化电路原理图

+

PACK

2 应用

•

笔记本电脑

LEDCNTLA

BAT

VC4

医疗与测试设备

LEDCNTLB

LEDCNTLC

便携式仪表

VC3

VC2

OUT

VC3

VC2

VC1

无线真空吸尘器和扫地机器人

Cell 3

Cell 2

DISP

SMBD

SMBC

PRES

VDD

GND

SMBD

SMBC

VC1

PBI

VSS SRP SRN TS1 TS2 TS3 TS4 BTP PRES

3 说明

Cell 1

BTP

德州仪器 (TI) 的 bq4050 器件采用补偿放电终止电压

(CEDV) 技术，是一款高度集成的高精度 1-4 节电池电

量测量仪表和保护解决方案，可实现自主的充电器控制

和电池平衡。

PACK–

Copyright

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLUSC67

bq4050

ZHCSEW9B –MARCH 2016–REVISED OCTOBER 2017

www.ti.com.cn

6.24 Electrical Characteristics: Internal 1.8-V LDO....... 14

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 7

6.1 Absolute Maximum Ratings ...................................... 7

6.2 ESD Ratings.............................................................. 7

6.3 Recommended Operating Conditions....................... 8

6.4 Thermal Information.................................................. 8

6.5 Electrical Characteristics: Supply Current................. 8

6.6 Electrical Characteristics: Power Supply Control...... 9

6.7 Electrical Characteristics: AFE Power-On Reset...... 9

6.25 Electrical Characteristics: High-Frequency

Oscillator .................................................................. 14

6.26 Electrical Characteristics: Low-Frequency

Oscillator .................................................................. 15

6.27 Electrical Characteristics: Voltage Reference 1.... 15

6.28 Electrical Characteristics: Voltage Reference 2.... 15

6.29 Electrical Characteristics: Instruction Flash .......... 15

6.30 Electrical Characteristics: Data Flash ................... 15

6.31 Electrical Characteristics: OCD, SCC, SCD1, SCD2

Current Protection Thresholds................................. 16

6.32 Timing Requirements: OCD, SCC, SCD1, SCD2

Current Protection Timing........................................ 17

6.33 Timing Requirements: SMBus .............................. 17

6.34 Timing Requirements: SMBus XL......................... 18

6.35 Typical Characteristics.......................................... 19

Detailed Description ............................................ 22

7.1 Overview ................................................................. 22

7.2 Functional Block Diagram ...................................... 22

7.3 Feature Description................................................. 23

7.4 Device Functional Modes........................................ 26

Applications and Implementation ...................... 27

8.1 Application Information .......................................... 27

8.2 Typical Applications ................................................ 28

Power Supply Recommendations...................... 42

6.8 Electrical Characteristics: AFE Watchdog Reset and

Wake Timer................................................................ 9

7

6.9 Electrical Characteristics: Current Wake

Comparator ................................................................ 9

6.10 Electrical Characteristics: VC1, VC2, VC3, VC4,

BAT, PACK .............................................................. 10

6.11 Electrical Characteristics: SMBD, SMBC.............. 10

6.12 Electrical Characteristics: PRES, BTP_INT, DISP

................................................................................. 10

8

9

6.13 Electrical Characteristics: LEDCNTLA, LEDCNTLB,

LEDCNTLC ............................................................. 11

6.14 Electrical Characteristics: Coulomb Counter ........ 11

6.15 Electrical Characteristics: CC Digital Filter ........... 11

6.16 Electrical Characteristics: ADC ............................. 12

6.17 Electrical Characteristics: ADC Digital Filter......... 12

6.18 Electrical Characteristics: CHG, DSG FET Drive . 12

6.19 Electrical Characteristics: PCHG FET Drive......... 13

6.20 Electrical Characteristics: FUSE Drive.................. 13

10 Layout................................................................... 42

10.1 Layout Guidelines ................................................. 42

10.2 Layout Example .................................................... 44

11 器件和文档支持 ..................................................... 46

11.1 文档支持................................................................ 46

11.2 社区资源................................................................ 46

11.3 商标....................................................................... 46

11.4 静电放电警告......................................................... 46

11.5 Glossary................................................................ 46

12 机械、封装和可订购信息....................................... 46

6.21 Electrical Characteristics: Internal Temperature

Sensor...................................................................... 13

6.22 Electrical Characteristics: TS1, TS2, TS3, TS4 .... 14

6.23 Electrical Characteristics: PTC, PTCEN ............... 14

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision A (April 2016) to Revision B

Page

•

已更改应用............................................................................................................................................................................. 1

2

bq4050

www.ti.com.cn

ZHCSEW9B –MARCH 2016–REVISED OCTOBER 2017

5 Pin Configuration and Functions

RSM Package

32-Pin VQFN with Exposed Thermal Pad

Top View

PBI

VC4

VC3

VC2

VC1

SRN

NC

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

PTCEN

PTC

LEDCNTLC

LEDCNTLB

LEDCNTLA

SMBC

Thermal

Pad

SMBD

SRP

DISP

Pin Functions

TYPE

DESCRIPTION

NAME

NUMBER

PBI

1

P⁽¹⁾

IA

Power supply backup input pin

Sense voltage input pin for the most positive cell, and balance current input for the most

positive cell

VC4

VC3

VC2

VC1

2

3

4

5

Sense voltage input pin for the second most positive cell, balance current input for the

second most positive cell, and return balance current for the most positive cell

IA

Sense voltage input pin for the third most positive cell, balance current input for the third

most positive cell, and return balance current for the second most positive cell

Sense voltage input pin for the least positive cell, balance current input for the least

positive cell, and return balance current for the third most positive cell

Analog input pin connected to the internal coulomb counter peripheral for integrating a

small voltage between SRP and SRN where SRP is the top of the sense resistor.

SRN

NC

6

7

8

I

—

I

Not internally connected. Connect to V_SS

.

Analog input pin connected to the internal coulomb counter peripheral for integrating a

small voltage between SRP and SRN where SRP is the top of the sense resistor.

SRP

VSS

TS1

9

P

IA

—

O

Device ground

10

11

12

13

14

15

Temperature sensor 1 thermistor input pin

Temperature sensor 2 thermistor input pin

Temperature sensor 3 thermistor input pin

Temperature sensor 4 thermistor input pin

TS2

TS3

TS4

NC

Not internally connected. Connect to V_SS

.

BTP_INT

Battery Trip Point (BTP) interrupt output

PRES or

SHUTDN

Host system present input for removable battery pack or emergency system shutdown

input for embedded packs

16

I

(1) P = Power Connection, O = Digital Output, AI = Analog Input, I = Digital Input, I/OD = Digital Input/Output

3

bq4050

ZHCSEW9B –MARCH 2016–REVISED OCTOBER 2017

www.ti.com.cn

Pin Functions (continued)

TYPE

DESCRIPTION

NAME

DISP

NUMBER

17

18

19

—

Display control for LEDs

SMBus data pin

SMBD

SMBC

I/OD

SMBus clock pin

LED display segment that drives the external LEDs depending on the firmware

configuration

LEDCNTLA

LEDCNTLB

20

21

—

LED display segment that drives the external LEDs depending on the firmware

configuration

LED display segment that drives the external LEDs depending on the firmware

configuration

LEDCNTLC

PTC

22

23

24

—

IA

Safety PTC thermistor input pin. To disable, connect PTC and PTCEN to V_SS

Safety PTC thermistor enable input pin. Connect to BAT. To disable, connect PTC and

PTCEN to V_SS

.

PTCEN

.

FUSE

VCC

PACK

DSG

NC

25

26

27

28

29

30

31

32

O

P

Fuse drive output pin

Secondary power supply input

Pack sense input pin

IA

O

—

O

P

NMOS Discharge FET drive output pin

Not internally connected. Connect to V_SS

PMOS Precharge FET drive output pin

NMOS Charge FET drive output pin

Primary power supply input pin

.

PCHG

CHG

BAT

4

bq4050

www.ti.com.cn

ZHCSEW9B –MARCH 2016–REVISED OCTOBER 2017

VC4

CDEN4

CDEN3

BAT

3.1 V

VCC

PACK

VC3

+

–

BATDET

ENVCC

PACK

Detector

VC2

ADC Mux

ADC

PACKDET

PBI

SHUTDOWN

Shutdown

Latch

CDEN2

Reference

System

1.8 V

Domain

SHOUT

VC1

ENBAT

BAT

Control

CDEN1

Power Supply Control

Cell Balancing

VCC

CHGEN

BAT

2 kΩ

CHG

Pump

8 kΩ

PCHG

2 kΩ

CHGOFF

PCHGEN

Pre-Charge Drive

PACK

BAT

DSGEN

ZVCD

BAT

2 kΩ

DSG

CHGEN

Pump

BAT

CHG

Pump

VCC

DSGOFF

ZVCHGEN

CHG, DSG Drive

Zero-Volt Charge

Figure 1. Pin Equivalent Diagram 1

5

bq4050

ZHCSEW9B –MARCH 2016–REVISED OCTOBER 2017

www.ti.com.cn

1.8 V

ADTHx

BAT

FUSEWKPUP

18 kΩ

2 kΩ

ADC Mux

ADC

150 nA

TS1,2,3,4

FUSEEN

2 kΩ

FUSE

1.8 V

100 kΩ

FUSEDIG

RCWKPUP

RCPUP

FUSE Drive

1 kΩ

RCIN

RCOUT

100 kΩ

SMBCIN

SMBC

Thermistor Inputs

SMBCOUT

SMBCEN

1 MΩ

PBI

100 kΩ

SMBDIN

SMBD

RHOEN

SMBDOUT

10 kΩ

SMBDEN

1 MΩ

PRES

SMBus Interface

RHOUT

100 kΩ

RHIN

High-Voltage GPIO

PTCEN

BAT

30 kΩ

PTCDIG

PTC

Comparator

PTC

Counter

PTC

Latch

RLOEN

290 nA

LED1, 2, 3

22.5 mA

RLOUT

100 kΩ

RLIN

PTC Detection

LED Drive

Figure 2. Pin Equivalent Diagram 2

6

bq4050

www.ti.com.cn

ZHCSEW9B –MARCH 2016–REVISED OCTOBER 2017

10 Ω

VC4

CHANx

Φ

2

3.8 kΩ

1.9 MΩ

0.1 MΩ

SRP

SRN

Φ

1

ADC Mux

ADC

Comparator

Array

Φ

2

1

3.8 kΩ

Φ

2

10 Ω

100 Ω

PACK

Φ

1

Coulomb

Counter

Φ

2

1

CHANx

100 Ω

Φ

1.9 MΩ

0.1 MΩ

ADC Mux

ADC

OCD, SCC, SCD Comparators and Coulomb Counter

VC4 and PACK Dividers

Figure 3. Pin Equivalent Diagram 3

6 Specifications

6.1 Absolute Maximum Ratings

Over-operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

30

UNIT

Supply voltage range, V_CCBAT, VCC, PBI

PACK, SMBC, SMBD, PRES or SHUTDN, BTP_INT, DISP

TS1, TS2, TS3, TS4

V

30

V_REG+ 0.3

V_BAT+ 0.3

0.3

PTC, PTCEN, LEDCNTLA, LEDCNTLB, LEDCNTLC

SRP, SRN

VC3 + 8.5 V, or

VSS + 30

VC4

VC3 – 0.3

VC2 – 0.3

VC1 – 0.3

VSS – 0.3

V

Input voltage range, V_IN

VC2 + 8.5 V, or

VSS + 30

VC3

VC2

VC1

VC1 + 8.5 V, or

VSS + 30

VSS + 8.5 V, or

VSS + 30 V

CHG, DSG

Output voltage range, V_O

PCHG, FUSE

–0.3

32

30

V

Maximum VSS current, I_SS

50

mA

°C

T_STG

Storage temperature

–65

150

300

Lead temperature (soldering, 10 s), T_SOLDER

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification

JESD22-C101⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7

bq4050

ZHCSEW9B –MARCH 2016–REVISED OCTOBER 2017

www.ti.com.cn

6.3 Recommended Operating Conditions

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

MIN

2.2

NOM

MAX

26

UNIT

V_CC

Supply voltage

BAT, VCC, PBI

V

V_SHUTDOWN–

Shutdown voltage

V_PACK< V_SHUTDOWN–

V_PACK> V_SHUTDOWN–+ V_HYS

1.8

2.0

2.2

V_SHUTDOWN+Start-up voltage

2.05

2.25

2.45

Shutdown voltage

hysteresis

V_HYS

V_SHUTDOWN+– V_SHUTDOWN–

250

mV

PACK, SMBC, SMBD, PRES, BTP_IN, DISP

26

V_REG

TS1, TS2, TS3, TS4

PTC, PTCEN, LEDCNTLA, LEDCNTLB, LEDCNTLC

V_BAT

SRP, SRN

VC4

–0.2

V_VC3

V_VC2

V_VC1

V_VSS

0.2

V_IN

Input voltage range

V

V_VC3+ 5

V_VC2+ 5

V_VC1+ 5

V_VSS+ 5

VC3

VC2

VC1

Output voltage

range

V_O

CHG, DSG, PCHG, FUSE

26

V

External PBI

capacitor

C_PBI

T_OPR

2.2

µF

°C

Operating

temperature

–40

85

6.4 Thermal Information

bq4050

RSM (QFN)

32 PINS

47.4

THERMAL METRIC⁽¹⁾

UNIT

R_{θJA, High K}

R_θJC(top)

R_θJB

Junction-to-ambient thermal resistance

Junction-to-case(top) thermal resistance

°C/W

40.3

Junction-to-board thermal resistance

14.7

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case(bottom) thermal resistance

0.8

ψ_JB

14.4

R_θJC(bottom)

3.8

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.5 Electrical Characteristics: Supply Current

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 20 V (unless otherwise noted)

PARAMETER

NORMAL mode

TEST CONDITIONS

CHG on. DSG on, no Flash write

MIN

TYP

336

75

MAX

UNIT

I_NORMAL

I_SLEEP

µA

CHG off, DSG on, no SBS communication

CHG off, DSG off, no SBS communication

SLEEP mode

µA

52

I_SHUTDOWN

SHUTDOWN mode

1.6

8

bq4050

www.ti.com.cn

ZHCSEW9B –MARCH 2016–REVISED OCTOBER 2017

6.6 Electrical Characteristics: Power Supply Control

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

BAT to V_CC

V_{SWITCHOVER–}

switchover

voltage

V_BAT< V_{SWITCHOVER–}

1.95

2.1

2.2

V

V_CCto BAT

switchover

voltage

V_SWITCHOVER+

V_BAT> V_{SWITCHOVER–}+ V_HYS

2.9

3.1

3.25

V

Switchover

voltage hysteresis

V_HYS

V_SWITCHOVER+– V_{SWITCHOVER–}

1000

mV

BAT pin, BAT = 0 V, VCC = 25 V, PACK = 25 V

PACK pin, BAT = 25 V, VCC = 0 V, PACK = 0 V

1

Input Leakage

current

I_LKG

µA

BAT and PACK terminals, BAT = 0 V, VCC = 0 V, PACK

= 0 V, PBI = 25 V

1

Internal pulldown

resistance

R_PD

PACK

30

40

50

kΩ

6.7 Electrical Characteristics: AFE Power-On Reset

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Negative-going

voltage input

V_REGIT–

V_HYS

V_REG

1.51

1.55

1.59

V

Power-on reset

hysteresis

V_REGIT+– V_REGIT–

70

100

300

130

400

mV

µs

Power-on reset

time

t_RST

200

6.8 Electrical Characteristics: AFE Watchdog Reset and Wake Timer

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

372

TYP

500

MAX

628

UNIT

t_WDT= 500

t_WDT= 1000

t_WDT= 2000

t_WDT= 4000

t_WAKE= 250

t_WAKE= 500

t_WAKE= 1000

t_WAKE= 512

744

1000

2000

4000

250

1256

2512

5024

314

AFE watchdog

timeout

t_WDT

ms

1488

2976

186

372

500

628

t_WAKE

AFE wake timer

ms

744

1000

2000

1256

2512

1488

FET off delay after

reset

t_FETOFF

t_FETOFF= 512

409

512

614

6.9 Electrical Characteristics: Current Wake Comparator

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_WAKE= ±0.625 mV

MIN

±0.3

±0.6

±1.2

±2.4

TYP

±0.625

±1.25

±2.5

MAX

±0.9

±1.8

±3.6

±7.2

UNIT

V_WAKE= ±1.25 mV

V_WAKE= ±2.5 mV

V_WAKE= ±5 mV

Wake voltage

threshold

V_WAKE

mV

±5.0

9

bq4050

ZHCSEW9B –MARCH 2016–REVISED OCTOBER 2017

www.ti.com.cn

Electrical Characteristics: Current Wake Comparator (continued)

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Temperature drift

of V_WAKEaccuracy

V_WAKE(DRIFT)

0.5%

°C

Time from

application of

current to wake

interrupt

t_WAKE

700

µs

Wake comparator

startup time

t_WAKE(SU)

500

1000

6.10 Electrical Characteristics: VC1, VC2, VC3, VC4, BAT, PACK

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VC1–VSS, VC2–VC1, VC3–VC2, VC4–VC3

BAT–VSS, PACK–VSS

MIN

TYP

MAX

0.2020

0.051

0.510

5

UNIT

0.1980 0.2000

K

Scaling factor

0.049

0.490

–0.2

0.050

0.500

—

V_REF2

VC1–VSS, VC2–VC1, VC3–VC2, VC4–VC3

BAT–VSS, PACK–VSS

V_IN

Input voltage range

Input leakage current

V

–0.2

20

VC1, VC2, VC3, VC4, cell balancing off, cell detach

detection off, ADC multiplexer off

I_LKG

R_CB

I_CD

1

200

70

µA

Ω

Internal cell balance

resistance

R_DS(ON)for internal FET switch at 2 V < V_DS< 4 V

VCx > VSS + 0.8 V

Internal cell detach

check current

30

50

µA

6.11 Electrical Characteristics: SMBD, SMBC

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

SMBC, SMBD, V_REG= 1.8 V

MIN

TYP

MAX

UNIT

V

V_IH

Input voltage high

Input voltage low

Output low voltage

Input capacitance

Input leakage current

Pulldown resistance

1.3

V_IL

SMBC, SMBD, V_REG= 1.8 V

0.8

0.4

V

V_OL

C_IN

I_LKG

R_PD

SMBC, SMBD, V_REG= 1.8 V, I_OL= 1.5 mA

V

5

pF

µA

MΩ

1

0.7

1.0

1.3

6.12 Electrical Characteristics: PRES, BTP_INT, DISP

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

High-level input

Low-level input

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

V_IH

V_IL

1.3

0.55

V

V_BAT> 5.5 V, I_OH= –0 µA

3.5

1.8

V_OH

Output voltage high

V

V_BAT> 5.5 V, I_OH= –10 µA

I_OL= 1.5 mA

V_OL

C_IN

Output voltage low

Input capacitance

Input leakage current

0.4

1

V

5

pF

µA

I_LKG

10

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Electrical Characteristics: PRES, BTP_INT, DISP (continued)

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Output reverse

resistance

R_O

Between PRES or BTP_INT or DISP and PBI

8

kΩ

6.13 Electrical Characteristics: LEDCNTLA, LEDCNTLB, LEDCNTLC

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

High-level input

Low-level input

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

V_IH

V_IL

1.45

0.55

V

V_BAT

–

V_OH

V_OL

I_SC

Output voltage high

Output voltage low

V_BAT> 3.0 V, I_OH= –22.5 mA

V

1.6

I_OL= 1.5 mA

0.4

High level output

current protection

–30

–45

–6 0

mA

Low level output

current

I_OL

V_BAT> 3.0 V, V_OH= 0.4 V

V_BAT= V_LEDCNTLx+ 2.5 V

15.75

22.5

29.25

mA

Current matching

between LEDCNTLx

I_LEDCNTLx

±1%

20

C_IN

Input capacitance

pF

µA

I_LKG

Input leakage current

1

Frequency of LED

pattern

f_LEDCNTLx

124

Hz

6.14 Electrical Characteristics: Coulomb Counter

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

Input voltage range

TEST CONDITIONS

MIN

–0.1

TYP

MAX

0.1

UNIT

V

Full scale range

Integral nonlinearity⁽¹⁾

Offset error

–V_REF1/10

V_REF1/10

±22.3

±10

V

16-bit, best fit over input voltage range

16-bit, Post-calibration

±5.2

±5

LSB

µV

Offset error drift

Gain error

15-bit + sign, Post-calibration

0.2

0.3

µV/°C

FSR

15-bit + sign, over input voltage range

±0.2%

±0.8%

Gain error drift

150 PPM/°C

Effective input resistance

2.5

MΩ

(1) 1 LSB = V_REF1/(10 × 2^N) = 1.215/(10 × 2¹⁵) = 3.71 µV

6.15 Electrical Characteristics: CC Digital Filter

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

Conversion time

Effective resolution

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ms

Single conversion

250

15

Bits

11

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6.16 Electrical Characteristics: ADC

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

Internal reference (V_REF1

External reference (V_REG

V_FS= V_REF1or V_REG

MIN

–0.2

–V_FS

TYP

MAX

1

UNIT

)

Input voltage range

V

)

0.8 × V_REG

V_FS

Full scale range

V

16-bit, best fit, –0.1 V to 0.8 × V_REF1

16-bit, best fit, –0.2 V to –0.1 V

16-bit, Post-calibration, V_FS= V_REF1

16-bit, –0.1 V to 0.8 × V_FS

±6.6

Integral nonlinearity⁽¹⁾

LSB

±13.1

±157

Offset error⁽²⁾

±67

0.6

µV

Offset error drift

Gain error

3

µV/°C

FSR

±0.2%

±0.8%

Gain error drift

Effective input resistance

16-bit, –0.1 V to 0.8 × V_FS

150 PPM/°C

8

MΩ

(1) 1 LSB = V_REF1/(2^N) = 1.225/(2¹⁵) = 37.4 µV (when t_CONV= 31.25 ms)

(2) For VC1–VSS, VC2–VC1, VC3–VC2, VC4–VC3, VC4–VSS, PACK–VSS, and V_REF1/2, the offset error is multiplied by (1/ADC

multiplexer scaling factor (K)).

6.17 Electrical Characteristics: ADC Digital Filter

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

31.25

15.63

7.81

MAX

UNIT

Single conversion

No missing codes

Conversion time

ms

1.95

Resolution

16

14

13

11

9

Bits

With sign, t_CONV= 31.25 ms

With sign, t_CONV= 15.63 ms

With sign, t_CONV= 7.81 ms

With sign, t_CONV= 1.95 ms

15

14

12

10

Effective resolution

6.18 Electrical Characteristics: CHG, DSG FET Drive

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Ratio_DSG= (V_DSG– V_BAT)/V_BAT, 2.2 V < V_BAT< 4.92 V,

10 MΩ between PACK and DSG

2.133

2.333

2.433

Output voltage

ratio

—

Ratio_CHG= (V_CHG– V_BAT)/V_BAT, 2.2 V < V_BAT< 4.92 V,

10 MΩ between BAT and CHG

2.133

10.5

2.333

11.5

2.433

12

V_DSG(ON)= V_DSG– V_BAT, 4.92 V ≤ V_BAT≤ 18 V, 10 MΩ

between PACK and DSG

Output voltage,

CHG and DSG on

V_(FETON)

V

V_CHG(ON)= V_CHG– V_BAT, 4.92 V ≤ V_BAT≤ 18 V, 10 MΩ

between BAT and CHG

12

V_DSG(OFF)= V_DSG– V_PACK, 10 MΩ between PACK and

DSG

–0.4

0.4

Output voltage,

CHG and DSG off

V_(FETOFF)

V_CHG(OFF)= V_CHG– V_BAT, 10 MΩ between BAT and CHG

V_DSGfrom 0% to 35% V_DSG(ON)(TYP), V_BAT≥ 2.2 V, C_L

=

4.7 nF between DSG and PACK, 5.1 kΩ between DSG

and C_L, 10 MΩ between PACK and DSG

200

500

t_R

Rise time

µs

V_CHGfrom 0% to 35% V_CHG(ON)(TYP), V_BAT≥ 2.2 V, C_L

4.7 nF between CHG and BAT, 5.1 kΩ between CHG

and C_L, 10 MΩ between BAT and CHG

=

12

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Electrical Characteristics: CHG, DSG FET Drive (continued)

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_DSGfrom V_DSG(ON)(TYP)to 1 V, V_BAT≥ 2.2 V, C_L= 4.7 nF

between DSG and PACK, 5.1 kΩ between DSG and C_L,

10 MΩ between PACK and DSG

40

300

t_F

Fall time

µs

V_CHGfrom V_CHG(ON)(TYP)to 1 V, V_BAT≥ 2.2 V, C_L= 4.7

nF between CHG and BAT, 5.1 kΩ between CHG and

C_L, 10 MΩ between BAT and CHG

40

200

6.19 Electrical Characteristics: PCHG FET Drive

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Output voltage,

PCHG on

V_PCHG(ON)= VV_CC– V_PCHG, 10 MΩ between V_CCand

PCHG

V_(FETON)

6

7

8

V

Output voltage,

PCHG off

V_PCHG(OFF)= VV_CC– V_PCHG, 10 MΩ between V_CCand

PCHG

V_(FETOFF)

–0.4

0.4

V

V_PCHGfrom 10% to 90% V_{PCHG(ON)(TYP)}, VV_CC≥ 8 V, C_L

4.7 nF between PCHG and V_CC, 5.1 kΩ between PCHG

and C_L, 10 MΩ between V_CCand CHG

=

t_R

Rise time

Fall time

40

200

µs

V_PCHGfrom 90% to 10% V_{PCHG(ON)(TYP)}, V_CC≥ 8 V, C_L

4.7 nF between PCHG and V_CC, 5.1 kΩ between PCHG

and C_L, 10 MΩ between V_CCand CHG

=

t_F

200

µs

6.20 Electrical Characteristics: FUSE Drive

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

8.65

V_BAT

2.5

UNIT

V

_BAT≥ 8 V, C_L= 1 nF, I_AFEFUSE= 0 µA

6

V_BAT– 0.1

1.5

7

Output voltage

high

V_OH

V

V_BAT< 8 V, C_L= 1 nF, I_AFEFUSE= 0 µA

V_IH

High-level input

2.0

V

Internal pullup

current

I_AFEFUSE(PU)

V_BAT≥ 8 V, V_AFEFUSE= VSS

150

330

3.2

nA

R_AFEFUSE

C_IN

Output impedance

Input capacitance

2

2.6

5

kΩ

pF

Fuse trip detection

delay

t_DELAY

t_RISE

128

256

20

µs

Fuse output rise

time

V_BAT≥ 8 V, C_L= 1 nF, V_OH= 0 V to 5 V

5

6.21 Electrical Characteristics: Internal Temperature Sensor

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

–1.9

TYP

–2.0

MAX

–2.1

UNIT

V_TEMPP

Internal temperature

sensor voltage drift

V_TEMP

mV/°C

V_TEMPP– V_TEMPN, assured by design

0.177

0.178

0.179

13

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6.22 Electrical Characteristics: TS1, TS2, TS3, TS4

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

TS1, TS2, TS3, TS4, V_BIAS= V_REF1

TS1, TS2, TS3, TS4, V_BIAS= V_REG

MIN

–0.2

TYP

MAX

0.8 × V_REF1

0.8 × V_REG

UNIT

Input voltage

range

V_IN

V

Internal pullup

resistance

R_NTC(PU)

TS1, TS2, TS3, TS4

14.4

18

21.6

kΩ

Resistance drift

over temperature

R_NTC(DRIFT)

–360

–280

–200 PPM/°C

6.23 Electrical Characteristics: PTC, PTCEN

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

R_PTC(TRIP)PTC trip resistance

V_PTC(TRIP)

TEST CONDITIONS

MIN

1.2

TYP

2.5

MAX

3.95

890

UNIT

MΩ

PTC trip voltage

V_PTC(TRIP)= V_PTCEN– V_PTC

200

500

mV

Internal PTC

current bias

I_PTC

T_A= –40°C to 110°C

200

40

290

80

350

145

nA

ms

t_PTC(DELAY)

PTC delay time

6.24 Electrical Characteristics: Internal 1.8-V LDO

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_REG

Regulator voltage

1.6

1.8

2.0

V

Regulator output

over temperature

ΔV_O(TEMP)

ΔV_REG/ΔT_A, I_REG= 10 mA

±0.25%

ΔV_O(LINE)

Line regulation

ΔV_REG/ΔV_BAT, V_BAT= 10 mA

–0 .6%

–1.5%

0.5%

1.5%

ΔV_O(LOAD)Load regulation

ΔV_REG/ΔI_REG, I_REG= 0 mA to 10 mA

Regulator output

current limit

I_REG

V_REG= 0.9 × V_REG(NOM), V_IN> 2.2 V

V_REG= 0 × V_REG(NOM)

20

25

mA

dB

Regulator short-

I_SC

40

55

circuit current limit

Power supply

PSRR_REG

ΔV_BAT/ΔV_REG, I_REG= 10 mA ,V_IN> 2.5 V, f = 10 Hz

rejection ratio

Slew rate

V_SLEW

enhancement

V_REG

1.58

1.65

V

voltage threshold

6.25 Electrical Characteristics: High-Frequency Oscillator

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

16.78

MAX

UNIT

f_HFO

Operating frequency

MHz

T_A= –20°C to 70°C, includes frequency drift

T_A= –40°C to 85°C, includes frequency drift

–2.5%

–3.5%

±0.25%

2.5%

3.5%

f_HFO(ERR)

Frequency error

T_A= –20°C to 85°C, oscillator frequency within

+/–3% of nominal

4

ms

µs

t_HFO(SU)

Start-up time

oscillator frequency within +/–3% of nominal

100

14

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6.26 Electrical Characteristics: Low-Frequency Oscillator

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

Operating frequency

TEST CONDITIONS

MIN

TYP

262.144

±0.25%

±0.25

MAX

UNIT

f_LFO

kHz

T_A= –20°C to 70°C, includes frequency drift

T_A= –40°C to 85°C, includes frequency drift

–1.5%

–2.5

1.5%

2.5

f_LFO(ERR)

Frequency error

Failure detection

frequency

f_LFO(FAIL)

30

80

100

kHz

6.27 Electrical Characteristics: Voltage Reference 1

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Internal reference

voltage

V_REF1

T_A= 25°C, after trim

1.21

1.215

1.22

V

T_A= 0°C to 60°C, after trim

T_A= –40°C to 85°C, after trim

±50

±80

Internal reference

voltage drift

V_REF1(DRIFT)

PPM/°C

6.28 Electrical Characteristics: Voltage Reference 2

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Internal reference

voltage

V_REF2

T_A= 25°C, after trim

1.22

1.225

1.23

V

T_A= 0°C to 60°C, after trim

T_A= –40°C to 85°C, after trim

±50

±80

Internal reference

voltage drift

V_REF2(DRIFT)

PPM/°C

6.29 Electrical Characteristics: Instruction Flash

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

Data retention

TEST CONDITIONS

MIN

TYP

MAX

UNIT

10

Years

Flash programming

write cycles

1000

Cycles

µs

Word programming

time

t_PROGWORD

T_A= –40°C to 85°C

40

t_MASSERASE

t_PAGEERASE

I_FLASHREAD

I_FLASHWRITE

I_FLASHERASE

Mass-erase time

Page-erase time

Flash-read current

Flash-write current

Flash-erase current

T_A= –40°C to 85°C

40

2

ms

mA

5

15

6.30 Electrical Characteristics: Data Flash

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Data retention

10

Years

Flash programming

write cycles

20000

Cycles

µs

Word programming

time

t_PROGWORD

T_A= –40°C to 85°C

40

15

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Electrical Characteristics: Data Flash (continued)

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A= –40°C to 85°C

MIN

TYP

MAX

40

1

UNIT

ms

t_MASSERASE

t_PAGEERASE

I_FLASHREAD

I_FLASHWRITE

I_FLASHERASE

Mass-erase time

Page-erase time

Flash-read current

Flash-write current

Flash-erase current

T_A= –40°C to 85°C

ms

mA

5

15

6.31 Electrical Characteristics: OCD, SCC, SCD1, SCD2 Current Protection Thresholds

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_OCD= V_SRP– V_SRN,AFE PROTECTION

CONTROL[RSNS] = 1

–16.6

–100

OCD detection

threshold voltage range

V_OCD

mV

V_OCD= V_SRP– V_SRN,AFE PROTECTION

CONTROL[RSNS] = 0

–8.3

–50

V_OCD= V_SRP– V_SRN,AFE PROTECTION

CONTROL[RSNS] = 1

–5.56

–2.78

OCD detection

threshold voltage

program step

ΔV_OCD

mV

V_OCD= V_SRP– V_SRN,AFE PROTECTION

CONTROL[RSNS] = 0

V_SCC= V_SRP– V_SRN,AFE PROTECTION

CONTROL[RSNS] = 1

44.4

22.2

200

100

SCC detection

threshold voltage range

V_SCC

V_SCC= V_SRP– V_SRN,AFE PROTECTION

CONTROL[RSNS] = 0

V_SCC= V_SRP– V_SRN,AFE PROTECTION

CONTROL[RSNS] = 1

22.2

11.1

SCC detection

threshold voltage

program step

ΔV_SCC

V_SCD1

ΔV_SCD1

V_SCD2

ΔV_SCD2

V_SCC= V_SRP– V_SRN,AFE PROTECTION

CONTROL[RSNS] = 0

V_SCD1= V_SRP– V_SRN,AFE PROTECTION

CONTROL[RSNS] = 1

–44.4

–22.2

–200

–100

SCD1 detection

threshold voltage range

V_SCD1= V_SRP– V_SRN,AFE PROTECTION

CONTROL[RSNS] = 0

V_SCD1= V_SRP– V_SRN,AFE PROTECTION

CONTROL[RSNS] = 1

–22.2

–11.1

SCD1 detection

threshold voltage

program step

V_SCD1= V_SRP– V_SRN,AFE PROTECTION

CONTROL[RSNS] = 0

V_SCD2= V_SRP– V_SRN,AFE PROTECTION

CONTROL[RSNS] = 1

–44.4

–22.2

–200

–100

SCD2 detection

threshold voltage range

V_SCD2= V_SRP– V_SRN,AFE PROTECTION

CONTROL[RSNS] = 0

V_SCD2= V_SRP– V_SRN,AFE PROTECTION

CONTROL[RSNS] = 1

–22.2

–11.1

SCD2 detection

threshold voltage

program step

mV

V_SCD2= V_SRP– V_SRN,AFE PROTECTION

CONTROL[RSNS] = 0

OCD, SCC, and SCDx

offset error

V_OFFSET

V_SCALE

Post-trim

–2.5

2.5

No trim

–10%

–5%

10%

5%

OCD, SCC, and SCDx

scale error

Post-trim

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6.32 Timing Requirements: OCD, SCC, SCD1, SCD2 Current Protection Timing

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

MIN

NOM

MAX

UNIT

OCD detection

delay time

t_OCD

1

31

ms

OCD detection

delay time

program step

Δt_OCD

2

ms

µs

SCC detection

delay time

t_SCC

0

915

SCC detection

delay time

Δt_SCC

61

program step

AFE PROTECTION CONTROL[SCDDx2] = 0

AFE PROTECTION CONTROL[SCDDx2] = 1

AFE PROTECTION CONTROL[SCDDx2] = 0

0

915

SCD1 detection

delay time

t_SCD1

Δt_SCD1

t_SCD2

µs

1850

SCD1 detection

delay time

program step

61

AFE PROTECTION CONTROL[SCDDx2] = 1

121

AFE PROTECTION CONTROL[SCDDx2] = 0

AFE PROTECTION CONTROL[SCDDx2] = 1

AFE PROTECTION CONTROL[SCDDx2] = 0

0

458

915

SCD2 detection

delay time

SCD2 detection

delay time

program step

30.5

61

Δt_SCD2

t_DETECT

t_ACC

µs

AFE PROTECTION CONTROL[SCDDx2] = 1

Current fault

detect time

V_SRP– V_SRN= V_T– 3 mV for OCD, SCD1, and SC2,

V_SRP– V_SRN= V_T+ 3 mV for SCC

160

Current fault

delay time

accuracy

Max delay setting

–10%

10%

6.33 Timing Requirements: SMBus

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

MIN

NOM

MAX

UNIT

f_SMB

f_MAS

SMBus operating frequency SLAVE mode, SMBC 50% duty cycle

10

100

kHz

SMBus master clock

MASTER mode, no clock low slave extend

frequency

51.2

kHz

µs

Bus free time between start

and stop

t_BUF

4.7

4.0

Hold time after (repeated)

start

t_HD(START)

µs

t_SU(START)

t_SU(STOP)

t_HD(DATA)

t_SU(DATA)

t_TIMEOUT

t_LOW

Repeated start setup time

Stop setup time

4.7

4.0

300

250

25

µs

ns

ms

µs

ns

Data hold time

Data setup time

Error signal detect time

Clock low period

35

4.7

4.0

t_HIGH

Clock high period

50

1000

300

t_R

Clock rise time

Clock fall time

10% to 90%

90% to 10%

t_F

Cumulative clock low slave

extend time

t_LOW(SEXT)

t_LOW(MEXT)

25

10

ms

Cumulative clock low

master extend time

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6.34 Timing Requirements: SMBus XL

Typical values stated where T_A= 25°C and VCC = 14.4 V, Min/Max values stated where T_A= –40°C to 85°C and VCC =

2.2 V to 26 V (unless otherwise noted)

MIN

NOM

MAX

UNIT

f_SMBXL

t_BUF

SMBus XL operating

frequency

SLAVE mode

40

400

kHz

Bus free time between start

and stop

4.7

µs

t_HD(START)

t_SU(START)

t_SU(STOP)

t_TIMEOUT

t_LOW

Hold time after (repeated) start

Repeated start setup time

Stop setup time

4.0

4.7

4.0

5

µs

ms

µs

Error signal detect time

Clock low period

20

t_HIGH

Clock high period

Tt_R

Tt_F

Tt_R

Tt_HIGH

T

t_SU(STOP)p

t_HD(START)

Tt_BUFT

Tt_LOWT

SMBC

SMBD

SMBC

SMBD

P

S

t_HD(DATA)

T

Tt_SU(DATA)

Start and Stop Condition

Wait and Hold Condition

t_SU(START)

T

Tt_TIMEOUT

SMBC

SMBD

SMBC

SMBD

S

Repeated Start Condition

Timeout Condition

Figure 4. SMBus Timing Diagram

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6.35 Typical Characteristics

0.15

0.10

±8.

ꢀ8.

Max CC Offset Error

Min CC Offset Error

ꢁ8.

0.05

ꢂ8.

0.00

.8.

±ꢂ8.

±ꢁ8.

±ꢀ8.

±±8.

œ0.05

œ0.10

œ0.15

Max ADC Offset Error

Min ADC Offset Error

0

20

40

60

80

100

120

œ40

œ20

.

ꢂ.

ꢁ.

ꢀ.

±.

1..

1ꢂ.

±ꢁ.

±ꢂ.

Temperature (°C)

C001

C..3

Figure 5. CC Offset Error vs. Temperature

Figure 6. ADC Offset Error vs. Temperature

1.24

1.23

1.22

1.21

1.20

264

262

260

258

256

254

252

250

0

20

40

60

80

100

0

20

40

60

80

100

œ40

œ20

œ40

œ20

Temperature (°C)

C006

C007

Figure 7. Reference Voltage vs. Temperature

Figure 8. Low-Frequency Oscillator vs. Temperature

16.9

16.8

16.7

16.6

œ24.6

œ24.8

œ25.0

œ25.2

œ25.4

œ25.6

œ25.8

0

20

40

60

80

100

120

0

20

40

60

80

100

120

œ40

œ20

œ40

œ20

Temperature (°C)

C008

C009

Threshold setting is –25 mV.

Figure 9. High-Frequency Oscillator vs. Temperature

Figure 10. Overcurrent Discharge Protection Threshold vs.

Temperature

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Typical Characteristics (continued)

87.4

œ86.0

œ86.2

œ86.4

œ86.6

œ86.8

œ87.0

œ87.2

87.2

87.0

86.8

86.6

86.4

86.2

0

20

40

60

80

100

120

0

20

40

60

80

100

120

œ40

œ20

œ40

œ20

Temperature (°C)

C010

C011

Threshold setting is 88.85 mV.

Threshold setting is –88.85 mV.

Figure 11. Short Circuit Charge Protection Threshold vs.

Temperature

Figure 12. Short Circuit Discharge 1 Protection Threshold

vs. Temperature

11.00

10.95

10.90

10.85

10.80

10.75

10.70

œ172.9

œ173.0

œ173.1

œ173.2

œ173.3

œ173.4

œ173.5

œ173.6

0

20

40

60

80

100

120

0

20

40

60

80

100

120

œ40

œ20

œ40

œ20

Temperature (°C)

C012

C013

Threshold setting is –177.7 mV.

Threshold setting is 11 ms.

Figure 14. Overcurrent Delay Time vs. Temperature

Figure 13. Short Circuit Discharge 2 Protection Threshold

vs. Temperature

452

450

448

446

444

442

440

438

436

434

432

480

460

440

420

400

0

20

40

60

80

100

120

0

20

40

60

80

100

120

œ40

œ20

œ40

œ20

Temperature (°C)

C014

C015

Threshold setting is 465 µs.

Threshold setting is 465 µs (including internal delay).

Figure 15. Short Circuit Charge Current Delay Time vs.

Temperature

Figure 16. Short Circuit Discharge 1 Delay Time vs.

Temperature

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Typical Characteristics (continued)

2.4984

2.49835

2.4983

2.49825

2.4982

2.49815

2.4981

2.49805

2.498

3.49825

3.4982

3.49815

3.4981

3.49805

3.498

0

20

40

60

80

100

120

0

20

40

60

80

100

120

œ40

œ20

œ40

œ20

Temperature (°C)

C016

C017

This is the V_CELLaverage for single cell.

Figure 17. V_CELLMeasurement at 2.5-V vs. Temperature

Figure 18. V_CELLMeasurement at 3.5-V vs. Temperature

4.24805

99.25

4.248

4.24795

4.2479

99.20

99.15

99.10

99.05

99.00

4.24785

4.2478

0

20

40

60

80

100

120

0

20

40

60

80

100

120

œ40

œ20

œ40

œ20

Temperature (°C)

C018

C019

This is the V_CELLaverage for single cell.

I_SET= 100 mA

Figure 19. V_CELLMeasurement at 4.25-V vs. Temperature

Figure 20. I Measured vs. Temperature

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7 Detailed Description

7.1 Overview

The bq4050 device, incorporating Compensated End-of-Discharge Voltage (CEDV) technology, provides cell

balancing while charging or at rest. This fully integrated, single-chip, pack-based solution, including a diagnostic

lifetime data monitor and black box recorder, provides a rich array of features for gas gauging, protection, and

authentication for 1-series, 2-series, 3-series, and 4-series cell Li-Ion and Li-Polymer battery packs.

7.2 Functional Block Diagram

Cell, Stack,

Pack

Voltage

High Side

N-CH FET

Drive

Cell

Balancing

Cell Detach

Detection

Power Mode

Control

P-CH

FET Drive

Zero Volt

Charge

Control

PTCEN

PTC

Wake

Comparator

Power On

Reset

PTC

Overtemp

Short Circuit

Comparator

FUSE

Control

FUSE

SRP

SRN

BTP_INT

Over

Current

Comparator

High

Voltage

I/O

Voltage

Reference2

PRES or SHUTDN

DISP

Random

Number

Generator

Watchdog

Timer

NTC Bias

TS1

TS2

TS3

TS4

LEDCNTLC

LEDCNTLB

LEDCNTLA

Internal

Temp

Sensor

LED Display

Drive I/O

Voltage

Reference1

ADC MUX

AFE Control

Low

Frequency

Oscillator

SBS High

Voltage

Translation

SMBD

SMBC

ADC/CC

FRONTEND

1.8V LDO

Regulator

AFE COM

Engine

High

Frequency

Oscillator

Low Voltage

I/O

I/O &

Interrupt

Controller

ADC/CC

Digital Filter

Timers&

PWM

AFE COM

Engine

SBS COM

Engine

Data (8bit)

DMAddr (16bit)

bqBMP

CPU

PMInstr

(8bit)

PMAddr

(16bit)

Program

Flash

EEPROM

Data Flash

EEPROM

Data

SRAM

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7.3 Feature Description

7.3.1 Primary (1st Level) Safety Features

The bq4050 gas gauge supports a wide range of battery and system protection features that can easily be

configured. See the bq4050 Technical Reference Manual (SLUUAQ3) for detailed descriptions of each protection

function.

The primary safety features include:

•

Cell Overvoltage Protection

Cell Undervoltage Protection

Overcurrent in Charge Protection

Overcurrent in Discharge Protection

Overload in Discharge Protection

Short Circuit in Charge Protection

Short Circuit in Discharge Protection

Overtemperature in Charge Protection

Overtemperature in Discharge Protection

Undertemperature in Charge Protection

Undertemperature in Discharge Protection

Overtemperature FET protection

Precharge Timeout Protection

Host Watchdog Timeout Protection

Overcharge Protection

Overcharging Voltage Protection

Overcharging Current Protection

Over Precharge Current Protection

7.3.2 Secondary (2nd Level) Safety Features

The secondary safety features of the bq4050 gas gauge can be used to indicate more serious faults via the

FUSE pin. This pin can be used to blow an in-line fuse to permanently disable the battery pack from charging or

discharging. See the bq4050 Technical Reference Manual (SLUUAQ3) for detailed descriptions of each

protection function.

The secondary safety features provide protection against:

•

Safety Overvoltage Permanent Failure

Safety Undervoltage Permanent Failure

Safety Overtemperature Permanent Failure

Safety FET Overtemperature Permanent Failure

Fuse Failure Permanent Failure

PTC Permanent Failure

Voltage Imbalance at Rest (VIMR) Permanent Failure

Voltage Imbalance Active (VIMA) Permanent Failure

Charge FET Permanent Failure

Discharge FET Permanent Failure

AFE Register Permanent Failure

AFE Communication Permanent Failure

Second Level Protector Permanent Failure

Instruction Flash Checksum Permanent Failure

Open Cell Connection Permanent Failure

Data Flash Permanent Failure

Open Thermistor Permanent Failure

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Feature Description (continued)

7.3.3 Charge Control Features

The bq4050 gas gauge charge control features include:

•

Supports JEITA temperature ranges. Reports charging voltage and charging current according to the active

temperature range

Handles more complex charging profiles. Allows for splitting the standard temperature range into two

subranges and allows for varying the charging current according to the cell voltage

Reports the appropriate charging current needed for constant current charging and the appropriate charging

voltage needed for constant voltage charging to a smart charger using SMBus broadcasts

Reduces the charge difference of the battery cells in fully charged state of the battery pack gradually using a

voltage-based cell balancing algorithm during charging. A voltage threshold can be set up for cell balancing to

be active. This prevents fully charged cells from overcharging and causing excessive degradation and also

increases the usable pack energy by preventing premature charge termination.

•

Supports precharging/0-volt charging

Supports charge inhibit and charge suspend if the battery pack temperature is out of temperature range

Reports charging fault and also indicates charge status via charge and discharge alarms

7.3.4 Gas Gauging

The bq4050 gas gauge uses the Compensated End-of-Discharge Voltage (CEDV) algorithm to measure and

calculate the available capacity in battery cells. The bq4050 device accumulates a measure of charge and

discharge currents, estimates self-discharge of the battery, and adjusts the self-discharge estimation based on

temperature. See the bq4050 Technical Reference Manual (SLUUAQ3) for further details.

7.3.5 Configuration

7.3.5.1 Oscillator Function

The bq4050 gas gauge fully integrates the system oscillators and does not require any external components to

support this feature.

7.3.5.2 System Present Operation

The bq4050 gas gauge checks the PRES pin periodically (1 s). If PRES input is pulled to ground by the external

system, the bq4050 device detects this as system present.

7.3.5.3 Emergency Shutdown

For battery maintenance, the emergency shutdown feature enables a push button action connecting the

SHUTDN pin to shut down an embedded battery pack system before removing the battery. A high-to-low

transition of the SHUTDN pin signals the bq4050 gas gauge to turn off the CHG and DSG FETs, disconnecting

the power from the system to safely remove the battery pack. The CHG and DSG FETs can be turned on again

by another high-to-low transition detected by the SHUTDN pin or when a data flash configurable timeout is

reached.

7.3.5.4 1-Series, 2-Series, 3-Series, or 4-Series Cell Configuration

In a 1-series cell configuration, VC4 is shorted to VC, VC2, and VC1. In a 2-series cell configuration, VC4 is

shorted to VC3 and VC2. In a 3-series cell configuration, VC4 is shorted to VC3.

7.3.5.5 Cell Balancing

The device reduces the charge difference of the battery cells in a fully charged state of the battery pack by

gradually using a voltage-based cell balancing algorithm during charging. A voltage threshold can be set up for

cell balancing to be active. This prevents fully charged cells from overcharging and causing excessive

degradation, and increases the usable pack energy by preventing premature charge termination.

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Feature Description (continued)

7.3.6 Battery Parameter Measurements

7.3.6.1 Charge and Discharge Counting

The bq4050 gas gauge uses an integrating delta-sigma analog-to-digital converter (ADC) for current

measurement, and a second delta-sigma ADC for individual cell and battery voltage and temperature

measurement.

The integrating delta-sigma ADC measures the charge/discharge flow of the battery by measuring the voltage

drop across a small-value sense resistor between the SRP and SRN terminals. The integrating ADC measures

bipolar signals from –0.1 V to 0.1 V. The bq4050 gauge detects charge activity when V_SR= V_(SRP)– V_(SRN)is

positive, and discharge activity when V_SR= V_(SRP)– V_(SRN)is negative. The bq4050 gas gauge continuously

integrates the signal over time, using an internal counter. The fundamental rate of the counter is 0.26 nVh.

7.3.7 Battery Trip Point (BTP)

Required for WIN8 OS, the battery trip point (BTP) feature indicates when the RSOC of a battery pack has

depleted to a certain value set in a DF register. This feature enables a host to program two capacity-based

thresholds that govern the triggering of a BTP interrupt on the BTP_INT pin and the setting or clearing of the

OperationStatus[BTP_INT] on the basis of RemainingCapacity().

An internal weak pullup is applied when the BTP feature is active. Depending on the system design, an external

pullup may be required to put on the BTP_INT pin. See Electrical Characteristics: PRES, BTP_INT, DISP for

details.

7.3.8 Lifetime Data Logging Features

The bq4050 gas gauge offers lifetime data logging for several critical battery parameters. The following

parameters are updated every 10 hours if a difference is detected between values in RAM and data flash:

•

Maximum and Minimum Cell Voltages

Maximum Delta Cell Voltage

Maximum Charge Current

Maximum Discharge Current

Maximum Average Discharge Current

Maximum Average Discharge Power

Maximum and Minimum Cell Temperature

Maximum Delta Cell Temperature

Maximum and Minimum Internal Sensor Temperature

Maximum FET Temperature

Number of Safety Events Occurrences and the Last Cycle of the Occurrence

Number of Valid Charge Termination and the Last Cycle of the Valid Charge Termination

Number of Shutdown Events

Cell Balancing Time for Each Cell

(This data is updated every 2 hours if a difference is detected.)

Total FW Runtime and Time Spent in Each Temperature Range

(This data is updated every 2 hours if a difference is detected.)

•

7.3.9 Authentication

The bq4050 gas gauge supports authentication by the host using SHA-1.

7.3.10 LED Display

The bq4050 gas gauge can drive a 3-, 4-, or 5- segment LED display for remaining capacity indication and/or a

permanent fail (PF) error code indication.

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Feature Description (continued)

7.3.11 Voltage

The bq4050 gas gauge updates the individual series cell voltages at 0.25-s intervals. The internal ADC of the

bq4050 device measures the voltage, and scales and calibrates it appropriately. This data is also used to

calculate the impedance of the cell for the CEDV gas gauging.

7.3.12 Current

The bq4050 gas gauge uses the SRP and SRN inputs to measure and calculate the battery charge and

discharge current using a 1-mΩ to 3-mΩ typ. sense resistor.

7.3.13 Temperature

The bq4050 gas gauge has an internal temperature sensor and inputs for four external temperature sensors. All

five temperature sensor options can be individually enabled and configured for cell or FET temperature usage.

Two configurable thermistor models are provided to enable monitoring of the cell temperature in addition to the

FET temperature, which use a different thermistor profile.

7.3.14 Communications

The bq4050 gas gauge uses SMBus v1.1 with MASTER mode and packet error checking (PEC) options per the

SBS specification.

7.3.14.1 SMBus On and Off State

The bq4050 gas gauge detects an SMBus off state when SMBC and SMBD are low for two or more seconds.

Clearing this state requires that either SMBC or SMBD transition high. The communication bus will resume

activity within 1 ms.

7.3.14.2 SBS Commands

See the bq4050 Technical Reference Manual (SLUUAQ3) for further details.

7.4 Device Functional Modes

The bq4050 gas gauge supports three power modes to reduce power consumption:

•

In NORMAL mode, the bq4050 gauge performs measurements, calculations, protection decisions, and data

updates in 250-ms intervals. Between these intervals, the bq4050 gauge is in a reduced power stage.

•

In SLEEP mode, the bq4050 gauge performs measurements, calculations, protection decisions, and data

updates in adjustable time intervals. Between these intervals, the bq4050 gauge is in a reduced power stage.

The bq4050 gauge has a wake function that enables exit from SLEEP mode when current flow or failure is

detected.

•

In SHUTDOWN mode, the bq4050 gauge is completely disabled.

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8 Applications and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The bq4050 gas gauge has primary protection support to be used with a 1-series to 4-series Li-Ion/Li Polymer

battery pack. To implement and design a comprehensive set of parameters for a specific battery pack, users

need the Battery Management Studio (bqStudio) graphical user-interface tool installed on a PC during

development. The firmware installed on the bqStudio tool has default values for this product, which are

summarized in the bq4050 Technical Reference Manual (SLUUAQ3). Using the bqStudio tool, these default

values can be changed to cater to specific application requirements during development once the system

parameters, such as fault trigger thresholds for protection, enable/disable of certain features for operation,

configuration of cells, chemistry that best matches the cell used, and more are known. This data is referred to as

the "golden image."

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8.2 Typical Applications

4P

9

EP

1

4

6

3

5

2

1

2

3

4

1

5

1

33

32

31

30

29

28

27

26

25

PWPD

BAT

9

VSS

10

TS1

CHG

PCHG

NC

11

TS2

12

TS3

13

1

TS4

DSG

PACK

VCC

1

5

14

NC

15

BTP_INT

4

1

16

PRES or SHUTDN

1

FUSE

3

2

1

3

2

MM3ZxxVyC

2

1

SMBD

SMBC

GND S2IDE

GND SIDE

SMBC

SMBD

1

7

6

1

CHGND

1

2

1

GND SIDE

2

GND SIDE

Figure 21. Application Schematic

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Typical Applications (continued)

8.2.1 Design Requirements

Table 1 shows the default settings for the main parameters. Use the bqStudio tool to update the settings to meet

the specific application or battery pack configuration requirements.

The device should be calibrated before any gauging test. Follow the information in the bqStudio Calibration

page to calibrate the device, and use the bqStudio Chemistry page to update the match chemistry profile to the

device.

Table 1. Design Parameters

DESIGN PARAMETER

Cell Configuration

EXAMPLE

3s1p (3-series with 1 Parallel)⁽¹⁾

Design Capacity

4400 mAh

Device Chemistry

1210 (LiCoO2/graphitized carbon)

Cell Overvoltage at Standard Temperature

Cell Undervoltage

4300 mV

2500 mV

Shutdown Voltage

2300 mV

Overcurrent in CHARGE Mode

Overcurrent in DISCHARGE Mode

Short Circuit in CHARGE Mode

Short Circuit in DISCHARGE Mode

Safety Overvoltage

6000 mA

–6000 mA

0.1 V/Rsense across SRP, SRN

4500 mV

Cell Balancing

Disabled

Internal and External Temperature Sensor

Undertemperature Charging

Undertemperature Discharging

BROADCAST Mode

External Temperature Sensors are used.

0°C

Disabled

Battery Trip Point (BTP) with active high interrupt

(1) When using the device the first time, if the a 1-s or 2-s battery pack is used, then a charger or power supply should be connected to the

PACK+ terminal to prevent device shutdown. Then update the cell configuration (see the bq4050 Technical Reference Manual

(SLUUAQ3) for details) before removing the charger connection.

8.2.2 Detailed Design Procedure

8.2.2.1 High-Current Path

The high-current path begins at the PACK+ terminal of the battery pack. As charge current travels through the

pack, it finds its way through protection FETs, a chemical fuse, the lithium-ion cells and cell connections, and the

sense resistor, and then returns to the PACK– terminal (see Figure 22). In addition, some components are

placed across the PACK+ and PACK– terminals to reduce effects from electrostatic discharge.

8.2.2.1.1 Protection FETs

Select the N-CH charge and discharge FETs for a given application. Most portable battery applications are a

good match for the CSD17308Q3. The TI CSD17308Q3 is a 47A, 30-V device with Rds(on) of 8.2 mΩ when the

gate drive voltage is 8 V.

If a precharge FET is used, R1 is calculated to limit the precharge current to the desired rate. Be sure to account

for the power dissipation of the series resistor. The precharge current is limited to (V_CHARGER– V_BAT)/R1 and

maximum power dissipation is (V_charger– V_bat)²/R1.

The gates of all protection FETs are pulled to the source with a high-value resistor between the gate and source

to ensure they are turned off if the gate drive is open.

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Capacitors C1 and C2 help protect the FETs during an ESD event. Using two devices ensures normal operation

if one becomes shorted. To have good ESD protection, the copper trace inductance of the capacitor leads must

be designed to be as short and wide as possible. Ensure that the voltage ratings of C1 and C2 are adequate to

hold off the applied voltage if one of the capacitors becomes shorted.

C1

0.1 ꢀF

C2

0.1 ꢀF

R1

300

Q1

FDN358P

Q4

2N7002K

Q3

Si7114DN

Q2

Si7114DN

R3

10M

R2

10M

R5

10M

R4

10K

R7

5.1K

R8

5.1K

R9

100

R10

5.1K

Figure 22. bq4050 Protection FETs

8.2.2.1.2 Chemical Fuse

The chemical fuse (Dexerials, Uchihashi, and so on) is ignited under command from either the bq294700

secondary voltage protection IC or from the FUSE pin of the gas gauge. Either of these events applies a positive

voltage to the gate of Q5, shown in Figure 23, which then sinks current from the third terminal of the fuse,

causing it to ignite and open permanently.

It is important to carefully review the fuse specifications and match the required ignition current to that available

from the N-CH FET. Ensure that the proper voltage, current, and Rds(on) ratings are used for this device. The

fuse control circuit is discussed in detail in FUSE Circuitry.

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F1

DNP

4P

2

1

3

Q5

3

Si1406DH

C3

R6

0.1 ꢀF

51K

to 2^ndLevel Protector

to FUSE Pin

5.1K

R17

R16

5.1K

Figure 23. FUSE Circuit

8.2.2.1.3 Lithium-Ion Cell Connections

The important part to remember about the cell connections is that high current flows through the top and bottom

connections; therefore, the voltage sense leads at these points must be made with a Kelvin connection to avoid

any errors due to a drop in the high-current copper trace. The location marked 4P in Figure 24 indicates the

Kelvin connection of the most positive battery node. The connection marked 1N is equally important. The VC5

pin (a ground reference for cell voltage measurement), which is in the older generation devices, is not in the

bq4050 device. Therefore, the single-point connection at 1N to the low-current ground is needed to avoid an

undesired voltage drop through long traces while the gas gauge is measuring the bottom cell voltage.

Figure 24. Lithium-Ion Cell Connections

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8.2.2.1.4 Sense Resistor

As with the cell connections, the quality of the Kelvin connections at the sense resistor is critical. The sense

resistor must have a temperature coefficient no greater than 50 ppm in order to minimize current measurement

drift with temperature. Choose the value of the sense resistor to correspond to the available overcurrent and

short-circuit ranges of the bq4050 gauge. Select the smallest value possible to minimize the negative voltage

generated on the bq4050 V_SSnode(s) during a short circuit. This pin has an absolute minimum of –0.3 V. Parallel

resistors can be used as long as good Kelvin sensing is ensured. The device is designed to support a 1-mΩ to 3-

mΩ sense resistor.

The ground scheme of bq4050 gauge is different from the older generation devices. In previous devices, the

device ground (or low current ground) is connected to the SRN side of the Rsense resistor pad. The bq4050

gauge, however, it connects the low-current ground on the SRP side of the Rsense resistor pad close to the

battery 1N terminal (see Lithium-Ion Cell Connections). This is because the bq4050 gauge has one less VC pin

(a ground reference pin VC5) compared to the previous devices. The pin was removed and was internally

combined to SRP.

R19

0.001

50 ppm

Figure 25. Sense Resistor

8.2.2.1.5 ESD Mitigation

A pair of series 0.1-μF ceramic capacitors is placed across the PACK+ and PACK– terminals to help in the

mitigation of external electrostatic discharges. The two devices in series ensure continued operation of the pack

if one of the capacitors becomes shorted.

Optionally, a tranzorb such as the SMBJ2A can be placed across the terminals to further improve ESD immunity.

8.2.2.2 Gas Gauge Circuit

The gas gauge circuit includes the bq4050 gauge and its peripheral components. These components are divided

into the following groups: Differential Low-Pass Filter, PBI, system present, SMBus Communication, FUSE

circuit, and LED.

8.2.2.2.1 Coulomb-Counting Interface

The bq4050 gauge uses an integrating delta-sigma ADC for current measurements. Add a 100-Ω resistor from

the sense resistor to the SRP and SRN inputs of the device. Place a 0.1-µF (C18) filter capacitor across the SRP

and SRN inputs. Optional 0.1-µF filter capacitors (C19 and C20) can be added for additional noise filtering if

required for a circuit.

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ZHCSEW9B –MARCH 2016–REVISED OCTOBER 2017

C18

0.1 µF

C19

DNP

R30

100

R31

100

C20

DNP

R19

0.001

50 ppm

Figure 26. Differential Filter

8.2.2.2.2 Power Supply Decoupling and PBI

The bq4050 gauge has an internal LDO that is internally compensated and does not require an external

decoupling capacitor.

The PBI pin is used as a power supply backup input pin providing power during brief transient power outages. A

standard 2.2-µF ceramic capacitor is connected from the PBI pin to ground as shown in Figure 27.

24

23

22

21

20

19

18

17

1

2

3

4

5

6

7

8

PBI

PTCEN

PTC

VC4

VC3

VC2

VC1

C13

LEDCNTL

3

2.2 μF

LEDCNTL2

LEDCNTL1

SMBC

SRN

NC

SMBD

DISP

SRP

Figure 27. Power Supply Decoupling

8.2.2.2.3 System Present

The system present signal is used to inform the gas gauge whether the pack is installed into or removed from the

system. In the host system, this pin is grounded. The PRES pin of the bq4050 gauge is occasionally sampled to

test for system present. To save power, an internal pullup is provided by the gas gauge during a brief 4-μs

sampling pulse once per second. A resistor can be used to pull the signal low and the resistance must be 20 kΩ

or lower to ensure that the test pulse is lower than the VIL limit. The pullup current source is typically 10 µA to

20 µA.

33

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ZHCSEW9B –MARCH 2016–REVISED OCTOBER 2017

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VIL

<20 K

GND

Figure 28. System Present Pull-Down Resistor

Because the system present signal is part of the pack connector interface to the outside world, it must be

protected from external electrostatic discharge events. An integrated ESD protection on the PRES device pin

reduces the external protection requirement to just R29 for an 8-kV ESD contact rating. However, if it is possible

that the system present signal may short to PACK+, then R28 and D4 must be included for high-voltage

protection.

34

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D5

D6

24

23

PTCEN

PTC

22

21

20

LED3

LED4

LEDCNTL3

LEDCNTL2

D9

LEDCNTL1

SMBC

LED5

D7

D8

19

18

17

SMBD

LED1

LED2

DISP

R24

200

R25

R27

100

4

3

2

R26

S2

100

SMBD

SMBC

VSS

A

B

A¹

B¹

1

J2

J3

R29

1 k

R28

200

3

2

Sys Pres

D2

D3

D4

1

2

1

PACK+

MM3Z5V6C

PACKœ

J4

Figure 29. System Present ESD and Short Protection

8.2.2.2.4 SMBus Communication

The SMBus clock and data pins have integrated high-voltage ESD protection circuits; however, adding a Zener

diode (D2 and D3) and series resistor (R24 and R26) provides more robust ESD performance.

The SMBus clock and data lines have internal pulldown. When the gas gauge senses that both lines are low

(such as during removal of the pack), the device performs auto-offset calibration and then goes into SLEEP

mode to conserve power.

35

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ZHCSEW9B –MARCH 2016–REVISED OCTOBER 2017

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R24

R26

200

R25

R27

100

4

3

2

SMBD

SMBC

1

VSS

J2

J3

R28

200

R29

1 k

3

Sys Pres

2

D2

D3

D4

1

PACK+

2

MM3Z5V6C

1

MM3Z5V6C

PACKœ

J4

Figure 30. ESD Protection for SMB Communication

8.2.2.2.5 FUSE Circuitry

The FUSE pin of the bq4050 gauge is designed to ignite the chemical fuse if one of the various safety criteria is

violated. The FUSE pin also monitors the state of the secondary-voltage protection IC. Q5 ignites the chemical

fuse when its gate is high. The 7-V output of the bq294700 is divided by R16 and R6, which provides adequate

gate drive for Q5 while guarding against excessive back current into the bq294700 if the FUSE signal is high.

Using C3 is generally a good practice, especially for RFI immunity. C3 may be removed, if desired, because the

chemical fuse is a comparatively slow device and is not affected by any submicrosecond glitches that come from

the FUSE output during the cell connection process.

F1

DNP

4P

2

1

3

Q5

3

Si1406DH

C3

R6

0.1 ꢀF

51K

to 2^ndLevel Protector

to FUSE Pin

R17

5.1K

R16

5.1K

Figure 31. FUSE Circuit

When the bq4050 gauge is commanded to ignite the chemical fuse, the FUSE pin activates to give a typical 8-V

output. The new design makes it possible to use a higher Vgs FET for Q5. This improves the robustness of the

system, as well as widens the choices for Q5.

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8.2.2.3 Secondary-Current Protection

The bq4050 gauge provides secondary overcurrent and short-circuit protection, cell balancing, cell voltage

multiplexing, and voltage translation. The following discussion examines cell and battery inputs, pack and FET

control, temperature output, and cell balancing.

8.2.2.3.1 Cell and Battery Inputs

Each cell input is conditioned with a simple RC filter, which provides ESD protection during cell connect and acts

to filter unwanted voltage transients. The resistor value allows some trade-off for cell balancing versus safety

protection.

The integrated cell balancing FETs allow the AFE to bypass cell current around a given cell or numerous cells,

effectively balancing the entire battery stack. External series resistors placed between the cell connections and

the VCx I/O pins set the balancing current magnitude. The internal FETs provide a 200-Ω resistance (2 V < VDS

< 4 V). Series input resistors between 100 Ω and 1 kΩ are recommended for effective cell balancing.

The BAT input uses a diode (D1) to isolate and decouple it from the cells in the event of a transient dip in voltage

caused by a short-circuit event.

Also, as described in High-Current Path, the top and bottom nodes of the cells must be sensed at the battery

connections with a Kelvin connection to prevent voltage sensing errors caused by a drop in the high-current PCB

copper.

D1 BAT54HT1

1

PBI

2

VC4

3

VC3

C14

4

VC2

C15

0.1 ꢀF

5

0.1 ꢀF

VC1

SRN

NC

C16

C13

6

7

8

C17

0.1 ꢀF

2.2 ꢀF

J5

J1

R20 100

R21

1

SRP

0.1 ꢀF

4P

3P

100

R23

2

3

1

2

R22

100

2P

1P

1N

100

Figure 32. Cell and BAT Inputs

8.2.2.3.2 External Cell Balancing

Internal cell balancing can only support up to 10 mA. External cell balancing is provided as another option for

faster cell balancing. For details, refer to the application note, Fast Cell Balancing Using External MOSFET

(SLUA420).

37

bq4050

ZHCSEW9B –MARCH 2016–REVISED OCTOBER 2017

www.ti.com.cn

8.2.2.3.3 PACK and FET Control

The PACK and V_CCinputs provide power to the bq4050 gauge from the charger. The PACK input also provides a

method to measure and detect the presence of a charger. The PACK input uses a 100-Ω resistor; whereas, the

V_CCinput uses a diode to guard against input transients and prevents misoperation of the date driver during

short-circuit events.

C1 0.1 μF C2 0.1 μF

R1

300

Q1

FDN358P

Q4

2N7002K

Q3

R2

10M

Q2

Si7114 DN

R3

10M

Si7114DN

R5

10M

R4

10K

R7

5.1K

R8

R10

5.1K

R9

R12

10K

5.1K

100

Figure 33. bq4050 PACK and FET Control

The N-CH charge and discharge FETs are controlled with 5.1-kΩ series gate resistors, which provide a switching

time constant of a few microseconds. The 10-MΩ resistors ensure that the FETs are off in the event of an open

connection to the FET drivers. Q4 is provided to protect the discharge FET (Q3) in the event of a reverse-

connected charger. Without Q4, Q3 can be driven into its linear region and suffer severe damage if the PACK+

input becomes slightly negative.

Q4 turns on in that case to protect Q3 by shorting its gate to source. To use the simple ground gate circuit, the

FET must have a low gate turn-on threshold. If it is desired to use a more standard device, such as the 2N7002

as the reference schematic, the gate should be biased up to 3.3 V with a high-value resistor. The bq4050 device

has the capability to provide a current-limited charging path typically used for low battery voltage or low

temperature charging. The bq4050 device uses an external P-channel, precharge FET controlled by PCHG.

8.2.2.3.4 Temperature Output

For the bq4050 device, TS1, TS2, TS3, and TS4 provide thermistor drive-under program control. Each pin can

be enabled with an integrated 18-kΩ (typical) linearization pullup resistor to support the use of a 10-kΩ at 25°C

(103) NTC external thermistor, such as a Mitsubishi BN35-3H103. The reference design includes four 10-kΩ

thermistors: RT1, RT2, RT3, and RT4. The bq4050 device supports up to four external thermistors. Connect

unused thermistor pins to V_SS

.

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ZHCSEW9B –MARCH 2016–REVISED OCTOBER 2017

RT2

10 K

RT3

10 K

RT4

10 K

RT5

10 K

Figure 34. Thermistor Drive

8.2.2.3.5 LEDs

Three LED control outputs provide constant current sinks for the driving external LEDs. These outputs are

configured to provide voltage and control for up to 5 LEDs. No external bias voltage is required. Unused

LEDCNTL pins can remain open or they can be connected to V_SS. The DISP pin should be connected to V_SS, if

the LED feature is not used.

D5

D6

24

23

PTCEN

PTC

22

21

LED3

LED4

LEDCNTL3

LEDCNTL2

D9

20

LEDCNTL1

LED5

D7

D8

19

18

17

SMBC

SMBD

LED1

LED2

DISP

Figure 35. LEDs

8.2.2.3.6 Safety PTC Thermistor

The bq4050 device provides support for a safety PTC thermistor. The PTC thermistor is connected between PTC

and PTCEN, and PTCEN is connected to BAT. It can be placed close to the CHG/DSG FETs to monitor the

temperature. A PTC fault is one of the permanent failure modes. It can only be cleared by a POR.

To disable, connect PTC and PTCEN to V_SS

.

39

bq4050

ZHCSEW9B –MARCH 2016–REVISED OCTOBER 2017

www.ti.com.cn

C12

0.1 ꢀF

24

RT1

10K

PTCEN

23

PTC

BAT

22

LEDCNTL3

21

LEDCNTL2

20

LEDCNTL1

19

SMBC

18

SMBD

17

DISP

Figure 36. PTC Thermistor

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ZHCSEW9B –MARCH 2016–REVISED OCTOBER 2017

8.2.3 Application Curves

œ24.6

œ24.8

œ25.0

œ25.2

œ25.4

œ25.6

œ25.8

87.4

87.2

87.0

86.8

86.6

86.4

86.2

0

20

40

60

80

100

120

0

20

40

60

80

100

120

œ40

œ20

œ40

œ20

Temperature (°C)

C009

C010

Threshold setting is –25 mV.

Threshold setting is 88.85 mV.

Figure 37. Overcurrent Discharge Protection Threshold Vs.

Temperature

Figure 38. Short Circuit Charge Protection Threshold Vs.

Temperature

œ86.0

œ86.2

œ86.4

œ86.6

œ86.8

œ87.0

œ87.2

œ172.9

œ173.0

œ173.1

œ173.2

œ173.3

œ173.4

œ173.5

œ173.6

0

20

40

60

80

100

120

œ40

œ20

0

20

40

60

80

100

120

œ40

œ20

Temperature (°C)

C012

C011

Threshold setting is –177.7 mV.

Threshold setting is –88.85 mV.

Figure 40. Short Circuit Discharge 2 Protection Threshold

Vs. Temperature

Figure 39. Short Circuit Discharge 1 Protection Threshold

Vs. Temperature

11.00

10.95

10.90

10.85

10.80

10.75

10.70

452

450

448

446

444

442

440

438

436

434

432

0

20

40

60

80

100

120

0

20

40

60

80

100

120

œ40

œ20

œ40

œ20

Temperature (°C)

C013

C014

Threshold setting is 11 ms.

Threshold setting is 465 µs.

Figure 41. Overcurrent Delay Time Vs. Temperature

Figure 42. Short Circuit Charge Current Delay Time Vs.

Temperature

41

bq4050

ZHCSEW9B –MARCH 2016–REVISED OCTOBER 2017

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9 Power Supply Recommendations

The device manages its supply voltage dynamically according to the operation conditions. Normally, the BAT

input is the primary power source to the device. The BAT pin should be connected to the positive termination of

the battery stack. The input voltage for the BAT pin ranges from 2.2 V to 26 V.

The VCC pin is the secondary power input, which activates when the BAT voltage falls below minimum V_CC. This

allows the device to source power from a charger (if present) connected to the PACK pin. The VCC pin should

be connected to the common drain of the CHG and DSG FETs. The charger input should be connected to the

PACK pin.

10 Layout

10.1 Layout Guidelines

A battery fuel gauge circuit board is a challenging environment due to the fundamental incompatibility of high-

current traces and ultra-low current semiconductor devices. The best way to protect against unwanted trace-to-

trace coupling is with a component placement, such as that shown in Figure 43, where the high-current section is

on the opposite side of the board from the electronic devices. Clearly, this is not possible in many situations due

to mechanical constraints. Still, every attempt should be made to route high-current traces away from signal

traces, which enter the bq4050 gauge directly. IC references and registers can be disturbed and in rare cases

damaged due to magnetic and capacitive coupling from the high-current path.

NOTE

During surge current and ESD events, the high-current traces appear inductive and can

couple unwanted noise into sensitive nodes of the gas gauge electronics, as illustrated in

Figure 44.

BAT +

C2

C3

Q1

Q2

Low Level Circuits

F1

C1

BAT –

J1

R1

Figure 43. Separating High- and Low-Current Sections Provides an Advantage in Noise Immunity

42

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ZHCSEW9B –MARCH 2016–REVISED OCTOBER 2017

Layout Guidelines (continued)

PACK+

COMM

BMU

PACK–

Figure 44. Avoid Close Spacing Between High-Current and Low-Level Signal Lines

Kelvin voltage sensing is important to accurately measure current and top and bottom cell voltages. Place all

filter components as close as possible to the device. Route the traces from the sense resistor in parallel to the

filter circuit. Adding a ground plane around the filter network can add additional noise immunity. Figure 45 and

Figure 46 demonstrate correct kelvin current sensing.

Current Direction

R

SNS

Current Sensing Direction

To SRP – SRN pin or HSRP – HSRN pin

Figure 45. Sensing Resistor PCB Layout

Sense Resistor

Ground Shield

Filter Circuit

Figure 46. Sense Resistor, Ground Shield, and Filter Circuit Layout

43

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ZHCSEW9B –MARCH 2016–REVISED OCTOBER 2017

www.ti.com.cn

Layout Guidelines (continued)

10.1.1 Protector FET Bypass and Pack Terminal Bypass Capacitors

Use wide copper traces to lower the inductance of the bypass capacitor circuit. In Figure 47, an example layout

demonstrates this technique.

BAT+

C2

C3

C2

C3

Q1

Q2

Pack+

F1

Low Level Circuits

F1

BATœ

C1

Packœ

C1

J1

R1

Figure 47. Use Wide Copper Traces to Lower the Inductance of Bypass Capacitors C1, C2, and C3

10.1.2 ESD Spark Gap

Protect the SMBus clock, data, and other communication lines from ESD with a spark gap at the connector. The

pattern in Figure 48 is recommended, with 0.2-mm spacing between the points.

Figure 48. Recommended Spark-Gap Pattern Helps Protect Communication Lines from ESD

10.2 Layout Example

THERMISTORS

CHARGE

AND

DISCHARGE

2^NDLEVEL

PATH

PROTECTOR

LEDS

CURRENT

FILTER

SENSE

RESISTOR

Figure 49. Top Layer

44

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ZHCSEW9B –MARCH 2016–REVISED OCTOBER 2017

Layout Example (continued)

Figure 50. Internal Layer 1

Figure 51. Internal Layer 2

CHARGE

AND

DISCHARGE

PATH

FILTER

COMPONENTS

Figure 52. Bottom Layer

45

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ZHCSEW9B –MARCH 2016–REVISED OCTOBER 2017

www.ti.com.cn

11 器件和文档支持

11.1 文档支持

11.1.1 相关文档

如需相关文档，请参阅《bq4050 技术参考手册》(SLUUAQ3)。

11.2 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

11.3 商标

E2E is a trademark of Texas Instruments.

Windows is a registered trademark of Microsoft.

All other trademarks are the property of their respective owners.

11.4 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

11.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据如有变更，恕不另行通知

和修订此文档。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航。

46

GENERIC PACKAGE VIEW

RSM 32

4 x 4, 0.4 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224982/A

www.ti.com

PACKAGE OUTLINE

RSM0032A

VQFN - 1 mm max height

S

C

A

L

E

3

.

0

PLASTIC QUAD FLATPACK - NO LEAD

B

4.1

3.9

A

0.5

0.3

PIN 1 INDEX AREA

4.1

3.9

0.25

0.15

DETAIL

OPTIONAL TERMINAL

TYPICAL

1 MAX

C

SEATING PLANE

0.08 C

0.05

0.00

2X 2.8

1.4 0.05

(0.2) TYP

4X (0.45)

28X 0.4

9

16

8

17

EXPOSED

THERMAL PAD

2X

SYMM

33

2.8

24

0.25

32X

1

SEE TERMINAL

DETAIL

0.15

0.1

C A B

25

32

PIN 1 ID

(OPTIONAL)

0.05

SYMM

0.5

0.3

32X

4219107/A 11/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RSM0032A

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

1.4)

SYMM

32

25

32X (0.6)

1

32X (0.2)

24

SYMM

33

(3.8)

28X (0.4)

(

0.2) VIA

17

8

(R0.05)

TYP

9

16

(3.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:20X

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219107/A 11/2017

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RSM0032A

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

1.3)

(R0.05) TYP

25

32

32X (0.6)

32X (0.2)

1

24

SYMM

33

(3.8)

28X (0.4)

METAL

TYP

17

8

16

9

SYMM

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

EXPOSED PAD 33:

86% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4219107/A 11/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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型号：	BQ4050
厂家：	TEXAS INSTRUMENTS
描述：	1 至 4 节串联 CEDV 电池电量监测计电池
文件：	总55页 (文件大小：2319K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BQ4050 [TI]

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