BTS711-L1 [ETC]
?5.0-34V. 4x200m?Limit(scr) 4A DSO-20-9? ; ? 5.0-34V 。 4x200米?极限( SCR) 4A DSO- 20-9 ?\n型号: | BTS711-L1 |
厂家: | ETC |
描述: | ?5.0-34V. 4x200m?Limit(scr) 4A DSO-20-9?
|
文件: | 总15页 (文件大小:196K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
®
PROFET BTS 711 L1
Smart Four Channel Highside Power Switch
Product Summary
Overvoltage Protection
Operating voltage
active channels:
On-state resistance RON
Nominal load current IL(NOM)
Features
Vbb(AZ)
43
5.0 ... 34
V
V
•
•
•
•
•
Overload protection
V
bb(on)
Current limitation
two parallel four parallel
one
200
1.9
4
Short-circuit protection
Thermal shutdown
Overvoltage protection
(including load dump)
100
2.8
4
50
4.4
4
mΩ
A
A
Current limitation
IL(SCr)
•
•
•
Fast demagnetization of inductive loads
Reverse battery protection
Undervoltage and overvoltage shutdown
with auto-restart and hysteresis
Open drain diagnostic output
1
)
•
• Open load detection in ON-state
•
•
•
CMOS compatible input
Loss of ground and loss of V protection
Electrostatic discharge (ESD) protection
bb
Application
•
µC compatible power switch with diagnostic feedback
for 12 V and 24 V DC grounded loads
All types of resistive, inductive and capacitive loads
Replaces electromechanical relays and discrete circuits
•
•
General Description
N channel vertical power FET with charge pump, ground referenced CMOS compatible input and diagnostic
feedback, monolithically integrated in Smart SIPMOS technology. Fully protected by embedded protection
functions.
Pin Definitions and Functions
Pin
1,10,
11,12,
15,16,
19,20
3
5
7
9
18
Symbol Function
Positive power supply voltage. Design the
Pin configuration (top view)
V
bb
wiring for the simultaneous max. short circuit
currents from channel 1 to 4 and also for low
thermal resistance
V
1 •
20 V
19 V
18 OUT1
17 OUT2
bb
bb
GND1/2 2
IN1 3
ST1/2 4
IN2 5
bb
IN1
IN2
Input 1 .. 4, activates channel 1 .. 4 in case of
logic high signal
IN3
IN4
16 V
bb
GND3/4 6
IN3 7
ST3/4 8
IN4 9
15 V
14 OUT3
13 OUT4
bb
OUT1
OUT2
OUT3
OUT4
ST1/2
Output 1 .. 4, protected high-side power output
of channel 1 .. 4. Design the wiring for the
max. short circuit current
17
14
13
4
12 V
bb
V
10
11 V
bb
bb
Diagnostic feedback 1/2 of channel 1 and
channel 2, open drain, low on failure
Diagnostic feedback 3/4 of channel 3 and
channel 4, open drain, low on failure
8
ST3/4
2
6
GND1/2 Ground 1/2 of chip 1 (channel 1 and channel 2)
GND3/4 Ground 3/4 of chip 2 (channel 3 and channel 4)
1)
With external current limit (e.g. resistor R =150 Ω) in GND connection, resistor in series with ST
GND
connection, reverse load current limited by connected load.
Semiconductor Group
1
06.96
BTS 711 L1
Block diagram
Four Channels; Open Load detection in on state;
+ V
bb
Le a d fra m e
18
Curre nt
lim it 1
G a te 1
p ro te c tio n
Vo lta g e
so urc e
Ove rvo lta g e
p ro te c tio n
Channel 1
V Logic
OUT1
Lim it fo r
unc la m p e d
ind . lo a d s 1
Le ve l shifte r
Re c tifie r 1
Vo lta g e
se nso r
Te m p e ra ture
se nso r 1
3
5
4
IN1
IN2
O p e n lo a d
Sho rt to Vb b
d e te c tio n 1
Cha rg e
p um p 1
Lo g ic
ESD
ST1/2
Cha rg e
p um p 2
G a te 2
p ro te c tio n
Curre nt
lim it 2
Channel 2
OUT2
17
Le ve l shifte r
Re c tifie r 2
Lim it fo r
unc la m p e d
ind . lo a d s 2
Load
2
GND1/2
Te m p e ra ture
se nso r 2
O p e n lo a d
Sho rt to Vb b
d e te c tio n 2
R
R
O1
O2
Signal GND
Chip 1
GND1/2
Chip 1
Load GND
+ V
bb
Le a d fra m e
Channel 3
14
OUT3
Logic and protection circuit of chip 2
(equivalent to chip 1)
7
9
8
IN3
IN4
ST3/4
Channel 4
OUT4
13
Load
6
GND3/4
PROFET
Chip 2
Le a d fra m e c o nne c te d to p in 1, 10, 11, 12, 15, 16, 19, 20
R
R
O3
GND3/4
O4
Signal GND
Chip 2
Load GND
T = 25°C unless otherwise specified
j
Maximum Ratings at
Parameter
Symbol
Values
Unit
Supply voltage (overvoltage protection see page 4)
Supply voltage for full short circuit protection
T
j,start =-40 ...+150°C
Vbb
Vbb
43
34
V
V
Semiconductor Group
2
BTS 711 L1
Maximum Ratings at Tj = 25°C unless otherwise specified
Parameter
Symbol
Values
Unit
Load current (Short-circuit current, see page 5)
IL
self-limited
60
A
V
4)
Load dump protection2) VLoadDump = UA + Vs, UA = 13.5 V VLoad dump
RI3) = 2 Ω, td = 200 ms; IN= low or high,
each channel loaded with RL = 7.1Ω,
Operating temperature range
Storage temperature range
Power dissipation (DC)5
(all channels active)
Tj
Tstg
-40 ...+150
-55 ...+150
°C
W
Ta = 25°C: Ptot
Ta = 85°C:
3.6
1.9
Inductive load switch-off energy dissipation, single pulse
Vbb =12V, Tj,start =150°C5),
150
320
800
mJ
IL = 1.9 A, ZL = 66mH, 0Ω
IL = 2.8 A, ZL = 66mH, 0Ω
IL = 4.4 A, ZL = 66mH, 0Ω
see diagrams on page 9 and page 10
one channel: EAS
two parallel channels:
four parallel channels:
Electrostatic discharge capability (ESD)
(Human Body Model)
VESD
1.0
kV
Input voltage (DC)
VIN
IIN
IST
-10 ... +16
±2.0
V
mA
Current through input pin (DC)
Current through status pin (DC)
see internal circuit diagram page 8
±5.0
Thermal resistance
junction - soldering point5),6)
each channel: Rthjs
16 K/W
junction - ambient5)
one channel active: Rthja
all channels active:
44
35
2)
Supply voltages higher than Vbb(AZ) require an external current limit for the GND and status pins, e.g. with a
150 Ω resistor in the GND connection and a 15 kΩ resistor in series with the status pin. A resistor for input
protection is integrated.
3)
4)
5)
R = internal resistance of the load dump test pulse generator
I
VLoad dump is setup without the DUT connected to the generator per ISO 7637-1 and DIN 40839
Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm2 (one layer, 70µm thick) copper area for V
connection. PCB is vertical without blown air. See page 15
bb
6)
Soldering point: upper side of solder edge of device pin 15. See page 15
Semiconductor Group
3
BTS 711 L1
Electrical Characteristics
Parameter and Conditions, each of the four channels Symbol
Values
Unit
at Tj = 25 °C, V = 12 V unless otherwise specified
bb
min
--
typ
max
Load Switching Capabilities and Characteristics
On-state resistance (V to OUT)
bb
mΩ
IL = 1.8 A
each channel,
Tj = 25°C: RON
Tj = 150°C:
165
320
200
400
two parallel channels, Tj = 25°C:
four parallel channels, Tj = 25°C:
83
42
100
50
--
Nominal load current
one channel active: IL(NOM)
two parallel channels active:
four parallel channels active:
1.7
2.6
4.1
1.9
2.8
4.4
A
Device on PCB5), Ta = 85°C, Tj ≤ 150°C
Output current while GND disconnected or pulled
IL(GNDhigh)
--
--
10 mA
up; V = 30 V, V = 0, see diagram page 9
bb
IN
Turn-on time
Turn-off time
to 90% VOUT: ton
to 10% VOUT: toff
80
80
200
200
400
400
µs
RL = 12 Ω, T =-40...+150°C
j
Slew rate on
10 to 30% VOUT, RL = 12 Ω,
dV/dton
0.1
0.1
--
--
1 V/µs
1 V/µs
T =-40...+150°C:
j
Slew rate off
70 to 40% VOUT, RL = 12 Ω,
-dV/dtoff
T =-40...+150°C:
j
Operating Parameters
Operating voltage7)
Tj =-40...+150°C: Vbb(on)
Tj =-40...+150°C: Vbb(under)
Tj =-40...+25°C: Vbb(u rst)
Tj =+150°C:
5.0
3.5
--
--
--
--
34
V
V
V
Undervoltage shutdown
Undervoltage restart
5.0
5.0
7.0
Undervoltage restart of charge pump
Vbb(ucp)
--
--
5.6
0.2
7.0
V
V
see diagram page 14
Tj =-40...+150°C:
Undervoltage hysteresis
∆Vbb(under) = Vbb(u rst) - Vbb(under)
∆Vbb(under)
--
Overvoltage shutdown
Overvoltage restart
Tj =-40...+150°C: Vbb(over)
Tj =-40...+150°C: Vbb(o rst)
Tj =-40...+150°C: ∆Vbb(over)
Tj =-40...+150°C: Vbb(AZ)
34
33
--
--
--
43
--
V
V
V
V
Overvoltage hysteresis
Overvoltage protection8)
0.5
47
--
42
--
I
bb = 40 mA
7)
8)
At supply voltage increase up to V =5.6V typ without charge pump, V
≈V - 2 V
bb
bb
OUT
see also V
in circuit diagram on page 8.
ON(CL)
Semiconductor Group
4
BTS 711 L1
Parameter and Conditions, each of the four channels Symbol
Values
Unit
at Tj = 25 °C, V = 12 V unless otherwise specified
bb
min
typ
max
Standby current, all channels off
VIN = 0
Tj =25°C: Ibb(off)
Tj =150°C:
--
--
28
44
60
70
µA
µA
Leakage output current (included in Ibb(off)
VIN = 0
)
IL(off)
--
--
12
Operating current 9), VIN = 5V, Tj =-40...+150°C
IGND
--
--
2
8
3
12
mA
IGND = IGND1/2 + IGND3/4
,
one channel on:
four channels on:
Protection Functions
Initial peak short circuit current limit, (see timing
diagrams, page 12)
each channel, Tj =-40°C: IL(SCp)
Tj =25°C:
5.5
4.5
2.5
9.5
7.5
4.5
13
11
7
A
Tj =+150°C:
two parallel channels
four parallel channels
Repetitive short circuit current limit,
twice the current of one channel
four times the current of one channel
Tj = Tjt
each channel IL(SCr)
two parallel channels
four parallel channels
--
--
--
4
4
4
--
--
--
A
(see timing diagrams, page 12)
Initial short circuit shutdown time
Tj,start =-40°C: toff(SC)
Tj,start = 25°C:
--
--
5.5
4
--
--
ms
V
(see page 11 and timing diagrams on page 12)
Output clamp (inductive load switch off)10)
at VON(CL) = Vbb - VOUT
VON(CL)
--
47
--
Thermal overload trip temperature
Thermal hysteresis
Tjt
150
--
--
--
--
°C
K
∆Tjt
10
Reverse Battery
Reverse battery voltage 11)
-Vbb
--
--
--
32
V
Drain-source diode voltage (V > V
)
-VON
610
-- mV
out
bb
IL =-1.9A, Tj =+150°C
9)
10)
Add I , if I > 0
ST
ST
If channels are connected in parallel, output clamp is usually accomplished by the channel with the lowest
V
ON(CL)
11)
Requires a 150 Ω resistor in GND connection. The reverse load current through the intrinsic drain-source
diode has to be limited by the connected load. Note that the power dissipation is higher compared to normal
operating conditions due to the voltage drop across the intrinsic drain-source diode. The temperature
protection is not active during reverse current operation! Input and Status currents have to be limited (see
max. ratings page 3 and circuit page 8).
Semiconductor Group
5
BTS 711 L1
Parameter and Conditions, each of the four channels Symbol
Values
Unit
at Tj = 25 °C, V = 12 V unless otherwise specified
bb
min
typ
max
Diagnostic Characteristics
Open load detection current, (on-condition)
10
10
10
--
--
--
200 mA
150
150
each channel, Tj = -40°C: I L (OL)
1
Tj = 25°C:
Tj = 150°C:
twice the current of one channel
four times the current of one channel
two parallel channels
four parallel channels
Open load detection voltage12)
Tj =-40..+150°C: VOUT(OL)
2
3
4
V
Internal output pull down
(OUT to GND), V
=5V
Tj =-40..+150°C: RO
4
10
30
kΩ
OUT
Input and Status Feedback13)
Input resistance
RI
2.5
1.7
1.5
3.5
--
6
3.5
--
kΩ
V
(see circuit page 8)
Tj =-40..+150°C:
Input turn-on threshold voltage
Input turn-off threshold voltage
Input threshold hysteresis
VIN(T+)
Tj =-40..+150°C:
VIN(T-)
--
V
Tj =-40..+150°C:
∆ VIN(T)
--
1
0.5
--
--
V
Off state input current
Tj =-40..+150°C:
VIN = 0.4 V: IIN(off)
50
µA
On state input current
Tj =-40..+150°C:
VIN = 5 V: IIN(on)
20
50
90
µA
µs
Delay time for status with open load after switch
off (other channel in off state)
td(ST OL4)
td(ST OL5)
td(ST)
100
320
800
(see timing diagrams, page 13),
Tj =-40..+150°C:
Delay time for status with open load after switch
off (other channel in on state)
--
--
5
20
µs
µs
(see timing diagrams, page 13),
Tj =-40..+150°C:
Status invalid after positive input slope
200
600
(open load)
Tj =-40..+150°C:
Status output (open drain)
Zener limit voltage Tj =-40...+150°C, IST = +1.6 mA: VST(high)
5.4
--
--
6.1
--
--
--
0.4
0.6
V
ST low voltage
Tj =-40...+25°C, IST = +1.6 mA: VST(low)
Tj = +150°C, IST = +1.6 mA:
12)
External pull up resistor required for open load detection in off state.
13)
If ground resistors R
are used, add the voltage drop across these resistors.
GND
Semiconductor Group
6
BTS 711 L1
Truth Table
IN1
IN3
IN2
IN4
OUT1
OUT3
OUT2
OUT4
ST1/2
ST3/4
ST1/2
ST3/4
Channel 1 and 2
Channel 3 and 4
Chip 1
Chip 2
(equivalent to channel 1 and 2)
BTS 711L1 BTS 712N1
Normal operation
Open load
L
L
H
H
L
L
H
L
H
X
L
L
H
L
H
X
L
X
H
L
H
X
X
X
L
H
L
H
L
H
X
L
L
H
L
H
X
L
L
H
L
H
X
X
X
L
H
X
L
L
H
H
Z
Z
H
L
H
X
H
H
H
L
H
X
L
L
L
L
L
X
X
L
L
H
L
H
L
H
X
Z
Z
H
L
H
X
H
H
H
L
L
L
X
X
L
L
L
H
H
H
H
H
H
H
H
L
H
H
L
14)
Channel 1 (3)
Channel 2 (4)
Channel 1 (3)
Channel 2 (4)
both channel
H(L
)
)
H
L
14)
H(L
H
L
H
H
15)
15)
Short circuit to V
L
L
L
bb
H
H
H
15)
16)
15)
H(L
L
)
H
H
H
H
L
L
H
L
H
L
H
16)
H(L
)
Overtemperature
H
L
L
H
L
H
L
H
Channel 1 (3)
Channel 2 (4)
Undervoltage/ Overvoltage
L = "Low" Level
H = "High" Level
X = don't care
Z = high impedance, potential depends on external circuit
Status signal valid after the time delay shown in the timing diagrams
Parallel switching of channel 1 and 2 (also channel 3 and 4) is easily possible by connecting the inputs and
outputs in parallel (see truth table). If switching channel 1 to 4 in parallel, the status outputs ST1/2 and ST3/4
have to be configured as a 'Wired OR' function with a single pull-up resistor.
Terms
I
bb
V
V
V
ON1
ON3
Leadframe
Leadframe
bb
V
V
ON2
ON4
I
I
I
I
IN1
IN2
IN3
IN4
V
V
bb
bb
3
5
7
9
I
I
I
I
IN1
IN3
L1
L3
18
17
14
13
OUT1
OUT2
OUT3
OUT4
PROFET
Chip 1
PROFET
Chip 2
IN2
IN4
L2
L4
I
I
ST3/4
ST1/2
4
8
ST1/2
ST3/4
V
V
V
V
GND1/2
2
GND3/4
6
V
V
IN4
IN1
IN3
IN2
ST1/2
V
ST3/4
V
OUT1
OUT3
V
V
OUT4
I
I
OUT2
GND1/2
GND3/4
R
R
GND1/2
GND3/4
Leadframe (V ) is connected to pin 1,10,11,12,15,16,19,20
bb
External R
optional; two resistors R
,R
GND3/4
=150 Ω or a single resistor R
=75 Ω for
GND
GND1/2
GND
reverse battery protection up to the max. operating voltage.
14)
15)
With additional external pull up resistor
An external short of output to Vbb in the off state causes an internal current from output to ground. If RGND is
used, an offset voltage at the GND and ST pins will occur and the VST low signal may be errorious.
16)
Low resistance to V may be detected by no-load-detection
bb
Semiconductor Group
7
BTS 711 L1
Input circuit (ESD protection), IN1...4
Overvoltage protection of logic part
GND1/2 or GND3/4
R
+ V
bb
I
IN
V
Z2
R
I
IN
IN
ESD-ZDI
I
I
Logic
GND
ST
RST
V
Z1
ESD zener diodes are not to be used as voltage clamp at
DC conditions. Operation in this mode may result in a drift of
the zener voltage (increase of up to 1 V).
GND
RGND
Signal GND
Status output, ST1/2 or ST3/4
V
Z1
= 6.1 V typ., V = 47 V typ., R = 3.5 kΩ typ.,
Z2
I
R
GND
= 150 Ω
+5V
R
ST(ON)
ST
Reverse battery protection
V
-
+ 5V
bb
ESD-
ZD
RST
GND
RI
IN
ESD-Zener diode: 6.1 V typ., max 5.0 mA; R
ST(ON)
< 380 Ω
OUT
ST
at 1.6 mA, ESD zener diodes are not to be used as voltage
clamp at DC conditions. Operation in this mode may result in
a drift of the zener voltage (increase of up to 1 V).
Power
Inverse
Diode
Logic
GND
RGND
RL
Inductive and overvoltage output clamp,
OUT1...4
Power GND
Signal GND
R
GND
= 150 Ω, R = 3.5 kΩ typ,
I
+V
bb
Temperature protection is not active during inverse current
operation.
V
Z
VON
OUT
PROFET
Power GND
V
ON
clamped to V = 47 V typ.
ON(CL)
Semiconductor Group
8
BTS 711 L1
Open-load detection, OUT1...4
ON-state diagnostic condition:
GND disconnect with GND pull up
(channel 1/2 or 3/4)
V
ON
< R ·I
; IN high
ON L(OL)
+ V
V
bb
bb
IN1
OUT1
OUT2
V
IN1
PROFET
IN2
ST
V
IN2
VON
GND
ON
OUT
V
Open load
detection
V
GND
Logic
unit
ST
V
bb
Any kind of load. If V
> V - V
device stays off
IN(T+)
GND
IN
Due to V
> 0, no V = low signal available.
ST
GND
OFF-state diagnostic condition:
V
disconnect with energized inductive
bb
V
OUT
> 3 V typ.; IN low
load
R
V
EXT
V
bb
IN1
OUT1
high
OFF
PROFET
IN2
ST
OUT2
OUT
GND
Open load
detection
Logic
unit
R
O
V
bb
Signal GND
For an inductive load current up to the limit defined by E
AS
(max. ratings see page 3 and diagram on page 10) each
switch is protected against loss of V
.
bb
GND disconnect
(channel 1/2 or 3/4)
Consider at your PCB layout that in the case of Vbb dis-
connection with energized inductive load the whole load
current flows through the GND connection.
I
bb
V
bb
V
bb
IN1
IN2
ST
OUT1
PROFET
OUT2
GND
V
V
V
V
IN1 IN2
GND
ST
Any kind of load. In case of IN=high is V
OUT
≈ V -V
.
IN IN(T+)
Due to VGND > 0, no V = low signal available.
ST
Semiconductor Group
9
BTS 711 L1
Inductive load switch-off energy
dissipation
E
bb
E
AS
E
E
Load
V
bb
IN
O U T
PROFET
L
=
ST
L
G N D
Z
L
{
E
R
R
L
Energy stored in load inductance:
2
L
1
E = / ·L·I
L
2
While demagnetizing load inductance, the energy
dissipated in PROFET is
E
AS
= Ebb + EL - ER= VON(CL)·i (t) dt,
L
∫
with an approximate solution for R > 0Ω:
L
I ·L
L
I ·R
L
L
OUT(CL)
E =
AS
(V +|V
|) ln (1+
OUT(CL)
)
bb
2·R
|V
|
L
Maximum allowable load inductance for
5)
a single switch off (one channel)
L = f (I ); T
= 150°C, V = 12 V, R = 0 Ω
L
j,start
bb
L
L [mH]
1000
100
10
1
1
1.5
2
2.5
3
I
[A]
L
Semiconductor Group
10
BTS 711 L1
Typ. on-state resistance
Typ. standby current
R
= f (V ,T ); I = 1.8 A, IN = high
I
= f (T ); V = 9...34 V, IN
= low
1...4
ON
L
bb(off)
j
bb
bb j
R
[mOhm]
I
[µA]
ON
bb(off)
60
500
450
400
350
300
250
200
150
100
50
50
40
30
20
10
0
Tj = 150°C
85°C
25°C
-40°C
0
-50
0
50
100
150
200
0
10
20
30
40
V
[V]
T [°C]
j
bb
Typ. open load detection current
Typ. initial short circuit shutdown time
I
= f (V ,T ); IN = high
t
= f (T
); V =12 V
bb
L(OL)
off(SC)
bb j
j,start
I
[mA]
t
[msec]
L(OL)
off(SC)
6
140
-40°C
120
100
80
60
40
20
0
5
4
3
2
1
25°C
85°C
Tj = 150°C
0
0
5
10
15
20
25
V
30
[V]
-50
0
50
100
150
T
200
[°C]
bb
j,start
Semiconductor Group
11
BTS 711 L1
Timing diagrams
Timing diagrams are shown for chip 1 (channel 1/2). For chip 2 (channel 3/4) the diagrams
are valid too. The channels 1 and 2, respectively 3 and 4, are symmetric and consequently
the diagrams are valid for each channel as well as for permuted channels
Figure 1a: V turn on:
Figure 2b: Switching an inductive load
bb
IN1
IN2
IN
t d(ST)
V
bb
ST
*)
V
OUT1
V
OUT
V
OUT2
I L
IL(OL)
ST open drain
t
t
*) if the time constant of load is too large, open-load-status may
occur
Figure 2a: Switching a lamp:
Figure 3a: Turn on into short circuit:
shut down by overtemperature, restart by cooling
IN
IN1
other channel: normal operation
ST
IL1
VOUT
I
L(SCp)
I
L(SCr)
IL
t
off(SC)
ST
t
t
The initial peak current should be limited by the lamp and not by
the initial short circuit current IL(SCp) = 7.5 A typ. of the device.
Heating up of the chip may require several milliseconds, depending
on external conditions (t vs. T see page 11)
off(SC)
j,start
Semiconductor Group
12
BTS 711 L1
Figure 3b: Turn on into short circuit:
Figure 5a: Open load: detection in ON-state, open
shut down by overtemperature, restart by cooling
(two parallel switched channels 1 and 2)
load occurs in on-state
IN1
IN1/2
IN2
channel 2: normal operation
I L1+ I
L2
I
L(SCp)
VOUT1
I
L(SCr)
channel 1:
open
load
IL1
open
load
normal
load
t
off(SC)
t d(ST OL1)
ST
t d(ST OL1)
t d(ST OL2)
ST1/2
t d(ST OL2)
t
t
td(ST OL1) = 30 µs typ., td(ST OL2) = 20 µs typ
Figure 4a: Overtemperature:
Figure 5b: Open load: detection in ON-state, turn
on/off to open load
Reset if T <T
j
jt
IN
IN1
IN2
channel 2: normal operation
ST
V
OUT1
VOUT
I L1
channel 1: open load
T
J
t
t
t
t
d(ST)
d(ST OL4)
d(ST)
d(ST OL5)
t
ST
t
The status delay time td(STOL4) allows to distinguish between the
failure modes "open load in ON-state" and "overtemperature".
Semiconductor Group
13
BTS 711 L1
Figure 5c: Open load: detection in ON- and OFF-state
(with R
), turn on/off to open load
Figure 6b: Undervoltage restart of charge pump
EXT
VON(CL)
IN1
Von
IN2
channel 2: normal operation
VOUT1
V bb(over)
IL1
channel 1: open load
V
Vbb(u rst)
V
bb(o rst)
bb(u cp)
t
ST
t d(ST OL5)
td(ST)
d(ST)
V
bb(under)
Vbb
t
td(ST OL5) depends on external circuitry because of high
impedance
IN = high, normal load conditions.
Charge pump starts at Vbb(ucp) = 5.6V typ.
Figure 6a: Undervoltage:
Figure 7a: Overvoltage:
IN
IN
V
bb
VON(CL)
V
V
bb(over)
bb(o rst)
V
bb
V
V
bb(u cp)
bb(under)
V
bb(u rst)
VOUT
V OUT
ST open drain
ST
t
t
Semiconductor Group
14
BTS 711 L1
Package and Ordering Code
Standard P-DSO-20-9
Ordering Code
BTS711L1
Q67060-S7000-A2
All dimensions in millimetres
1) Does not include plastic or metal protrusions of 0.15 max per side
2) Does not include dambar protrusion of 0.05 max per side
Definition of soldering point with temperature T :
s
upper side of solder edge of device pin 15.
Pin 15
Printed circuit board (FR4, 1.5mm thick, one layer
70µm, 6cm2 active heatsink area) as a reference for
max. power dissipation P , nominal load current
tot
I
and thermal resistance R
L(NOM)
thja
Semiconductor Group
15
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