BTS71220-4ESE [INFINEON]
The device is integrated in SMART7 technology.;
| 型号： | BTS71220-4ESE |
| 厂家： | 
Infineon |
| 描述： | The device is integrated in SMART7 technology. 接口集成电路 |
| 文件： | 总88页 (文件大小：2975K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BTS71220-4ESE
SPOC™ +2
2x 9.5 mΩ
Serial Interface Power Controller
2x 22.5 mΩ
Package
Marking
PG-TSDSO-24
71220-4ESE
1
Overview
Potential Applications
•
•
•
Suitable for resistive, inductive and capacitive loads
Replaces electromechanical relays, fuses and discrete circuits
Driving capability suitable for 5 A and 3 A loads and high inrush current
loads such as 55W bulb or equivalent electronic loads (e.g. LED modules)
and 27W bulb or equivalent electronic loads (e.g. LED modules)
VBAT
Optional
ZWIRE
Fail-safe
Control
Optional
Logic Supply
CVSGND
CVS1
RGND
CVSGND
CVS1
RGND
T1
CVDD
VS
GND
IN
GND
VS
OUT
VDD
IN0
IN1
EDO
EDD
LHI
RVDD
EDO_IN
VDD
RIN
GPIO
GPIO
GPIO
GPIO
RIN
EDD_DEN
OUT0
OUT1
OUT2
OUT3
DEN
RDEN
RIN
EDO_IN
PRO_IS
EDD_DEN
IS
RLHI
RCSN
RSCLK
CSN
SCLK
MISO
MOSI
ADC
CSN
SCLK
SO
DZ2
CVS2
RSO
SI
RSI
IS
RADC
RIS_PROT
VSS
PRO_IS
DZ1
CADC
Logic GND
Optional
Application_4ch_ED.emf
Power GND
*See Chapter 1 „Potential Applications“
Chassis GND
**See Chapter 11.2 „External Components“
Figure 1
Application Diagram. Further information in Chapter 11
Data Sheet
www.infineon.com
Rev. 1.10
2021-03-23
1
BTS71220-4ESE
SPOC™ +2
Overview
Basic Features
•
•
•
•
•
•
•
•
•
High-Side Switch with Diagnosis and Embedded Protection
Part of SPOC™ +2 Family
Daisy Chain capable SPI interface
3.3 V and 5 V compatible logic pins
Slew rate control for internal Channels
Integrated control for one external smart power switch
ReverseON for low power dissipation in Reverse Polarity
Switch ON capability while Inverse Current condition (InverseON)
Green Product (RoHS compliant)
Protection Features
•
•
•
•
Absolute and dynamic temperature limitation with controlled restart
Overcurrent protection (tripping) with Programmable Restart Control and Current Threshold
Undervoltage shutdown
Overvoltage protection with external components
Diagnostic Features
•
•
•
•
Proportional load current sense multiplexed
Open Load in ON and OFF state
Short circuit to ground and battery
Diagnosis feedback via SPI
Functional Safety Features
•
•
•
•
Limp Home mode
Monitoring of Input pin status (IN and LHI)
Checksum verification of Configuration Registers
Current Sense verification mode
Product Validation
Qualified for automotive applications. Product validation according to AEC-Q100 Grade 1.
Description
The BTS71220-4ESE is a Serial Interface Power Controller, providing protection functions and diagnosis. The
device is integrated in SMART7 technology.
Data Sheet
2
Rev.1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Overview
Table 1
Product Summary
Parameter
Symbol
VS(OP)
Values
4.1 V
Minimum Operating voltage (at switch ON)
Minimum Operating voltage (cranking)
Maximum Operating voltage
Digital Supply voltage
VS(UV)
3.1 V
VS
28 V
VDD
3.3 V or 5 V
35 V
Minimum Overvoltage protection (TJ ≥ 25 °C)
Maximum current in Sleep mode (TJ ≤ 85 °C)
Maximum operative current
VDS(CLAMP)_25
IVS(SLEEP)_85
IGND(ACTIVE)
RDS(ON)_150
0.7 µA
7 mA
Maximum ON-state resistance (TJ = 150 °C)
16.5 mΩ
channels 0 and 3
Maximum ON-state resistance (TJ = 150 °C)
channels 1 and 2
RDS(ON)_150
IL(NOM)
IL(NOM)
kILIS
38 mΩ
5 A
Nominal load current (TA = 85 °C)
channels 0 and 3
Nominal load current (TA = 85 °C)
channels 1 and 2
3 A
Typical current sense ratio at IL = IL(NOM)
channels 0 and 3
5000
2000
5 MHz
Typical current sense ratio at IL = IL(NOM)
channels 1 and 2
kILIS
Serial Clock Frequency
fSCLK(max)
Data Sheet
3
Rev.1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Block Diagram and Terms
2
Block Diagram and Terms
2.1
Block Diagram
VS
Channel 0
Channel 1
Channel 2
Channel 3
VDD
SO
Voltage Sensor
SI
Ov ertemp eratur e
T
Overvoltage
Clamping
SCLK
CSN
LHI
Gate Co ntrol
&
Chargepump
OUT0
OUT1
Driver
Logic
ESD
Protection
+
Ov ercurr ent
Protection
OUT2
OUT3
ReverseON
In verseON
I/O Logic
IN0
IN1
EDO
EDD
IS
Output Voltage Limitation
Load Current Sense Multiplexer
Internal Power Supply
Overvoltage Protection
Reverse Polarity
Protection
VS Mo nitoring
Limp Home Control
In ter nal L ogi c Suppl y
External
Driver
Cont rol
GND Circuitry
SPI Interface
GND
BlockDiagram_4chED.emf
Figure 2
Block Diagram of BTS71220-4ESE
Data Sheet
4
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Block Diagram and Terms
2.2
Terms
Figure 3 shows all terms used in this data sheet, with associated convention for positive values.
IVS
VSIS
IDD
VS
VDD
ISO
VS
SO
VDSn
VDD
SI
VSO
SCLK
CSN
LHI
INn
EDD
EDO
IS
VSI
ICSN
I Ln
OUTn
ILHI
VSCLK
VCSN
IINn
VLH I
IEDD
VINn
IEDO
VOUTn
VEDD
IIS
VEDO
GND
IGND
VIS
Terms_ED.emf
Figure 3
Voltage and Current Convention
Data Sheet
5
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Pin Configuration
3
Pin Configuration
3.1
Pin Assignment
(top view)
1
2
3
4
5
24
23
22
21
20
19
18
17
16
15
14
GND
VDD
SO
OUT0
OUT0
OUT0
OUT0
OUT1
OUT1
OUT2
OUT2
OUT3
OUT3
OUT3
OUT3
SI
SCLK
CSN
LHI
IN0
IN1
EDD
EDO
IS
6
VS
7
8
9
10
11
12expos ed pad (bo tto m) 13
PinOut_SPOC_220_ED.emf
Figure 4
Pin Configuration
Data Sheet
6
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Pin Configuration
3.2
Pin Definitions and Functions
Table 2
Pin
Pin Definition
Symbol I/O Function
EP
VS
-
Power Supply Voltage
(exposed pad)
Battery voltage
1
GND
VDD
SO
-
-
O
I
Ground
2
Digital Supply Voltage
3
Serial output of SPI interface
4
SI
Serial input of SPI interface (“high” active)
Serial clock of SPI interface (“high” active)
Chip select of SPI interface (“low” active); integrated pull up to VDD
Limp Home activation signal (“high” active)
5
SCLK
CSN
LHI
I
6
I
7
I
8, 9
INn
I
Input Channel n
Digital signal to switch ON the channel n (“high” active)
If not used: connect with a 10 kΩ resistor either to GND pin or to module
ground
10
11
12
EDD
EDO
IS
O
O
External driver diagnosis enable signal
Digital signal to activate the diagnosis of an external controlled device
External driver output enable signal
Digital signal to activate the output of an external controlled device
O
O
Current sense output signal
21-24 OUTn
19-20
Output n
Protected high-side power output of channel n1)
17-18
13-16
1) All output pins of the channel must be connected together on the PCB. All pins of the output are internally connected
together. PCB traces have to be designed to withstand the maximum current which can flow.
Data Sheet
7
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
General Product Characteristics
4
General Product Characteristics
4.1
Absolute Maximum Ratings - General
Table 3
Absolute Maximum Ratings1)
TJ = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
Supply pins
Power Supply Voltage
Digital Supply Voltage
Load Dump Voltage
VS
-0.3
-0.3
–
–
–
–
28
5.5
35
V
V
V
–
P_4.1.0.1
P_4.1.0.29
P_4.1.0.3
VDD
–
VBAT(LD)
suppressed
Load Dump
acc. to
ISO16750-2
(2010).
Ri = 2 Ω
Supply Voltage for Short Circuit VBAT(SC)
Protection
0
–
–
–
24
16
V
V
Setup acc. to
AEC-Q100-012
P_4.1.0.25
P_4.1.0.5
Reverse Polarity Voltage
-VBAT(REV)
t ≤ 2 min
TA = +25 °C
Setup as
described in
Chapter 11
Current through GND Pin
Current through VDD Pin
IGND
-50
–
50
mA
RGND according P_4.1.0.9
to Chapter 11
IVDD(REV)
-10
50
–
–
30
–
mA
ms
t ≤ 2 min
P_4.1.0.10
P_4.1.0.35
Counter Reset Delay Time after tRETRY
–
Fault Condition
Logic & control pins (Digital Input = DI)
DI = INn, CS, SCLK, SI, LHI
2)
Current through DI Pin
IDI
-1
-1
–
–
2
mA
mA
P_4.1.0.14
P_4.1.0.36
2)
Current through DI Pin
IDI(REV)
10
Reverse Battery Condition
t ≤ 2 min
Logic & control pins (Digital Output = DO)
DO = SO, EDO, EDD
2)
Current through DO Pin
IDO
-2
–
–
1
1
mA
mA
P_4.1.0.33
P_4.1.0.37
2)
Current through DO Pin
IDO(REV)
-10
Reverse Battery Condition
t ≤ 2 min
Data Sheet
8
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
General Product Characteristics
Table 3
Absolute Maximum Ratings1) (continued)
TJ = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
IS pin
Voltage at IS Pin
Current through IS Pin
VIS
IIS
-1.5
-25
–
–
VS
V
IIS = 10 μA
P_4.1.0.16
P_4.1.0.18
IIS(SAT),M mA
–
AX
Temperatures
Junction Temperature
Storage Temperature
ESD Susceptibility
TJ
-40
-55
–
–
150
150
°C
°C
–
–
P_4.1.0.19
P_4.1.0.20
TSTG
ESD Susceptibility all Pins
(HBM)
VESD(HBM)
-2
–
–
–
–
2
kV
kV
V
HBM3)
HBM3)
CDM4)
CDM4)
P_4.1.0.21
P_4.1.0.22
P_4.1.0.23
P_4.1.0.24
ESD Susceptibility OUTn vs
GND and VS connected (HBM)
VESD(HBM)_OUT -4
VESD(CDM) -500
4
ESD Susceptibility all Pins
(CDM)
500
750
ESD Susceptibility Corner Pins VESD(CDM)_CRN -750
(pins 1, 12, 13, 24)
V
1) Not subject to production test - specified by design.
2) Maximum VDI to be considered for Latch-Up tests: 5.5 V.
3) ESD susceptibility, Human Body Model "HBM", according to AEC Q100-002.
4) ESD susceptibility, Charged Device Model "CDM", according to AEC Q100-011.
Notes
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
Data Sheet
9
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
General Product Characteristics
4.2
Absolute Maximum Ratings - Power Stages
4.2.1
Power Stages - 9.5 mΩ channels
Table 4
Absolute Maximum Ratings - 9.5 mΩ channels1)
TJ = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
–
Unit Note or
Test Condition
Number
Min.
Max.
Maximum Energy Dissipation EAS
Single Pulse
–
55
mJ
IL = 2*IL(NOM)
TJ(0) = 150 °C
VS = 28 V
P_4.2.15.1
Maximum Energy Dissipation EAR
Repetitive Pulse
–
–
–
24
mJ
IL = IL(NOM)
TJ(0) = 85 °C
VS = 13.5 V
1M cycles
P_4.2.15.2
P_4.2.15.3
Load Current
|IL|
–
IL(OVL),MAX
A
–
1) Not subject to production test - specified by design.
4.2.2
Power Stages - 22.5 mΩ channels
Table 5
Absolute Maximum Ratings - 22.5 mΩ channels1)
TJ = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Typ.
–
Unit Note or
Test Condition
Number
Min.
Max.
Maximum Energy Dissipation EAS
Single Pulse
–
28
mJ
IL = 2*IL(NOM)
TJ(0) = 150 °C
VS = 28 V
P_4.2.16.1
Maximum Energy Dissipation EAR
Repetitive Pulse
–
–
–
8.5
mJ
IL = IL(NOM)
TJ(0) = 85 °C
VS = 13.5 V
1M cycles
P_4.2.16.2
P_4.2.16.3
Load Current
|IL|
–
IL(OVL),MAX
A
–
1) Not subject to production test - specified by design.
Data Sheet
10
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
General Product Characteristics
4.3
Functional Range
Table 6
Functional Range - Supply Voltages and Temperature1)
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
Power Supply Voltage
Range for Normal Operation
VS(NOR)
6
13.5
18
V
–
P_4.3.0.1
P_4.3.0.2
2)3)
Lower Extended Power
Supply Voltage Range for
Operation
VS(EXT,LOW)
3.1
–
6
V
(parameter
deviations possible)
3)
Upper Extended Power
Supply Voltage Range for
Operation
VS(EXT,UP)
18
–
28
V
V
P_4.3.0.3
(parameter
deviations possible)
Digital Supply Voltage
Range
VDD(NOR)
TJ
3.0
-40
–
–
5.5
–
–
P_4.3.0.4
P_4.3.0.5
Junction Temperature
150 °C
1) Not subject to production test - specified by design.
2) In case of VS voltage decreasing: VS(EXT,LOW),MIN = 3.1 V. In case of VS voltage increasing: VS(EXT,LOW),MIN = 4.1 V.
3) Protection functions still operative.
Note:
Within the functional or operating range, the IC operates as described in the circuit description. The
electrical characteristics are specified within the conditions given in the Electrical Characteristics
tables.
4.4
Thermal Resistance
Note:
This thermal data was generated in accordance with JEDEC JESD51 standards. For more
information, go to www.jedec.org.
Table 7
Thermal Resistance1)
Parameter
Symbol
Values
Typ.
0.9
Unit Note or
Test Condition
Number
Min.
Max.
2)
Thermal Characterization
Parameter Junction-Top
ΨJTOP
–
1.5
K/W
P_4.4.0.15
P_4.4.0.16
2)
Thermal Resistance
Junction-to-Case
RthJC
–
–
0.5
26
0.9
–
K/W
simulated at
exposed pad
2)
Thermal Resistance
Junction to Ambient
RthJA
K/W
P_4.4.0.6
1) Not subject to production test - specified by design.
2) According to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; the Product (Chip + Package) was
simulated on a 76.2 × 114.3 × 1.5 mm board with 2 inner copper layers (2 × 70 µm Cu, 2 × 35 µm Cu). Where applicable
a thermal via array under the exposed pad contacted the first inner copper layer. Simulation done at TA = 105°C,
P
DISSIPATION = 1 W.
Data Sheet
11
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
General Product Characteristics
4.4.1
PCB Setup
70 µm modeled (traces, cooling area)
70 µm, 5% metalization*
*: means percentual Cu metalization on each layer
PCB_Zth_1s0p.emf
Figure 5
1s0p PCB Cross Section
70 µm modeled (traces)
35 µm, 90% metalization*
35 µm, 90% metalization*
70 µm, 5% metalization*
*: means percentual Cu metalization on each layer
PCB_Zth_2s2p.emf
Figure 6
2s2p PCB Cross Section
PCB 1s0p + 600 mm2 cooling
PCB 2s2p / 1s0p footprint
PCB_sim_setup_TSDSO24.emf
Figure 7
PCB setup for thermal simulations
PCB_2s2p_vias_TSDSO24.emf
Figure 8
Thermal vias on PCB for 2s2p PCB setup
Data Sheet
12
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
General Product Characteristics
4.4.2
Thermal Impedance
BTS71220-4ESx
100
10
1
0.1
2s2p
1s0p - 600 mm²
1s0p - 300 mm²
1s0p - footprint
0.01
0.0001
0.001
0.01
0.1
1
10
100
1000
Time [s]
Figure 9
Typical Thermal Impedance. PCB setup according Chapter 4.4.1
BTS71220-4ESx
90
80
70
60
50
40
30
1s0p - Ta = 105 °C
0
100
200
300
400
500
600
Cooling area [mm²]
Figure 10 Thermal Resistance on 1s0p PCB with various cooling surfaces
Data Sheet
13
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Logic Pins
5
Logic Pins
The device has 9 digital pins to configure and control the device. They can be grouped based on their function
into input pins, SPI pins, external driver pins and Limp Home pin.
5.1
Input Pins (INn)
The input pins IN0 and IN1 activate the corresponding output channel, if the device is either in Sleep, Stand-
by, Ready or in Limp Home mode. The input circuitry is compatible with 3.3V and 5V microcontroller. The
electrical equivalent of the input circuitry is shown in Figure 11. In case the pin is not used, it must be
connected with a 10 kΩ resistor either to GND pin or to module ground.
VS
IN
VS(CLAMP)
IDI
IDI
ESD
VDI(CLAMP)
VDI
GND
IGND
Input_IN_INTDIO.emf
Figure 11 Input circuitry
The logic thresholds for “low” and “high” states are defined by parameters VDI(TH) and VDI(HYS). The relationship
between these two values is shown in Figure 12. The voltage VIN needed to ensure a “high” state is always
higher than the voltage needed to ensure a “low” state.
Data Sheet
14
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Logic Pins
VDI
VDI(TH ),MAX
VDI(TH)
VDI(HYS)
VDI(TH ),MIN
t
t
Internal channel
activation signal
0
x
1
x
0
Input_VDITH_2.emf
Figure 12 Input Threshold voltages and hysteresis
There are two ways of using the input pins in combination with the register OUT by programming bit
HWCR.COLin register HWCR(see Table 35).
•
•
HWCR.COL= 0B: A channel is switched ON either by the according OUT.OUTnbit or by the input pin.
HWCR.COL= 1B: A channel is switched ON by the according OUT.OUTnbit only, when the input pin is
“high”. In this configuration, a PWM signal can be applied to the input pin and the channel is activated by
the SPI register OUT(see Table 35).
The default state (HWCR.COL= 0B) is the OR-combination of the input signal and the SPI-bit. In Limp Home
mode (LHI pin set to “high”) the combinatorial logic is in default state to enable a channel activation via the
input pins only. Figure 13 shows the complete input switch matrix.
The logic level of the input pins can be monitored via the input status monitor. In case of a “high” level on an
input pin, the corresponding ICS.INSTnbit is set and cleared on read.
Data Sheet
15
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Logic Pins
MUX≠111 OUT2 OUT1 OUT3 OUT0
PCC0
&
&
&
&
OR
&
IN0
IN1
IIN 0
Gate Control 0
Gate Control 3
OR
OR
OR
&
IIN 2
Gate Control 1
Gate Control 2
COL
PCC1
LogicPins_InputMatr ix_4chED_PCC.emf
Figure 13 Input Switch Matrix
5.2
Advanced Features Pins
5.2.1
SPI Pins
The serial peripheral interface (SPI) is a full duplex synchronous serial slave interface, which uses four lines:
SO, SI, SCLK and CSN. See Chapter 10 for further information.
5.2.2
Limp Home Input (LHI) Pin
For activating the fail-safe state, the device features a Limp Home Input pin. When the pin is set to “high” for
a time longer than tLHI(AC), the Limp Home mode will be activated. See Chapter 6.1.7 and Chapter 6.1.8 for
further information.
5.2.3
External Driver Pins
One external smart power driver can be controlled by the BTS71220-4ESE via the external driver control block.
There are two control outputs available: one output for controlling the input (EDO) and one output for
diagnosis enable input (EDD). The current sense output of the external smart power driver can be connected
to the IS pin. For details please refer to the Application Circuit Example in Chapter 11. The external driver
output signals can be used in Stand-by and Active mode.
The external driver can be activated via SPI bit OUT.OUT4.
Note:
The usable duty cycle range and diagnostic timings depend on the external driver’s characteristics.
Data Sheet
16
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Logic Pins
5.3
Electrical Characteristics Logic Pins
VDD = 3.0 V to 5.5 V, VS = 6 V to 18 V, TJ = -40 °C to +150 °C
Typical values: VDD = 5.0 V, VS = 13.5 V, TJ = 25 °C
Digital Input (DI) pins = IN
Table 8
Electrical Characteristics: Logic Pins - General
Parameter
Symbol
Values
Typ.
1.3
Unit Note or
Test Condition
Number
Min.
Max.
Digital Input Voltage
Threshold
VDI(TH)
0.8
2
V
See Figure 11 and P_5.4.0.1
Figure 12
1)
Digital Input Clamping
Voltage
VDI(CLAMP1)
–
7
–
V
P_5.4.0.2
IDI = 1 mA
See Figure 11 and
Figure 12
Digital Input Clamping
Voltage
VDI(CLAMP2)
VDI(HYS)
IDI(H)
6.5
–
7.5
0.25
10
8.5
–
V
IDI = 2 mA
See Figure 11 and
Figure 12
1)
P_5.4.0.3
P_5.4.0.4
P_5.4.0.5
P_5.4.0.6
Digital Input Hysteresis
V
See Figure 11 and
Figure 12
Digital Input Current
(“high”)
2
25
25
µA
µA
VDI = 2 V
See Figure 11 and
Figure 12
Digital Input Current (“low”) IDI(L)
2
10
VDI = 0.8 V
See Figure 11 and
Figure 12
1) Not subject to production test - specified by design.
5.4
Electrical Characteristics Logic Pins - Advanced Features
Table 9
Electrical Characteristics: Logic Pins - Advanced
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
SPI pins
Digital Input Voltage
Threshold of Pin CSN
VCSN(TH)
0.8
0.8
0.8
–
1.3
1.3
1.3
7
2
V
V
V
V
V
–
P_5.5.0.1
P_5.5.0.2
P_5.5.0.3
P_5.5.0.4
P_5.5.0.5
1)
Digital Input Voltage
Threshold of Pin SCLK
VSCLK(TH)
VSI(TH)
VCSN(CLAMP1)
VCSN(CLAMP2)
2
Digital Input Voltage
Threshold of Pin SI
2
–
2)
Digital Input Clamping
Voltage of Pin CSN
–
ICSN = 1 mA
ICSN = 2 mA
Digital Input Clamping
Voltage of Pin CSN
6.5
7.5
8.5
Data Sheet
17
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Logic Pins
Table 9
Electrical Characteristics: Logic Pins - Advanced (continued)
Parameter
Symbol
Values
Typ.
7
Unit Note or
Test Condition
Number
Min.
Max.
2)
Digital Input Clamping
Voltage of Pin SCLK
VSCLK(CLAMP1)
–
–
V
P_5.5.0.6
P_5.5.0.7
P_5.5.0.8
P_5.5.0.9
P_5.5.0.11
P_5.5.0.13
P_5.5.0.15
P_5.5.0.10
P_5.5.0.12
P_5.5.0.14
P_5.5.0.16
P_5.5.0.18
P_5.5.0.20
P_5.5.0.22
P_5.5.0.23
P_5.5.0.24
ISCLK = 1 mA
ISCLK = 2 mA
Digital Input Clamping
Voltage of Pin SCLK
VSCLK(CLAMP2) 6.5
7.5
7
8.5
–
V
2)
Digital Input Clamping
Voltage of Pin SI
VSI(CLAMP1)
VSI(CLAMP2)
–
V
ISI = 1 mA
ISI = 2 mA
Digital Input Clamping
Voltage of Pin SI
6.5
–
7.5
0.25
0.25
0.25
10
10
10
10
10
10
–
8.5
–
V
2)
Digital Input Hysteresis of VCSN(HYS)
Pin CSN
V
See Figure 12
2)
Digital Input Hysteresis of VSCLK(HYS)
Pin SCLK
–
–
V
See Figure 12
2)
Digital Input Hysteresis of VSI(HYS)
Pin SI
–
–
V
See Figure 12
VCSN = 0.5 V
Digital Input Current
(“low”) of Pin CSN
-ICSN(L)
-ICSN(H)
ISCLK(L)
ISCLK(H)
ISI(L)
2
25
25
25
25
25
25
0.5
VDD
1
μA
μA
μA
μA
μA
μA
V
Digital Input Current
(“high”) of Pin CSN
2
VCSN = 2.6 V
VSCLK = 0.5 V
VSCLK = 2.6 V
VSI = 0.5 V
Digital Input Current
(“low”) of Pin SCLK
2
Digital Input Current
(“high”) of Pin SCLK
2
Digital Input Current
(“low”) of Pin SI
2
Digital Input Current
(“high”) of Pin SI
ISI(H)
2
VSI = 2.6 V
Digital Output Voltage
(“low”) of Pin SO
VSO(L)
VSO(H)
ISO(OFF)
0
ISO = -0.5 mA
ISO = 0.5 mA
Digital Output Voltage
(“high”) of Pin SO
VDD
-
–
V
0.5 V
Output Tristate Leakage
Current of Pin SO
-1
–
μA
VCSN = VDD
VSO = 0 V or
V
CSN = VDD
VSO = VDD
LHI pin
Digital Input Voltage
Threshold of Pin LHI
VLHI(TH)
1.4
–
1.9
7
2.6
–
V
V
V
–
P_5.5.0.25
P_5.5.0.27
P_5.5.0.28
2)
Digital Input Clamping
Voltage of Pin LHI
VLHI(CLAMP1)
VLHI(CLAMP2)
ILHI = 1 mA
ILHI = 2 mA
Digital Input Clamping
Voltage of Pin LHI
6.5
7.5
8.5
Data Sheet
18
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Logic Pins
Table 9
Electrical Characteristics: Logic Pins - Advanced (continued)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
2)
Digital Input Hysteresis of VLHI(HYS)
Pin LHI
–
0.25
–
V
P_5.5.0.29
P_5.5.0.30
P_5.5.0.32
Digital Input Current
(“high”) of Pin LHI
ILHI(H)
ILHI(L)
10
10
32
24
65
45
µA
µA
VLHI = 5 V
V
DD = 0 V
VLHI = 0.8 V
DD = 0 V
Digital Input Current
(“low”) of Pin LHI
V
External Driver Pins
Digital Output Voltage
(“low”) of Pin EDO
VEDO(L)
VEDO(H)
VEDD(L)
VEDD(H)
0
–
–
–
–
0.5
VDD
0.5
VDD
V
V
V
V
IEDO = -0.2 mA
IEDO = 0.2 mA
IEDD = -0.2 mA
IEDD = 0.2 mA
P_5.5.0.33
P_5.5.0.34
P_5.5.0.36
P_5.5.0.37
Digital Output Voltage
(“high”) of Pin EDO
VDD -
0.5 V
Digital Output Voltage
(“low”) of Pin EDD
0
Digital Output Voltage
(“high”) of Pin EDD
VDD
0.5 V
-
1) Functional test only.
2) Not subject to production test - specified by design.
Data Sheet
19
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Power Supply
6
Power Supply
The BTS71220-4ESE is supplied by two supply voltages:
•
•
Power Supply Voltage (VS)
Digital Supply Voltage (VDD
)
The VS supply line is connected to a battery feed and used for the driving circuitry of the power stages, while
DD is used for the SPI logic and for driving SO pin. VS and VDD supply voltages have an undervoltage detection
V
circuit, which prevents the activation of the associated function in case the measured voltage is below the
undervoltage threshold. More in detail:
•
•
An undervoltage on VDD supply prevents SPI communication. SPI registers are reset to their default values
An undervoltage on VS supply switches OFF all channels, even in Limp Home mode. The channels are
enabled again as soon as VS ≥ VS(OP)
The voltage at pin VS is also monitored. In case of a negative voltage transient on VS resulting in VS < VS(TP) when
the device is out of Sleep mode, any SPI command sent by the microcontroller is not accepted (see
Chapter 6.2 and Chapter 10.5 for further information). An overview of channel behavior according to
different VS and VDD supply voltages is shown in Table 10.
1)
Table 10 Device capability as function of VS and VDD
VDD ≤ VDD(PO)
VDD > VDD(PO)
(VDD(PO) see P_6.4.1.1)
VS ≤ VS(TP)
(VS(TP) see P_6.4.0.5)
Channels are OFF
SPI registers reset
Channels are OFF
SPI registers protected
SPI communication not available
SPI communication available2)
(fSCLK = 0 MHz)
(fSCLK = 5 MHz)
Limp Home mode not available
Channels are OFF
Limp Home mode not available
Channels are OFF
VS(TP) < VS ≤ VS(UV)
(VS(UV) see P_6.4.0.1)
SPI registers reset
SPI registers available
SPI communication not available
SPI communication available
(fSCLK = 0 MHz)
(fSCLK = 5 MHz)
Limp Home mode available
(channels are OFF)
Limp Home mode available
(channels are OFF)
3)
VS > VS(UV)
Channels cannot be controlled by SPI
SPI registers reset
Channels can be controlled by SPI
SPI registers available
SPI communication not available
SPI communication available
(fSCLK = 0 MHz)
(fSCLK = 5 MHz)
Limp Home mode available
Limp Home mode available
1) Valid after a successful supply voltage ramp-up.
2) Write commands are ignored. Furthermore the device responds with STDDIAGonly.
3) The undervoltage condition on VS supply must be considered. See Chapter 6.2.
Data Sheet
20
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Power Supply
6.1
Operation Modes
BTS71220-4ESE has the following operation modes:
•
•
•
•
•
•
Sleep mode
Active mode
Stand-by mode
Ready mode
Limp Home mode
Limp Home Active mode
The transition between operation modes is determined according to these variables:
•
•
•
•
•
•
Digital supply level (VDD
Logic level at INn pins
Logic level at LHI pin
)
Current sense multiplexer state (DCR.MUX)
Output register state (OUT.OUTn)
Configuration registers state
The state diagram including the possible transitions is shown in Figure 14. The behavior of BTS71220-4ESE as
well as some parameters may change in dependence from the operation mode of the device. Furthermore,
due to the undervoltage detection circuitry which monitors VS supply voltage, some changes within the same
operation mode can be seen accordingly.
There are five parameters describing each operation mode of BTS71220-4ESE:
•
•
•
•
•
Status of the output channels
Status of SPI registers
Status of SPI communication
Current consumption at VS pin (measured by IVS in Sleep mode, IGND in all other operative modes)
Current consumption at VDD pin (IVDD
)
Table 11 shows the correlation between operation modes, VS and VDD supply voltages, and the state of the
most important functions (channel status, SPI communication and SPI registers).
Data Sheet
21
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Power Supply
LHI = "high"
Power-up
Unsupplied
DCR.MUX
=
111B or SPI_Reset
LHI = "low"
LHI = "high"
Stand-by
Sleep
DCR.MUX
≠ 111B
OUT.OUTn
= 1B
or INn = "high"
INn = "low" or INn = "low" & SPI_Reset
OUT.OUTn = 0B or
SPI_Reset
INn = "low" &
OUT.OUTn
=
0B
Limp Home
INn = "high"
OUT.OUTn
111B or INn = "high"
111B & INn = "low"
= 1B
DCR.MUX
DCR.MUX
≠
LHI = "high"
LHI = "high" & INn = "low"
Ready
=
INn = "low"
Active
INn = "high"
LHI = "high" & INn = "high"
LHI = "low" & INn = "high"
Limp Home
Active
Note: SPI bits which are not stated are considered to have the default value or are unchanged compared to the previous state. Supplyvoltages are
considered to be in operative range if not specified different. SPI_Reset is performed if VDD < VDD(PO) or HWCR.RST
= 1B
Dashed lines indicate transitions between modes which should not be used for normal operation.
PowerS up pl y_O pMo des .emf
Figure 14 Operation Mode state diagram
Table 11 Device function in relation to operation modes, VDD and VS voltages
Operative Mode Function
VS ≤ VS(TP)
VS(TP) ≤ VS ≤ VS(UV)
OFF
VS > VS(UV)
OFF
Sleep
Channels
OFF
SPI registers available1)
available1)
available1)
OFF
available1)
available1)
OFF
SPI comm.
available1)
Stand-by
Ready
Active
Channels
OFF
SPI registers protected1)
available1)
available1)
available1)
OFF
available1)
available1)
SPI comm.
all commands rejected1) available1)
Channels
OFF
OFF
available1)
SPI registers protected1)
SPI comm.
Channels
all commands rejected1) available1)
OFF
OFF
follow SPI and/or Input
pins
SPI registers protected1)
available1)
available1)
available1)
follow Input pins
reset
SPI comm.
Channels
all commands rejected1) available1)
Limp Home /
Limp Home
Active
OFF
OFF
SPI registers protected1)
reset
(Diagnosis available)1) (Diagnosis available)1)
SPI comm.
all commands
rejected1)2)
read-only1)
read-only1)
1) In case VDD > VDD(PO) otherwise not available or in reset.
2) In case all input pins are set to “low”, SPI communication is in read-only mode.
Data Sheet
22
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Power Supply
6.1.1
Unsupplied
In this state, the device is either unsupplied (no voltage applied to VS pin and VDD pin) or the supply voltages
are both below the corresponding undervoltage threshold.
6.1.2
Power-up
The Power-up condition is entered when one of the supply voltages (VS or VDD) is applied to the device. Both
supplies are rising until they are above the undervoltage thresholds VS(OP) and VDD(PO) therefore the internal
Power-On signals are set. The SPI interface can be accessed after wake up time tWU(PO)
.
6.1.3
Sleep mode
The device is in Sleep mode when all Digital Input pins (INn, LHI) are set to “low” and DCR.MUXis still set to
111B. When BTS71220-4ESE is in Sleep mode, all outputs are OFF. The SPI registers can be programmed if VDD
> VDD(PO). The current consumption is minimum (see parameter IVS(SLEEP)). No Overtemperature or Overload
protection mechanism is active when the device is in Sleep mode. The circuitry that monitors VS versus VS(UV)
and VS versus VS(TP) is disabled. This allows the programming of the registers even if VS < VS(TP)
.
6.1.4
Stand-by mode
The device is in Stand-by mode when DCR.MUX≠ 111B and no command to switch ON a channel was received
(either via SPI or via Input pins). All channels are OFF but the internal supply circuitry is working and therefore
the device current consumption is increased. A command to switch ON one or more outputs is accepted and
executed, bringing the device into Active mode. SPI communication is possible.
6.1.5
Ready mode
In Ready mode, one or more outputs received a command to switch ON (either via SPI or via Input pins if
HWCR.COL= 1B). Nevertheless, all outputs are OFF because of DCR.MUXbits still set to 111B. It is necessary
to change the value of those bits to bring the device into Active mode and switch ON the channels.
Note:
Since OUT register is blanked with DCR.MUX = 111B it is not possible to enter Active mode when
HWCR.COL bit is set to 1B.
6.1.6
Active mode
Active mode is the normal operation mode of BTS71220-4ESE when no Limp Home condition is set and one or
more outputs are switched ON. Device current consumption is specified by parameter IGND(ACTIVE). An
undervoltage condition on VDD supply voltage brings the device into Sleep mode in case all Input pins are set
to “low”.
6.1.7
Limp Home mode
The device enters Limp Home mode when LHI pin is set to “high” for t > tLHI(AC). SPI registers are reset to the
default values when Limp Home mode is entered. The corresponding bit in the standard diagnosis
(STDDIAG.LHI) will be set to 1B once the LHI pin is set to “high” and latched until next STDDIAG
transmission. See Figure 15 for further information. SPI registers are available for read access. ERRDIAG,
STDDIAG, WRNDIAG and ICS can be used for diagnosis in Limp Home.
When the device is in transient protection (VS ≤ VS(TP)) and the LHI pin is set to "high", the STDDIAG.LHIbit
will be set but the device will not change its state to Limp Home mode. Furthermore STDDIAG.VSMONand
STDDIAG.TERbits will be set to report the battery transient protection.
Data Sheet
23
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Power Supply
VS
VS(TP)
t
t < tLHI(AC )
LHI
pin
t
STDDIAG
.LHI
t
Read STDDIAG
Read STDDIAG
Read STDDIAG
SPI
tLHI(AC )
tLHI(AC )
tLHI(AC )
ava ila ble
ava ila ble
re ad-only
re se t
ava ila ble
ava ila ble
all command reject ed
protected
comm.
registers
t
Note: Devic e out o f Sleep mod e when SP I comm. „availab le“
PowerSupply_LimpHomeActive.emf
Figure 15 Limp Home Activation as function of VS
6.1.8
Limp Home Active mode
Limp Home Active mode is entered when the device is in Limp Home mode and one of the IN pins is set to
“high”. Overload, Overtemperature and Overvoltage protections are active. Since SPI registers cannot be
written current sensing is not available.
Data Sheet
24
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Power Supply
6.1.9
Definition of Operation modes transition times
The channel turn-ON time is as defined by parameter tON when BTS71220-4ESE is in Active mode or in Limp
Home mode. In all other cases, it is necessary to add the transition time required to reach one of the two
aforementioned operation modes (as shown in Figure 16).
tLHI(AC)
tWU(PO)
Unsupplied
tTRANS2SLP
tLHI(AC)
tLHI(AC)
+
tTRANS2SLP
Stand-by
Sleep
tTRANS2STBY
+
tTRANS2STBY
tON
tON
+
tTRANS2STBY
tTRANS2SLP
tTRANS2STBY
tTRANS2SLP
Limp Home
tOFF
tOFF
+
tON
tOFF
+
tLHI(AC)
+
tTRANS2STBY
tLHI(AC)
+
Ready
Active
tOFF
+
tLHI(AC)
tLHI(AC)
Limp Home
Active
Note: Dashed lines indicate transition timings between modes which should not be used for normal operation.
PowerS up pl y_O pMo des _Ti min gs.emf
Figure 16 Transition Time diagram
6.2
Undervoltage on VS
Between VS(OP) and VS(UV) the undervoltage mechanism is triggered. If the device is operative (in Active or Limp
Home Active mode) and the supply voltage drops below the undervoltage threshold VS(UV), the internal logic
switches OFF the output channels. When the device is either in Stand-by, Active or Limp Home mode the bit
STDDIAG.VSMONis set and latched until readout. When the state is changed from Sleep to any other state,
a delay of t ≥ tTRANS2STBY has to be considered until STDDIAG.VSMONis valid.
As soon as the supply voltage VS is above the operative threshold VS(OP), the channels having the corresponding
input pin set to “high” or the bit in the OUTregister set to 1B are switched ON again. The restart is delayed with
a time tDELAY(UV) which protects the device in case the undervoltage condition is caused by a short circuit event
(according to AEC-Q100-012), as shown in Figure 17.
Data Sheet
25
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Power Supply
VS
VS(O P)
VS(HY S)
VS(UV )
VS(TP)
t
tDEL AY(UV )
VO UT
t
STDDIAG.
VSMON
t
t
t
Read STDDIAG
Read STDDIAG
STDDIAG.
TER
Read STDDIAG
Read STDDIAG
Opera tio n
Mode
Stand-by
Ac tive
Sleep
Ready
Ac tive
PowerSupply_UVRVS.emf
Figure 17 VS undervoltage behavior
6.3
Reset Condition
One of the following conditions reset the SPI registers to their default value:
•
V
DD is not present or below the undervoltage threshold VDD(PO)
–
SPI registers will be reset to their default values (in the first communication after reset the
STDDIAG.TERwill be set to 1B).
–
Restart counters will not be reset if VS is available or LHI is "high".
•
•
LHI pin is set to “high” for t > tLHI(AC) and VS > VS(TP)
–
–
Configuration registers will be reset to their default values. ERRDIAGand WRNDIAGwill be reset.
Restart counters will be reset.
Reset command (HWCR.RST= 1B) is executed and VS > VS(TP)
–
Configuration registers will be reset to their default values. ERRDIAG, WRNDIAGand STDDIAGwill not
be reset.
–
Restart counters will not be reset.
In case all Input pins are set to “low” after any reset condition, all channels are switched OFF.
Data Sheet
26
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Power Supply
6.4
Electrical Characteristics Power Supply
VDD = 3.0 V to 5.5 V, VS = 6 V to 18 V, TJ = -40 °C to +150 °C
Typical values: VDD = 5.0 V, VS = 13.5 V, TJ = 25 °C
Typical resistive loads connected to the outputs for testing (unless otherwise specified):
9.5 mΩ: RL = 2.6 Ω
22.5 mΩ: RL = 4.8 Ω
Table 12 Electrical Characteristics: Power Supply - General
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
VS pin
Power Supply Undervoltage VS(UV)
Shutdown
1.8
2.0
0.6
2.3
3.0
1.0
3.1
4.1
1.8
V
V
V
VS decreasing
IN = “high” or
OUT.OUTn= 1B
From VDS ≤ 0.5 V to
P_6.4.0.1
V
DS = VS
See Figure 17
Power Supply Minimum
Operating Voltage
VS(OP)
VS increasing
IN = “high”or
OUT.OUTn= 1B
From VDS = VS to
P_6.4.0.3
P_6.4.0.5
V
DS ≤ 0.5 V
See Figure 17
Power Supply Voltage
Threshold for Battery
Transients Protection
VS(TP)
VS decreasing
STDDIAG.VSMON= 1B
STDDIAG.TER= 1B
DCR.MUX≠111B
See Figure 17
1)
Power Supply Undervoltage VS(HYS)
Shutdown Hysteresis
–
0.7
4
–
V
P_6.4.0.6
VS(OP) - VS(UV)
See Figure 17
1)
Power Supply Undervoltage tDELAY(UV)
2.5
5.5
ms
P_6.4.0.10
Recovery Time
dVS/dt ≤ 0.5 V/µs
VS ≥ 0 V
See Figure 17
1)
Breakdown Voltage
between GND and VS Pins in
Reverse Battery
-VS(REV)
16
–
30
V
P_6.4.0.9
IGND(REV) = 14 mA
TJ = 150 °C
1) Not subject to production test - specified by design.
Data Sheet
27
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Power Supply
6.4.1
Electrical Characteristics Power Supply - SPOC™
Table 13 Electrical Characteristics: Power Supply - SPOC™
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
VDD pin
1)
Digital Supply Operating
Voltage
VDD(OP)
VDD(PO)
2.45
1.4
4.3
1.9
1.8
5.5
2.3
2.2
V
V
V
P_6.4.1.1
P_6.4.1.9
P_6.4.1.2
fSCLK = 5 MHz
1)
Digital Supply Power-On
Reset Threshold Voltage
VDD increasing
Digital Supply Undervoltage VDD(UV)
1.3
VDD decreasing
Shutdown
OUT.OUTn= 1B
From VDS ≤ 0.5 V to
VDS = VS
1)
Digital Supply Undervoltage VDD(HYS)
Shutdown Hysteresis
–
–
6
0.1
6.5
7
–
–
8
V
V
V
P_6.4.1.3
P_6.4.1.11
P_6.4.1.12
1)
Digital Supply Clamping
Voltage
VDD(CLAMP1)
VDD(CLAMP2)
tWU(PO)
IDD = 1 mA
IDD = 20 mA
Digital Supply Clamping
Voltage
1)
1)
Power-On Wake Up Time
–
5
10
10
30
30
μs
μs
P_6.4.1.13
P_6.4.1.4
Transition Time to Stand-by tTRANS2STBY
Mode
1)2)
1)
Transition Time to Sleep
Mode
tTRANS2SLP
tLHI(AC)
1
5
60
40
μs
P_6.4.1.5
P_6.4.1.6
Limp Home
10
20
µs
Acknowledgement Time
1) Not subject to production test - specified by design.
2) If output channel enters inductive clamping, clamping time has to be added.
Data Sheet
28
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Power Supply
6.5
Electrical Characteristics Power Supply - Product Specific
VDD = 3.0 V to 5.5 V, VS = 6 V to 18 V, TJ = -40 °C to +150 °C
Typical values: VDD = 5.0 V, VS = 13.5 V, TJ = 25 °C
Typical resistive loads connected to the outputs for testing (unless otherwise specified):
9.5 mΩ: RL = 2.6 Ω
22.5 mΩ: RL = 4.8 Ω
6.5.1
BTS71220-4ESE
Table 14 Electrical Characteristics: Power Supply BTS71220-4ESE
Parameter
Symbol
Values
Typ.
80
Unit Note or
Test Condition
Number
Min.
Max.
Digital Supply Current
Consumption in Normal
Operation
IDD
–
200
µA
fSCLK = 0 MHz
VS > VS(UV)
P_6.5.31.1
VCSN = VDD = 5 V
DCR.MUX≠ 111B
1)2)
Digital Supply Current
Consumption in Normal
Operation during SPI Traffic
(Average)
IDD(ACTIVE)
–
2.5
–
mA
P_6.5.31.2
fSCLK = 5 MHz
VS > VS(UV)
VDD = 5 V
VCSN = 0 V
C
L(SO) = 50 pF
DCR.MUX≠ 111B
Digital Supply Current
Consumption in Sleep Mode
IDD(SLEEP)
–
–
17
17
50
35
µA
µA
fSCLK = 0 MHz
VS > VS(UV)
VCSN = VDD = 5 V
DCR.MUX= 111B
P_6.5.31.3
Digital Supply Current
Consumption in Sleep Mode
IDD(SLEEP)
fSCLK = 0 MHz
VS > VS(UV)
P_6.5.31.12
VCSN = VDD = 5 V
DCR.MUX= 111B
TJ ≤ 85 °C
2)3)
Power Supply Current
IVS(SLEEP)_85
–
0.05
0.7
µA
P_6.5.31.4
Consumption in Sleep Mode
with Loads at TJ ≤ 85 °C
VS = 18 V
VOUT = 0 V
INx = “low”
TJ ≤ 85 °C
Power Supply Current
Consumption in Sleep Mode
with Loads at TJ = 150 °C
IVS(SLEEP)_150
–
–
2
5
100
7
µA
VS = 18 V
VOUT = 0 V
INx = “low”
TJ = 150 °C
P_6.5.31.5
P_6.5.31.6
Operating Current in Active IGND(ACTIVE)
mA
VS = 18 V
Mode (all Channels ON)
VDD = 5 V
INx = “high” or
OUT.OUTn= 1B
Data Sheet
29
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Power Supply
Table 14 Electrical Characteristics: Power Supply BTS71220-4ESE (continued)
Parameter
Symbol
Values
Typ.
80
Unit Note or
Test Condition
Number
Min.
Max.
Operating Current in Ready IGND(READY)
Mode
–
200
µA
VS = 18 V
CSN = VDD = 5 V
P_6.5.31.8
V
fSCLK = 0 MHz
DCR.MUX= 111B
OUT.OUTn= 1B
Operating Current in Stand- IGND(STBY)
–
1.25
2
mA
VS = 18 V
P_6.5.31.9
by Mode
V
DD = 5 V
DCR.MUX≠ 111B
1) Test pattern shifted-in on SI: 0101010101010101 and 1010101010101010.
2) Not subject to production test - specified by design.
3) If VDD < VDD(PO), LHI = ”low” and any restart counter > 0, IGND(STBY) has to be considered.
Data Sheet
30
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Power Stages
7
Power Stages
The high-side power stages are built using a N-channel vertical Power MOSFET with charge pump.
7.1
Output ON-State Resistance
The ON-state resistance RDS(ON) depends mainly on junction temperature TJ. Figure 18 shows the variation of
RDS(ON) across the whole TJ range. The value “2” on the y-axis corresponds to the maximum RDS(ON) measured
at TJ = 150 °C.
RDS(ON) variation over TJ
2.20
Reference value:
"2" = RDS(ON),MAX @ 150 °C
2.00
1.80
1.60
1.40
1.20
1.00
0.80
0.60
0.40
Typical
0.20
0.00
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160
Junction Temperature (°C)
Figure 18 RDS(ON) variation factor
The behavior in Reverse Polarity is described in Chapter 8.4.1.
7.2
Switching loads
7.2.1
Switching Resistive Loads
When switching resistive loads, the switching times and slew rates shown in Figure 19 can be considered. The
switch energy values EON and EOFF are proportional to load resistance and times tON and tOFF
.
Data Sheet
31
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Power Stages
IN /
OUT.OUTn
VIN(TH)
VIN(HYS)
t
VOUT
tON
90% of VS
tOFF(DELAY)
70% of VS
70% of VS
30% of VS
(dV/dt)ON
-(dV/dt)OFF
30% of VS
tOFF
tON(DELAY)
10% of VS
t
PDMOS
EON
EOFF
t
Figure 19 Switching a Resistive Load
7.2.2
Switching Inductive Loads
When switching OFF inductive loads with high-side switches, the voltage VOUT drops below ground potential,
because the inductance intends to continue driving the current. To prevent the destruction of the device due
to overvoltage, a voltage clamp mechanism is implemented. The clamping structure limits the negative
output voltage so that VDS = VDS(CLAMP). Figure 20 shows a concept drawing of the implementation. The
clamping structure protects the device in all operation modes listed in Chapter 6.1.
VS
High-side
Channel
VS
VDS
VSIS(CLAMP)
VDS(CLAMP)
IS
IL
VOU Tn
VS(CLAMP)
OUTn
GND
L,
RL
IL
PowerStage_Clamp_INTDIO.emf
Figure 20 Output Clamp concept
Data Sheet
32
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Power Stages
During demagnetization of inductive loads, energy has to be dissipated in BTS71220-4ESE. The energy can be
calculated with Equation (7.1):
RL IL
ln 1 – ------------------------------------------- + IL
VS – VDS(CLAMP)
-------------------------------------------
RL
L
RL
æ
ö
------
E = VDS(CLAMP)
(7.1)
è
ø
VS – VDS(CLAMP)
The maximum energy, therefore the maximum inductance for a given current, is limited by the thermal design
of the component.
7.2.3
Output Voltage Limitation
To increase the current sense accuracy, VDS voltage is monitored. When the output current IL decreases while
the channel is diagnosed (channel selected via DCR.MUX- see Figure 21) bringing VDS equal or lower than
VDS(SLC), the output DMOS gate is partially discharged. This increases the output resistance so that VDS = VDS(SLC)
even for very small output currents. The VDS increase allows the current sensing circuitry to work more
efficiently, providing better kILIS accuracy for output current in the low range.
IN /
OUT.OUTn
t
CS
DCR.MUX
110
000
110
t
IL
t
tsIS(ON)
tsIS(OFF)
VDS
VS
VDS(SLC)
t
PowerStage_GBR_diag.emf
Figure 21 Output Voltage Limitation activation during diagnosis
7.2.4
Switching Capacitive Loads
When switching ON a capacitive load, the capacitance is causing a high inrush current. The current is
depending on the value of the capacitance, the ESR, the impedance of the system and the slew rate of the
driver. To improve the load driving capability, BTS71220-4ESE offers a slew rate control feature. When the slew
rate bit SRC.SRCnis set, the slew rate of the respective channel is reduced to the half (see Chapter 7.4.1).
Data Sheet
33
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Power Stages
7.3
Advanced Switching Characteristics
7.3.1
Inverse Current behavior
When VOUT > VS, a current IINV flows into the power output transistor (see Figure 22). This condition is known
as “Inverse Current”.
If the channel is in OFF state, the current flows through the intrinsic body diode generating high power losses
therefore an increase of overall device temperature. This may lead to a switch OFF of unaffected channels due
to Overtemperature. If the channel is in ON state, RDS(INV) can be expected and power dissipation in the output
stage is comparable to normal operation in RDS(ON)
.
During Inverse Current condition, the channel remains in ON or OFF state as long as IINV < IL(INV)
.
With InverseON, it is possible to switch ON the channel during Inverse Current condition as long as IINV < IL(INV)
(see Figure 23).
VBAT
VS
Gate
Driver
VINV = VOU T > VS
IINV
Device
Logic
INV
Comp.
OUT
GND
PowerStage_InvCurr_INTDIO.emf
Figure 22 Inverse Current Circuitry
Data Sheet
34
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Power Stages
IN
IN
CASE 1 : Switch is ON
CASE 2 : Switch is OFF
OFF
ON
t
t
t
IL
IL
NORMAL
NORMAL
NORMAL
NORMAL
t
INVERSE
OFF
INVERSE
ON
DMOS state
DMOS state
t
t
CASE 3 : Switch ON into Inverse Current
CASE 4 : Switch OFF into Inverse Current
IN
IN
OFF
ON
OFF
ON
t
t
IL
IL
NORMAL
NORMAL
NORMAL
NORMAL
t
t
t
t
INVERSE
INVERSE
DMOS state
DMOS state
ON
OFF
OFF
ON
PowerStage_InvCurr_INVON.emf
Figure 23 InverseON - Channel behavior in case of applied Inverse Current
Note:
No protection mechanism like Overtemperature or Overload protection is active during applied
Inverse Currents.
7.3.2
Switching Channels in Parallel
When switching channels in parallel to drive a single load it may happen that the two channels switch OFF
asynchronously in case of a fault condition which brings additional stress to the channel that switches OFF
last. In order to avoid this condition, it is possible to synchronize the protection of two channels when used in
parallel. There are 2 bits in the SPI (PCS.PCCn), which allow to synchronize channels 0&3 and 1&2. When the
corresponding PCS.PCCnbit is set, the switch-OFF and restart of the channels are synchronized and the
current trip levels will be reduced to IL(OVL3). In case the current trip level for one channel is set to the low level
(OCR.OCTn= 1B), the current for both channels will be reduced to IL(OVL2). Since the restart counters of the
channels in parallel are synchronized, both channels will latch-OFF as soon one counter has reached
nRESTART(CR). Due to this reason it is recommended to clear counters before switching channels in parallel. In
case the slew rate adjustment for one channels is used, (SRC.SRCn= 1B), both channels operating in parallel
mode will use the adjusted slew rate. When channels are switched in parallel (PCS.PCCn= 1B), the Output
Voltage Drop Limitation at Small Load Currents is disabled. Therefore the current sense ratio specifications at
lower currents are not valid. See Chapter 9.7 for further information. To improve current sense accuracy in
parallel channel operation, parallel mode has to be deactivated (PCS.PCCn= 0B). Since the current sense of
the two channels used in parallel is not synchronized, the total current has to be calculated out of the current
sense reading of each single channel. Unless otherwise specified parameter deviations are possible when
parallel mode is activated.
Data Sheet
35
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Power Stages
When two channels are used in parallel, the total current capability IL(NOM) is doubled. It has to be ensured that
the outputs used in parallel mode are connected together with a symmetric and low impedance connection
either on the PCB or in the wire harness.
7.3.3
Cross Current robustness with H-Bridge configuration
When BTS71220-4ESE is used as high-side switch e.g. in a bridge configuration (therefore paired with a low-
side switch as shown in Figure 24), the maximum slew rate applied to the output by the low-side switch must
be lower than | dVOUT / dt |. Otherwise the output stage may turn ON in linear mode (not in RDS(ON)) while the
low-side switch is commutating. This creates an unprotected overheating for the DMOS due to the cross-
conduction current.
VBAT
R/L cable
VS
T
T
INy
OFF
ON (DC)
INx
OUTy
OUTx
| dVOUT / dt |
Cross
Current
Current through Motor
M
ON (PWM)
OFF
Power St age_Passive Slew_SPOC.emf
Figure 24 High-Side switch used in Bridge configuration
Data Sheet
36
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Power Stages
7.4
Electrical Characteristics Power Stages
VDD = 3.0 V to 5.5 V, VS = 6 V to 18 V, TJ = -40 °C to +150 °C
Typical values: VDD = 5.0 V, VS = 13.5 V, TJ = 25 °C
Typical resistive loads connected to the outputs for testing (unless otherwise specified):
9.5 mΩ: RL = 2.6 Ω
22.5 mΩ: RL = 4.8 Ω
Table 15 Electrical Characteristics: Power Stages - General
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
Voltages
Drain to Source Clamping VDS(CLAMP)_-40 33
Voltage at TJ = -40 °C
36.5
38
42
V
V
IL = 5 mA
P_7.4.0.1
P_7.4.0.2
TJ = -40°C
See Figure 20
1)
Drain to Source Clamping VDS(CLAMP)_25 35
Voltage at TJ ≥ 25 °C
44
IL = 5 mA
TJ ≥ 25°C
See Figure 20
1) Tested at TJ = 150°C.
7.4.1
Electrical Characteristics Power Stages - SPOC™
Table 16 Electrical Characteristics: Power Stages - SPOC™
Parameter
Symbol
Values
Typ.
Unit Note or
Number
Test Condition
Min.
Max.
Timings
Switch-ON Delay
tON(DELAY)
10
30
40
60
μs
μs
VS = 13.5 V
VOUT = 10% VS
PCS.PCCn= 0B
2)
P_7.4.2.1
Switch-ON Delay
(parallel mode)
tON(DELAY)
10
80
P_7.4.2.16
VS = 13.5 V
VOUT = 10% VS
PCS.PCCn= 1B
Switch-OFF Delay
Switch-ON Time
tOFF(DELAY)
tON
10
20
30
55
60
μs
μs
VS = 13.5 V
VOUT = 90% VS
P_7.4.2.2
P_7.4.2.3
100
VS = 13.5 V
VOUT = 90% VS
SRC.SRCn= 0B
PCS.PCCn= 0B
2)
Switch-ON Time
(parallel mode)
tON
20
70
125
μs
P_7.4.2.20
VS = 13.5 V
VOUT = 90% VS
SRC.SRCn= 0B
PCS.PCCn= 1B
Data Sheet
37
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Power Stages
Table 16 Electrical Characteristics: Power Stages - SPOC™ (continued)
Parameter
Symbol
Values
Typ.
75
Unit Note or
Test Condition
Number
Min.
Max.
Switch-ON Time
tON
30
150
μs
μs
μs
μs
VS = 13.5 V
OUT = 90% VS
SRC.SRCn= 1B
P_7.4.2.4
V
Switch-OFF Time
Switch-OFF Time
tOFF
tOFF
ΔtSW
20
55
75
0
100
150
50
VS = 13.5 V
VOUT = 10% VS
SRC.SRCn= 0B
P_7.4.2.6
P_7.4.2.7
P_7.4.2.9
30
VS = 13.5 V
VOUT = 10% VS
SRC.SRCn= 1B
Switch-ON/OFF Matching
-50
VS = 13.5 V
tON - tOFF
PCS.PCCn= 0B
Voltage Slope
Switch-ON Slew Rate
(dV/dt)ON
(dV/dt)ON
0.3
0.6
0.3
0.6
0.9
V/μs VS = 13.5 V
P_7.4.2.11
P_7.4.2.12
P_7.4.2.14
P_7.4.2.15
VOUT = 30% to 70%
of VS
SRC.SRCn= 0B
Switch-ON Slew Rate
Switch-OFF Slew Rate
Switch-OFF Slew Rate
0.15
0.45
0.9
V/μs VS = 13.5 V
VOUT = 30% to 70%
of VS
SRC.SRCn= 1B
-(dV/dt)OFF 0.3
V/μs VS = 13.5 V
OUT = 70% to 30%
V
of VS
SRC.SRCn= 0B
-(dV/dt)OFF 0.125 0.3
0.45
V/μs VS = 13.5 V
OUT = 70% to 30%
V
of VS
SRC.SRCn= 1B
1)
Slew Rate Matching
Δ(dV/dt)SW -30
0
30
18
%
P_7.4.2.17
P_7.4.2.18
VS = 13.5 V
Voltages
2)
Output Voltage Drop
Limitation at Small Load
Currents
VDS(SLC)
2
10
mV
IL = IL(OL) = 20 mA
1) Δ(dV/dt)SW = ((dV/dt)ON - (dV/dt)OFF) / (((dV/dt)ON + (dV/dt)OFF) / 2).
2) Not subject to production test - specified by design.
Data Sheet
38
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Power Stages
7.5
Electrical Characteristics - Power Output Stages
VDD = 3.0 V to 5.5 V, VS = 6 V to 18 V, TJ = -40 °C to +150 °C
Typical values: VDD = 5.0 V, VS = 13.5 V, TJ = 25 °C
Typical resistive loads connected to the outputs for testing (unless otherwise specified):
9.5 mΩ: RL = 2.6 Ω
22.5 mΩ: RL = 4.8 Ω
7.5.1
Power Output Stage - 9.5 mΩ
Table 17 Electrical Characteristics: Power Stages - 9.5 mΩ
Parameter
Symbol
Values
Unit Note or
Test Condition
Number
Min. Typ. Max.
Output characteristics
1)
ON-State Resistance at
TJ = 25 °C
RDS(ON)_25
–
–
–
–
9.5
–
–
mΩ
P_7.5.15.1
P_7.5.15.2
P_7.5.15.3
P_7.5.15.4
TJ = 25 °C
ON-State Resistance at
TJ = 150 °C
RDS(ON)_150
RDS(ON)_CRANK
RDS(INV)_25
16.5
20.5
–
mΩ TJ = 150 °C
ON-State Resistance in
Cranking
–
mΩ TJ = 150 °C
VS = 3.1 V
1)
ON-State Resistance in
9.5
mΩ
Inverse Current at TJ = 25 °C
TJ = 25 °C
IL = -IL(NOM)
1)
ON-State Resistance in
Inverse Current at TJ = 150 °C
RDS(INV)_150
–
–
–
20.5
–
mΩ
P_7.5.15.5
P_7.5.15.6
TJ = 150 °C
IL = -IL(NOM)
1)
ON-State Resistance in
RDS(REV)_25
19
mΩ
Reverse Polarity at TJ = 25 °C
TJ = 25 °C
VS = -13.5 V
IL = -IL(NOM)
RSENSE = 1.2 kΩ
1)
ON-State Resistance in
Reverse Polarity at
TJ = 150 °C
RDS(REV)_150
–
–
33
mΩ
P_7.5.15.7
TJ = 150 °C
VS = -13.5 V
IL = -IL(NOM)
RSENSE = 1.2 kΩ
1)
Nominal Load Current per IL(NOM)
Channel (all Channels
Active)
–
–
5
–
A
P_7.5.15.8
P_7.5.15.9
TA = 85 °C
TJ ≤ 150 °C
1)
Output Leakage Current at IL(OFF)_85
TJ ≤ 85 °C
0.06
0.3
μA
VOUT = 0 V
V
IN = “low” and
OUT.OUTn= 0B
TA ≤ 85 °C
Data Sheet
39
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Power Stages
Table 17 Electrical Characteristics: Power Stages - 9.5 mΩ (continued)
Parameter
Symbol
Values
Typ.
–
Unit Note or
Test Condition
Number
Min.
Max.
Output Leakage Current at IL(OFF)_150
TJ = 150 °C
–
12
μA
VOUT = 0 V
IN = “low” and
P_7.5.15.10
V
OUT.OUTn= 0B
TA = 150 °C
1)
Inverse Current Capability
IL(INV)
–
5
–
A
P_7.5.15.11
VS < VOUT
IN = “high” or
OUT.OUTn= 1B
Voltage Slope
1)
Passive Slew Rate (e.g. for
Half Bridge Configuration)
|dVOUT / dt|
–
–
–
10
V/μs
P_7.5.15.12
P_7.5.15.13
VS = 13.5 V
Voltages
1)
Drain Source Diode Voltage |VDS(DIODE)
|
500
600
mV
IL = -190 mA
TJ = 150 °C
Switching Energy
1)
Switch-ON Energy
EON
–
–
0.53
0.68
–
–
mJ
mJ
P_7.5.15.14
P_7.5.15.15
VS = 18 V
SRC.SRCn= 0B
PCS.PCCn= 0B
1)
Switch-OFF Energy
EOFF
VS = 18 V
SRC.SRCn= 0B
PCS.PCCn= 0B
1) Not subject to production test - specified by design.
7.5.2
Power Output Stage - 22.5 mΩ
Table 18 Electrical Characteristics: Power Stages - 22.5 mΩ
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
Output characteristics
1)
ON-State Resistance at
TJ = 25 °C
RDS(ON)_25
–
–
–
–
22.5
–
–
mΩ
mΩ
mΩ
mΩ
P_7.5.16.1
P_7.5.16.2
P_7.5.16.3
P_7.5.16.4
TJ = 25 °C
TJ = 150 °C
ON-State Resistance at
TJ = 150 °C
RDS(ON)_150
RDS(ON)_CRANK
RDS(INV)_25
38
44
–
ON-State Resistance in
Cranking
–
TJ = 150 °C
VS = 3.1 V
1)
ON-State Resistance in
22.5
Inverse Current at TJ = 25 °C
TJ = 25 °C
IL = -IL(NOM)
Data Sheet
40
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Power Stages
Table 18 Electrical Characteristics: Power Stages - 22.5 mΩ (continued)
Parameter
Symbol
Values
Typ.
–
Unit Note or
Test Condition
Number
Min.
Max.
1)
ON-State Resistance in
RDS(INV)_150
–
44
mΩ
P_7.5.16.5
Inverse Current at TJ = 150 °C
TJ = 150 °C
IL = -IL(NOM)
1)
ON-State Resistance in
Reverse Polarity at TJ = 25 °C
RDS(REV)_25
RDS(REV)_150
IL(NOM)
–
–
45
–
–
mΩ
P_7.5.16.6
P_7.5.16.7
TJ = 25 °C
VS = -13.5 V
IL = -IL(NOM)
RSENSE = 1.2 kΩ
1)
ON-State Resistance in
Reverse Polarity at
TJ = 150 °C
70
mΩ
TJ = 150 °C
VS = -13.5 V
IL = -IL(NOM)
RSENSE = 1.2 kΩ
1)
Nominal Load Current per
Channel (all Channels
Active)
–
–
3
–
A
P_7.5.16.8
P_7.5.16.9
TA = 85 °C
TJ ≤ 150 °C
1)
Output Leakage Current at IL(OFF)_85
TJ ≤ 85 °C
0.03
0.15
μA
VOUT = 0 V
V
IN = “low” and
OUT.OUTn= 0B
TA ≤ 85 °C
Output Leakage Current at IL(OFF)_150
TJ = 150 °C
–
–
–
3
10
–
μA
VOUT = 0 V
P_7.5.16.10
P_7.5.16.11
V
IN = “low” and
OUT.OUTn= 0B
TA = 150 °C
1)
Inverse Current Capability
IL(INV)
A
VS < VOUT
IN = “high” or
OUT.OUTn= 1B
Voltage Slope
1)
Passive Slew Rate (e.g. for
Half Bridge Configuration)
|dVOUT / dt|
–
–
–
10
V/μs
P_7.5.16.12
P_7.5.16.13
VS = 13.5 V
Voltages
1)
Drain Source Diode Voltage |VDS(DIODE)
|
500
600
mV
IL = -190 mA
TJ = 150 °C
Data Sheet
41
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Power Stages
Table 18 Electrical Characteristics: Power Stages - 22.5 mΩ (continued)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
Switching Energy
1)
Switch-ON Energy
EON
–
0.30
–
mJ
mJ
P_7.5.16.14
VS = 18 V
SRC.SRCn= 0B
PCS.PCCn= 0B
1)
Switch-OFF Energy
EOFF
–
0.38
–
P_7.5.16.15
VS = 18 V
SRC.SRCn= 0B
PCS.PCCn= 0B
1) Not subject to production test - specified by design.
Data Sheet
42
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Protection
8
Protection
The BTS71220-4ESE is protected against Overtemperature, Overload, Reverse Battery (with ReverseON) and
Overvoltage. Overtemperature and Overload protections are working when the device is not in Sleep mode.
Overvoltage protection works in all operation modes. Reverse Battery protection works when the GND and VS
pins are reverse supplied.
8.1
Overtemperature Protection
The device incorporates both an absolute (TJ(ABS)) and a dynamic (TJ(DYN)) temperature protection circuitry for
each channel. An increase of junction temperature TJ above either one of the two thresholds (TJ(ABS) or TJ(DYN)
)
switches OFF the overheated channel to prevent destruction. The corresponding WRNDIAG.WRNnbits are set
and cleared on read. The channel remains switched OFF until junction temperature has reached the “Restart”
condition described in Table 19. The behavior is shown in Figure 25 (absolute Overtemperature Protection)
and Figure 26 (dynamic Overtemperature Protection). TJ(REF) is the reference temperature used for dynamic
temperature protection.
IN /
OUT.OUTn
t
IL
IL(O VL)
t
TJ
TJ(ABS)
t
IIS
t
Internal
counter
0
0
1
2
t
WRNDIAG.WRNn
1
0
t
Read WRNDIAG
Protect ion_OT_Resta rt.emf
Figure 25 Overtemperature Protection (Absolute)
Data Sheet
43
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Protection
IN /
OUT.OUTn
t
IL
IL(O VL)
t
TJ
TJ(ABS)
TJ(start)
TJ(REF)
t
t
IIS
Internal
counter
0
0
1
2
3
4
5
6
nRESTART(CR) + 1
0
0
1
1
t
t
t
WRNDIAG.WRNn
ERRDIAG.ERRn
1
0
1
1
Read WRNDIAG
Read WRNDIAG
0
1
0
HWCR.CLC = 1B
Protection_dT_Restart.emf
Figure 26 Overtemperature Protection (Dynamic)
When the Overtemperature protection circuitry allows the channel to be switched ON again, the restart
strategy described in Chapter 8.3.1 is followed.
Data Sheet
44
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Protection
8.2
Overload Protection
The BTS71220-4ESE is protected in case of Overload or short circuit to ground. Two Overload thresholds are
defined (see Figure 27) and selected automatically depending on the voltage VDS across the power DMOS:
•
•
I
L(OVL0) when VDS < 13 V
IL(OVL1) when VDS > 22 V
In addition, the Overload threshold can be reduced by setting OCR.OCTn.
Overload threshold variation ("1" = IL(OVL0) @ VDS = 5 V)
1.1
IL(OVL0)
OCR.OCTn = 0
OCR.OCTn = 1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
IL(OVL1)
4
8
12
16
20
24
28
Drain Source Voltage (V)
Figure 27 Overload current thresholds
When IL ≥ IL(OVL) (either IL(OVL0) or IL(OVL1)), the channel is switched OFF. The channel is allowed to restart
according to the restart strategy described in Chapter 8.3.1.
8.3
Protection and Diagnosis in case of Fault
Any event that triggers a protection mechanism (either Overtemperature or Overload) has 3 consequences:
•
•
•
The affected channel switches OFF and the internal counter is incremented
The current sense of the affected channel is set to high impedance
The corresponding WRNDIAG.WRNnare set to 1B and latched until readout.
The channel can be switched ON again if all the protection mechanisms fulfill the “restart” conditions
described in Table 19 and the internal restart counter is enabled (RCD.RCDnset to 0B).
Data Sheet
45
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Protection
Table 19 Protection “Restart” Condition
Fault condition
Switch OFF event
TJ ≥ TJ(ABS) or (TJ - TJ(REF)) ≥ TJ(DYN)
“Restart” Condition
Overtemperature
TJ < TJ(ABS) and (TJ - TJ(REF)) < TJ(DYN)
(including hysteresis)
nRESTART < nRESTART(CR)
RCD.RCDn= 0
Overload
IL ≥ IL(OVL)
IL < 50 mA
TJ within TJ(ABS) and TJ(DYN) ranges
(including hysteresis)
nRESTART < nRESTART(CR)
RCD.RCDn= 0
8.3.1
Restart Strategy
When INx or OUT.OUTnis set to “high”, the corresponding channel is switched ON. In case of fault condition
the output stage is switched OFF. The channel is allowed to restart only in case the “restart” conditions for the
protection mechanisms are fulfilled (see Table 19). The WRNDIAG.WRNnis set during Overcurrent shutdown.
It is reset when the internal fault signal is cleared and the WRNDIAGis transmitted, unless latched state is
reached by exceeding nRESTART(CR). The next Overcurrent event set the WRNDIAG.WRNnagain. In case the
automatic restarts are not required, they can be deactivated by setting RCD.RCDnto 1B. When RCD.RCDnis
set to 1B, the restart counter will be reset. When a channel reaches latched state, the corresponding
ERRDIAG.ERRnbit is set. The restart latch and counter are cleared by setting the SPI bit HWCR.CLCto 1B. If
the input pin is “high” or OUT.OUTnis still set to 1B, the channel is switched ON immediately after the
command that set HWCR.CLC bit to 1B. To ensure an adequate cool down after latch-OFF condition,
application software needs to wait for t > tRETRY before restarting the channel.
The restart strategy is shown in Figure 28.
IN/
OUT.OUTn
t
Short circuit
to ground
t
1)
t > tRETRY
IL
IL(O VL)
t
t
0
0
0
0
0
0
Internal
counter
0
0
0
1
2
3
4
4
5
5
6
6
nRESTART(CR) + 1
1
1
2
2
... nRESTART(CR) + 1
1
1
0
0
0
WRNDIAG.WRNn
RCS.RCSn
1
0
1
1
t
Read WRNDIAG
1
2
3
7
...
7
1
t
HWCR.CLC = 1B
1) Note: Maximum peak current depend ing on s ystem impedance
RCD.RCDn
=
1B
HWCR.CLC = 1B
Protect ion_Resta rt.emf
Figure 28 Restart Strategy timing diagram
Data Sheet
46
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Protection
tL HI(AC)
t
<
tDEL AY(CR)
t
≥
tDEL AY(CR)
t ≥ tRETRY
IN
t
t
t
LHI
Short circuit
to ground
1)
IL
IL(O VL)
t
t
Internal
counter
0
0
1
2
3
4
5
0
6
nRESTART(CR) + 1
0
1
2
3
4
5
6
nRESTART(CR) + 1
0
0
1
2
3
4
5
6 nRESTART(CR) + 1
WRNDIAG.WRNn
1
1
1
0
1
1
1
t
Read WRNDIAG
Read WRNDIAG
Read WRNDIAG
Read WRNDIAG
Read WRNDIAG
Protection_Restart_LH.emf
1) Note: Maxim um peak current depend ing on s ystem impeda nce
Figure 29 Restart Strategy timing diagram in Limp Home
8.4
Additional protections
8.4.1
Reverse Polarity Protection
In Reverse Polarity condition (also known as Reverse Battery), the output stages are switched ON (see
parameter RDS(REV)) because of ReverseON feature which limits the power dissipation in the output stages.
Each ESD diode of the logic contributes to total power dissipation. The reverse current through the output
stages must be limited by the connected loads. The current through digital power supply VDD and Digital Input
pins has to be limited as well by an external resistor (please refer to the Absolute Maximum Ratings listed in
Chapter 4.1 and to Application Information in Chapter 11).
Figure 30 shows a typical application including a device with ReverseON. A current flowing into GND pin
(-IGND) during Reverse Polarity condition is necessary to activate ReverseON, therefore a resistive path
between module ground and device GND pin must be present.
Data Sheet
47
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Protection
-VBAT(REV)
5V (reverse protected)
IVDD
RVDD
VDD
VS
High-side Channel
VDD
µC
IDI
DO
DI
RDI
ReverseON
OUTn
-IO UT
GND
IS
GND
L, C, R
-IIS
-IGN D
Protection_RevBatt_SPI.emf
Figure 30 Reverse Battery Protection (application example)
8.4.2
Overvoltage Protection
In the case of supply voltages between VS(EXT,UP) and VBAT(LD), the output transistors are still operational and
follow the input pins or the OUTregister. In addition to the output clamp for inductive loads as described in
Chapter 7.2.2, there is a clamp mechanism available for Overvoltage protection for the logic and the output
channels, monitoring the voltage between VS and GND pins (VS(CLAMP)).
Data Sheet
48
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Protection
8.5
Protection against loss of connection
8.5.1
Loss of Battery and Loss of Load
The loss of connection to battery or to the load has no influence on device robustness when load and wire
harness are purely resistive. In case of driving an inductive load, the energy stored in the inductance must be
handled. BTS71220-4ESE can handle the inductivity of the wire harness up to 10 µH with IL(NOM). In case of
applications where currents and/or the aforementioned inductivity are exceeded, an external suppressor
diode (like diode DZ2 shown in Chapter 11) is recommended to handle the energy and to provide a well-
defined path to the load current.
Note:
In case of a lost battery connection the VS monitoring function protects the SPI registers as soon the
device is out of Sleep mode. This means that any command sent to the device will be ignored and the
device will just send back the STDDIAG. Furthermore, the status of the LHI pin is blanked, which
means that it is not possible to enter Limp Home mode.
8.5.2
Loss of Ground
In case of loss of device ground, it is recommended to have a resistor connected between any Digital Input pin
and the microcontroller to ensure a channel switch OFF (as described in Chapter 11).
Note:
In case any Digital Input pin is pulled to ground (either by a resistor or active) a parasitic ground path
is available, which could keep the device operational during loss of device ground. The same
behavior applies for the SPI functionality.
Data Sheet
49
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Protection
8.6
Electrical Characteristics Protection
VDD = 3.0 V to 5.5 V, VS = 6 V to 18 V, TJ = -40 °C to +150 °C
Typical values: VDD = 5.0 V, VS = 13.5 V, TJ = 25 °C
Typical resistive loads connected to the outputs for testing (unless otherwise specified):
9.5 mΩ: RL = 2.6 Ω
22.5 mΩ: RL = 4.8 Ω
Table 20 Electrical Characteristics: Protection - General
Parameter
Symbol
Values
Typ.
175
Unit Note or
Test Condition
Number
Min.
Max.
1)2)
Thermal Shutdown
Temperature (Absolute)
TJ(ABS)
150
200
°C
P_8.6.0.1
P_8.6.0.2
P_8.6.0.3
P_8.6.0.6
See Figure 25
3)
Thermal Shutdown
Hysteresis (Absolute)
THYS(ABS)
TJ(DYN)
–
–
30
–
K
See Figure 25
3)
Thermal Shutdown
Temperature (Dynamic)
80
–
K
See Figure 26
Power Supply Clamping
Voltage at TJ = -40 °C
VS(CLAMP)_-40 33
36.5
42
V
IVS = 5 mA
TJ = -40 °C
See Figure 20
2)
Power Supply Clamping
Voltage at TJ ≥ 25 °C
VS(CLAMP)_25 35
38
44
V
V
P_8.6.0.7
P_8.6.0.8
IVS = 5 mA
TJ ≥ 25 °C
See Figure 20
3)
Power Supply Voltage
Threshold for Overcurrent
Threshold Reduction in case
of Short Circuit
VS(JS)
20.5
22.5
24.5
Setup acc. to AEC-
Q100-012
1) Functional test only.
2) Tested at TJ = 150°C only.
3) Not subject to production test - specified by design.
8.6.1
Electrical Characteristics Protection - SPOC™
Table 21 Electrical Characteristics: Protection - SPOC™
Parameter
Symbol
Values
Typ.
70
Unit Note or
Test Condition
Number
Min.
Max.
1)
Counter Reset Delay Time
after Fault Condition in Limp
Home
tDELAY(CR)
40
100
ms
P_8.6.2.1
LHI = “high”
INx = “low”
1)
Automatic Restarts in Case nRESTART(CR)
of Fault after a Counter
Reset
–
6
–
–
P_8.6.2.2
1) Not subject to production test - specified by design.
Data Sheet
50
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Protection
8.7
Electrical Characteristics Protection - Power Output Stages
VDD = 3.0 V to 5.5 V, VS = 6 V to 18 V, TJ = -40 °C to +150 °C
Typical values: VDD = 5.0 V, VS = 13.5 V, TJ = 25 °C
Typical resistive loads connected to the outputs for testing (unless otherwise specified):
9.5 mΩ: RL = 2.6 Ω
22.5 mΩ: RL = 4.8 Ω
8.7.1
Protection Power Output Stage - 9.5 mΩ
Table 22 Electrical Characteristics: Protection - 9.5 mΩ
Parameter
Symbol
Values
Typ.
89
Unit Note or
Test Condition
Number
Min.
Max.
1)
Overload Detection Current IL(OVL0)
79
99
A
P_8.7.15.3
High Level
OCR.OCTn= 0B
TJ = -40 °C to 50 °C
dI/dt = 0.4 A/µs
2)
Overload Detection Current IL(OVL0)
65
72
79
A
P_8.7.15.4
High Level
OCR.OCTn= 0B
TJ = 150 °C
dI/dt = 0.4 A/µs
2)
Overload Detection Current IL(OVL2)
Low Level
36
38
45
54
54
62
A
A
P_8.7.15.2
P_8.7.15.6
OCR.OCTn= 1B
dI/dt = 0.4 A/µs
2)3)
Overload Detection Current IL(OVL3)
High Level (parallel mode)
OCR.OCTn= 0B
PCS.PCCn= 1B
dI/dt = 0.4 A/µs
2)
Overload Detection Current IL(OVL1)
at High VDS
–
–
54
54
–
–
A
A
P_8.7.15.5
P_8.7.15.7
dI/dt = 0.4 A/µs
2)
Overload Detection Current IL(OVL_JS)
Jump Start Condition
OCR.OCTn= 0B
VS > VS(JS)
dI/dt = 0.4 A/µs
1) Tested at TJ = -40 °C.
2) Not subject to production test - specified by design.
3) IL(OVL3) applies for one channel. Total current for two channels in parallel IL(OVL) ≤ 2 x IL(OVL3)
.
Data Sheet
51
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Protection
8.7.2
Protection Power Output Stage - 22.5 mΩ
Table 23 Electrical Characteristics: Protection - 22.5 mΩ
Parameter
Symbol
Values
Typ.
48
Unit Note or
Test Condition
Number
Min.
Max.
1)
Overload Detection Current IL(OVL0)
44
53
A
P_8.7.16.3
High Level
OCR.OCTn= 0B
TJ = -40 °C to 50 °C
dI/dt = 0.2 A/µs
2)
Overload Detection Current IL(OVL0)
35
39
44
A
P_8.7.16.4
High Level
OCR.OCTn= 0B
TJ = 150 °C
dI/dt = 0.2 A/µs
2)
Overload Detection Current IL(OVL2)
Low Level
19
22
24
31
29
36
A
A
P_8.7.16.2
P_8.7.16.6
OCR.OCTn= 1B
dI/dt = 0.2 A/µs
2)3)
Overload Detection Current IL(OVL3)
High Level (parallel mode)
OCR.OCTn= 0B
PCS.PCCn= 1B
dI/dt = 0.2 A/µs
2)
Overload Detection Current IL(OVL1)
at High VDS
–
–
29
29
–
–
A
A
P_8.7.16.5
P_8.7.16.7
dI/dt = 0.2 A/µs
2)
Overload Detection Current IL(OVL_JS)
Jump Start Condition
OCR.OCTn= 0B
VS > VS(JS)
dI/dt = 0.2 A/µs
1) Tested at TJ = -40 °C.
2) Not subject to production test - specified by design.
3) IL(OVL3) applies for one channel. Total current for two channels in parallel IL(OVL) ≤ 2 x IL(OVL3)
.
Data Sheet
52
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Diagnosis
9
Diagnosis
For diagnosis purpose, the BTS71220-4ESE provides a current sense at pin IS as well as a diagnosis feedback
via SPI. In case of disabled diagnostic, IS pin becomes high impedance. The integrated current sense
multiplexer is controlled via SPI.
A sense resistor RSENSE must be connected between IS pin and module ground if the current sense diagnosis is
used. RSENSE value has to be higher than 820 Ω (or 400 Ω when a central Reverse Battery protection is present
on the battery feed) to limit the power losses in the sense circuitry. A typical value is RSENSE = 1.2 kΩ.
Due to the internal connection between IS pin and VS supply voltage, it is not recommended to connect the IS
pin to the sense current output of other devices, if they are supplied by a different battery feed or using a
different sense concept.
See Figure 31 for details as an overview. For diagnosis feedback at different operation modes, please see
Chapter 9.2.
VS
IIS0
Temperature
Sensor
T
Latch
Gate
Control
Overcurrent
Protection
OR
OUT3
OUT2
OUT1
OUT0
Latch
ERR0
Load
Current
Sense
Channel 0
VS
VDS(SB)
DCR.MUX
DCR.SBM
Current Sense Multiplexer
IS
RSENSE
Diag nosis_4ch.emf
Figure 31 Diagnosis block diagram
Data Sheet
53
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Diagnosis
9.1
Overview
Table 24 gives a quick reference to the state of the IS pin during BTS71220-4ESE operation.
Table 24 Diagnosis feedback, Function of Operation Mode
Operation Mode
Input level VOUT
Current sense IIS
WRNDIAG STDDIAG
OUT.OUTn
.WRNn
.SBM
Normal operation Low / 0B
~ GND
~ GND
Z
Z
Z
Z
Z
0
0
1
0
1
1
x
0
OFF
Short circuit to GND
Overtemperature
Short circuit to VS
Open Load
VS
< VS - VDS(SB)
> VS - VDS(SB)
Z
Z
0
0
1
0
1)
Sense verification2)
x
IIS(VER)
x
0
0
1
1
0
0
x
0
0
0
x
1
x
0
0
0
0
Normal operation High / 1B
~ VS
< VS
~ GND
Z
IIS = IL(NOM) / kILIS
ON
Overload
IIS = IL / kILIS
Short circuit to GND
Overtemperature
Short circuit to VS
Open Load
Z
Z
VS
IIS < IL / kILIS
IIS = IIS(EN)
3)
~ VS
Sense verification2)
x
IIS(VER)
4)
Under load (e.g.
Output Voltage
~ VS
IIS(EN) < IIS < IL(NOM) / kILIS
Limitation
condition)
1) With additional pull-up resistor.
2) DCR.MUX= 101B.
3) The output current has to be smaller than IL(OL)
.
4) The output current has to be higher than IL(OL)
.
Data Sheet
54
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Diagnosis
9.2
Diagnosis Word at SPI
Diagnostic information about the status of each channel is provided through SPI. The fault flags, an OR
combination of the overtemperature flags and the Overload monitoring signals are provided in the WRNDIAG
register.
The Overload monitoring signals are latched in the WRNDIAG.WRNnbits and cleared each time the WRNDIAG
is transmitted via SPI unless the maximum number of restarts is reached and the channel protects itself. The
protection latches are cleared by SPI command HWCR.CLC.
9.3
Diagnosis in ON state
A current proportional to the load current (ratio kILIS = IL / IIS) is provided at pin IS when the following conditions
are fulfilled:
•
•
•
A power output stage is switched ON with VDS < VDS(SB)
The diagnosis is enabled for that channel
No fault (as described in Chapter 8.3) is present
If a “hard” failure mode is present or occurs for the channel selected using the DCR.MUXbits, the IS pin
remains in or changes to “high impedance” state.
9.3.1
Current Sense (kILIS)
The accuracy of the sense current depends on temperature and load current. IIS increases linearly with IL
output current until it reaches the saturation current IIS(SAT). In case of Open Load at the output stage (IL close
to 0 A), the maximum sense current IIS(EN) (no load, diagnosis enabled) is specified. This condition is shown in
Figure 33. The blue line represents the ideal kILIS line, while the red lines show the behavior of a typical
product.
An external RC filter between IS pin and microcontroller ADC input pin is recommended to reduce signal ripple
and oscillations (a minimum time constant of 1 µs for the RC filter is recommended).
The kILIS factor is specified with limits that take into account effects due to temperature, supply voltage and
manufacturing process. Tighter limits are possible (within a defined current window) with calibration:
•
•
•
A well-defined and precise current (IL(CAL)) is applied at the output during End of Line test at customer side
The corresponding current at IS pin is measured and the kILIS is calculated (kILIS @ IL(CAL)
)
Within the current range going from IL(CAL)_L to IL(CAL)_H the kILIS is equal to kILIS @ IL(CAL) with limits defined by
ΔkILIS
The derating of kILIS after calibration is calculated using the formulas in Figure 32 and it is specified by ΔkILIS
Diagnosis_dKILIS.emf
Figure 32 ΔkILIS calculation formulas
The calibration is intended to be performed at TA(CAL) = 25°C. The parameter ΔkILIS includes the drift
overtemperature as well as the drift over the current range from IL(CAL)_L to IL(CAL)_H
.
Data Sheet
55
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Diagnosis
IIS
IIS(OL)
IIS(EN)
IL( OL )
IL
Di agnosis _O LO N.emf
Figure 33 Current Sense Ratio in Open Load at ON condition
9.3.2
Current Sense Multiplexer
There is a current sense multiplexer implemented in the BTS71220-4ESE that routes the sense current of the
selected channel to the diagnosis pin IS. The channel is selected via SPI register DCR.MUX. The sense current
can also be disabled by SPI register DCR.MUX. For details on timing of the current sense multiplexer, refer to
Figure 34. In addition DCR.MUXis used in combination with other SPI bits to address further functions of the
device. To verify the function of the current sensing path in ON and OFF state, the device offers a sense
verification mode. In this mode a predefined current IIS(VER) is provided on the current sense pin independent
on the load condition of any channel. This enables the microcontroller to verify the sense path at any time. The
sense verification mode is enabled when DCR.MUX= 101B.
All commands and functions involving the DCR.MUXbits are listed below:
•
•
•
The main function of DCR.MUXis to switch the current sense multiplexer
Executing PCS.CLCS= 1B clears the counter and latches OFF the channel selected by DCR.MUX
Executing PCS.SRCS= 1B the slew rate of the channel selected by DCR.MUXwill be changed. See
Chapter 7.4.1 for further information
•
When reading RCS.RCSnbits, the status of the internal counter of the channel selected by DCR.MUXis
responded
•
•
When setting DCR.MUX= 101B the sense verification mode is enabled
When setting PCS.SRCS= 1b, the slew rate of the channel selected by DCR.MUXwill be adjusted
Data Sheet
56
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Diagnosis
CSN
DCR.MUX
110
001
010
110
t
tsI S(ON)
tsI S(CC)
tsIS (O FF)
IIS
t
Diagnosis_MuxTiming.emf
Figure 34 Current Sense Multiplexer Timings
9.4
Diagnosis in OFF state
When a power output stage is in OFF state, the BTS71220-4ESE can measure the output voltage and compare
it with a threshold voltage. In this way, using some additional external components (a pull-down resistor and
a switchable pull-up current source), it is possible to detect if the load is missing or if there is a short circuit to
battery.
9.4.1
Switch Bypass Monitor
To detect short circuit to VS, there is a switch bypass monitor implemented. In case of short circuit between
the output pin OUT and VS in ON state, the current flows through the power transistor as well as through the
short circuit (bypass) with undefined share between the two. As a result, the current sense signal shows lower
values than expected by the load current. In OFF state, the output voltage remains close to VS potential which
leads to a small VDS. The switch bypass monitor compares the threshold VDS(SB) with the voltage VDS across the
power transistor of that channel which is selected by the current sense multiplexer (DCR.MUX). The result of
the comparison can be read in the standard diagnosis STDDIAG.SBM. In addition the switch bypass monitor
can be used to detect an Open Load in OFF state. In this case a switchable pull-up resistor has to be placed to
pull the OUT to VS potential.
9.5
SENSE Timings
Figure 35 shows the timing during settling tsIS(ON) and disabling tsIS(OFF) of the SENSE (including the case of load
change). As a proper signal cannot be established before the load current is stable (therefore before tON),
tsIS(DIAG) = tsIS(ON) + tON.
IN /
OUT.OUTn
OF F
ON
OF F
t
t
tOFF
S
EN SE
EN ABLE
tON
tON(D ELA Y)
tOFF(D ELA Y)
IL
t
t
tdI S (O FF )
tsIS(D IAG )
tsIS(LC)
tsIS(OFF)
tsIS(ON)
IIS
Diagnosis_Sense Timi ng.emf
Figure 35 SENSE Settling / Disabling Timing
Data Sheet
57
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Diagnosis
9.6
Electrical Characteristics Diagnosis
VDD = 3.0 V to 5.5 V, VS = 6 V to 18 V, TJ = -40 °C to +150 °C
Typical values: VDD = 5.0 V, VS = 13.5 V, TJ = 25 °C
Typical resistive loads connected to the outputs for testing (unless otherwise specified):
9.5 mΩ: RL = 2.6 Ω
22.5 mΩ: RL = 4.8 Ω
Table 25 Electrical Characteristics: Diagnosis - General
Parameter
Symbol
Values
Typ.
–
Unit Note or
Test Condition
Number
Min.
Max.
1)
SENSE Saturation Current
IIS(SAT)
4.2
15
mA
P_9.6.0.12
RSENSE = 1.2 kΩ
1)
SENSE Saturation Current
IIS(SAT)
5
–
15
mA
P_9.6.0.17
RSENSE = 1.2 kΩ
VS = 8 V to 18 V
SENSE Leakage Current
when Disabled
IIS(OFF)
–
–
0.01
0.2
0.5
1
µA
µA
IL ≥ IL(NOM)
VIS = 0 V
DCR.MUX= 110B
1)
P_9.6.0.2
P_9.6.0.3
SENSE Leakage Current
IIS(EN)_85
when Enabled at TJ ≤ 85 °C
TJ ≤ 85 °C
DCR.MUX≠
<110B,111B>
See Figure 33
SENSE Leakage Current
when Enabled at TJ = 150 °C
IIS(EN)_150
–
–
1
2
1
µA
V
TJ = 150 °C
DCR.MUX≠
<110B,111B>
See Figure 33
1)
P_9.6.0.11
P_9.6.0.6
Saturation Voltage in kILIS
Operation
VSIS_k
0.5
VS = 6 V
(VS - VIS)
INx = “high” or
OUT.OUTn= 1B
IL ≤ 2 * IL(NOM)
Power Supply to IS Pin
Clamping Voltage at
TJ = -40 °C
VSIS(CLAMP)_-40 33
36.5
38
42
44
V
V
IIS = 1 mA
TJ = -40 °C
See Figure 20
2)
P_9.6.0.9
Power Supply to IS Pin
Clamping Voltage at
TJ ≥ 25 °C
VSIS(CLAMP)_25 35
P_9.6.0.10
IIS = 1 mA
TJ ≥ 25 °C
See Figure 20
1) Not subject to production test - specified by design.
2) Tested at TJ = 150°C.
Data Sheet
58
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Diagnosis
9.6.1
Electrical Characteristics Diagnosis - SPOC™
Table 26 Electrical Characteristics: Diagnosis - Thresholds, Timings
Parameter
Symbol
Values
Typ.
1.9
Unit Note or
Test Condition
Number
Min.
Max.
Switch Bypass Monitor
Threshold
VDS(SB)
tsIS(ON)
1.3
2.5
V
OFF state
P_9.6.2.1
P_9.6.2.2
SENSE Settling Time with
Nominal Load Current
Stable
–
–
8
20
60
µs
VS = 13.5 V
IL = IL(NOM)
DCR.MUX: 110B →
001B
2)
SENSE Settling Time with
Small Load Current Stable
tsIS(ON)_SLC
–
µs
µs
µs
P_9.6.2.10
P_9.6.2.4
P_9.6.2.11
VS = 13.5 V
IL = IL(CAL)_OL
DCR.MUX: 110B →
001B
1)
SENSE Settling Time after
Channel Change
tsIS(CC)
–
–
–
–
20
60
VS = 13.5 V
IL = IL(NOM)
DCR.MUX: 001B →
010B
2)
SENSE Settling Time after
Channel Change with Small
Load Current
tsIS(CC)_SLC
VS = 13.5 V
Start channel:
IL = IL(CAL)
End channel:
IL = IL(CAL)_OL
DCR.MUX: 001B →
010B
1)
SENSE Disable Time
tsIS(OFF)
–
–
20
µs
P_9.6.2.5
VS = 13.5 V
IL = IL(NOM)
DCR.MUX: 010B →
110B
2)
SENSE Settling Time after
Load Change
tsIS(LC)
–
–
–
20
µs
µs
P_9.6.2.6
2)
SENSE Settling Time after
Load Change with Small
Load Current
tsIS(LC)_SLC
250
400
P_9.6.2.12
VS = 13.5 V
from IL = IL(CAL) to
IL = IL(CAL)_OL
2)
SENSE Disable Time after
Channel Deactivation
tdIS(OFF)
IIS(VER)
–
–
20
µs
P_9.6.2.7
SENSE Current in Sense
Verification Mode
400
500
600
µA
DCR.MUX= 101B P_9.6.2.8
1) Production test for functionality within parameter limits.
2) Not subject to production test - specified by design.
Data Sheet
59
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Diagnosis
9.7
Electrical Characteristics Diagnosis - Power Output Stages
VDD = 3.0 V to 5.5 V, VS = 6 V to 18 V, TJ = -40 °C to +150 °C
Typical values: VDD = 5.0 V, VS = 13.5 V, TJ = 25 °C
Typical resistive loads connected to the outputs for testing (unless otherwise specified):
9.5 mΩ: RL = 2.6 Ω
22.5 mΩ: RL = 4.8 Ω
9.7.1
Diagnosis Power Output Stage - 9.5 mΩ
Table 27 Electrical Characteristics: Diagnosis - 9.5 mΩ - high range1)
Parameter
Symbol
Values
Typ.
18
Unit Note or
Test Condition
Number
Min.
Max.
2)
Open Load Output Current IL(OL)_4u
at IIS = 4 µA
5
50
mA
P_9.7.15.1
P_9.7.15.4
P_9.7.15.7
P_9.7.15.9
P_9.7.15.12
P_9.7.15.15
P_9.7.15.17
P_9.7.15.19
P_9.7.15.40
IIS = IIS(OL) = 4 µA
2)
Current Sense Ratio at
IL = IL02
kILIS02
kILIS05
kILIS07
kILIS10
kILIS13
kILIS15
kILIS17
ΔkILIS(OL)
-65% 5000
-60% 5000
-55% 5000
-40% 5000
-24% 5000
+65%
+60%
+55%
+40%
+24%
+8%
IL02 = 20 mA
2)
Current Sense Ratio at
IL = IL05
IL05 = 100 mA
2)
Current Sense Ratio at
IL = IL07
IL07 = 250 mA
2)
Current Sense Ratio at
IL = IL10
IL10 = 1 A
Current Sense Ratio at
IL = IL13
IL13 = 2.8 A
Current Sense Ratio at
IL = IL15
-8%
-8%
-30
5000
5000
0
IL15 = 5.5 A
Current Sense Ratio at
IL = IL17
+8%
IL17 = 10 A
2)3)
SENSE Current Derating
with Low Current
Calibration
+30
%
%
IL(CAL)_OL = IL05
IL(CAL)_OL_H = IL07
IL(CAL)_OL_L = IL02
TA(CAL) = 25 °C
2)3)
SENSE Current Derating
with Nominal Current
Calibration
ΔkILIS(NOM) -9
0
+9
P_9.7.15.41
IL(CAL) = IL15
IL(CAL)_H = IL17
IL(CAL)_L = IL13
TA(CAL) = 25 °C
1) Parameter valid only if KRC.KRCn= 0B.
2) Parameter valid only if PCS.PCCn= 0B.
3) Not subject to production test - specified by design.
Data Sheet
60
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Diagnosis
Table 28 Electrical Characteristics: Diagnosis - 9.5 mΩ - low range1)
Parameter
Symbol
Values
Typ.
9
Unit Note or
Test Condition
Number
Min.
Max.
2)3)
Open Load Output Current IL(OL)_4u
at IIS = 4 µA
2
15
mA
P_9.7.15.20
P_9.7.15.22
P_9.7.15.24
P_9.7.15.27
P_9.7.15.30
P_9.7.15.32
P_9.7.15.34
P_9.7.15.36
P_9.7.15.39
P_9.7.15.42
IIS = IIS(OL) = 4 µA
2)3)
Current Sense Ratio at
IL = IL01
kILIS01
kILIS03
kILIS05
kILIS07
kILIS08
kILIS10
kILIS12
kILIS15
ΔkILIS(OL)
-65% 1660
-60% 1660
-55% 1660
-45% 1660
-35% 1660
-24% 1660
+65%
+60%
+55%
+45%
+35%
+24%
+8%
IL01 = 10 mA
2)3)
Current Sense Ratio at
IL = IL03
IL03 = 30 mA
2)3)
Current Sense Ratio at
IL = IL05
IL05 = 100 mA
2)3)
Current Sense Ratio at
IL = IL07
IL07 = 250 mA
2)3)
Current Sense Ratio at
IL = IL08
IL08 = 450 mA
3)
Current Sense Ratio at
IL = IL10
IL10 = 1 A
3)
Current Sense Ratio at
IL = IL12
-8%
-8%
-30
1660
1660
0
IL12 = 2 A
3)
Current Sense Ratio at
IL = IL15
+8%
IL15 = 5.5 A
2)4)
SENSE Current Derating
with Low Current
Calibration
+30
%
%
IL(CAL)_OL = IL03
IL(CAL)_OL_H = IL05
IL(CAL)_OL_L = IL01
TA(CAL) = 25 °C
2)4)
SENSE Current Derating
with Nominal Current
Calibration
ΔkILIS(NOM) -9
0
+9
P_9.7.15.43
IL(CAL) = IL10
IL(CAL)_H = IL12
IL(CAL)_L = IL08
TA(CAL) = 25 °C
1) Parameter valid only if KRC.KRCn= 1B.
2) Parameter valid only if PCS.PCCn= 0B.
3) kILIS accuracy valid if 1 µs RC filter is placed at ADC input.
4) Not subject to production test - specified by design.
Data Sheet
61
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Diagnosis
9.7.2
Diagnosis Power Output Stage - 22.5 mΩ
Table 29 Electrical Characteristics: Diagnosis - 22.5 mΩ - high range1)
Parameter
Symbol
Values
Typ.
7
Unit Note or
Test Condition
Number
Min.
Max.
2)
Open Load Output Current IL(OL)_4u
at IIS = 4 µA
2
15
mA
P_9.7.16.1
P_9.7.16.3
P_9.7.16.5
P_9.7.16.7
P_9.7.16.9
P_9.7.16.12
P_9.7.16.14
P_9.7.16.17
P_9.7.16.37
IIS = IIS(OL) = 4 µA
2)
Current Sense Ratio at
IL = IL01
kILIS01
kILIS03
kILIS05
kILIS07
kILIS10
kILIS12
kILIS15
ΔkILIS(OL)
-65% 2000
-60% 2000
-55% 2000
-45% 2000
-24% 2000
+65%
+60%
+55%
+45%
+24%
+8%
IL01 = 10 mA
2)
Current Sense Ratio at
IL = IL03
IL03 = 30 mA
2)
Current Sense Ratio at
IL = IL05
IL05 = 100 mA
2)
Current Sense Ratio at
IL = IL07
IL07 = 250 mA
IL10 = 1 A
Current Sense Ratio at
IL = IL10
Current Sense Ratio at
IL = IL12
-8%
-8%
-30
2000
2000
0
IL12 = 2 A
Current Sense Ratio at
IL = IL15
+8%
IL15 = 5.5 A
2)3)
SENSE Current Derating
with Low Current
Calibration
+30
%
%
IL(CAL)_OL = IL03
IL(CAL)_OL_H = IL05
IL(CAL)_OL_L = IL01
TA(CAL) = 25 °C
3)
SENSE Current Derating
with Nominal Current
Calibration
ΔkILIS(NOM) -9
0
+9
P_9.7.16.38
IL(CAL) = IL12
IL(CAL)_H = IL15
IL(CAL)_L = IL10
TA(CAL) = 25 °C
1) Parameter valid only if KRC.KRCn= 0B.
2) Parameter valid only if PCS.PCCn= 0B.
3) Not subject to production test - specified by design.
Data Sheet
62
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Diagnosis
Table 30 Electrical Characteristics: Diagnosis - 22.5 mΩ - low range1)
Parameter
Symbol
Values
Typ.
3.2
Unit Note or
Test Condition
Number
Min.
Max.
2)3)
Open Load Output Current IL(OL)_4u
at IIS = 4 µA
0.5
6
mA
P_9.7.16.18
P_9.7.16.19
P_9.7.16.20
P_9.7.16.23
P_9.7.16.26
P_9.7.16.29
P_9.7.16.31
P_9.7.16.33
P_9.7.16.35
P_9.7.16.39
IIS = IIS(OL) = 4 µA
2)3)
Current Sense Ratio at
IL = IL00
kILIS00
kILIS01
kILIS03
kILIS05
kILIS07
kILIS08
kILIS10
kILIS12
ΔkILIS(OL)
-65% 660
-60% 660
-55% 660
-45% 660
-30% 660
-20% 660
+65%
+60%
+55%
+45%
+30%
+20%
+8%
IL00 = 5 mA
2)3)
Current Sense Ratio at
IL = IL01
IL01 = 10 mA
2)3)
Current Sense Ratio at
IL = IL03
IL03 = 30 mA
2)3)
Current Sense Ratio at
IL = IL05
IL05 = 100 mA
2)3)
Current Sense Ratio at
IL = IL07
IL07 = 250 mA
3)
Current Sense Ratio at
IL = IL08
IL08 = 450 mA
3)
Current Sense Ratio at
IL = IL10
-8%
-8%
-30
660
660
0
IL10 = 1 A
3)
Current Sense Ratio at
IL = IL12
+8%
IL12 = 2 A
2)4)
SENSE Current Derating
with Low Current
Calibration
+30
%
%
IL(CAL)_OL = IL01
IL(CAL)_OL_H = IL03
IL(CAL)_OL_L = IL00
TA(CAL) = 25 °C
2)4)
SENSE Current Derating
with Nominal Current
Calibration
ΔkILIS(NOM) -9
0
+9
P_9.7.16.40
IL(CAL) = IL10
IL(CAL)_H = IL12
IL(CAL)_L = IL08
TA(CAL) = 25 °C
1) Parameter valid only if KRC.KRCn= 1B.
2) Parameter valid only if PCS.PCCn= 0B.
3) kILIS accuracy valid if 1 µs RC filter is placed at ADC input.
4) Not subject to production test - specified by design.
Data Sheet
63
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Serial Peripheral Interface (SPI)
10
Serial Peripheral Interface (SPI)
The serial peripheral interface (SPI) is a full duplex synchronous serial slave interface, which uses four lines:
SO, SI, SCLK and CSN. Data is transferred by the lines SI and SO at the rate given by SCLK. The falling edge of
CSN indicates the beginning of an access. Data is sampled-in on line SI at the falling edge of SCLK and shifted
out on line SO at the rising edge of SCLK. Each access must be terminated by a rising edge of CSN. A modulo 8
counter ensures that data is taken only when a multiple of 8 bit has been transferred. The interface provides
daisy chain capability with modulo 8 bit SPI devices.
MSB
6
6
5
5
4
4
3
3
2
2
1
1
LSB
LSB
SO
SI
MSB
CSN
SCLK
time
SPI _8bit.emf
Figure 36 Serial Peripheral Interface
10.1
SPI Signal Description
CSN - Chip Select Negated
The system microcontroller selects the BTS71220-4ESE by means of the CSN pin. Whenever the pin is in “low”
state, data transfer can take place. When CSN is in “high” state, any signals at the SCLK and SI pins are ignored
and SO is forced into a “high impedance” state.
CSN “high” to “low” Transition
•
•
The requested information is transferred into the shift register.
SO changes from “high impedance” state to “low” state.
CSN “low” to “high” Transition
•
Command decoding is only done, when after the falling edge of CSN exactly a multiple (1, 2, 3, …) of eight
SCLK signals have been detected. In case of an incorrect SCLK count, the transmission error flag
(STDDIAG.TER) is set and the command is ignored.
•
Data from shift register is transferred into the addressed register.
SCLK - Serial Clock
This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the
falling edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising edge of the
serial clock. It is essential that the SCLK pin is in “low” state whenever chip select CSN makes any transition,
otherwise the command may not be accepted.
SI - Serial Input
Serial input data bits are shifted in at this pin, the most significant bit first. SI information is read on the falling
edge of SCLK. The input data consists of two parts, control bits followed by data bits. Please refer to
Chapter 10.5 for further information.
Data Sheet
64
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Serial Peripheral Interface (SPI)
SO Serial Output
Data is shifted out serially at this pin, the most significant bit first. SO is in “high impedance” state until the
CSN pin goes to “low” state. New data will appear at the SO pin following the rising edge of SCLK.
Please refer to Chapter 10.5 for further information.
10.2
Daisy Chain Capability
The SPI of BTS71220-4ESE provides daisy chain capability for modulo 8 bit SPI devices. In this configuration
several devices are activated by the same CSN signal MCSN. The SI line of one device is connected with the SO
line of another device (see Figure 37), in order to build a chain. The end of the chain is connected to the output
and input of the master device, MO and MI respectively. The master device provides the master clock MCLK
which is connected to the SCLK line of each device in the chain.
device 1
SPI
device 2
SPI
device 3
SPI
SI
SO
SI
SO
SI
SO
MOSI
MISO
MCSN
MCLK
SPI_DaisyChain_1.emf
Figure 37 Daisy Chain Configuration
In the SPI block of each device, there is one shift register where each bit from SI line is shifted in each SCLK.
The bit is shifted out on SO pin. After eight SCLK cycles, the data transfer for one device is finished. In single
chip configuration, the CSN line must turn “high” to make the device acknowledge the transferred data. In
daisy chain configuration, the data shifted out at device 1 has been shifted into device 2. When using three
devices in daisy chain, three times 8 bits have to be shifted through the devices. After that, the MCSN line must
turn “high” (see Figure 38).
MOSI
MISO
frame device 3
frame device 2
frame device 1
response device 3
response device 2
response device 1
MCSN
MSCLK
8 clocks
8 clocks
8 clocks
SPI_DaisyChain_2.emf
Figure 38 Data Transfer in Daisy Chain Configuration
Data Sheet
65
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Serial Peripheral Interface (SPI)
10.3
Timing Diagrams
tCSN(LEAD)
tSCLK (P)
tCSN(LAG )
tCSN(TD)
VCSN(TH), max
VCSN(TH), mi n
CSN
tSCLK (H)
tSCLK (L)
VSCLK (TH), max
VSCLK (TH), mi n
SCLK
SI
tSI(SU)
tSI(H)
VSI(TH), max
VSI(TH), mi n
tSO(EN)
tSO(V)
tSO(DI S)
VSO(H)
VSO(L)
SO
SPI_Timings.emf
Figure 39 Timing Diagram SPI Access
Data Sheet
66
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Serial Peripheral Interface (SPI)
10.4
Electrical Characteristics
VDD = 3.0 V to 5.5 V, VS = 6 V to 18 V, TJ = -40 °C to +150 °C
Typical values: VDD = 5.0 V, VS = 13.5 V, TJ = 25 °C
Table 31 Electrical Characteristics Serial Peripheral Interface (SPI)
Parameter
Symbol
Values
Typ.
Unit Note or
Test Condition
Number
Min.
Max.
Timings
1)
1)
1)
1)
Enable Lead Time (falling CSN tCSN(LEAD) 200
to rising SCLK)
–
–
ns
ns
ns
ns
ns
P_10.4.0.1
P_10.4.0.2
P_10.4.0.3
P_10.4.0.4
P_10.4.0.5
Enable Lag Time (falling SCLK tCSN(LAG)
to rising CSN)
200
500
–
–
–
Transfer Delay Time (rising CSN tCSN(TD)
to falling CSN)
–
–
Output Enable Time (falling
CSN to SO valid)
tSO(EN)
tSO(DIS)
30
30
100
100
CL(SO) = 50 pF
1)
Output Disable Time (rising
CSN to SO tristate)
–
CL(SO) = 50 pF
1)
Serial Clock Frequency
Serial Clock Period
fSCLK
0
–
–
–
–
–
5
–
–
–
–
MHz
ns
P_10.4.0.6
P_10.4.0.7
P_10.4.0.8
P_10.4.0.9
P_10.4.0.10
1)
1)
1)
1)
tSCLK(P)
tSCLK(H)
tSCLK(L)
tSI(SU)
200
90
90
20
Serial Clock “High” Time
Serial Clock “Low” Time
ns
ns
Data Setup Time (required
Time SI to falling SCLK)
ns
1)
Data Hold Time (falling SCLK to tSI(H)
SI)
20
–
–
–
–
ns
ns
P_10.4.0.11
P_10.4.0.12
1)
Output Data Valid Time with
Capacitive Load
tSO(V)
60
CL(SO) = 50 pF
1) Not subject to production test - specified by design.
Data Sheet
67
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Serial Peripheral Interface (SPI)
10.5
SPI Protocol
The relationship between SI and SO content during SPI communication is shown in Figure 40. SI line
represents the frame sent from the µC and SO line is the answer provided by BTS71220-4ESE. The “previous
response” means that the frame sent back depends on the command frame sent from the µC before.
SI
frame A
frame B
frame C
previous
response
response to
frame A
response to
frame B
SO
SPI_SI2SO.emf
Figure 40 Relationship between SI and SO during SPI communication
The SPI protocol provides the answer to a command frame only with the next transmission triggered by the
µC. The responses of write commands are deterministic and can be decoded as STDDIAG or WRNDIAG frame.
For responses of read commands previous transmission has to be considered for decoding.
More in detail, the sequence of commands to “read” and “write” the content of a register will look as follows:
SI
write register A
write register B
STDDIAG
read register A
WRNDIAG
new command
previous
response
register A
content
SO
SPI_RWseq_a.emf
Figure 41 Register content sent back to µC (a)
SI
write register A
read register A
STDDIAG
write register B
new command
WRNDIAG
previous
response
register A
content
SO
SPI_RWseq_b.emf
Figure 42 Register content sent back to µC (b)
There are 3 special situations where the frame sent back to the µC doesn't depend on the previous received
frame:
•
In case an error in transmission happened during the previous frame (for instance, the clock pulses were
not multiple of 8), shown in Figure 43
•
•
When BTS71220-4ESE digital supply comes out of Power-On reset condition, as shown in Figure 44
When VS < VS(TP) and DCR.MUX≠ 111B, as shown in Figure 45
Data Sheet
68
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Serial Peripheral Interface (SPI)
frame A
(error in transmission)
SI
(new command)
STDDIAG + TER
SO
(previous response)
SPI_SO_TER.emf
Figure 43 SPI response after an error in transmission
VDD
VDD(PO)
SI
frame A
frame B
frame C
STDDIAG
+ TER + SLP
SO
(SO=“Z“)
response frame B
SPI_SO_POR.emf
Figure 44 SPI response after coming out of Power-On reset at VDD
VS
VS(TP),max
VS(TP),min
t
t
STDDIAG.
0
x
1
x
1
0
VSMON
frame B
frame C
frame D
frame E
frame A
(response)
SI
(response to
frame A)
STDDIAG + TER
+ VSMON
STDDIAG + TER
+ VSMON
(response to
frame D)
SO
Note: Valid if the device is out of Sleep mode.
SPI_SO_VS MON.emf
Figure 45 SPI response in case of voltage drop on battery
A summary of all possible SPI commands is presented in Table 32, including the answer that BTS71220-4ESE
will send back at the next transmission.
Data Sheet
69
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Serial Peripheral Interface (SPI)
Table 32 SPI Command Summary
Requested Operation
Frame sent to SPOC™ (SI pin)
Frame received from SPOC™
(SO pin) with the next command
Write OUTregister
DCR.SWR= xB
100dddddB
where:
00ddddddB - STDDIAGor
01ddddddB - WRNDIAG
“dddddB” = new OUTregister content (Standard Diagnosis or Warning
Diagnosis will be sent alternating)
Read OUTregister
Read RCSregister
0xxxaaaaB
100dddddB
(“dddddB” = OUTregister content)
where:
“aaaaB” = ADDR11)
(“xB” = don't care)
0xxxaaaaB
10000dddB
where:
(“dddB” = RCSregister content)
“aaaaB” = ADDR11)
(“xB” = don't care)
Write Configuration
registers
11aaddddB
00ddddddB - STDDIAG
01ddddddB - WRNDIAG
(Standard Diagnosis or Warning
Diagnosis will be sent alternating)
where:
“aaB” = ADDR01)
“ddddB” = new register content
Read Configuration registers 0xxxaaaaB
11aaddddB
where:
where:
“aaaaB” = ADDR11)
“aaB” = ADDR01)
“ddddB” = register content
(“xB” = don't care)
Read Warning Diagnosis
Read Standard Diagnosis
Read Error Diagnosis
0xxxx001B
(“xB” = don't care)
0100ddddB - WRNDIAG
(Warning Diagnosis)
0xxxx010B
(“xB” = don't care)
00ddddddB - STDDIAG
(Standard Diagnosis)
0xxxx011B
0100ddddB - ERRDIAG
(“xB” = don't care)
(Error Diagnosis)
1) ADDR0and ADDR1are defined according to Table 33.
Data Sheet
70
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Serial Peripheral Interface (SPI)
10.6
SPI Diagnosis Registers
10.6.1
Diagnosis Registers - Read Commands
Name
7
6
5
4
3
2
1
0
WRNDIAG
STDDIAG
ERRDIAG
0
0
0
x
x
x
x
x
x
x
x
x
0
0
0
0
0
0
0
1
1
1
0
1
10.6.2
Diagnosis Registers - Responses
Name
7
6
5
4
3
2
1
0
Default
WRNDIAG
STDDIAG
0
0
1
0
0
0
WRNDIAG.WRNn
40H
STDDIAG STDDIAG STDDIAG STDDIAG STDDIAG STDDIAG 24H
.TER
.CSV
.LHI
.SLP
.SBM
.VSMON
ERRDIAG
0
1
0
0
ERRDIAG.ERRn
40H
Field
Bits
Type
Description
STDDIAG.TER
5
r
Transmission Error
0B Previous transmission was successful (modulo 8 clocks
received)
1B (default) Previous transmission failed or first transmission
after Power-On reset or VS < VS(TP) if STDDIAG.VSMON= 1B
STDDIAG.CSV
4
r
Checksum Verification1)
0B (default) Checksum verification was pass or no checksum
calculated
1B Previous checksum verification was fail
STDDIAG.LHI
STDDIAG.SLP
STDDIAG.SBM
3
2
1
r
r
r
r
Limp Home monitor
0B (default) “Low” level at pin LHI
1B “High” level at pin LHI
Sleep mode monitor
0B Device out of Sleep mode
1B (default) Device is in Sleep mode
Switch Bypass Monitor2)
0B VDS < VDS(SB)
1B VDS > VDS(SB)
STDDIAG.VSMON 0
VS monitor
0B (default) VS always > VS(UV) since last Standard Diagnosis
readout
1B VS < VS(UV) at least once or VS < VS(TP) if STDDIAG.TER= 1B
Data Sheet
71
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Serial Peripheral Interface (SPI)
Field
Bits
Type
Description
WRNDIAG.WRNn 3:0
r
Warning Diagnosis of Channel n
n = 3 to 0
0B (default) No failure
1B Overcurrent, Overtemperature or delta T detected
ERRDIAG.ERRn 3:0
n = 3 to 0
r
Error Diagnosis of Channel n
0B (default) No failure
1B Channel latched OFF
1) See Chapter 10.8 for details on checksum calculation.
2) The switch bypass monitor compares the threshold VDS(SB) with the voltage VDS across the power transistor of that
channel which is selected by the current sense multiplexer (DCR.MUX).
10.7
SPI Configuration Registers
The following table provides an overview on the registers available and the available address space.
Table 33 Register Overview
Name
OUT
SWR 1)
x/0 2)
1
RB
0
ADDR0
(na)
ADDR1
0000
Content
Output configuration
Restart counter status (read-only)
RCS
0
(na)
1000
SRC
OCR
RCD
KRC
PCS
HWCR
ICS
DCR
1
0
1
0
1
0
1
x
0
1
1
1
1
1
1
1
(na)
00
00
01
01
10
10
11
1001
0100
1100
0101
1101
0110
1110
x111
Slew Rate Control register (read-only)
Overcurrent threshold configuration
Restart counter disable
KILIS range control
Parallel channel and Slew Rate control
Hardware configuration
Input status & checksum input
Diagnostic configuration and Swap bit
1) DCR.SWRbit is only changed for write commands. For read commands it is used as part of the read address.
2) For writing to OUTregister DCR.SWR= x, for read address DCR.SWR= 0B.
Table 34 Configuration Registers - Write Commands RB-0
Bit
7
7
6
5
5
4
3
3
2
2
1
1
0
0
Name SWR
RB
4
OUT
x
1
0
0
OUT.OUTn1)
1) OUT.OUT4controls the logic state of EDO pin.
Table 35 Configuration Registers - Write Commands RB-1
Bit
7
7
6
5
4
3
3
2
2
1
0
0
Name SWR
RB
ADDR0
1
OCR
RCD
KRC
0
1
0
1
1
1
1
1
1
0
0
0
0
0
1
OCR.OCTn
RCD.RCDn
KRC.KRCn
Data Sheet
72
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Serial Peripheral Interface (SPI)
Table 35 Configuration Registers - Write Commands RB-1
Bit
7
7
6
5
4
3
2
2
1
1
0
0
Name SWR
RB
ADDR0
3
PCS
HWCR
ICS
DCR
1
0
1
x
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
1
PCS.PCCn
PCS.CLCS PCS.SRCS
0
HWCR.COL HWCR.RST HWCR.CLC
ICS.CSRn1)
DCR.SWR DCR.MUX
1) See Chapter 10.8 for details on checksum calculation.
Table 36 Configuration Registers - Read Commands
Bit
7
7
6
6
5
5
4
4
3
2
1
0
Name
OUT
RCS
SRC
OCR
RCD
KRC
PCS
HWCR
ICS
DCR
ADDR1
0
0
0
0
0
0
0
0
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
1
1
0
1
0
1
0
1
x
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
0
0
1
0
0
1
1
0
0
1
Data Sheet
73
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Serial Peripheral Interface (SPI)
Table 37 Configuration Registers - Responses
Bit
7
7
6
6
5
5
4
3
3
2
2
1
1
0
0
Name
OUT
RCS
SRC
OCR
RCD
KRC
PCS
HWCR
ICS
DCR
4
Default
80H
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
OUT.OUTn1)
0
1
0
0
1
1
0
0
1
0
RCS.RCSn
80H
SRC.SRCn
OCR.OCTn
RCD.RCDn
KRC.KRCn
PCS.PCCn
0
90H
C0H
C0H
D0H
D0H
E2H
0
0
HWCR.COL HWCR.SLP 0
ICS.INSTn
0
0
E0H
DCR.SWR DCR.MUX
F7H
1) OUT.OUT4controls the logic state of EDO pin.
Field
Bits
Type Description
RB
6
rw
rw
r
Register Bank
0B (default) Read/write to OUT/RCSregister
1B Read/write to other registers
OUT.OUTn
n = 4 to 0
4:0
2:0
Output Control Register of Channel n
0B (default) channel is OFF
1B Channel is ON
RCS.RCSn
n = 2 to 0
Restart Counter Status of Channel selected via MUX
000B (default) Restart counter value = 0
001B Restart counter value = 1
010B Restart counter value = 2
011B Restart counter value = 3
100B Restart counter value = 4
101B Restart counter value = 5
110B Restart counter value = 6
111B Restart counter value = 7
SRC.SRCn
n = 3 to 0
3:0
3:0
3:0
3:0
r
Set Slew Rate control for Channel n (read only)
0B (default) Normal Slew Rate
1B Adjusted Slew Rate
OCR.OCTn
n = 3 to 0
rw
rw
rw
Set Overcurrent Level for Channel n
0B (default) High level of overcurrent threshold IL(OVL0)
1B Low level of overcurrent threshold IL(OVL2)
RCD.RCDn
n = 3 to 0
Set Restart Strategy for Channel n
0B (default) Automatic restart mode
1B Latch mode
KRC.KRCn
n = 3 to 0
Set Current Sense Ratio Range for Channel n
0B (default) High range of current sense ratio
1B Low range of current sense ratio
Data Sheet
74
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Serial Peripheral Interface (SPI)
Field
Bits
Type Description
PCS.SRCS
0
w
Set Slew Rate control for Channel selected by DCR.MUX
0B (default) Normal Slew Rate
1B Adjusted Slew Rate
PCS.CLCS
1
w
Clear Restart Counters and Latches for Channel selected by DCR.MUX
0B (default) Restart counters and latches are untouched
1B Restart counters and latches are reset
PCS.PCCn
3:2
rw
Parallel Channel Configuration
n = 1 to 0
00B (default) Channels are operating independent
01B OUT0 + OUT3 are in parallel configuration
10B OUT1 + OUT2 are in parallel configuration
11B OUT0 + OUT3 and OUT1 + OUT2 are in parallel configuration
HWCR.CLC
HWCR.RST
HWCR.SLP
HWCR.COL
0
1
1
2
w
w
r
Clear Restart Counters and Latches
0B (default) Restart counters and latches are untouched
1B Restart counters and latches are reset for all channels
Reset Command
0B (default) Normal operation
1B Execute reset command
Sleep Mode
0B Device is awake
1B (default) DCR.MUX= 111B
rw
Input Combinatorial Logic Configuration
0B (default) Input signal OR-combined with according OUTregister bit1)
1B Input signal AND-combined with according OUTregister bit
ICS.CSRn
n = 3 to 0
3:0
1:0
w
r
Checksum Input Register
4 bit Checksum is written to this register
ICS.INSTn
n = 1 to 0
Input Status Monitor Channel n
0B (default) Input signal is “low”
1B Input signal is “high”
Data Sheet
75
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Serial Peripheral Interface (SPI)
Field
Bits
Type Description
rw Set Current Sense Multiplexer Configuration in OFF state
DCR.MUX
2:0
000B IS pin is “high impedance”
001B IS pin is “high impedance”
010B IS pin is “high impedance”
011B IS pin is “high impedance”
100B Diagnosis enable of external driver activated (EDD set to “high”)
101B Current sense verification mode
110B IS pin is “high impedance”
111B Sleep mode (IS pin is “high impedance”)
Set Multiplexer Configuration in ON state
000B Current sense of channel 0 is routed to IS pin
001B Current sense of channel 1 is routed to IS pin
010B Current sense of channel 2 is routed to IS pin
011B Current sense of channel 3 is routed to IS pin
100B Diagnosis enable of external driver activated (EDD set to “high”)
101B Current sense verification mode
110B IS pin is “high impedance”
111B Sleep mode (IS pin is “high impedance”)
DCR.SWR
3
rw
Switch Register
0B (default) Registers OUT, OCR, KRC, HWCRand DCRcan be written
1B
Registers OUT, RCD, PCS, ICSand DCRcan be written
1) In Limp Home mode (LHI pin set to “high”) the combinatorial logic is switched to OR-mode.
Data Sheet
76
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Serial Peripheral Interface (SPI)
10.8
SPI Checksum Verification
BTS71220-4ESE offers a simple parity check to identify unexpected content or unintended changes of
configuration registers. For the checksum calculation a subset of the configuration bits is used, which is
expected not to be changed periodically. The checksum calculation is an easy column parity calculation. The
configuration bits which are used for the calculation are shown in Table 39. The SPI master writes the result
to ICS.CSRn. After the 4bit checksum is written to ICSregister, the device is doing once the comparison and
the result can be read within the next STDDIAGframe in the bit STDDIAG.CSV. The STDDIAG.CSVbit is
cleared with the next STDDIAGreadout. In case the ICSregister is not written, the checksum comparison is
disabled and the bit STDDIAG.CSV= 0B. If Limp Home mode is entered after ICS.CSRnis written but before
STDDIAG.CSVis read, the checksum verification is not valid. Same applies in case STDDIAG.TERand
STDDIAG.VSMONare set to 1B. In these cases checksum verification result shall be discarded.
Table 38 Conventions for parity calculation
Number of ‘1’ in a column
Result with EVEN-parity
Result with ODD-parity
EVEN
ODD
0
1
1
0
Table 39 Checksum calculation bit matrix
Name
OCR
3
2
1
0
OCT3
RCD3
KRC3
SRC3
0
OCT2
RCD2
KRC2
SRC2
COL
OCT1
RCD1
KRC1
SRC1
PCC
OCT0
RCD0
KRC0
SRC0
PCC0
odd
RCD
KRC
SRC
HWCR/PCS
Parity
ICS
even
CSR3
odd
even
CSR1
CSR2
CSR0
Table 40 Checksum calculation bit matrix example
Name
OCR
3
2
1
0
0
1
0
0
RCD
1
0
0
0
KRC
0
1
1
0
SRC
0
0
1
0
HWCR/PCS
Parity
ICS
0
0
0
0
even
1
odd
1
even
0
odd
1
Data Sheet
77
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Serial Peripheral Interface (SPI)
10.9
SPI command quick list
A summary of the most used SPI commands (read and write operations) is shown in Table 154.
Table 41 SPI command quick list
Name
OUT
RCS
SRC
OCR
RCD
KRC
PCS
HWCR
ICS
DCR
“read” command 1)
0xxx0000B
0xxx1000B
0xxx1001B
0xxx0100B
0xxx1100B
0xxx0101B
0xxx1101B
0xxx0110B
0xxx1110B
0xxxx111B
“write” command 2)
SWR 3)
10ddddddB
x
1100ddddB
1100ddddB
1101ddddB
1101ddddB
1110ddddB
1110ddddB
1111ddddB
0
1
0
1
0
1
x
WRNDIAG
STDDIAG
0xxx0001B
0xxx0010B
0xxx0011B
ERRDIAG
1) x = don’t care bits.
2) d = data bits.
3) DCR.SWRbit needs to be set for writing a register. For reading a register the DCR.SWRbit is part of the read address.
Data Sheet
78
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Application Information
11
Application Information
Note:
11.1
The following information is given as a hint for the implementation of the device only and shall not
be regarded as a description or warranty of a certain functionality, condition or quality of the device.
Application setup - SPOC™
VBAT
Optional
ZWIRE
Fail-safe
Control
Optional
Logic Supply
CVSGND
CVS1
RGND
CVSGND
CVS1
RGND
T1
CVDD
VS
GND
IN
GND
VS
OUT
VDD
IN0
IN1
EDO
EDD
LHI
RVDD
EDO_IN
VDD
RIN
GPIO
GPIO
GPIO
GPIO
RIN
EDD_DEN
OUT0
OUT1
OUT2
OUT3
DEN
RDEN
RIN
EDO_IN
PRO_IS
EDD_DEN
IS
RLHI
RCSN
RSCLK
CSN
SCLK
MISO
MOSI
ADC
CSN
SCLK
SO
DZ2
CVS2
RSO
SI
RSI
IS
RADC
RIS_PROT
VSS
PRO_IS
DZ1
CADC
Logic GND
Optional
Application_4ch_ED.emf
Power GND
*See Chapter 1 „Potential Applications“
Chassis GND
**See Chapter 11.2 „External Components“
Figure 46 Application Diagram
Note:
This is a very simplified example of an application circuit. The function must be verified in the real
application.
Data Sheet
79
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Application Information
11.2
External Components
Table 42 Suggested Component values
Reference
RVDD
Value
470 Ω
4.7 kΩ
Purpose
Device logic protection
RIN
Protection of the microcontroller during overvoltage, reverse polarity
Guarantee BTS71220-4ESE output OFF during Loss of Ground
RIS_PROT
4.7 kΩ
Protection resistor for overvoltage, reverse polarity and Loss of Ground
Value to be tuned with µC specification
RSENSE
RADC
RCSN
RSCLK
RSO
1.2 kΩ
4.7 kΩ
1.2 kΩ
1.2 kΩ
1.2 kΩ
1.2 kΩ
4.7 kΩ
4.7 kΩ
4.7 kΩ
220 pF
Sense resistor
µC-ADC voltage spikes filtering
Protection of the µC during overvoltage and reverse polarity
Protection of the µC during overvoltage and reverse polarity
Protection of the µC during overvoltage and reverse polarity
Protection of the µC during overvoltage and reverse polarity
Protection of the µC during overvoltage and reverse polarity
Protection of the device during overvoltage, reverse polarity of external driver
Protection of the device during overvoltage, reverse polarity of external driver
RSI
RLHI
REDO
REDD
CADC
µC-ADC voltage spikes filtering
A time constant (RADC * CADC) longer than 1 µs is recommended
CVDD
470 nF
Digital supply voltage spikes filtering and for improved robustness against
battery voltage transients
CVS1
100 nF
-
Battery voltage spikes filtering
CVS2
Filtering / buffer capacitor located at VBAT connector
Battery voltage spikes filtering
CVS3
100 nF
22 nF
10 nF
47 Ω
CVSGND
COUT
RGND
Battery voltage spikes filtering
For improved electromagnetic compatibility (EMC)
Ground voltage spikes filtering for improved robustness against battery
voltage transients
T1
BC 807
Switch the battery voltage for Open Load in OFF diagnosis
RPD
47 kΩ
Output polarization (pull-down)
Ensure polarization of BTS71220-4ESE output to distinguish between Open
Load and Short to VS in OFF diagnosis
ROL
1.5 kΩ
Output polarization (pull-up)
Ensure polarization of BTS71220-4ESE output during Open Load in OFF
diagnosis
Note:
The suggested component values above are determined for typical applications with 5 V
microcontrollers. Based on the application circuit and the used components connected to
BTS71220-4ESE, it could be necessary to adjust the recommended values to stay below the
maximum ratings for all components under all operating conditions (e.g. reverse battery, transients
on battery, etc.).
Data Sheet
80
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Application Information
11.3
Further Application Information
•
•
Please contact us for information regarding the Pin FMEA
For further information you may contact http://www.infineon.com/
Data Sheet
81
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Package Outlines
12
Package Outlines
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Data Sheet
82
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Package Outlines
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VROGHU PDVN
VWHQFLO DSHUWXUHV
$// ',0(16,216 $5( ,1 81,76 00
Figure 48 PG-TSDSO-24 (Thin (Slim) Dual Small Outline 24 pins) Package pads and stencil
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant
with government regulations the device is available as a green product. Green products are RoHS-Compliant
(i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
Further information on packages
https://www.infineon.com/packages
Data Sheet
83
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Revision History
13
Revision History
Table 43 BTS71220-4ESE - List of changes
Revision
Changes
1.10, 2021-03-23 General: Datasheet quality improved
General: updated (ReverSave™ → ReverseON)
General: updated (channel description)
Icon “PRO-SIL™ ISO 26262-ready” added to front page
Chapter 1 updated (Package description)
Chapter 1 updated (Potential Applications updated and Product Validation added)
Harmonization of Application Diagram (Figure 1, Figure 46)
P_4.4.0.15, P_4.4.0.16 updated (Typ. value and Max. value)
P_6.4.0.10 updated (Note or Test Condition)
P_6.4.1.5 updated (Max. value updated and footnote added)
P_6.5.31.2 added
P_9.6.0.6 updated parameter name
P_9.6.0.17 added
P_9.6.2.11 footnote removed
Figure 14 and Figure 16 updated
Figure 28 and Figure 29 updated
Figure 33 updated
Figure 37 and Figure 38 updated
Chapter 10.4 typical value for VDD harmonized
Chapter 11 updated (figures and descriptions)
1.00, 2018-06-11 Data Sheet available
Data Sheet
84
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Table of Contents
Table of Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2
2.1
2.2
Block Diagram and Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
3.1
3.2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
4.1
4.2
4.2.1
4.2.2
4.3
4.4
4.4.1
4.4.2
General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute Maximum Ratings - General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute Maximum Ratings - Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power Stages - 9.5 mΩ channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power Stages - 22.5 mΩ channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
PCB Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5
5.1
5.2
5.2.1
5.2.2
5.2.3
5.3
Logic Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Input Pins (INn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Advanced Features Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SPI Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Limp Home Input (LHI) Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
External Driver Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Electrical Characteristics Logic Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Electrical Characteristics Logic Pins - Advanced Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.4
6
6.1
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Unsupplied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Ready mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Limp Home mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Limp Home Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Definition of Operation modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Undervoltage on VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Reset Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Electrical Characteristics Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Electrical Characteristics Power Supply - SPOC™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Electrical Characteristics Power Supply - Product Specific . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
BTS71220-4ESE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
6.1.8
6.1.9
6.2
6.3
6.4
6.4.1
6.5
6.5.1
7
7.1
7.2
Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Output ON-State Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Switching loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Data Sheet
85
Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Table of Contents
7.2.1
7.2.2
7.2.3
7.2.4
7.3
7.3.1
7.3.2
7.3.3
7.4
7.4.1
7.5
7.5.1
7.5.2
Switching Resistive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Switching Inductive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Output Voltage Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Switching Capacitive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Advanced Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Inverse Current behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Switching Channels in Parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Cross Current robustness with H-Bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Electrical Characteristics Power Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Electrical Characteristics Power Stages - SPOC™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Electrical Characteristics - Power Output Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Power Output Stage - 9.5 mΩ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Power Output Stage - 22.5 mΩ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8
8.1
8.2
8.3
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Overtemperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Protection and Diagnosis in case of Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Restart Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Additional protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Protection against loss of connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Loss of Battery and Loss of Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Loss of Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Electrical Characteristics Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Electrical Characteristics Protection - SPOC™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Electrical Characteristics Protection - Power Output Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Protection Power Output Stage - 9.5 mΩ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Protection Power Output Stage - 22.5 mΩ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.3.1
8.4
8.4.1
8.4.2
8.5
8.5.1
8.5.2
8.6
8.6.1
8.7
8.7.1
8.7.2
9
9.1
9.2
9.3
9.3.1
9.3.2
9.4
9.4.1
9.5
9.6
9.6.1
9.7
Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Diagnosis Word at SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Diagnosis in ON state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Current Sense (kILIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Current Sense Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Diagnosis in OFF state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Switch Bypass Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
SENSE Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Electrical Characteristics Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Electrical Characteristics Diagnosis - SPOC™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Electrical Characteristics Diagnosis - Power Output Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Diagnosis Power Output Stage - 9.5 mΩ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Diagnosis Power Output Stage - 22.5 mΩ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.7.1
9.7.2
10
10.1
10.2
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Daisy Chain Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Data Sheet
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Rev. 1.10
2021-03-23
BTS71220-4ESE
SPOC™ +2
Table of Contents
10.3
10.4
10.5
10.6
10.6.1
10.6.2
10.7
10.8
10.9
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
SPI Diagnosis Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Diagnosis Registers - Read Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Diagnosis Registers - Responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
SPI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
SPI Checksum Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
SPI command quick list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
11
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Application setup - SPOC™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Further Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
11.1
11.2
11.3
12
13
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Data Sheet
87
Rev. 1.10
2021-03-23
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Edition 2021-03-23
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hereby disclaims any and all warranties and liabilities
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Document reference
Z8F65320939
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