BU5071_技术文档

TS5070

TS5071

PROGRAMMABLE CODEC/FILTER

COMBO 2ND GENERATION

COMPLETE CODEC AND FILTER SYSTEM

INCLUDING :

– TRANSMIT AND RECEIVE PCM CHANNEL

FILTERS

– µ-LAW OR A-LAW COMPANDING CODER

AND DECODER

– RECEIVE POWER AMPLIFIER DRIVES

300 Ω

– 4.096 MHz SERIAL PCM DATA (max)

PROGRAMMABLE FUNCTIONS :

– TRANSMIT GAIN : 25.4 dB RANGE, 0.1 dB

STEPS

– RECEIVE GAIN : 25.4 dB RANGE, 0.1 dB

STEPS

– HYBRID BALANCE CANCELLATION FIL-

TER

DIP20 (Plastic)

ORDERING NUMBER:TS5071N

– TIME-SLOT ASSIGNMENT: UP TO 64

SLOTS/FRAME

– 2 PORT ASSIGNMENT (TS5070)

– 6 INTERFACE LATCHES (TS5070)

– A OR µ-LAW

– ANALOG LOOPBACK

– DIGITAL LOOPBACK

DIRECT INTERFACE TO SOLID-STATE

SLICs

SIMPLIFIES TRANSFORMER SLIC, SINGLE

WINDING SECONDARY

PLCC28

ORDERING NUMBER: TS5070FN

STANDARD SERIAL CONTROL INTERFACE

80 mW OPERATING POWER (typ)

1.5mW STANDBY POWER (typ)

MEETS OR EXCEEDS ALL CCITT AND

LSSGR SPECIFICATIONS

TTL AND CMOS COMPATIBLE DIGITAL IN-

TERFACES

Channel gains are programmable over a 25.4 dB

range in each direction, and a programmable filter

is included to enable Hybrid Balancing to be ad-

justed to suit a wide range of loop impedance con-

ditions.

Both transformer and active SLIC interface circuits

with real or complex termination impedances can

be balanced by this filter, with cancellation in ex-

cess of 30 dB beingreadily achievablewhenmeas-

ured acrossthe passbandagainststandardtest ter-

mination networks.

To enable COMBO IIG to interface to the SLICcon-

trol leads, a number of programmable latches are

included ; each may be configured as either an in-

put or an output. The TS5070 provides 6 latches

and the TS5071 5 latches.

DESCRIPTION

The TS5070 series are thesecondgenerationcom-

bined PCM CODEC and Filter devices optimized

for digital switching applicationson subscriber and

trunk line cards.

Using advancedswitched capacitortechniquesthe

TS5070 and TS5071 combine transmit bandpass

and receive lowpass channel filters with a com-

panding PCM encoder and decoder. The devices

are A-law and µ-law selectable and employ a con-

ventional serial PCM interface capable of being

clocked up to 4.096 MHz. A number of programma-

ble functions may be controlledvia a serial control

port.

March 1994

1/30

TS5070 - TS5071

BLOCK DIAGRAM

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Value

Unit

V

V_CC

V_SS

V_CCto GND

7

V_SSto GND

– 7

V_CC+ 0.5 to V_SS– 0.5

V_CC+ 0.5 to GND – 0.5

± 100

V

Voltage at VFXI

V

V_IN

Voltage at Any Digital Input

Current at VFRO

V

mA

°C

I_O

Current at Any Digital Output

Storage Temperature Range

± 50

T_stg

T_lead

– 65, + 150

300

Lead Temperature Range (soldering, 10 seconds)

2/30

TS5070 - TS5071

PIN CONNECTIONS

DIP20

TS5071N

PLCC28

TS5070FN

POWER SUPPLY, CLOCK

Type

TS5070 TS5071

Name

Function

Description

FN

N

V_CC

V_SS

S

27

3

19

3

Positive Power

Supply

Negative

Power Supply

Ground

+ 5 V ± 5 %

– 5 V ± 5 %

GND

1

All analog and digital signals are referenced to this pin.

BCLK

MCLK

I

16

17

12

Bit Clock

Bit clock input used to shift PCM data into and out of the

D_Rand D_Xpins. BCLK may vary from 64 kHz to 4.096

MHz in 8 kHz increments, and must be synchronous with

MCLK (TS5071 only).

I

Master Clock

Master clock input used by the switched capacitor filters

and the encoder and decoder sequencing logic. Must be

512 kHz, 1. 536/1. 544 MHz,

2.048 MHz or 4.096 MHz and synchronous with BCLK.

BCLK and MCLK are wired together in the TS5071.

3/30

TS5070 - TS5071

TRANSMIT SECTION

Type

TS5070 TS5071

Name

Function

Description

FN

N

FS_X

I

22

15

Transmit

Frame Sync.

Normally a pulse or squarewave waveform with an 8 kHz

repetition rate is applied to this input to define the start of

the transmit time-slot assigned to this device (non-delayed

data mode) or the start of the transmit frame (delayed

data mode using the internal time-slot assignment

counter).

VF_XI

I

28

20

Transmit

Analog

This is a high–impedance input. Voice frequency signals

present on this input are encoded as an A–law or µ–law

PCM bit stream and shifted out on the selected D_Xpin.

D_X0

D_X1

0

18

19

13

–

Transmit Data

D_X1 is available on the TS5070 only, D_X0 is available on

all devices. These transmit data TRI–STATE outputs

remain in the high impedance state except during the

assigned transmit time–slot on the assigned port, during

which the transmit PCM data byte is shifted out on the

rising edges of BCLK.

TS_X0

TS_X1

0

20

21

14

–

Transmit

Time–slot

TS_X1 is available on the TS5070 only.

TS_X0 is available on all devices. Normally these opendrain

outputs are floating in a high impedance state except

when a time–slot is active on one of the D_Xoutputs, when

the apppropriate TS_Xoutput pulls low to

enable a backplane line–driver. Should be strapped to

ground (GND) when not used.

RECEIVE SECTION

Type

TS5070 TS5071

Name

Function

Description

FN

N

FS_R

I

8

6

Receive Frame Normally a pulse or squarewave waveform with an 8 kHz

Sync.

repetition rate is applied to this input to define the start of

the receive time–slot assigned to this device (non-delayed

frame mode) or the start of the receive frame (delayed

frame mode using the internal time-slot assignment

counter.

VF_R0

0

2

Receive Analog The receive analog power amplifier output, capable of

driving load impedances as low as 300 Ω (depending on

the peak overload level required). PCM data received on

the assigned D_Rpin is decoded and appears at this output

as voice frequency signals.

D_R0

D_R1

I

10

9

7

–

Receive Data

D_R1 is available on the TS5070 only, D_R0 is available on

all devices. These receive data input(s) are inactive

except during the assigned receive time–slot of the

assigned port when the receive PCM data is shifted in on

the falling edges of BCLK.

4/30

TS5070 - TS5071

INTERFACE, CONTROL, RESET

Type

TS5070 TS5071

Name

Function

Description

FN

N

IL5

IL4

IL3

IL2

IL1

IL0

I/O

23

24

6

7

25

26

–

16

4

5

17

18

Interface

Latches

IL5 through IL0 are available on the TS5070,

IL4 through IL0 are available on the TS5071.

Each interface Latch I/O pin may be individually

programmed as an input or an output determined by the

state of the corresponding bit in the Latch Direction

Register (LDR) . For pins configured as inputs, the logic

state sensed on each input is latched into the interface

Latch Register (ILR) whenever control data is written to

COMBO IIG, while CS is low, and the information is

shifted out on the CO (or CI/O) pin. When configured as

outputs, control data written into the ILR appears at the

corresponding IL pins.

CCLK

CI/O

I

13

–

9

8

Control Clock

This clock shifts serial control information into or out of CI

or CO (or CI/O) when the CS input is low depending on

the current instruction. CCLK may be asynchronous with

the other system clocks.

I/O

Control Data

Input/output

This is Control Data I/O pin wich is provided on the

TS5071. Serial control information is shifted into or out of

COMBO IIG on this pin when CS is low. The direction of

the data is determined by the current instruction as defined

in Table 1.

CI

I

12

11

–

Control Data

Input

Control Data

Output

These are separate controls, availables only on the

TS5070. They can be wired together if required.

CO

O

CS

I

14

15

10

11

Chip Select

When this pins is low, control information can be written to

or read from the COMBO IIG via the CI and CO pins (or

CI/O).

MR

Master Reset

This logic input must be pulled low for normal operation of

COMBO IIG. When pulled momentarily high, all

programmable registers in the device are reset to the

states specified under ”Power–on Initialization”.

CI/O pin is set as an input ready for the first con-

trol byte of the initialization sequence. Other initial

states in the Control Register are indicated in Ta-

ble 2.

A reset to these same initial conditions may also be

forced by driving the MR pin momentarily high. This

maybe doneeither when powered-upor down. For

normal operation this pin must be pulled low. If not

used, MR should be hard-wired to ground.

FUNCTIONAL DESCRIPTION

POWER-ON INITIALIZATION

When power is first applied, power-on reset cir-

cuitry initializes COMBO IIG and puts it into the

power-down state. The gain control registers for

the transmit and receive gain sections are pro-

grammed for no output, the hybrid balance circuit

is turned off, the power amp is disabled and the

device is in the non-delayed timing mode. The

Latch Direction Register (LDR) is pre-set with all

IL pins programmed as inputs, placing the SLIC

interface pins in a high impedance state. The

The desired modes for all programmable functions

may be initialized via the control port prior to a

Power-up command.

5/30

TS5070 - TS5071

Register, isincluded,andfinallya Post-Filter/Power

Amplifier capable of driving a 300 Ω load to ± 3.5

V, a 600 Ω load to ± 3.8 V or 15 kΩ load to ± 4.0 V

at peak overload.

A decode cycle begins immediately after each re-

ceive time-slot, and 10 µs later the Decoder DAC

output is updated. The total signal delay is 10 µs

plus 120 µs (filter delay) plus 62.5 µs (1/2 frame)

which gives approximately 190 µs.

POWER-DOWN STATE

Following a period of activity in the powered-up

state the power-down state may be re-entered by

writing any of the control instructions into the serial

control port with the ”P” bit set to ”1” It is recom-

mended that the chip be powered down beforewrit-

ing any additional instructions. In the power-down

state, all non-essential circuitry is de-activated and

theD_X0 and D_X1 outputsare in the high impedance

TRI-STATE condition.

The coefficientsstoredin the Hybrid Balancecircuit

and the Gain Control registers, the data in the LDR

and ILR, and all control bits remain unchanged in

the power-down state unless changed by writing

new data via the serial control port, which remains

operational. The outputs of the Interface Latches

also remain active, maintaining the ability to moni-

tor and control a SLIC.

PCM INTERFACE

The FS_Xand FS_Rframe sync inputs determine the

beginning of the 8-bit transmit and receive time-

slots respectively. They may have any duration

from a single cycle of BCLK to one MCLK period

LOW. Two different relationships may be estab-

lishedbetweenthe framesync inputsandtheactual

time-slots on the PCM busses by setting bit 3 in the

Control Register (see table 2). Non delayed data

mode is similar to long-frame timing on the

ETC5050/60 series of devices : time-slots being

nominally coincident with the rising edge of the ap-

propriate FS input. The alternative is to use De-

layed Data mode which is similar to short-frame

sync timing, in which each FS input must be high

at least a half-cycle of BCLK earlier than the time-

slot.

TRANSMIT FILTER AND ENCODER

The Transmit section input, VF_XI, is a high imped-

ancesumming input which is used as the differenc-

ing pointfor the internalhybrid balancecancellation

signal. No external componentsare needed to set

the gain. Following this circuit is a programmable

gain/attenuationamplifier which is controlled by the

contents of the Transmit Gain Register (see Pro-

grammable Functions section). An active prefilter

then precedes the 3rd order high-pass and 5th or-

der low-pass switched capacitor filters. The A/D

converterhas a compressingcharacteristicaccord-

ing to the standard CCITT A or µ255 coding laws,

which must be selectedby a control instruction dur-

ing initialization (see table 1 and 2). A precision on-

chip voltage reference ensuresaccurate andhighly

stable transmission levels. Any offset voltage aris-

ing in the gain-set amplifier, the filters or the com-

parator is cancelled by an internal auto-zerocircuit.

Each encode cycle begins immediately following

the assigned Transmit time-slot. The total signal

delay referenced to the start of the time-slot is ap-

proximately 165 µs (due to the Transmit Filter)

plus 125 µs (due to encoding delay), which totals

290 µs. Data is shifted out on D_X0 or D_X1 during

the selected time slot on eight rising edges of

BCLK.

The Time-Slot Assignment circuit on the device can

only be used with DelayedData timing. When using

Time-Slot Assignment, the beginning of the first

time-slot in a frame is identified by the appropriate

FSinput. The actualtransmit andreceive time-slots

are then determined by the internal Time-Slot As-

signment counters. Transmit and Receive frames

and time-slots may be skewed from each other by

any number of BCLK cycles.

During each assigned transmit time-slot, the se-

lected D_X0/1 output shifts data out from the PCM

register on the rising edges of BCLK. TS_X0 (or

TS_X1 as appropriate) also pulls low for the first 7

1/2 bit times of the time-slot to control the TRI-

STATE Enable of a backplane line driver. Serial

PCM data is shifted into the selected D_R0/1 input

during each assigned Receive time slot on the

falling edges of BCLK. D_X0 or D_X1 and D_R0 or

D_R1 are selectable on the TS5070 only.

SERIAL CONTROL PORT

DECODER AND RECEIVE FILTER

Control information and data are written into or

readback from COMBO IIG via the serial control

port consistingof the controlclock CCLK ; theserial

data input/output CI/O (or separate input CI, and

output CO on the TS5070 only) ; and the Chip Se-

lect input CS. All control instructions require 2

bytes, aslisted intable1,with theexceptionof asin-

gle byte power-up/down command. The byte 1 bits

are used as follows: bit 7 specifies power-up or

power-down; bits 6, 5, 4 and 3 specify the register

address; bit 2 specifies whether the instructions is

read or write; bit 1 specifies a one or two byte in-

PCM data is shifted into the Decoder’s Receive

PCM Register via the D_R0 or D_R1 pinduring these-

lectedtime-slot on the 8 falling edgesof BCLK. The

Decoder consists of an expandingDAC with either

A or µ255 law decoding characteristic, which is se-

lectedby thesame controlinstructionusedto select

the Encode law during initialization. Following the

Decoder is a 5th order low-pass switched capacitor

filter with integral Sin x/x correction for the 8 kHz

sample and hold. A programmable gain amplifier,

which must be set by writing to the Receive Gain

6/30

TS5070 - TS5071

struction; and bit 0 is not used. To shift control data

into COMBO IIG, CCLK must be pulsed high 8

times while CS is low. Data on the CI or CI/O input

is shifted into the serial input register on the falling

edge of each CCLK pulse. After all data is shifted

in, the contents of the input shift register are de-

coded, and may indicate that a 2nd byte of control

data will follow. This second byte may either be de-

finedby a secondbyte-wide CSpulse ormayfollow

the first continuously, i.e. it is not mandatoryfor CS

to return high in between the first and second con-

trol bytes. On the falling edge of the 8^thCCLK clock

pulse in the 2nd control byte the data is loaded into

the appropriateprogrammableregister. CSmay re-

main low continuously when programming succes-

siveregisters, ifdesired. However CS shouldbe set

high when no data transfers are in progress.

To readbackinterfaceLatch data or status informa-

tion from COMBO IIG, the first byte of the appropri-

ateinstructionis strobedinduring thefirst CS pulse,

as defined intable 1. CS must then be taken low for

a further 8 CCLK cycles, during which the data is

shifted onto the CO or CI/O pin on the rising edges

of CCLK. When CS is high the CO or CI/O pin is in

thehigh-impedanceTRI-STATE, enablingthe CI/O

pins of many devices to be multiplexed together.

Thus, to summarize, 2-byte READ and WRITE in-

structions may use either two 8-bit wide CS pulses

or a single 16-bit wide CS pulse.

Table 1: Programmable Register Instructions

Byte 1

Function

Byte 2

7

6

5

4

3

2

1

0

Single Byte Power–up/down

P

X

0

X

None

Write Control Register

Read–back Control Register

P

0

1

X

See Table 2

Write Latch Direction Register (LDR)

Read Latch Direction Register

P

0

1

0

1

X

See Table 4

Write Latch Content Register (ILR)

Read Latch Content Register

P

0

1

0

1

X

See Table 5

Write Transmit Time–slot/port

Read–back Transmit Time–slot/port

P

1

0

1

0

1

X

See Table 6

Write Receive Time–slot/port

Read–back Receive Time–slot/port

P

1

0

1

0

1

X

See Table 6

Write Transmit Gain Register

Read Transmit Gain Register

P

0

1

0

1

0

1

X

See Table 7

Write Receive Gain Register

Read Receive Gain Register

P

0

1

0

1

X

See Table 8

Write Hybrid Balance Register ≠ 1

Read Hybrid Balance Register ≠ 1

P

0

1

0

1

X

See Table 9

Write Hybrid Balance Register ≠ 2

Read Hybrid Balance Register ≠ 2

P

0

1

0

1

X

See Table 10

Write Hybrid Balance Register ≠ 3

Read Hybrid Balance Register ≠ 3

P

1

0

1

X

Notes: 1. Bit 7 of bytes 1 and 2 is always the first bit clocked into or out of the CI, CO or CI/CO pin.

2. ”P” is the power-up/down control bit, see ”Power-up” section (”0” = Power Up ”1” = Power Down).

rate single-byte instruction. Any of the program-

PROGRAMMABLE FUNCTIONS

POWER-UP/DOWN CONTROL

mable registers may also be modified while the

device is powered-up or down be setting the ”P”

bit as indicated. When the power up or down con-

trol is entered as a single byte instruction, bit one

(1) must be set to a 0.

When a power-up command is given, all de-acti-

vated circuits are activated, but the TRI-STATE

PCM output(s), D_X0 (and D_X1), will remain in the

high impedance state until the second FS_Xpulse

after power-up.

Following power-on initialization, power-up and

power-down control may be accomplished by

writing any of the control instructions listed in ta-

ble 1 into COMBO IIG with the ”P” bit set to ”0”

for power-up or ”1” for power-down. Normally it is

recommended that all programmable functions be

initially programmed while the device is powered

down. Power state control can then be included

with the last programming instruction or the sepa-

7/30

TS5070 - TS5071

CONTROL REGISTER INSTRUCTION

ANALOG LOOPBACK

The first byte of a READ or WRITE instruction to

the Control Register is as shown in table 1. The

second byte functions are detailed in table 2.

Analog Loopback mode is entered by setting the

”AL” and ”DL” bits in the Control Register as shown

in table 2. In the analog loopback mode, the Trans-

mit input VF_XI is isolated from the input pin and in-

ternally connected to the VF_RO output, forming a

loop from the Receive PCM Register back to the

Transmit PCM Register. The VF_RO pin remains ac-

tive, and the programmed settings of the Transmit

and Receive gains remain unchanged, thus care

must be taken to ensure that overload levels are

not exceededanywhere in the loop.

MASTER CLOCK FREQUENCY SELECTION

A Master clock must be provided to COMBO IIG

for operation of the filter and coding/decoding

functions. The MCLK frequency must be either

512 kHz, 1.536 MHz, 1.544 MHz, 2.048 MHz, or

4.096 MHz and must be synchronous with BCLK.

Bits F1 and F0 (see table 2) must be set during

initialization to select the correct internal divider.

Hybrid balancing must be disabled for meaning

ful analog loopback Function.

CODING LAW SELECTION

Bits ”MA” and ”IA” in table 2 permit the selection

of µ255 coding or A-law coding with or without

even-bit inversion.

DIGITAL LOOPBACK

Digital Loopback mode is entered by setting the

”DL” bit in the Control Register as shown intable 2.

Table 2: Control Register Byte 2 Functions

Bit Number

Function

0

7

6

5

4

3

2

1

F1

F0

MA

IA

DN

DL

AL

PP

0

1

0

1

0

1

MCLK = 512 kHz

MCLK = 1. 536 or 1. 544 MHz

MCLK = 2. 048 MHz ^*

MCLK = 4. 096 MHz

0

1

X

0

1

Select µ. 255 Law ^*

A–law, Including Even Bit Inversion

A–Law, No Even Bit Inversion

0

1

Delayed Data Timing

Non–delayed Data Timing ^*

0

1

0

X

1

Normal Operation ^*

Digital Loopback

Analog Loopback

0

1

Power Amp Enabled in PDN

Power Amp Disabled in PDN

*

(*) State at power-on initialization (bit 4 = 0)

Table 3: Coding Law Conventions.

m255 Law

True A-law with

even bit inversion

MSB LSB

A-law without

even bit inversion

MSB LSB

V_IN= +Full Scale

V_IN= 0V

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

V_IN= -Full Scale

0

1

0

1

0

1

0

1

Note: The MSB is always the first PCM bit shifted in or out of COMBO IIG.

8/30

TS5070 - TS5071

This mode provides another stage of path verifica-

tion by enabling data written into the Receive PCM

Register to be read back from that register in any

Transmit time-slot at D_X0 or D_X1.

For Analog Loopback as well as for Digital Loop-

back PCM decoding continues and analog output

appears at VF_RO. The output can be disabled by

pro gramming ”No Output” in the Receive Gain

Register (see table 8).

INTERFACE LATCH STATES

Interface Latches configured as outputs assume

the state determined by the appropriate data bit in

the 2-byte instruction written to the Latch Content

Register (ILR) as shown in tables 1 and 5.

Latches configured as inputs will sense the state

applied by an external source, such as the Off-

Hook detect output of a SLIC. All bits of the ILR,

i.e. sensed inputs and the programmed state of

outputs, can be read back in the 2nd byte of a

READ from the ILR. It is recommended that, dur-

ing initialization, the state of IL pins to be config-

ured as outputs should first be programmed, fol-

lowed immediately by the Latch Direction

Register.

INTERFACE LATCH DIRECTIONS

Immediately following power-on, all Interface

Latches assume they are inputs, and therefore all

IL pins are in a high impedance state. Each IL pin

may be individually programmed as a logic input or

output by writing the appropriate instruction to the

LDR, see table 1 and 4. Bits L₅-L₀must be set by

writing the specific instruction to the LDR with the

L bits in the second byte set as specified in table 4.

Unused interface latches should be programmed

as outputs. For the TS5071, L5 should always be

programmed as an output.

Table 5: InterfaceLatch Data Bit Order

Bit Number

7

6

5

4

3

2

1

0

D0

D1

D2

D3

D4

D5

X

Table 4: Byte 2 Function of Latch Direction Register

Bit Number

TIME-SLOT ASSIGNMENT

7

6

5

4

3

2

1

0

COMBO IIG can operate in either fixed time-slot or

time-slot assignment mode for selecting the Trans-

mit and Receive PCM time-slots. Following power-

on, the deviceis automaticallyin Non-Delayed Tim-

ing mode, in which the time-slot always begins with

the leading (rising) edge of frame sync inputs FS_X

and FS_R. Time-Slot Assignment may only be used

with Delayed Data timing : see figure 6. FS_Xand

FS_Rmay have any phase relationship with each

other in BCLK period increments.

L0

L1

L2

L3

L4

L5

X

L_NBit

IL Direction

0

1

Input ^*

Output

(*) State at power-on initilization.

Note: L5 should be programmed as an output for the TS5071.

Table 6: Byte 2 of Time-slot and Port Assignment Instructions

Bit Number

Function

6

PS

5

T5

7

EN

4

T4

3

T3

2

T2

1

T1

0

T0

(note 1) (note 2)

Disable D_XOutputs (transmit instruction) *

Disable D_RInputs (receive instruction) *

0

1

X

0

X

Assign One Binary Coded Time-slot from 0–63

Enable D_X0 Output, Disable D_X1 Output

(Transmit instruction)

Enable D_R0 Input, Disable D_R1 Input

(Receive Instruction)

Assign One Binary Coded Time-slot from 0–63

Enable D_X1 Output, Disable D_X0 Output

(Transmit instruction)

Enable D_R1 Input, Disable D_R0 Input

1

(Receive Instruction)

Notes:

1. The ”PS” bit MUST always be set to 0 for the TS5071.

2. T5 is the MSB of the time-slot assignment.

(*) State at power-on initialization

9/30

TS5070 - TS5071

assignmentinstruction using the ”PS” bit inthe sec-

ond byte.

On the TS5071, only ports D_X0 and D_R0 are avail-

able, therefore the ”PS” bit MUST always be set to

0 for these devices.

Table 6 shows the format for the second byte of

bothtransmit andreceive time-slot and port assign-

ment instructions.

Alternatively, the internal time-slot assignment

counters and comparators can be used to access

anytime-slot in aframe,usingtheframe sync inputs

as marker pulses for the beginning of transmit and

receive time-slot 0. In this mode, a frame may con-

sist of up to 64 time-slots of 8 bits each. A time-slot

is assignedby a 2-byte instructionasshown intable

1 and6. The last 6 bits of the second byte indicate

the selected time-slot from 0-63 using straight bi-

nary notation. A new assignment becomes active

on the second frame following the end of the Chip

Select for the second control byte. The ”EN” bit al-

lows the PCM inputsD_R0/1 or outputsD_X0/1 as ap-

propriate, to be enabled or disabled.

TRANSMIT GAIN INSTRUCTION BYTE 2

The transmit gain can be programmed in 0.1 dB

steps by writing to the Transmit Gain Register as

defined in tables 1 and 7. This corresponds to a

range of 0 dBm0 levels at VF_XI between 1.619

Vrms and 0.087 Vrms (equivalent to + 6.4 dBm to

– 19.0 dBm in 600 Ω).

Time-Slot Assignment mode requires that the FS_X

and FS_Rpulsesmust conformto the delayed timing

format shown in figure 6.

To calculate the binary code for byte 2 of this in-

struction for any desired input 0 dBm0 level in

Vrms, take the nearest integer to the decimal

number given by :

PORT SELECTION

On the TS5070 only, an additional capability is

available : 2 Transmit serial PCM ports, D_X0 and

D_X1, and 2 receive serial PCM ports, D_R0 andD_R1,

are provided to enable two-way space switching to

be implemented. Port selections for transmit and

receive are made within the appropriate time-slot

200 X log₁₀(V/√6 ) + 191

and convert to the binary equivalent. Some exam-

ples are given in table 7.

Table 7: Byte 2 of Transmit Gain Instructions.

Bit Number

0dBm0 Test Leve at VF_XI

7

6

5

4

3

2

1

0

In dBm (Into 600Ω)

In Vrms (approx.)

0

No Output

0

1

0

– 19

– 18.9

0.087

0.088

1

0

1

0

0.775

1

0

1

+6.3

+6.4

1.60

1.62

(*) State at power initialization

RECEIVE GAIN INSTRUCTION BYTE 2

into a load of ≥ 300 Ω to GND.

The receive gain can be programmed in 0.1 dB

stepsby writingto the Receive Gain Register asde-

fined in table 1 and 8. Note the following restriction

on output drive capability :

To calculate the binary code for byte 2 of this in-

struction for any desired output 0 dBm0 level in

Vrms, take the nearest integer to the decimal num-

ber given by :

a) 0 dBm0 levels ≤ 8.1dBm at VF_RO may be

driven into a load of ≥ 15 kΩ to GND,

200 X log₁₀(V/√6 ) + 174

and convert to the binary equivalent. Some exam-

ples are given in table 8.

b) 0 dBm0 levels ≤ 7.6dBm at VF_RO may be

driven into a load of ≥ 600 Ω to GND,

c) 0 dBm levels ≤ 6.9dBm at VF_RO may be driven

10/30

TS5070 - TS5071

Table 8: Byte 2 of Receive Gain Instructions.

Bit Number

0dBm0 Test Leve at VF_R0

7

6

5

4

3

2

1

0

In dBm (Into 600Ω)

In Vrms (approx.)

0

No Output

0

1

0

– 17.3

– 17.2

0.106

0.107

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0.775

1.71

1.86

1.07

1

+ 6.9 (note 1)

+ 7.6 (note 2)

+ 8.1 (note 3)

1

Notes:

1. Maximum level into 300Ω ; 2. Maximum level into 600Ω;

3. R_L≥15KΩ (*) State at power on initialization

attenuator.

HYBRID BALANCE FILTER

The Bi-Quad mode of Hybal1 is most suitable for

balancing interfaces with transformers having high

inductance of 1.5 Henries or more. An alternative

configuration for smaller transformers is available

by converting Hybal1 to a simple first-order section

witha single real low frequencypole and0 Hz zero.

In this mode, the pole/zero frequency may be pro-

grammed.

Many line interfaces can be adequately balanced

by use of the Hybal1 section only, in which case

the Hybal2 filter should be de-selected to bypass

it.

The Hybrid Balance Filter on COMBO IIG is a

programmable filter consisting of a second-order

Bi-Quad section, Hybal1, followed by a first-order

section, Hybal2, and a programmable attenuator.

Either of the filter sections can be bypassed if

only one is required to achieve good cancellation.

A selectable 180 degree inverting stage is in-

cluded to compensate for interface circuits which

also invert the transmit input relative to the re-

ceive output signal. The Bi-Quad is intended

mainly to balance low frequency signals across a

transformer SLIC, and the first order section to

balance midrange to higher audio frequency sig-

nals. The attenuator can be programmed to com-

pensate for VF_RO to VF_XI echos in the range

of -2.5 to – 8.5 dB.

As a Bi-Quad, Hybal1 has a pair of low frequency

zeroes and a pair of complex conjugate poles.

When configuring the Bi-Quad, matching the

phase of the hybrid at low to midband frequencies

is most critical. Once the echo path is correctly

balancedin phase, the magnitude of the cancella-

tion signal can be corrected by the programmable

Hybal2, the higher frequencyfirst-order section, is

provided for balancing an electronic SLIC, and is

also helpful with a transformer SLIC in providing

additional phase correction for mid and high-band

frequencies, typically 1 kHz to 3.4 kHz. Such a

correction is particularly useful if the test balance

impedance includes a capacitor of 100 nF or less,

such as the loaded and non-loaded loop test net-

works in the United States. Independent place-

ment of the pole and zero location is provided.

Table 9: Hybrid Balance Register 1 Byte 2 Instruction.

Bit

State

Function

7

0

Disable Hybrid Balance Circuit Completely.

No internal cancellation is provided. ^*

1

0

Enable Hybrid Balance Cancellation Path

6

Phase of the internal cancellation signal assumes inverted phase of the echo

path from VF_RO to VF_XI.

1

Phase of the internal cancellation signal assumes no phase inversion in the line

interface.

5

0

1

Bypass Hybal 2 Filter Section

Enable Hybal 2 Filter Section

G4–G0

Attenuation Adjustment for the Magnitude of the Cancellation Signal. Range is

– 2.5 dB (00000) to – 8.5 dB (11000)

(*) State at power on initialization

Setting = Please refer to software TS5077 2

11/30

TS5070 - TS5071

former andthe impedanceof the 2 W loop, Z_L. If the

impedance reflected back into the transformer pri-

mary is expressed as Z_L’ then the echo path trans-

fer function from VF_RO to VF_XI is :

Figure 1 shows a simplified diagram of the local

echo path for a typical application with a trans-

former interface. The magnitude and phase of the

local echo signal, measured at VF_XI, are a function

of the termination impedance Z_T, the line trans-

H(W) = Z_L’ /(Z_T+ Z_L’)

(1)

Figure 1: Simplified Diagram of Hybrid Balance Circuit

PROGRAMMING THE FILTER

Register2: select/de-select Hybal1 filter;

set Hybal1 to Bi-Quad or 1st order;

program pole and zero frequency.

On initial power-up the Hybrid Balance filter is dis-

abled. Before the hybrid balance filter can be pro-

grammed it is necessary to design the transformer

and terminationimpedanceinorder tomeet system

2 W input return loss specifications, which are nor-

mally measured against a fixed test impedance

(600 or 900 Ω in most countries). Only then can the

echo path be modeled and the hybrid balance filter

programmed. Hybrid balancing is also measured

against a fixed test impedance, specified by each

national Telecom administration to provide ade-

quate control of talker and listener echo over the

majority of their network connections. This test im-

pedance is Z_Lin figure 1. The echo signal and the

degree of transhybrid loss obtained by the pro-

grammable filter must be measured from the PCM

digital input D_R0, to the PCM digital output D_X0,

eitherbydigital test signalanalysisorby conversion

back to analog by a PCM CODEC/Filter.

Table 10: Hybrid Balance Register 2 Byte 2 in-

structions

Bit Number

Function

7

6

5

4

3

2

1

0

By Pass Hybal 1

Filter

X

Pole/zero Setting

Register 3 : program pole frequencyin Hybal2 filter;

programzero frequencyin Hybal2 filter;

settings = Please refer to software

TS5077-2.

Standard filter design techniques may be used to

model the echo path (see equation (1)) and design

a matchinghybridbalance filterconfiguration.Alter-

natively, the frequency response of the echo path

can be measured and the hybrid balance filter pro-

grammed to replicate it.

Three registers must be programmed in COMBO

IIG to fully configure the Hybrid Balance Filter as

follows :

Register 1: select/de-select Hybrid Balance Filter;

invert/non-invert cancellation signal;

select/de-select Hybal2 filter section;

attenuatorsetting.

An Hybrid Balance filter design guide and soft-

ware optimization program are available under li-

cense from SGS-THOMSON Microelectronics (or-

der TS5077-2).

12/30

TS5070 - TS5071

foreanyother connectionsare made shouldalways

be followed.In applicationswheretheprintedcircuit

card may be plugged into a hot socket with power

and clocks already present, an extra long ground

pinon the connectorshouldbeusedand aSchottky

diode connected between V_SSand GND. To mini-

mize noise sources all ground connections to each

device should meet at a common point as close as

possible to the GND pin in order to prevent the in-

teraction of ground return currents flowing through

a common bus impedance. Power supply decou-

plingcapacitorsof 0.1µF should beconnectedfrom

this common device ground point to V_CCand V_SS

asclose tothedevicepinsas possible.V_CCandV_SS

should also be decoupledwith low effective series

resis-tancecapacitorsofatleast 10µF locatednear

the card edge connector.

APPLICATION INFORMATION

Figure 2 shows a typical application of the TS5070

together with a transformer SLIC.

The design of the transformer is greatly simplified

due to the on-chip hybridbalancecancellationfilter.

Only one single secondarywinding is required(see

application note AN.091 - Designing a subscriber

line card module using the TS5070/COMBOIIG).

Figures 3 and 4 show an arrangement with SGS-

Thomson monolithic SLICS.

POWER SUPPLIES

Whilethe pins of the TS5070 and TS5071/COMBO

IIG devices are well protected against electrical

misuse, it is recommended that the standard

CMOS practice of applying GND to the device be-

13/30

TS5070 - TS5071

Figure 2: Transformer SLIC + COMBO IIG.

14/30

TS5070 - TS5071

Figure 4: Interface with L3092 + L3000 Silicon SLIC.

15/30

TS5070 - TS5071

electrical testing at T_A= 25 °C. All other limits are

assured by correlation with other production tests

and/or productdesign and characterisation. All sig-

nals referencedto GND. Typicals specifiedat V_{CC =}

+ 5 V, V_SS= − 5 V, T_A= 25 °C.

ELECTRICAL OPERATING CHARACTERISTICS

Unless otherwisenoted, limits in BOLD characters

are guaranteed for V_CC= + 5 V ± 5 % ; V_SS= – 5

V ± 5 %. T_A=0 °C to 70°C bycorrelationwith 100%

DIGITAL INTERFACE

Symbol

V_IL

Parameter

Min.

2.0

Typ.

Max.

0.7

Unit

V

Input Low Voltage All Digital Inputs (DC measurement)

Input High Voltage All Digital Inputs (DC measurement)

V_IH

V

V_OL

Output Low Voltage

D_X0 and D_X1, TS_X0, TS_X1 and CO, I_L= 3.2mA

All Other Digital Outputs, I_L= 1mA

0.4

V

V_OH

Output High Voltage DX0 and DX1 and CO, I_L= -3.2mA

All other digital outputs except TS_X, I_L= -1mA

All Digital Outputs, I_L= -100µA

2.4

V_CC-0.5

V

I_IL

I_IH

Input Low Current all Digital Inputs (GND < V_IN< V_IL)

Input High Current all Digital Inputs Except MR (V_IH< V_IN< V_CC

Input High Current on MR

-10

10

µA

)

I_IH

100

10

I_OZ

Output Current in High Impedance State (TRI-STATE)

DX0 and DX1, CO and CI/O (as an input) IL5-IL0 as inputs

(GND < V_O< V_CC

)

ANALOG INTERFACE

Symbol

Parameter

Min.

-10

Typ.

620

Max.

10

Unit

µA

I_VFXI

R_VFXI

VOS_X

Input Current VF_XI (-3.3V < VF_XI < 3.3V)

Input Resistance VF_XI (-3.3V < VF_XI < 3.3V)

390

kΩ

Input offset voltage at VF_XI

0dBm0 = -19dBm

0dBm0 = +6.4dBm

10

200

mV

RL_VFROLoad Resistance at VF_RO

0dBm0 = 8.1dBm

15

600

300

kΩ

Ω

0dBm0 = 7.6dBm

0dBm0 = 6.9dBm

CL_VFROLoad Capacitance CLVFRO from VFRO to GND

200

3

pF

RO_VFROOutput Resistance VFRO (steady zero PCM code applied to DR0 or

D_R1)

1

Ω

V_OSR

Output Offset Voltage at VF_RO (alternating ±zero PCM code applied

-200

200

mV

to D_R0 or D_R1, 0dBm0 = 8.1dBm)

16/30

TS5070 - TS5071

ELECTRICAL OPERATING CHARACTERISTICS (continued)

POWER DISSIPATION

Symbol

Parameter

Min.

Typ.

Max.

1.5

Unit

ICC0

Power Down Current (CCLK, CI/O, CI = 0.4V, CS = 2.4V)

Interface Latches set as Outputs with no load

All over Inputs active, Power Amp Disabled

0.3

mA

-ISS0

ICC1

Power Down Current (as above)

0.1

0.3

mA

Power Up Current (CCLK, CI/O, CI = 0.4V, CS = 2.4V)

No Load on Power Amp

Interface Latches set as Outputs with no Load

7

2

11

3

mA

-ISS1

ICC2

-ISS2

Power Up Current (as above)

Power Down Current with Power Amp Enabled

3

sured by correlation with other production tests

and/or product design and characterization. All sig-

nals referenced to GND. Typicals specified at

V_CC= + 5 V, V_SS= -5 V, T_A= 25 °C. All timing pa-

rameters are measuredat V_OH= 2.0 V and V_OL=0.7 V.

See Definitions and Timing Conventions section

for test methods information.

TIMING SPECIFICATIONS

Unless otherwise noted, limits in BOLD characters are

guaranteedfor V_CC=+ 5 V ± 5 %; V_SS= -5V ± 5 %.

T_A= 0 °C to 70 °C by correlation with 100 % elec-

trical testing at T_A= 25 °C. All other limits are as-

MASTER CLOCK TIMING

Symbol

Parameter

Min.

Typ.

Max.

Unit

f_MCLK

Frequency of MCLK

(selection of frequency is programmable, see table 2)

512

kHz

MHz

1.536

1.544

2.048

4.096

t_WMH

t_WML

t_RM

Period of MCLK High (measured from V_IHto V_IH, see note 1)

Period of MCLK Low (measured from V_ILto V_IL, see note 1 )

Rise Time of MCLK (measured from V_ILor V_IH)

80

ns

30

t_FM

Fall Time of MCLK (measured from V_IHto V_IL)

t_HBM

t_WFL

Hold Time, BCLK Low to MCLK High (TS5070 only)

Period of FS_Xor FS_RLow (Measured from V_ILto V_IL)

50

ns

(*)

1

(*) MCLK period

17/30

TS5070 - TS5071

TIMING SPECIFICATIONS (continued)

PCM INTERFACE TIMING

Symbol

Parameter

Min.

64

Typ.

Max.

4096

Unit

f_BCLK

Frequency of BCLK (may vary from 64KHz to 4.096MHz in 8KHz

increments, TS5070 only)

kHz

t_WBH

t_WBL

t_RB

Period of BCLK High (measured from V_IHto V_IH)

Period of BCLK Low (measured from V_ILto V_IL)

Rise Time of BCLK (measured from V_ILto V_IH)

Fall Time of BCLK (measured from V_IHto V_IL)

Hold Time, BCLK Low to FS_X/RHigh or Low

Setup Time FS_X/RHigh to BCLK Low

80

ns

30

t_FB

t_HBF

t_SFB

t_DBD

30

Delay Time, BCLK High to Data Valid (load = 100pF plus 2 LSTTL

loads)

80

t_DBZ

Delay Time from BCLK8 Low to Dx Disabled (if FSx already low);

FSx Low to Dx Disabled (if BCLK8 low);

BCLK9 High to Dx Disabled (if FSx still high)

15

80

ns

t_DBT

t_ZBT

Delay Time from BCLK and FSx Both High to TSx Low (Load = 100pF

plus 2 LSTTL loads)

60

ns

Delay Time from BCLK8 low to TSx Disabled (if FSx already low);

15

60

FSx Low to TSx Disabled

BCLK9 High to TSx Disabled

(if BCLK8 low);

(if FSx still high);

t_DFD

Delay Time, FSx High to Data Valid (load = 100pF plus 2 LSTTL

loads, applies if FSx rises later than BCLK rising edge in non-

delayed data mode only)

80

ns

t_SDB

t_HBD

Setup Time, D_R0/1 Valid to BCLK Low

Hold Time, BCLK Low to DR0/1 Invalid

30

20

ns

Figure 5: Non Delayed Data Timing (short frame mode)

18/30

TS5070 - TS5071

Figure 6: Delayed Data Timing (short frame mode)

SERIAL CONTROL PORT TIMING

Symbol

f_CCLK

t_WCH

t_WCL

t_RC

Parameter

Min.

Typ.

Max.

Unit

MHz

ns

Frequency of CCLK

2.048

Period of CCLK High (measured from V_IHto V_IH)

Period of CCLK Low (measured from V_ILto V_IL)

Rise Time of CCLK (measured from V_ILto V_IH)

Fall Time of CCLK (measured from V_IHto V_IL)

Hold Time, CCLK Low to CS Low (CCLK1)

Hold Time, CCLK Low to CS High (CCLK8)

Setup Time, CS Transition to CCLK Low

160

ns

50

ns

t_FC

ns

t_HCS

t_HSC

t_SSC

10

100

70

ns

t_SSCO

Setup Time, CS Transition to CCLK High (to insure CO is not

enabled for single byte)

50

ns

t_SDC

t_HCD

t_DCD

Setup Time, CI (CI/O) Data in to CCLK low

Hold Time, CCLK Low to CI (CI/O) Invalid

50

ns

50

Delay Time, CCLK High to CO (CI/O) Data Out Valid

(load = 100 pF plus 2 LSTTL loads)

50

80

t_DSD

t_DDZ

Delay Time, CS Low to CO (CI/O) Valid

(applies only if separate CS used for byte 2)

ns

Delay Time, CS or CCLK9 High to CO (CI/O) High Impedance

(applies to earlier of CS high or CCLK9 high)

15

INTERFACE LATCH TIMING

Symbol

Parameter

Min.

100

50

Typ.

Max.

200

Unit

ns

t_SLC

t_HCL

t_DCL

Setup Time, I_LValid to CCLK 8 of Byte 1 Low. I_Las Input

Hold Time, I_LValid from CCLK 8 of Byte 1 Low. I_Las Input

Delay Time, CCLK 8 of Byte 2 Low to I_L. C_L= 50 pF. I_Las Output

ns

MASTER RESET PIN

Symbol

Parameter

Duration of Master Reset High

Min.

Max.

Unit

t_WMR

1

µs

19/30

TS5070 - TS5071

Figure 7: Control Port Timing

20/30

TS5070 - TS5071

f = 1031.25 Hz, VF_XI = 0 dBm0, D_R0 or D_R1 = 0

dBm0PCM code, Hybrid Balance filterdisabled. All

other limits are assured by correlation with other

production tests and/or product design and char-

acterization. All signals referenced to GND. dBm

levels are into 600 ohms. Typicals specified at

V_CC= + 5 V, V_SS= -5 V, T_A= 25 °C.

TRANSMISSION CHARACTERISTICS

Unless otherwise noted, limits printed in BOLD

characters are guaranteed for V_CC= + 5 V ± 5 % ;

V_SS= – 5 V ± 5 %, T_A= 0 °C to 70 °C by correlation

with 100 % electrical testing at T_A= 25 °C (-40°C

to 85°C for TS5070-Xand TS5071-X).

AMPLITUDE RESPONSE

Symbol

Parameter

Min.

Typ.

Max.

Unit

Absolute levels

The nominal 0 dBm 0 levels are :

VF_XI

0 dB Tx Gain

25.4 dB Tx Gain

1.618

86.9

Vrms

mVrms

VF_RO

0 dB Rx Attenuation (RL ≥ 15 kΩ)

0.5 dB Rx Attenuation (RL ≥ 600 Ω)

1.2 dB Rx Attenuation (RL ≥ 300 Ω)

25.4 dB Rx Attenuation

1.968

1.858

1.714

105.7

Vrms

mVrms

Maximum Overload

The nominal overload levels are :

A-law

VF_XI

0 dB Tx Gain

2.323

124.8

Vrms

mVrms

25.4 dB Tx Gain

VF_RO

0 dB Rx Attenuation (R_L≥ 15 kΩ)

0.5 dB Rx Attenuation (R_L≥ 300 Ω)

1.2 dB Rx Attenuation (R_L≥ 300 Ω)

25.4 dB Rx Attenuation

2.825

2.667

2.461

151.7

Vrms

mVrms

µ-law

VF_XI

0 dB Tx Gain

25.4 dB Tx Gain

2.332

125.2

Vrms

mVrms

VF_RO

0 dB Rx Attenuation (R_L≥ 15 kΩ)

0.5 dB Rx Attenuation (R_L≥ 600 Ω)

1.2 dB Rx Attenuation (R_L≥ 300 Ω)

25.4 dB Rx Attenuation

2.836

2.677

2.470

152.3

Vrms

mVrms

Transmit Gain Absolute Accurary

GXA

Transmit Gain Programmed for 0 dBm0 = 6.4 dBm, A-law

Measure Deviation of Digital Code from Ideal 0 dBm0 PCM Code

at D_X0/1, f = 1031.25 Hz

T

_A= 25 °C, V_CC= 5 V, V_SS= – 5 V

– 0.15

– 0.1

0.15

0.1

dB

Transmit gain Variation with Programmed Gain

GXAG

– 19 dBm ≤ 0 dBm0 ≤ 6.4 dBm

Calculate the Deviation from the Programmed Gain Relative to

GXA

i.e., GXAG = Gactual – Gprog – GXA

T

_A= 25 °C, V_CC= 5 V, V_SS= – 5 V

21/30

TS5070 - TS5071

AMPLITUDE RESPONSE (continued)

Symbol

Parameter

Min.

Typ.

Max.

Unit

GXAF

Transmit Gain Variation with Frequency

Relative to 1031.25 Hz (note 2)

-19 dBm < o dBm0 < 6.4 dBm

D_R0 (or D_R1) = 0 dBm0 Code

f = 60Hz

f = 200 Hz

f = 300 Hz to 3000 Hz

f = 3400 Hz

-26

-0.1

0.15

0

-14

-32

dB

-1.8

-0.15

-0.7

f = 4000 Hz

f > 4600 Hz Measure Response at Alias Frequency from 0 kHz to 4 kHz

0 dBm0 = 6.4 dBm

VFXI = -4 dBm0 (note2)

f = 62.5 Hz

f = 203.125 Hz

f = 2093.750 Hz

f = 2984.375 Hz

f = 3296.875 Hz

f = 3406.250 Hz

-24.9

-0.1

0.15

0

dB

-1.7

-0.15

-0.74

f = 3984.375 Hz

-13.5

-32

f = 5250 Hz, Measure 2750 Hz

f = 11750Hz, Measure 3750 Hz

f = 49750 Hz, Measure 1750 Hz

GXAT

GXAV

Transmit Gain Variation with Temperature

Measured Relative to GXA, VCC = 5V, VSS = -5V -19dBm < 0dBm < 6.4dBm

-0.1

0.1

dB

Transmit Gain Variation with Supply

V

_CC= 5V ± 5%, V_SS= -5V ± 5%

Measured Relative to GXA

T_A= 25 °C, o dBm0 = 6.4dBm

-0.05

0.05

dB

GXAL

GRA

Transmit Gain Variation with Signal Level

Sinusoidal Test Method, Reference Level = 0 dBm0

VF_XI = -40 dBm0 to + 3 dBm0

VF_XI = -50 dBm0 to -40 dBm0

-0.2

-0.4

-1.2

0.2

0.4

1.2

dB

VF_XI = -55 dBm0 to -50 dBm0

Receive Gain Absolute Accuracy

0 dBm0 = 8.1 dBm, A-law

Apply 0 dBm0 PCM Code to D_R0 or D_R1 Measure VF_RO, f =1015.625Hz

T_A= 25 °C, V_CC= 5V, V_SS= -5V

-0.15

-0.1

0.15

0.1

dB

GRAG Receive Gain Variation with Programmed Gain

-17.3 dBm < 0 dBm0 < 8.1 dBm

Calculate the Deviation from the Programmed Gain Relative to GRA

I.e. GRAG = Gactual - Gprog - GRA T_A= 25°C, V_CC= 5V, V_SS= -5V

22/30

TS5070 - TS5071

AMPLITUDE RESPONSE (continued)

Symbol

Parameter

Min.

-0.1

Typ.

Max.

0.1

Unit

dB

GRAT

Receive Gain Variation with Temperature

Measure Relative to GRA

V_CC= 5V, V_SS= -5V -17dBm < 0dBm0 < 8.1dBm

GRAV

GRAF

Receive Gain Variation with Supply

Measured Relative to GRA

V_CC= 5V ± 5%, V_SS= -5V ± 5%

T_A= 25°C, 0dBm 0 = 8.1 dBm

-0.05

0.05

dB

Receive Gain Variation with Frequency

Relative to 1015.625 Hz, (note 2)

D_R0 or D_R1 = 0 dBm0 Code

-17.3dBm < 0 dBm0 < 8.1dBm

f = 200Hz

f = 300Hz to 3000Hz

f = 3400Hz

-0.25

-0.15

-0.7

0.15

0

dB

f = 4000Hz

-14

GR = 0dBm0 = 8.1dBm

D_R0 = -4dBm0

Relative to 1015.625 (note 2)

f = 296.875 Hz

f = 1906.250Hz

f = 2812.500Hz

f = 2984.375Hz

-0.15

-0.74

0.15

0

dB

f = 3406.250Hz

f = 3984.375Hz

-13.5

GRAL

Receive Gain Variation with Signal Level

Sinusoidal Test Method Reference Level = 0dBm0

D_R0 = -40dBm0 to +3dBm0

D_R0 = -50dBm0 to -40dBm0

D_R0 = -55dBm0 to -50dBm0

DR0 = 3.1dBm0

-0.2

-0.4

-1.2

0.2

0.4

1.2

dB

R_L= 600Ω, 0dBm0 = 7.6dBm

R_L= 300Ω, 0dBm0 = 6.9dBm

-0.2

0.2

dB

23/30

TS5070 - TS5071

ENVELOPE DELAY DISTORTION WITH FREQUENCY

Symbol

Parameter

Min.

Typ.

Max.

Unit

DXA

Tx Delay Absolute

f = 1600 Hz

315

µs

DXR

Tx Delay, Relative to DXA

f = 500 – 600 Hz

f = 600 – 800 Hz

f = 800 – 1000 Hz

f = 1000 – 1600 Hz

f = 1600 – 2600 Hz

f = 2600 – 2800 Hz

f = 2800 – 3000 Hz

220

145

75

40

75

µs

105

155

DRA

DRR

Rx Delay, Absolute

f = 1600 Hz

200

µs

Rx Delay, Relative to DRA

f = 500 – 1000 Hz

f = 1000 – 1600 Hz

f = 1600 – 2600 Hz

f = 2600 – 2800 Hz

f = 2800 – 3000 Hz

– 40

– 30

µs

90

125

175

24/30

TS5070 - TS5071

NOISE

Symbol

Parameter

Min.

Typ.

Max.

Unit

NXC

Transmit Noise, C Message Weighted

µ-law Selected (note 3)

12

15

dBrnC0

0 dBm0 = 6.4dBm

NXP

NRC

NRP

NRS

Transmit Noise, Psophometric Weighted

A-law Selected (note 3)

0 dBm0 = 6.4dBm

-74

8

-67

11

dBm0p

dBrnC0

dBm0p

dBm0

Receive Noise, C Message Weighted

µ-law Selected

PCM code is alternating positive and negative zero

Receive Noise, Psophometric Weighted

A-law Selected

PCM Code Equals Positive Zero

-82

-79

-53

Noise, Single Frequency

f = 0Hz to 100kHz, Loop Around Measurement VF_XI = 0Vrms

PPSRX Positive Power Supply Rejection Transmit

_CC= 5V_DC+ 100mVrms

V

f = 0Hz to 4000Hz (note 4)

f = 4kHz to 50kHz

30

dBp

NPSRX Negative Power Supply Rejection Transmit

V

_SS= -5V_DC+ 100mVrms

f = 0Hz to 4000Hz (note 4)

f = 4kHz to 50kHz

30

dBp

PPSRR Positive Power Supply Rejection Receive

PCM Code Equals Positive Zero

V

_CC= 5V_DC+ 100mVrms

Measure VFR0

f = 0Hz to 4000Hz

f = 4kHz to 25kHz

f = 25kHz to 50kHz

30

40

36

dBp

dB

NPSRR Negative Power Supply Rejection Receive

PCM Code Equals Positive Zero

V

_SS= -5V_DC+ 100mVrms

Measure VFR0

f = 0Hz to 4000Hz

f = 4kHz to 25kHz

f = 25kHz to 50kHz

30

40

36

dBp

dB

SOS

Spurious Out-of Band Signals at the Channel Output

0dBm0 300Hz to 3400Hz input PCM code applied at D_R0 (D_R1)

Relative to f = 1062.5Hz

4600Hz to 7600Hz

7600Hz to 8400Hz

8400Hz to 50000Hz

-30

-40

-30

dB

25/30

TS5070 - TS5071

DISTORTION

Symbol

Parameter

Min.

Typ.

Max.

Unit

STDX

Signal to Total Distortion Transmit

Sinusoidal Test Method

Half Channel

Level = 3dBm0

Level = -30dBm0 to 0dBm0

Level = -40dBm0

33

36

30

25

dBp

Level = -45dBm0

STDR

Signal to Total Distortion Receive

Sinusoidal Test Method

Half Channel

Level = 3dBm0

Level = -30dBm0 to 0dBm0

Level = -40dBm0

Level = -45dBm0

33

36

30

25

dBp

SFDX

SFDR

IMD

Single Frequency Distortion Transmit

Single Frequency Distortion Receive

-46

-41

dB

Intermodulation Distortion Transmit or Receive

Two Frequencies in the Range 300Hz to 3400Hz

CROSSTALK

Symbol

Parameter

Min.

Typ.

Max.

-75

Unit

CTX-R Transmit to Receive Crosstalk,

0dBm0 Transmit Level

-90

dB

f = 300 to 3400Hz

DR = Idle PCM Code

CTR-X Receive to Transmit Crosstalk,

0dBm0 Receive Level

-90

-70

dB

f = 300 to 3400Hz (note 4)

Notes:

1. Applies only to MCLK frequencies ≥ 1.536 MHz. At 512 kHz A 50:50 ± 2 % duty cycle must be used.

2. A multi-tone test technique is used (peak/rms ≤ 9.5 dB).

3. Measured by grounded input at VF_XI.

4. PPSRX, NPSRX and CTR-X are measured with a – 50 dBm0 activation signal applied to VF_XI.

A signal is Valid if it is above V_IHor below V_ILand invalid if it is between V_ILand V_IH. For the purpose of the specification the following conditions

apply :

a) All input signals are defined as V_IL= 0.4 V, V_IH= 2.7 V, t_R< 10 ns, t_F10 ns

b) t_Ris measured from V_ILto V_IH, t_Fis measured from V_IHto V_IL

c) Delay Times are measured from the input signal Valid to the clock input invalid

d) Setup Times are measured from the data input Valid to the clock input invalid

e) Hold Times are measured from the clock signal Valid to the data input invalid

f) Pulse widths are measured from V_ILto V_ILor from V_IHto V

IH

26/30

TS5070 - TS5071

DEFINITIONS AND TIMING CONVENTIONS

DEFINITIONS

V_IH

VIH is the D.C. input level above which an input level is guaranteed to appear as a logical one.

This parameter is to be measured by performing a functional test at reduced clock speeds and

nominal timing (i.e. not minimum setup and hold times or output strobes), with the high level of

all driving signals set to V_IHand maximum supply voltages applied to the device.

V_IL

VIL is the D.C. input level below which an input level is guaranteed to appear as a logical zero

the device. This parameter is measured in the same manner as V_IHbut with all driving signal

low levels set to V_ILand minimum supply voltage applied to the device.

V_OH

V_OL

VOH is the minimmum D.C. output level to which an output placed in a logical one state will

converge when loaded at the maximum specified load current.

VOL is the maximum D.C. output level to which an output placed in a logical zero state will

converge when loaded at the maximum specified load current.

Threshold Region

Valid Signal

The threshold region is the range of input voltages between V_ILand V_IH.

A signal is Valid if it is in one of the valid logic states. (i.e. above V_IHor below V_IL). In timing

specifications, a signal is deemed valid at the instant it enters a valid state.

Invalid signal

A signal is invalid if it is not in a valid logic state, i.e., when it is in the threshold region between

V_ILand V_IH. In timing specifications, a signal is deemed Invalid at the instant it enters the

threshold region.

TIMING CONVENTIONS

For the purpose of this timing specifications the following conventions apply :

Input Signals

Period

All input signals may be characterized as : V_L= 0.4 V, V_H= 2.4 V, tR < 10 ns, tF < 10 ns.

The period of the clock signal is designated as tPxx where xx represents the mnemonic of the

clock signal being specified.

Rise Time

Rise times are designated as tRyy, where yy represents a mnemonic of the signal whose rise

time is being specified, tRyy is measured from V_ILto V_IH.

Fall Time

Fall times are designated as tFyy, where yy represents a mnemonic of the signal whose fall

time is being specified, tFyy is measured from V_IHto V_IL.

Pulse Width High

The high pulse width is designated as tWzzH, where zz represents the mnemonic of the input

or output signal whose pulse width is being specified. High pulse width are measured from V_IH

to V_IH.

Pulse Width Low

Setup Time

The low pulse is designated as tWzzL’ where zz represents the mnemonic of the input or output

signal whose pulse width is being specified. Low pulse width are measured from V_ILto V_IL.

Setup times are designated as tSwwxx where ww represents the mnemonic of the input signal

whose setup time is being specified relative to a clock or strobe input represented by mnemonic

xx. Setup times are measured from the ww Valid to xx Invalid.

Hold Time

Hold times are designated as THwwxx where ww represents the mnemonic of the input signal

whose hold time is being specified relative to a clock or strobe input represented by the

mnemonic xx. Hold times are measured from xx Valid to ww Invalid

Delay Time

Delay times are designated as TDxxyy [H/L], where xx represents the mnemonic of the input

reference signal and yy represents the mnemonic of the output signal whose timing is being

specified relative to xx. The mnemonic may optionally be terminated by an H or L to specify the

high going or low going transition of the output signal. Maximum delay times are measured from

xx Valid to yy Valid. Minimum delay times are measured from xx Valid to yy Invalid. This

parameter is tested under the load conditions specified in the Conditions column of the Timing

Specifications section of this datasheet.

27/30

TS5070 - TS5071

PLCC28 PACKAGE MECHANICAL DATA

mm

inch

TYP.

DIM.

MIN.

12.32

11.43

4.2

TYP.

MAX.

12.57

11.58

4.57

MIN.

0.485

0.450

0.165

0.090

0.020

0.390

MAX.

0.495

0.456

0.180

0.120

A

B

D

D1

D2

E

2.29

0.51

9.91

3.04

10.92

0.430

e

1.27

7.62

0.46

0.71

0.050

0.300

0.018

0.028

e3

F

F1

G

0.101

0.004

M

1.24

0.049

0.045

M1

1.143

28/30

TS5070 - TS5071

DIP20 PACKAGE MECHANICAL DATA

mm

inch

TYP.

DIM.

MIN.

0.254

1.39

TYP.

MAX.

MIN.

0.010

0.055

MAX.

a1

B

b

1.65

0.065

0.45

0.25

0.018

0.010

b1

D

E

e

25.4

1.000

8.5

2.54

0.335

0.100

0.900

e3

F

22.86

7.1

0.280

0.155

I

3.93

L

3.3

0.130

Z

1.34

0.053

29/30

TS5070 - TS5071

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the

consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No

license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications men-

tioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.

SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without ex-

press written approval of SGS-THOMSON Microelectronics.

1994 SGS-THOMSON Microelectronics - All RightsReserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore -

Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A.

30/30


型号：	BU5071
厂家：	ETC
描述：
文件：	总30页 (文件大小：394K)
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