CAT25C11SA-1.8 [ETC]
EEPROM ; EEPROM\n
| 型号： | CAT25C11SA-1.8 |
| 厂家： | 
ETC |
| 描述： | EEPROM
|
| 文件： | 总11页 (文件大小：88K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E
CAT25C11/03/05/09/17
1K/2K/4K/8K/16K SPI Serial CMOS EEPROM
FEATURES
TM
■ 1,000,000 program/erase cycles
■ 100 year data retention
■ Self-timed write cycle
■ 10 MHz SPI compatible
■ 1.8 to 6.0 volt operation
■ Hardware and software protection
■ Zero standby current
■ 8-pin DIP/SOIC, 8/14-pin TSSOP and 8-pin MSOP
■ 16/32-byte page write buffer
■ Low power CMOS technology
■ SPI modes (0,0 & 1,1)*
■ Write protection
– Protect first page, last page, any 1/4 array or
lower 1/2 array
■ Commercial, industrial, automotive and extended
temperature ranges
DESCRIPTION
input (SCK), data in (SI) and data out (SO) are required
to access the device. The HOLD pin may be used to
suspend any serial communication without resetting the
serialsequence.TheCAT25C11/03/05/09/17isdesigned
with software and hardware write protection features
including Block Write protection. The device is available
in 8-pin DIP, 8-pin SOIC, 8/14-pin TSSOP and 8-pin
MSOP packages.
The CAT25C11/03/05/09/17 is a 1K/2K/4K/8K/16K-Bit
SPI Serial CMOS EEPROM internally organized as
128x8/256x8/512x8/1024x8/2048x8 bits. Catalyst’s
advanced CMOS Technology substantially reduces
device power requirements. The CAT25C11/03/05
features a 16-byte page write buffer. The 25C09/17
featuresa32-bytepagewritebuffer.Thedeviceoperates
via the SPI bus serial interface and is enabled though a
ChipSelect(CS).InadditiontotheChipSelect,theclock
PIN CONFIGURATION
DIP Package (P, L)
SOIC Package (S, V)
TSSOP Package (U, Y)
TSSOP Package (U14, Y)
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
5
6
7
14
13
12
11
10
9
V
CC
V
CS
SO
WP
CS
SO
CS
SO
NC
NC
V
CC
1
2
3
4
8
7
6
5
CC
CS
V
CC
HOLD
SCK
SI
HOLD
SCK
SI
HOLD
SO
HOLD
SCK
SI
NC
WP
WP
NC
V
V
V
SS
SS
SS
NC
NC
WP
SCK
SI
MSOP Package (R, Z)*
BLOCK DIAGRAM
V
SS
8
1
2
3
4
8
7
6
5
CS
SO
WP
V
CC
HOLD
SCK
SENSE AMPS
SHIFT REGISTERS
V
SI
SS
*CAT25C11/03 only
COLUMN
DECODERS
PIN FUNCTIONS
WORD ADDRESS
BUFFERS
Pin Name
SO
Function
Serial Data Output
Serial Clock
SO
SI
I/O
CONTROL
SCK
WP
CS
EEPROM
ARRAY
SPI
CONTROL
LOGIC
XDEC
Write Protect
WP
HOLD
SCK
VCC
+1.8V to +6.0V Power Supply
Ground
VSS
BLOCK
PROTECT
LOGIC
CS
Chip Select
DATA IN
STORAGE
SI
Serial Data Input
Suspends Serial Input
No Connect
HOLD
NC
HIGH VOLTAGE/
TIMING CONTROL
STATUS
REGISTER
* Other SPI modes available on request.
© 2002 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1017, Rev. F
1
CAT25C11/03/05/09/17
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
Voltage on any Pin with
Respect to VSS(1) .................. –2.0V to +VCC +2.0V
VCC with Respect to VSS ................................ –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Min.
1,000,000
100
Max.
Units
Cycles/Byte
Years
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
(3)
NEND
(3)
TDR
Data Retention
ESD Susceptibility
Latch-Up
(3)
VZAP
2000
Volts
(3)(4)
ILTH
100
mA
D.C. OPERATING CHARACTERISTICS
= +1.8V to +6.0V, unless otherwise specified.
V
CC
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
ICC1
Power Supply Current
(Operating Write)
5
3
0
mA
VCC = 5V @ 5MHz
SO=open; CS=Vss
ICC2
ISB
Power Supply Current
(Operating Read)
mA
VCC = 5.5V
FCLK = 5MHz
Power Supply Current
(Standby)
µA
CS = VCC
VIN = VSS or VCC
ILI
Input Leakage Current
Output Leakage Current
2
3
µA
µA
ILO
VOUT = 0V to VCC
,
CS = 0V
(5)
VIL
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
-1
VCC x 0.3
VCC + 0.5
0.4
V
V
V
V
(5)
VIH
VCC x 0.7
VOL1
VOH1
2.7V≤V <5.5V
CC
I
I
= 3.0mA
= -1.6mA
OL
OH
VCC - 0.8
VCC-0.2
VOL2
VOH2
Output Low Voltage
Output High Voltage
0.2
V
V
1.8V≤VCC<2.7V
IOL = 150µA
IOH = -100µA
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V +2.0V for periods of less than 20 ns.
CC
CC
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.
CC
(5) V
and V
are reference values only and are not tested.
ILMIN
IHMAX
Doc. No. 1017, Rev. F
2
CAT25C11/03/05/09/17
(1)
PIN CAPACITANCE
Applicable over recommended operating range from TA=25˚C, f=1.0 MHz, VCC=+5.0V (unless otherwise noted).
Symbol
COUT
CIN
Test Conditions
Max.
Units
pF
Conditions
VOUT=0V
VIN=0V
Output Capacitance (SO)
8
6
Input Capacitance (CS, SCK, SI, WP, HOLD)
pF
A.C. CHARACTERISTICS
SYMBOL PARAMETER
Limits
1.8V-6.0V
Min.
2.5V-6.0V
4.5V-5.5V
Test
Max. Min.
Max. Min. Max.
UNITS Conditions
tSU
tH
Data Setup Time
Data Hold Time
50
50
20
20
75
75
DC
20
20
40
40
ns
ns
ns
ns
MHz
ns
µs
µs
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWH
tWL
fSCK
tLZ
SCK High Time
250
250
DC
SCK Low Time
Clock Frequency
HOLD to Output Low Z
Input Rise Time
1
50
2
5
50
2
DC
10
50
2
(1)
tRI
CL = 50pF
(note 2)
(1)
tFI
Input Fall Time
2
2
2
tHD
tCD
HOLD Setup Time
HOLD Hold Time
Write Cycle Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD to Output High Z
CS High Time
100
100
40
40
40
40
(3)
tWC
tV
10
5
5
250
75
40
tHO
tDIS
tHZ
0
0
0
250
150
75
50
75
50
tCS
500
500
500
150
150
100
100
100
50
100
100
100
50
tCSS
tCSH
tWPS
tCSH
CS Setup Time
CS Hold Time
WP Setup Time
CS Hold Time
50
50
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) AC Test Conditions:
Input Pulse Voltages: 0.3V to 0.7V
CC
CC
Input rise and fall times: ≤10ns
Input and output reference voltages: 0.5V
CC
Output load: current source IOL max/IOH max; C = 50pF
L
(3)
t
is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
WC
Doc. No. 1017, Rev. F
3
CAT25C11/03/05/09/17
the operation to be performed.
FUNCTIONAL DESCRIPTION
The CAT25C11/03/05/09/17 supports the SPI bus data
transmission protocol. The synchronous Serial Periph-
eral Interface (SPI) helps the CAT25C11/03/05/09/17 to
interface directly with many of today’s popular
microcontrollers. The CAT25C11/03/05/09/17 contains
an8-bitinstructionregister. (Theinstructionset andthe
operation codes are detailed in the instruction set table)
PIN DESCRIPTION
SI: Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses, and data to be written to the
25C11/03/05/09/17.Input data is latched on the rising
edge of the serial clock for SPI modes (0, 0 & 1, 1).
After the device is selected with CS going low, the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
Thefirstbytecontainsoneofthesixop-codesthatdefine
SO: Serial Output
SO is the serial data output pin. This pin is used to transfer
data out of the 25C11/03/05/09/17. During a read cycle,
data is shifted out on the falling edge of the serial clock for
Figure 1. Sychronous Data Timing
t
CS
VIH
CS
VIL
t
CSH
t
CSS
VIH
VIL
t
t
WL
SCK
SI
WH
t
t
H
SU
VIH
VALID IN
V
IL
t
RI
FI
t
t
V
t
t
HO
DIS
VOH
VOL
HI-Z
HI-Z
SO
Note: Dashed Line= mode (1, 1) – – – –
INSTRUCTION SET
Instruction
Opcode
Operation
WREN
WRDI
0000 0110
0000 0100
0000 0101
0000 0001
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
RDSR
WRSR
READ
WRITE
(1)
0000 X011
0000 X010
(1)
(2)(3)
Power-Up Timing
Symbol
Parameter
Max.
Units
ms
tPUR
Power-up to Read Operation
Power-up to Write Operation
1
1
tPUW
ms
Note:
(1) X=0 for 25C11, 25C03, 25C09, 25C17. X=A8 for 25C05
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) t
and t
are the delays required from the time V is stable until the specified operation can be initiated.
PUR
PUW
CC
Doc. No. 1017, Rev. F
4
CAT25C11/03/05/09/17
and forces the devices into a Standby Mode (unless an
internal write operation is underway) The CAT25C11/03/
05/09/17 draws ZERO current in the Standby mode. A
high to low transition on CS is required prior to any
sequence being initiated. A low to high transition on CS
after a valid write sequence is what initiates an internal
write cycle.
SPI modes (0,0 & 1,1).
SCK: Serial Clock
SCK is the serial clock pin. This pin is used to synchronize
the communication between the microcontroller and the
25C11/03/05/09/17. Opcodes, byte addresses, or data
present on the SI pin are latched on the rising edge of the
SCK. Data on the SO pin is updated on the falling edge of
the SCK for SPI modes (0,0 & 1,1).
WP: Write Protect
WPistheWriteProtectpin. TheWriteProtectpinwillallow
normalread/writeoperationswhenheldhigh.WhenWPis
tiedlowandtheWPENbitinthestatusregisterissetto"1",
all write operations to the status register are inhibited. WP
going low while CS is still low will interrupt a write to the
status register. If the internal write cycle as already been
initiated, WP going low will have no effect on any write
CS: Chip Select
CS is the Chip select pin. CS low enables the CAT25C11/
03/05/09/17 and CS high disables the CAT25C11/03/05/
09/17. CShigh takes the SO output pin to high impedance
BYTE ADDRESS
Device
Address Significant Bits
Address Don't Care Bits
# Address Clock Pulse
CAT25C11
CAT25C03
CAT25C05
CAT25C09
CAT25C17
A6 - A0
A7
—
8
8
A7 - A0
A7 - A0 (A8 = X bit from Opcode)
A9 - A0
—
8
A15 - A10
A15 - A11
16
16
A10 - A0
STATUS REGISTER
7
6
1
5
1
4
3
2
1
0
WPEN
BP2
BP1
BP0
WEL
RDY
MEMORY PROTECTION
25C11
25C03
25C05
25C09
25C17
BP2
0
BP1
0
BP0
0
Q1
Q2
Q3
Q4
H1
P0
Pn
00-1F
20-3F
40-5F
60-7F
00-3F
00-0F
70-7F
00-3F 000-07F 000-0FF 000-1FF
40-7F 080-0FF 100-1FF 200-3FF
80-BF 100-17F 200-2FF 400-5FF
C0-FF 180-1FF 300-3FF 600-7FF
00-7F 000-0FF 000-1FF 000-3FF
00-0F 000-00F 000-01F 000-01F
F0-FF 1F0-1FF 3E0-3FF 7E0-7FF
Non-Protection
Q1 Protected
Q2 Protected
Q3 Protected
Q4 Protected
H1 Protected
P0 Protected
Pn Protected
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
WRITE PROTECT ENABLE OPERATION
Protected
Blocks
Unprotected
Blocks
Status
Register
WPEN
WP
WEL
0
X
0
Protected
Protected
Protected
Protected
Protected
Protected
Protected
Writable
Protected
Writable
Protected
Writable
Protected
Writable
0
1
1
X
X
X
1
0
1
0
1
Low
Low
High
High
Protected
Protected
Protected
Writable
Doc. No. 1017, Rev. F
5
CAT25C11/03/05/09/17
operation to the status register. The WP pin function is
blockedwhentheWPENbitissetto0.Figure10illustrates
the WP timing sequence during a write operation.
03/05/09/17 is busy with a write operation. When set to
1awritecycleisinprogressandwhensetto0thedevice
indicates it is ready. This bit is read only the WEL (Write
Enable) bit indicates the status of the write enable latch.
When set to 1, the device is in a Write Enable state and
when set to 0 the device is in a Write Disable state. The
WELbitcanonlybesetbytheWRENinstructionandcan
be reset by the WRDI instruction.
HOLD: Hold
HOLD is the HOLD pin. The HOLD pin is used to pause
transmission to the CAT25C11/03/05/09/17 while in the
middle of a serial sequence without having to re-transmit
entire sequence at a later time. To pause, HOLD must be
brought low while SCK is low. The SO pin is in a high
impedance state during the time the part is paused, and
transitions on the SI pins will be ignored. To resume
communication, HOLD is brought high, while SCK is low.
HOLD should be held high any time this function is not
being used. HOLD may be tied high directly to VCC or tied
to VCC through a resistor. Figure 9 illustrates hold timing
sequence.
The BP0, BP1 and BP2 bits indicate which part of the
memory array is currently protected. These bits are set
by the user issuing the WRSR instruction. The user is
allowed to protect from one page to as much as half the
entire array. Once the three protection bits are set the
associated memory can be read but not written until the
protection bits are reset. These bits are non volatile.
TheWPEN(WriteProtectEnable)isanenablebitforthe
WP pin. The WP pin and WPEN bit in the status register
control the programmable hardware write protect fea-
ture. Hardware write protection is enabled when WP is
low and WPEN bit is set to high. The user cannot write
to the status register, (including the block protect bits
STATUS REGISTER
The Status Register indicates the status of the device.
The RDY (Ready) bit indicates whether the CAT25C11/
Figure 2. WREN Instruction Timing
CS
SK
1
1
0
SI
0
0
0
0
0
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) – – – –
Figure 3. WRDI Instruction Timing
CS
SK
SI
1
0
0
0
0
0
0
0
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) – – – –
Doc. No. 1017, Rev. F
6
CAT25C11/03/05/09/17
and the WPEN bit) and the block protected sections in
the memory array when the chip is hardware write
protected. Only the sections of the memory array that
are not block protected can be written. Hardware write
protection is disabled when either WP pin is high or the
WPEN bit is zero.
After the correct read instruction and address are sent,
the data stored in the memory at the selected address is
shifted out on the SO pin. The data stored in the memory
atthenextaddresscanbereadsequentiallybycontinuing
to provide clock pulses. The internal address pointer is
automatically incremented to the next higher address
after each byte of data is shifted out. When the highest
address is reached, the address counter rolls over to
0000hallowingthereadcycletobecontinuedindefinitely.
DEVICE OPERATION
Write Enable and Disable
The read operation is terminated by pulling the CS high.
Read sequece is illustrated in Figure 4. Reading status
register is illustrated in Figure 5. To read the status
register, RDSR instruction should be sent. The contents
of the status register are shifted out on the SO line. If a
non-volatile write is in progress, the RDSR instruction
returns a high on SO. When the non-volatile write cycle
is completed, the status register data is read out.
The CAT25C11/03/05/09/17 contains a write enable
latch. This latch must be set before any write operation.
The device powers up in a write disable state when Vcc
is applied. WREN instruction will enable writes (set the
latch) to the device. WRDI instruction will disable writes
(reset the latch) to the device. Disabling writes will
protect the device against inadvertent writes.
READ Sequence
WRITE Sequence
The part is selected by pulling CS low. The 8-bit read
instructionistransmittedtotheCAT25C11/03/05/09/17,
followed by the 16-bit address for 25C09/17 (only 10-bit
addresses are used for 25C09, 11-bit addresses are
used for 25C17. The rest of the bits are don't care bits)
and 8-bit address for 25C11/03/05 (for the 25C05, bit 3
of the read data instruction contains address A8).
The CAT25C11/03/05/09/17 powers up in a Write Dis-
able state. Prior to any write instructions, the WREN
instruction must be sent to CAT25C11/03/05/09/17.
The device goes into Write enable state by pulling the
CS low and then clocking the WREN instruction into
CAT25C11/03/05/09/17. The CS must be brought high
Figure 4. Read Instruction Timing
CS
*
*
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
SK
OPCODE
BYTE ADDRESS*
A
N
A
0
SI
0
0
0
0
X*
0
1
1
DATA OUT
HIGH IMPEDANCE
SO
7
6
5
4
3
2
1
0
MSB
*Please check the Byte Address Table.
*X = 0 for CAT25C11, CAT25C03, CAT25C09 and CAT25C17; X = A8 for CAT25C05.
Note: Dashed Line= mode (1, 1) – – – –
Doc. No. 1017, Rev. F
7
CAT25C11/03/05/09/17
enable latch will not have been properly set. Also, for a
successful write operation the address of the memory
location(s) to be programmed must be outside the pro-
tected address field.
device.Ifthewriteoperationisinitiatedimmediatelyafter
the WREN instruction without CS being brought high,
the data will not be written to the array because the write
up to 16 bytes of data to the CAT25C11/03/05 and 32
bytes of data for 25C09/17. After each byte of data
received, lower order address bits are internally
incremented by one; the high order bits of address
willremain constant.The only restriction is that the X
(X=16 for 25C11/03/05 and X=32 for 25C09/17) bytes
must reside on the same page. If the address counter
reaches the end of the page and clock continues, the
counter will “rollover”tothefirstaddressofthepageand
overwrite any data that may have been written. The
CAT25C11/03/05/09/17 is automatically returned to the
write disable state at the completion of the write cycle.
Figure 8 illustrates the page write sequence.
Byte Write
Once the device is in a Write Enable state, the user may
proceed with a write sequence by setting the CS low,
issuing a write instruction via the SI line, followed by the
16-bit address for 25C09/17. (only 10-bit addresses are
used for 25C09, 11-bit addresses are used for 25C17.
The rest of the bits are don't care bits) and 8-bit address
for 25C11/03/05 (for the 25C05, bit 3 of the read data
instructioncontainsaddressA8). Programmingwillstart
aftertheCSisbroughthigh.Figure6illustratesbytewrite
sequence.
To write to the status register, the WRSR instruction
should be sent. Only Bit 2, Bit 3, Bit 4 and Bit 7 of the
status register can be written using the write status
register instruction. Figure 7 illustrates the sequence of
writing to status register.
Page Write
The CAT25C11/03/05/09/17 features page write capa-
bility. After the initial byte, the host may continue to write
after the WREN instruction to enable writes to thee
Figure 5. RDSR Instruction Timing
CS
0
1
2
3
4
5
1
6
0
7
1
8
9
10
11
12
13
14
SCK
OPCODE
0
0
0
0
0
SI
DATA OUT
HIGH IMPEDANCE
SO
5
7
6
4
3
2
1
0
MSB
Note: Dashed Line= mode (1, 1) – – – –
Figure 6. Write Instruction Timing
CS
*
*
0
1
2
3
4
5
6
7
8
21 22 23 24 25 26 27 28 29 30 31
SK
SI
OPCODE
BYTE ADDRESS*
A
DATA IN
A
N
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
X*
0
1
0
HIGH IMPEDANCE
SO
*Please check the Byte Address Table
X = 0 for CAT25C11, CAT25C03, CAT25C09 and CAT25C17; X = A8 for CAT25C05
Note: Dashed Line= mode (1, 1) – – – –
Doc. No. 1017, Rev. F
8
CAT25C11/03/05/09/17
DESIGN CONSIDERATIONS
number of clock cycles to start an internal write cycle.
Access to the array during an internal write cycle is
ignored and programming is continued. On power up,
SO is in a high impedance. If an invalid op code is
received, no data will be shifted into the CAT25C11/03/
05/09/17, and the serial output pin (SO) will remain in a
high impedance state until the falling edge of CS is
detected again.
The CAT25C11/03/05/09/17 powers up in a write dis-
able state and in a low power standby mode. A WREN
instruction must be issued to perform any writes to the
device after power up. Also,on power up CS should be
brought low to enter a ready state and receive an
instruction. After a successful byte/page write or status
register write the CAT25C11/03/05/09/17 goes into a
writedisablemode.CSmustbesethighaftertheproper
Figure 7. WRSR Instruction Timing
CS
0
1
2
3
4
5
6
7
1
8
9
6
10
5
11
4
12
13
2
14
1
15
0
SCK
OPCODE
DATA IN
SI
0
0
0
0
0
0
0
7
3
MSB
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) – – – –
Figure 8. Page Write Instruction Timing
CS
24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1
0
1
2
3
4
5
6
7
8
21 22 23
32-39
24-31
SK
SI
DATA IN
Data Data
Byte 2 Byte 3
BYTE ADDRESS*
A
OPCODE
Data
Byte 1
Data Byte N
A
0
0
0
0
X*
0
1
0
N
0
0
7..1
HIGH IMPEDANCE
SO
*Please check the Byte Address Table.
*X = 0 for CAT25C11, CAT25C03, CAT25C09 and CAT25C17; X = A8 for CAT25C05
Note: Dashed Line= mode (1, 1) – – – –
Doc. No. 1017, Rev. F
9
CAT25C11/03/05/09/17
Figure 9. HOLD Timing
CS
t
t
CD
CD
SCK
t
HD
t
HD
HOLD
SO
t
HZ
HIGH IMPEDANCE
t
LZ
Figure 10. WP Timing
t
t
WPH
WPS
CS
SCK
WP
t
CSH
WP
Note: Dashed Line= mode (1, 1) – – – –
Doc. No. 1017, Rev. F
10
ORDERING INFORMATION
Prefix
Device #
Suffix
-1.8
25C17
CAT
TE13
I
S
Optional
Company ID
Temperature Range
Tape & Reel
Product
Blank = Commercial (0°C to +70°C)
I = Industrial (-40°C to +85°C)
A = Automotive (-40°C to +105°C)
E = Extended (-40°C to +125°C)
TE13: 2000/Reel
Number
25C17:16K
25C09: 8K
25C05: 4K
25C03: 2K
25C11: 1K
Operating Voltage
Blank (Vcc=2.5 to 6.0V)
1.8 (Vcc=1.8 to 6.0V)
Package
P = 8-pin PDIP
R = 8-pin MSOP2
S = 8-pin SOIC
U = 8-pin TSSOP
U14 = 14-pin TSSOP
L = PDIP (Lead free, Halogen free)
V = SOIC, JEDEC (Lead free, Halogen free)
X = SOIC, EIAJ (Lead free, Halogen free)
Y = TSSOP (Lead free, Halogen free)
Z = MSOP2 (Lead free, Halogen free)
Notes:
(1) The device used in the above example is a 25C17SI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating Voltage,
Tape & Reel)
(2) CAT25C11 and CAT25C03 only.
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™
DPPs ™ AE2 ™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
Publication #: 1017
Revison:
Issue date:
Type:
F
9/24/02
www.catalyst-semiconductor.com
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