CAT523J-TE13_技术文档

CAT523

Configured Digitally Programmable Potentiometer (DPP™): Programmable Voltage Applications

APPLICATIONS

FEATURES

■ Two 8-bit DPPs Configured as Programmable

■ Automated product calibration.

■ Remote control adjustment of equipment

Voltage Sources in DAC-like Applications

■ Common Reference Inputs

■ Offset, gain and zero adjustments in Self-

■ Non-volatile NVRAM Memory Wiper Storage

■ Output voltage range includes both supply rails

Calibrating and Adaptive Control systems.

■ Tamper-proof calibrations.

■ 2 independently addressable buffered

■ DAC (with memory) substitute

output wipers

■ 1 LSB Accuracy, High Resolution

■ Serial Microwire-like interface

■ Single supply operation: 2.7V-5.5V

■ Setting read-back without effecting outputs

DESCRIPTION

values without effecting the stored settings and stored

settings can be read back without disturbing the

DPP’s output.

The CAT523 is a dual, 8-bit digitally-programmable

potentiometer (DPP™) configured for programmable

voltage and DAC-like applications. Intended for final

calibration of products such as camcorders, fax

machines and cellular telephones on automated high

volume productionlines, it is also well suited for systems

capable of self calibration, and applications where

equipment which is either difficult to access or in a

hazardous environment, requires periodic adjustment.

Control of the CAT523 is accomplished with a simple 3

wire, Microwire-like serial interface. A Chip Select pin

allows several CAT523's to share a common serial

interface and communication back to the host controller

is via a single serial data line thanks to the CAT523’s Tri-

Stated Data Output pin. A RDY/BSY output working in

concert with an internal low voltage detector signals

properoperationofnon-volatileNVRAMmemoryErase/

Write cycle.

The two independently programmable DPPs have a

common output voltage range which includes both

supply rails. The wipers are buffered by rail to rail op

amps. Wiper settings, stored in non-volatile NVRAM

memory, are not lost when the device is powered down

and are automatically reinstated when power is

returned. Each wiper can be dithered to test new output

The CAT523 is available in the 0 to 70° C Commercial

and –40° C to + 85° C Industrial operating temperature

ranges and offered in 14-pin plastic DIP and SOIC

mount packages.

PIN CONFIGURATION

FUNCTIONAL DIAGRAM

RDY/BSY

V

DD

REFH

SOIC Package (J)

DIP Package (P)

14

3

1

7

PROGRAM

CONTROL

V

DD

V

PROG

V

1

2

3

4

5

6

14

13

12

11

10

9

1

2

3

4

5

6

14

13

12

11

10

9

DD

REFH

CLK

RDY/BSY

CS

CLK

OUT1

V

RDY/BSY

CS

OUT2

NC

OUT2

NC

CAT

523

CAT

523

5

2

DI

13

12

+

WIPER

CONTROL

REGISTER

AND

DI

V

DI

NC

V

NC

V

OUT1

28KΩ

SERIAL

CONTROL

DO

REFL

CLK

NVRAM

PROG

GND

PROG

GND

8

7

8

7

4

CS

V

28KΩ

OU

SERIAL

DATA

6

DO

OUTPUT

REGISTER

CAT523

8

9

GND

V

REFL

Doc. No. 2005, Rev. A

1

Characteristics subject to change without notice

CAT523

ABSOLUTE MAXIMUM RATINGS

Operating Ambient Temperature

Commercial (‘C’ or Blank suffix)

Industrial (‘I’ suffix)

Junction Temperature

Storage Temperature

0°C to +70°C

– 40°C to +85°C

+150°C

–65°C to +150°C

+300°C

Supply Voltage*

V_DDto GND

Inputs

–0.5V to +7V

CLK to GND

CS to GND

DI to GND

–0.5V to V_DD+0.5V

Lead Soldering (10 sec max)

*StressesabovethoselistedunderAbsoluteMaximumRatings

may cause permanent damage to the device. Absolute

Maximum Ratings are limited values applied individually while

other parameters are within specified operating conditions,

and functional operation at any of these conditions is NOT

implied.Deviceperformanceandreliabilitymaybeimpairedby

exposure to absolute rating conditions for extended periods of

time.

RDY/BSY to GND

PROG to GND

V_REFH to GND

V_REFL to GND

Outputs

D₀to GND

V_OUT1– 4 to GND

–0.5V to V_DD+0.5V

RELIABILITY CHARACTERISTICS

Symbol

Parameter

Min

Max

Units

Test Method

(1)

V_ZAP

ESD Susceptibility

Latch-Up

2000

100

Volts

mA

MIL-STD-883, Test Method 3015

JEDEC Standard 17

(1)(2)

I_LTH

NOTES: 1. This parameter is tested initially and after a design or process change that affects the parameter.

2. Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to V_CC+ 1V.

POWER SUPPLY

I_DD1

I_DD2

Supply Current (Read)

Supply Current (Write)

Normal Operating

Programming, V_DD= 5V

V_DD= 3V

—

400

1600

1000

—

600

2500

1600

5.5

µA

V

—

V_DD

Operating Voltage Range

2.7

LOGIC INPUTS

I_IH

Input Leakage Current

V_IN= V_DD

V_IN= 0V

—

2

—

10

-10

V_DD

0.8

µA

V

I_IL

Input Leakage Current

High Level Input Voltage

Low Level Input Voltage

V_IH

V_IL

0

V

LOGIC OUTPUTS

V_OH

V_IL

High Level Output Voltage I_OH= -40µA

V_DD-0.3

—

V

Low Level Output Voltage I_OL= 1 mA, V_DD= +5V

I_OL= 0.4 mA, V_DD= +3V

—

0.4

Doc. No. 2005, Rev. A

2

CAT523

POTENTIOMETER CHARACTERISTICS

V_DD= +2.7V to +5.5V, V_REFH = V_DD, V_REFL = 0V, unless otherwise specified

Symbol Parameter

Conditions

Min

Typ

28kΩ

+0.5

Max

Units

R_POT

Potentiometer Resistance

R_POTto R_POTMatch

Pot Resistance Tolerance

Voltage on V_REFHpin

Voltage on V_REFLpin

Resolution

—

+1

+15

%

2.7

OV

V_DD

V

V_DD- 2.7

V

0.4

0.5

%

INL

Integral Linearity Error

Differential Linearity Error

Buffer Output Resistance

Buffer Output Current

TC of Pot Resistance

1

0.5

10

3

LSB

Ω

DNL

0.25

R_OUT

I_OUT

mA

TC_RPOT

300

8/8

ppm/˚C

Ω

TC_RATIORatiometric TC

R_ISO

V_N

Isolation Resistance

Noise

nV/√Hz

pF

C_H/C_L

fc

Potentiometer Capacitances

Frequency Response

Passive Attenuator

MHz

AC ELECTRICAL CHARACTERISTICS:

V_DD= +2.7V to +5.5V, V_REFH = V_DD, V_REFL = 0V, unless otherwise specified

Symbol Parameter

Conditions

Min

Typ

Max

Units

Digital

t_CSMIN

t_CSS

t_CSH

t_DIS

Minimum CS Low Time

150

100

0

—

400

4

—

150

—

5

ns

CS Setup Time

CS Hold Time

ns

DI Setup Time

50

ns

CL=100pF,

t_DIH

DI Hold Time

50

ns

see note 1

t_DO1

t_DO0

t_HZ

Output Delay to 1

Output Delay to 0

Output Delay to High-Z

Output Delay to Low-Z

Erase/Write Cycle Time

PROG Setup Time

Minimum Pulse Width

Minimum CLK High Time

Minimum CLK Low Time

Clock Frequency

—

ns

—

ns

—

ns

t_LZ

—

ns

t_BUSY

t_PS

—

ms

ns

150

700

500

300

DC

—

1

t_PROG

ns

t_CLK

f_C

H

ns

L

ns

MHz

Analog

t_DS

DPP Settling Time to 1 LSB

C_LOAD= 10 pF, V_DD= +5V

C_LOAD= 10 pF, V_DD= +3V

—

3

6

10

µs

NOTES: 1. All timing measurements are defined at the point of signal crossing V_DD/ 2.

2. These parameters are periodically sampled and are not 100% tested.

Doc. No. 2005, Rev. A

3

CAT523

A. C. TIMING DIAGRAM

t

1

2

3

4

5

o

t

H

CLK

t

L

t

CSH

CSS

CLK

CS

t

CSMIN

t

DIS

DI

t

DIH

t

DO0

t

LZ

DO

t

HZ

t

DO1

PROG

t

PS

t

PROG

RDY/BSY

t

BUSY

t

1

2

3

4

5

o

Doc. No. 2005, Rev. A

4

CAT523

PIN DESCRIPTION

DPP addressing is as follows:

Name

Function

DPP OUTPUT

A0

0

A1

0

1

2

3

4

5

6

7

V_DD

CLK

Power supply positive.

Clock input pin.Clock input pin.

Ready/Busy Output

Chip Select

V

OUT1

OUT2

1

0

RDY/BSY

CS

DI

Serial data input pin.

Serial data output pin.

DO

PROG

EEPROM Programming Enable

Input

8

GND

V_REFL

NC

Power supply ground.

Minimum DPP output voltage.

No Connect.

9

10

11

12

13

14

NC

No Connect.

V_OUT2

V_OUT1

V_REFH

DPP output channel 2.

DPP output channel 1.

Maximum DPP output voltage.

DEVICE OPERATION

readandwriteoperations. WhenCSishighdatamaybe

read to or from the chip, and the Data Output (DO) pin is

active. Data loaded into the DPP control registers will

remain in effect until CS goes low. Bringing CS to a logic

low returns all DPP outputs to the settings stored in non-

volatile memory and switches DO to its high impedance

Tri-State mode.

The CAT523 is a dual 8-bit configured digitally

programmable potentiometer (DPP) whose outputs can

be programmed to any one of 256 individual voltage

steps. Once programmed, these output settings are

retained in non-volatile memory and will not be lost

when power is removed from the chip. Upon power up

the DPPs return to the settings stored in non-volatile

memory. Each DPP can be written to and read from

independentlywithouteffectingtheoutputvoltageduring

the read or write cycle. Each output can also be

temporarily adjusted without changing the stored output

setting, which is useful for testing new output settings

before storing them in memory.

Because CS functions like a reset the CS pin has been

equipped with a 30 ns to 90 ns filter circuit to prevent

noise spikes from causing unwanted resets and the loss

of volatile data.

CLOCK

The CAT523’s clock controls both data flow in and out of

theICandnon-volatilememorycellprogramming. Serial

data is shifted into the DI pin and out of the DO pin on the

clock’srisingedge. Whileitisnotnecessaryfortheclock

to be running between data transfers, the clock must be

operating in order to write to non-volatile memory, even

though the data being saved may already be resident in

the DPP wiper control register.

DIGITAL INTERFACE

The CAT523 employs a 3 wire, Microwire-like, serial

control interface consisting of Clock (CLK), Chip Select

(CS) and Data In (DI) inputs. For all operations, address

and data are shifted in LSB first. In addition, all digital

data must be preceded by a logic “1” as a start bit. The

DPP address and data are clocked into the DI pin on the

clock’s rising edge. When sending multiple blocks of

information a minimum of two clock cycles is required

between the last block sent and the next start bit.

No clock is necessary upon system power-up. The

CAT523’s internal power-on reset circuitry loads data

from non-volatile memory to the DPPs without using the

external clock.

Multiple devices may share a common input data line by

selectively activating the CS control of the desired IC.

Data Outputs (DO) can also share a common line

because the DO pin is Tri-Stated and returns to a high

impedance when not in use.

As data transfers are edge triggered clean clock

transitions are necessary to avoid falsely clocking data

intothecontrolregisters. StandardCMOSandTTLlogic

families work well in this regard and it is recommended

thatanymechanicalswitchesusedforbreadboardingor

device evaluation purposes be debounced by a flip-flop

or other suitable debouncing circuit.

CHIP SELECT

Chip Select (CS) enables and disables the CAT523’s

Doc. No. 2005, Rev. A

5

CAT523

V

followedbyatwobitDPPaddressandeightdatabitsare

clockedintotheDPPcontrolregisterviatheDIpin. Data

enters on the clock’s rising edge. The DPP output

changes to its new setting on the clock cycle following

D7, the last data bit.

REF

V_REF,thevoltageappliedbetweenpinsV_REFHandV_REFL

,

sets the DPP’s Zero to Full Scale output range where

V_REFL= Zero and V_REFH= Full Scale. V_REFcan span the

full power supply range or just a fraction of it. In typical

applications V_REFHandV_REFLare connected across the

power supply rails. When using less than the full supply

voltage V_REFHis restricted to voltages between V_DDand

V_DD/2 and V_REFLto voltages between GND and V_DD/2.

Programming is achieved by bringing PROG high for a

minimum of 3 ms. PROG must be brought high some-

time after the start bit and at least 150 ns prior to the

rising edge of the clock cycle immediately following the

D7 bit. Two clock cycles after the D7 bit the DAC control

register will be ready to receive the next set of address

and data bits. The clock must be kept running through-

out the programming cycle. Internal control circuitry

takes care of ramping the programming voltage for data

transfertothenon-volatilememorycells. TheCAT523’s

non-volatilememorycellswillendureover100,000write

cycles and will retain data for a minimum of 100 years

without being refreshed.

READY/BUSY

When saving data to non-volatile memory, the Ready/

Busy output (RDY/BSY) signals the start and duration of

the non-volatile erase/write cycle. Upon receiving a

command to store data (PROG goes high) RDY/BSY

goes low and remains low until the programming cycle

is complete. During this time the CAT523 will ignore any

data appearing at DI and no data will be output on DO.

RDY/BSYisinternallyANDedwithalowvoltagedetector

circuitmonitoringV_DD.IfV_DDisbelowtheminimumvalue

required for non-volatile programming, RDY/BSY will

remain high following the program command indicating

afailuretorecordthedesireddatainnon-volatilememory.

READING DATA

Each time data is transferred into a DPP wiper control

register currently held data is shifted out via the D0 pin,

thusineverydatatransactionareadcycleoccurs. Note,

however, that the reading process is destructive. Data

must be removed from the register in order to be read.

Figure 2 depicts a Read Only cycle in which no change

occurs in the DPP’s output. This feature allows µPs to

poll DPPs for their current setting without disturbing the

output voltage but it assumes that the setting being read

is also stored in non-volatile memory so that it can be

restored at the end of the read cycle. In Figure 2 CS

returns low before the 13^thclock cycle completes. In

doingsothenon-volatilememorysettingisreloadedinto

the DPP wiper control register.

DATA OUTPUT

Data is output serially by the CAT523, LSB first, via the

Data Out (DO) pin following the reception of a start bit

and two address bits by the Data Input (DI). DO

becomes active whenever CS goes high and resumes

itshighimpedanceTri-StatemodewhenCSreturnslow.

Tri-Stating the DO pin allows several 523s to share a

single serial data line and simplifies interfacing multiple

523s to a microprocessor.

WRITING TO MEMORY

Programming the CAT523’s non-volatile memory is

accomplished through the control signals: Chip Select

(CS) and Program (PROG). With CS high, a start bit

Figure 1. Writing to Memory

Figure 2. Reading from Memory

t

1

2

3

4

5

6

7

8

9

10 11 12

o

CS

DI

NEW DPP DATA

1

A0 A1

CURRENT DPP DATA

DO

D0 D1 D2 D3 D4 D5 D6 D7

PROG

RDY/BSY

DPP

CURRENT

DPP VALUE

DPP

OUTPUT

DPP VALUE

NON-VOLATILE

Doc. No. 2005, Rev. A

6

CAT523

Sincethisvalueisthesameasthatwhichhadbeenthere

previously no change in the DPP’s output is noticed.

Had the value held in the control register been different

from that stored in non-volatile memory then a change

would occur at the read cycle’s conclusion.

this feature, the new value must be reloaded into the

DPP wiper control register prior to programming. This is

becausetheCAT523’sinternalcontrolcircuitrydiscards

the new data from the programming register two clock

cycles after receiving it (after reception is complete) if no

PROG signal is received.

TEMPORARILY CHANGE OUTPUT

Figure 3. Temporary Change in Output

TheCAT523 allowstemporarychangesinDPP’soutput

to be made without disturbing the settings retained in

non-volatile memory. This feature is particularly useful

when testing for a new output setting and allows for user

adjustment of preset or default values without losing the

original factory settings.

t

1

2

3

4

5

6

7

8

9

10 11 12

N

N+1 N+2

o

CS

DI

NEW DPP DATA

1

A0 A1 D0 D1 D2 D3 D4 D5 D6 D7

Figure 3 shows the control and data signals needed to

effect a temporary output change. DPP wiper settings

may be changed as many times as required and can be

made to any of the two DPPs in any order or sequence.

The temporary setting(s) remain in effect long as CS

remains high. When CS returns low all two DPPs will

returntotheoutputvaluesstoredinnon-volatilememory.

CURRENT DPP DATA

D0 D1 D2 D3 D4 D5 D6 D7

DO

PROG

DPP

OUTPUT

CURRENT

DPP VALUE

NEW

CURRENT

DPP VALUE

NON-VOLATILE

VOLATILE

NON-VOLATILE

When it is desired to save a new setting acquired using

APPLICATION CIRCUITS

DPP INPUT

DPP OUTPUT

ANALOG

OUTPUT

CODE

255

V

= ——— (V - V

) + V

+5V

DPP

FS

ZERO

V

R

i

F

= 0.99 V

REF

FS

V

= 5V

F

REF

R = R

V

= 0.01 V

MSB LSB

1111 1111

+15V

I

ZERO

REF

V

REFH

DD

V

–

255

OUT

—— (.98 V

) + .01 V

= .990 V

V

= +4.90V

REF

OUT

CONTROL

& DATA

+

CAT523

OP 07

128

1000 0000

0111 1111

0000 0001

—— (.98 V

255

) + .01 V

= .502 V

= .498 V

= .014 V

V

= +0.02V

= -0.02V

= -4.86V

-15V

REF

OUT

GND

V

REFL

127

255

—— (.98 V

V

R

F

V

=

(

R ) -V

R +

F i

i

OUT

DPP

R

1

255

i

—— (.98 V

For R =R

i

F

V

= 2V -V

OUT

DPP i

0

0000 0000 —— (.98 V

) + .01 V

= .010 V

V

= -4.90V

REF

OUT

255

Bipolar DPP Output

+5V

R

i

R

F

+15V

V

REFH

DD

–

V

OUT

CONTROL

& DATA

+

CAT523

OP 07

-15V

GND

V

REFL

R

F

V

= (1 + –––) V

OUT

DPP

R

I

Amplified DPP Output

Doc. No. 2005, Rev. A

7

CAT523

APPLICATION CIRCUITS (Cont.)

+5V

V

+V

REF

V

REF

V

R

= —————

C

DD

REFH

256 1 µA

*

+5V

V

REF

Fine adjust gives ± 1 LSB change in V

OFFSET

127R

C

FINE ADJUST

DPP

V

REF

V

when V

= ———

DD

REFH

OFFSET

2

+

)

OFFSET

(+V

) - (V

REF

R

= ———————————

1 µA

C

127R

C

FINE ADJUST

DPP

+

(-V

) + (V

)

REF

OFFSET

R

= ———————————

1 µA

o

R

C

COARSE ADJUST

DPP

+V

GND

V

REFL

R

C

V

OFFSET

+V

-V

COARSE ADJUST

DPP

+

R

o

V

OFFSET

+

-V

REF

–

GND

V

REFL

Coarse-Fine Offset Control by Averaging DPP Outputs

for Single Power Supply Systems

Coarse-Fine Offset Control by Averaging DPP Outputs

for Dual Power Supply Systems

28 - 32V

V+

15K

I > 2 mA

10 µF

1N5231B

5.1V

V

= 5.000V

REF

V

DD

REFH

V

REFH

DD

10K

CONTROL

& DATA

CONTROL

& DATA

LT 1029

+

MPT3055EL

CAT523

–

LM 324

4.02 K

GND

V

REFL

GND

V

REFL

OUTPUT

10 µF

35V

0 - 25V

@ 1A

1.00K

Digitally Trimmed Voltage Reference

Digitally Controlled Voltage Reference

Doc. No. 2005, Rev. A

8

CAT523

APPLICATION CIRCUITS (Cont.)

+5V

2.2K

V

REFH

4.7 µA

DD

LM385-2.5

+15V

I

= 2 - 255 mA

1 mA steps

SINK

+

DPP

2N7000

+5V

–

10K

39Ω1W

39Ω 1W

CONTROL

& DATA

CAT523

DPP

+

5 µA steps

2N7000

3.9K

–

GND

V

REFL

5 meg

10K

5 meg

10K

–

TIP 30

+

-15V

Current Sink with 4 Decades of Resolution

+15V

51K

+

TIP 29

–

10K

+5V

V

DD

REFH

5 meg

39 Ω1W

39Ω1W

DPP

–

CONTROL

& DATA

CAT523

BS170P

3.9K

1 mA steps

+

5 meg

DPP

–

GND

V

REFL

BS170P

5 µA steps

+

LM385-2.5

-15V

I

= 2 - 255 mA

SOURCE

Current Source with 4 Decades of Resolution

Doc. No. 2005, Rev. A

9

CAT523

ORDERING INFORMATION

Prefix

Device #

Suffix

-TE13

CAT

523

J

I

Optional

Company ID

Product

Number

Package

P: PDIP

J: SOIC

Tape & Reel

TE13: 2000/Reel

Temperature Range

Blank = Commercial (0˚C to +70˚C)

I = Industrial (-40˚C to +85˚C)

Notes:

(1) The device used in the above example is a CAT523JI-TE13 (SOIC, Industrial Temperature, Tape & Reel)

Copyrights, Trademarks and Patents

Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:

DPP ™

AE²™

Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents

issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.

CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS

PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE

RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING

OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.

Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or

other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a

situation where personal injury or death may occur.

Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets

labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.

Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate

typical semiconductor applications and may not be complete.

Catalyst Semiconductor, Inc.

Corporate Headquarters

1250 Borregas Avenue

Sunnyvale, CA 94089

Phone: 408.542.1000

Fax: 408.542.1200

www.catsemi.com

Publication #: 2005

Revison:

Issue date:

Type:

A

08/02/01

Final

Doc. No. 2005, Rev. A

10


型号：	CAT523J-TE13
厂家：	ETC
描述：	DIGITAL POTENTIOMETER\|SOP\|14PIN\|PLASTIC 数字电位器\|专科\| 14PIN \|塑料\n 电位器
文件：	总10页 (文件大小：103K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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