CAT523LI [ONSEMI]
Dual Digitally Programmable Potentiometer (DPP?) with 256 Taps and Microwire Interface; 双数字可编程电位计( DPP ? )与256丝锥和Microwire接口型号: | CAT523LI |
厂家: | ONSEMI |
描述: | Dual Digitally Programmable Potentiometer (DPP?) with 256 Taps and Microwire Interface |
文件: | 总15页 (文件大小:180K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Not Recommended for New Design
CAT523
Dual Digitally Programmable Potentiometer (DPP™) with
256 Taps and Microwire Interface
FEATURES
DESCRIPTION
The CAT523 is a dual, 8-bit digitally-programmable
potentiometer (DPP™) configured for programmable
voltage and DAC-like applications. Intended for final
calibration of products such as camcorders, fax
machines and cellular telephones on automated high
volume production lines, it is also well suited for
systems capable of self calibration, and applications
where equipment which is either difficult to access or in a
hazardous environment, requires periodic adjustment.
Two 8-bit DPPs configured as programmable
voltage sources in DAC-like applications
Common reference inputs
Non-volatile NVRAM memory wiper storage
Output voltage range includes both supply rails
2 independently addressable buffered
output wipers
1 LSB accuracy, high resolution
Serial microwire-like interface
The two independently programmable DPPs have a
common output voltage range which includes both
supply rails. The wipers are buffered by rail to rail op
amps. Wiper settings, stored in non-volatile NVRAM
memory, are not lost when the device is powered
down and are automatically reinstated when power is
returned. Each wiper can be dithered to test new
output values without effecting the stored settings and
stored settings can be read back without disturbing
the DPP’s output.
Single supply operation: 2.7V - 5.5V
Setting read-back without effecting outputs
For Ordering Information details, see page 14.
APPLICATIONS
Automated product calibration.
Control of the CAT523 is accomplished with a simple
3-wire, Microwire-like serial interface. A Chip Select
pin allows several CAT523's to share a common serial
interface and communication back to the host
controller is via a single serial data line thanks to the
CAT523’s Tri-Stated Data Output pin. A RDY/¯B¯S¯Y¯
output working in concert with an internal low voltage
detector signals proper operation of non-volatile
NVRAM memory Erase/Write cycle.
Remote control adjustment of equipment
Offset, gain and zero adjustments in self-
calibrating and adaptive control systems.
Tamper-proof calibrations.
DAC (with memory) substitute
PIN CONFIGURATION
PDIP 14-Lead (L)
SOIC 14-Lead (W)
The CAT523 is available in the 0°C to 70°C
Commercial and -40°C to + 85°C Industrial operating
temperature ranges and offered in 14-pin plastic DIP
and SOIC mount packages.
VDD
1
2
3
4
5
6
7
14 VREFH
13 VOUT1
12 VOUT2
11 NC
CLK
¯¯¯¯
RDY/BSY
CAT523
CS
DI
10 NC
DO
9
8
VREFL
GND
PROG
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
1
Doc. No. MD-2005 Rev. I
CAT523
Not Recommended for New Design
FUNCTIONAL DIAGRAM
V
V
DD
1
REFH
14
3
RDY/BSY
PROGRAM
CONTROL
7
PROG
+
–
13
12
V
V
OUT1
OUT2
5
2
4
DI
+
–
SERIAL
CONTROL
CLK
CS
SERIAL
DATA
OUTPUT
REGISTER
6
DO
CAT523
8
9
GND
V
REFL
Doc. No. MD-2005 Rev. I
2
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
Not Recommended for New Design
CAT523
ABSOLUTE MAXIMUM RATINGS
Parameters
Supply Voltage(1)
VDD to GND
Inputs
Ratings
Parameters
Outputs
Ratings
Units
Units
V
-0.5 to VDD +0.5
-0.5 to VDD +0.5
V
V
-0.5 to +7
D0 to GND
VOUT 1– 4 to GND
CLK to GND
CS to GND
DI to GND
-0.5 to VDD +0.5
-0.5 to VDD +0.5
-0.5 to VDD +0.5
-0.5 to VDD +0.5
-0.5 to VDD +0.5
-0.5 to VDD +0.5
-0.5 to VDD +0.5
V
V
V
V
V
V
V
Operating Ambient Temperature
Commercial
0 to +70
°C
(‘C’ or Blank suffix)
Industrial (‘I’ suffix)
Junction Temperature
Storage Temperature
Lead Soldering (10 sec max)
-40 to +85
+150
°C
°C
°C
°C
¯¯¯¯
RDY/BSY to GND
PROG to GND
VREFH to GND
VREFL to GND
-65 to +150
+300
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Test Method
Min Max Units
(2)
VZAP
ESD Susceptibility
Latch-Up
MIL-STD-883, Test Method 3015
JEDEC Standard 17
2000
100
V
(2)(3)
ILTH
mA
POWER SUPPLY
Symbol
IDD1
Parameter
Conditions
Min
—
Typ
Max Units
Supply Current (Read)
Supply Current (Write)
Normal Operating
Programming, VDD = 5V
VDD = 3V
400
600
µA
µA
µA
V
IDD2
—
1600 2500
1000 1600
—
VDD
Operating Voltage Range
2.7
—
5.5
LOGIC INPUTS
Symbol
Parameter
Conditions
VIN = VDD
VIN = 0V
Min
—
—
2
Typ
—
Max Units
IIH
IIL
Input Leakage Current
Input Leakage Current
High Level Input Voltage
Low Level Input Voltage
10
-10
VDD
0.8
µA
µA
V
—
VIH
VIL
—
0
—
V
LOGIC OUTPUTS
Symbol
VOH
Parameter
High Level Output Voltage
Low Level Output Voltage
Conditions
Min
Typ
—
Max Units
IOH = -40µA
VDD -0.3
—
V
V
V
VIL
IOL = 1mA, VDD = +5V
IOL = 0.4mA, VDD = +3V
—
—
—
0.4
0.4
—
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC + 1V.
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
3
Doc. No. MD-2005 Rev. I
CAT523
Not Recommended for New Design
POTENTIOMETER CHARACTERISTICS
VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified
Symbol Parameter
Conditions
Min
Typ
24
Max
Units
kΩ
Potentiometer Resistance
See note 3
RPOT
RPOT to RPOT Match
Pot Resistance Tolerance
Voltage on VREFH pin
Voltage on VREFL pin
Resolution
—
±0.5
±1
±20
%
%
2.7
0
VDD
V
VDD - 2.7
V
0.4
0.5
%
INL
DNL
Integral Linearity Error
Differential Linearity Error
Buffer Output Resistance
Buffer Output Current
TC of Pot Resistance
Potentiometer Capacitances
1
0.5
10
3
LSB
LSB
Ω
0.25
ROUT
IOUT
mA
ppm/ºC
pF
TCRPOT
CH/CL
300
8/8
AC ELECTRICAL CHARACTERISTICS
VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified
Symbol Parameter
Digital
Conditions
Min
Typ
Max
Units
tCSMIN
tCSS
tCSH
tDIS
Minimum CS Low Time
150
100
0
—
—
—
—
—
—
—
400
400
4
—
—
—
—
—
150
150
—
—
5
ns
ns
CS Setup Time
CS Hold Time
ns
DI Setup Time
50
ns
CL = 100pF (1)
tDIH
DI Hold Time
50
ns
tDO1
tDO0
tHZ
Output Delay to 1
Output Delay to 0
Output Delay to High-Z
Output Delay to Low-Z
Erase/Write Cycle Time
PROG Setup Time
Minimum Pulse Width
Minimum CLK High Time
Minimum CLK Low Time
Clock Frequency
—
ns
—
ns
—
ns
tLZ
—
ns
tBUSY
tPS
—
ms
ns
150
700
500
300
DC
—
—
—
—
—
—
—
—
—
1
tPROG
ns
tCLK
tCLK
fC
H
ns
L
ns
MHz
Analog
tDS
DPP Settling Time to 1 LSB
CLOAD = 10pF, VDD = +5V
CLOAD = 10pF, VDD = +3V
—
—
3
6
10
10
µs
µs
Notes:
(1) All timing measurements are defined at the point of signal crossing VDD / 2.
(2) These parameters are periodically sampled and are not 100% tested.
(3) The 24kΩ +20% resistors are configured as 4 resistors in parallel which would provide a measured value between VREFH and VREFL of 6kΩ
+20%. The individual 24kΩ resistors are not measurable but guaranteed by design and verification of the 6kΩ +20% value.
Doc. No. MD-2005 Rev. I
4
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
Not Recommended for New Design
A.C. TIMING DIAGRAM
CAT523
t
1
2
3
4
5
o
t
H
CLK
CLK
CS
DI
t
t
L
t
CSH
CSS
CLK
t
CSMIN
t
DIS
t
DIH
t
DO0
t
LZ
DO
t
HZ
t
DO1
PROG
t
PS
t
PROG
RDY/BSY
t
BUSY
4
t
1
2
3
5
o
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
5
Doc. No. MD-2005 Rev. I
CAT523
Not Recommended for New Design
PIN DESCRIPTION
DPP addressing is as follows:
DPP OUTPUT
Pin
1
Name
VDD
Function
Power supply positive
Clock input pin
A0 A1
2
CLK
VOUT1
VOUT2
0
1
0
0
¯¯¯¯
RDY/BSY
3
Ready/Busy output
Chip select
4
CS
DI
5
Serial data input pin
Serial data output pin
6
DO
EEPROM Programming Enable
Input
7
PROG
8
GND
VREFL
NC
Power supply ground
Minimum DAC output voltage
No Connect
9
10
11
12
13
14
NC
No Connect
VOUT2
VOUT1
VREFH
DPP output channel 2
DPP output channel 1
Maximum DPP output voltage
Multiple devices may share a common input data line
by selectively activating the CS control of the desired
IC. Data Outputs (DO) can also share a common line
because the DO pin is Tri-Stated and returns to a high
impedance when not in use.
DEVICE OPERATION
The CAT523 is a dual 8-bit configured digitally
programmable potentiometer (DPP) whose outputs
can be programmed to any one of 256 individual
voltage steps.
Once programmed, these output
CHIP SELECT
settings are retained in non-volatile memory and will
not be lost when power is removed from the chip.
Upon power up the DPPs return to the settings stored
in non-volatile memory. Each DPP can be written to
and read from independently without effecting the
output voltage during the read or write cycle. Each
output can also be temporarily adjusted without
changing the stored output setting, which is useful for
testing new output settings before storing them in
memory.
Chip Select (CS) enables and disables the CAT523’s
read and write operations. When CS is high data may
be read to or from the chip, and the Data Output (DO)
pin is active. Data loaded into the DPP control
registers will remain in effect until CS goes low.
Bringing CS to a logic low returns all DPP outputs to
the settings stored in non-volatile memory and
switches DO to its high impedance Tri-State mode.
Because CS functions like a reset the CS pin has
been equipped with a 30 ns to 90 ns filter circuit to
prevent noise spikes from causing unwanted resets
and the loss of volatile data.
DIGITAL INTERFACE
The CAT523 employs a 3 wire, Microwire-like, serial
control interface consisting of Clock (CLK), Chip
Select (CS) and Data In (DI) inputs. For all ope–
rations, address and data are shifted in LSB first. In
addition, all digital data must be preceded by a logic
“1” as a start bit. The DPP address and data are
clocked into the DI pin on the clock’s rising edge.
When sending multiple blocks of information a
minimum of two clock cycles is required between the
last block sent and the next start bit.
CLOCK
The CAT523’s clock controls both data flow in and out
of the IC and non-volatile memory cell programming.
Serial data is shifted into the DI pin and out of the DO
pin on the clock’s rising edge. While it is not
necessary for the clock to be running between data
transfers, the clock must be operating in order to write
to non-volatile memory, even though the data being
saved may already be resident in the DPP wiper
control register.
Doc. No. MD-2005 Rev. I
6
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
Not Recommended for New Design
CAT523
¯¯¯¯
No clock is necessary upon system power-up. The
CAT523’s internal power-on reset circuitry loads data
from non-volatile memory to the DPPs without using
the external clock.
RDY/BSY will remain high following the program
command indicating a failure to record the desired
data in non-volatile memory.
DATA OUTPUT
As data transfers are edge triggered clean clock
transitions are necessary to avoid falsely clocking
data into the control registers. Standard CMOS and
TTL logic families work well in this regard and it is
recommended that any mechanical switches used for
breadboarding or device evaluation purposes be
debounced by a flip-flop or other suitable debouncing
circuit.
Data is output serially by the CAT523, LSB first, via
the Data Out (DO) pin following the reception of a
start bit and two address bits by the Data Input (DI).
DO becomes active whenever CS goes high and
resumes its high impedance Tri-State mode when CS
returns low. Tri-Stating the DO pin allows several
523s to share a single serial data line and simplifies
interfacing multiple 523s to a microprocessor.
VREF
WRITING TO MEMORY
VREF, the voltage applied between pins VREFH & VREFL,
Programming the CAT523’s non-volatile memory is
accomplished through the control signals: Chip Select
(CS) and Program (PROG). With CS high, a start
bitfollowed by a two bit DPP address and eight data
bits are clocked into the DPP control register via the
DI pin. Data enters on the clock’s rising edge. The
DPP output changes to its new setting on the clock
cycle following D7, the last data bit.
sets the DPP’s Zero to Full Scale output range where
VREFL = Zero and VREFH = Full Scale. VREF can span
the full power supply range or just a fraction of it. In
typical applications VREFH & VREFL are connected
across the power supply rails. When using less than
the full supply voltage VREFH is restricted to voltages
between VDD and VDD/2 and VREFL to voltages between
GND and VDD/2.
Programming is achieved by bringing PROG high
sometime after the start bit and at least 150 ns prior to
the rising edge of the clock cycle immediately
following the D7 bit. Two clock cycles after the D7 bit
the DAC control register will be ready to receive the
next set of address and data bits. The clock must be
kept running throughout the programming cycle.
Internal control circuitry takes care of ramping the
programming voltage for data transfer to the non-
volatile memory cells. The CAT523’s non-volatile
memory cells will endure over 100,000 write cycles
and will retain data for a minimum of 100 years
without being refreshed.
¯¯¯¯¯
READY/BUSY
When saving data to non-volatile memory, the
Ready/Busy output (RDY/BSY) signals the start and
duration of the non-volatile erase/write cycle. Upon
receiving a command to store data (PROG goes high)
¯¯¯¯
¯¯¯¯
RDY/BSY goes low and remains low until the
programming cycle is complete. During this time the
CAT523 will ignore any data appearing at DI and no
data will be output on DO.
¯¯¯¯
RDY/BSY is internally ANDed with a low voltage
detector circuit monitoring VDD. If VDD is below the
minimum value required for non-volatile programming,
Figure 1. Writing to Memory
t
1
2
3
4
5
6
7
8
9
10
11 12
N
N+1 N+2
o
CS
DI
NEW DPP DATA
1
A0 A1 D0 D1 D2 D3 D4 D5 D6 D7
CURRENT DPP DATA
DO
PROG
D0 D1 D2 D3 D4 D5 D6 D7
RDY/BSY
DPP
OUTPUT
CURRENT
DPP VALUE
NEW
DPP VALUE
NEW
DPP VALUE
NON-VOLATILE
VOLATILE
NON-VOLATILE
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
7
Doc. No. MD-2005 Rev. I
CAT523
Not Recommended for New Design
READING DATA
TEMPORARILY CHANGE OUTPUT
Each time data is transferred into a DPP wiper control
register currently held data is shifted out via the D0
pin, thus in every data transaction a read cycle
occurs. Note, however, that the reading process is
destructive. Data must be removed from the register
in order to be read. Figure 2 depicts a Read Only
cycle in which no change occurs in the DPP’s output.
This feature allows µPs to poll DPPs for their current
setting without disturbing the output voltage but it
assumes that the setting being read is also stored in
non-volatile memory so that it can be restored at the
end of the read cycle. In Figure 2 CS returns low
before the 13th clock cycle completes. In doing so the
non-volatile memory setting is reloaded into the DPP
wiper control register.
The CAT523 allows temporary changes in DPP’s
output to be made without disturbing the settings
retained in non-volatile memory. This feature is
particularly useful when testing for a new output
setting and allows for user adjustment of preset or
default values without losing the original factory
settings.
Figure 3 shows the control and data signals needed
to effect a temporary output change. DPP wiper
settings may be changed as many times as required
and can be made to any of the two DPPs in any order
or sequence. The temporary setting(s) remain in
effect long as CS remains high. When CS returns low
all two DPPs will return to the output values stored in
non-volatile memory.
Since this value is the same as that which had been
there previously no change in the DPP’s output is
noticed. Had the value held in the control register
been different from that stored in non-volatile memory
then a change would occur at the read cycle’s
conclusion.
When it is desired to save a new setting acquired
using this feature, the new value must be reloaded
into the DPP wiper control register prior to
programming. This is because the CAT523’s internal
control circuitry discards the new data from the
programming register two clock cycles after receiving
it (after reception is complete) if no PROG signal is
received.
Figure 2. Reading from Memory
Figure 3. Temporary Change in Output
t
1
2
3
4
5
6
7
8
9
10
11 12
t
1
2
3
4
5
6
7
8
9
10
11 12
N
N+1 N+2
o
o
CS
DI
CS
NEW DPP DATA
1
A0 A1
1
A0 A1 D0 D1 D2 D3 D4 D5 D6 D7
DI
CURRENT DPP DATA
CURRENT DPP DATA
DO
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
DO
PROG
PROG
RDY/BSY
RDY/BSY
CURRENT
DPP VALUE
DPP
OUTPUT
DPP
OUTPUT
CURRENT
DPP VALUE
NEW
DPP VALUE
CURRENT
DPP VALUE
NON-VOLATILE
NON-VOLATILE
VOLATILE
NON-VOLATILE
Doc. No. MD-2005 Rev. I
8
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
Not Recommended for New Design
CAT523
APPLICATION CIRCUITS
+5V
DPP INPUT DPP OUTPUT
ANALOG OUTPUT
V
R
I
R
F
I
CODE
255
VFS = 0.99VREF
VDPP
=
x (V - V
) + V
ZERO ZERO
FS
+15V
VREF =5V
RI =RF
MSB LSB
–
V
V
DD
REFH
V
=0.01V
REF
V
OUT
ZERO
255
V
DPP
+
VOUT = +4.90V
VOUT =+0.02V
CONTROL
& DATA
×0.98V
REF
+0.01V
=0.990V
REF
1111 1111
1000 0000
0111 1111
0000 0001
0000 0000
REF
CAT523
255
128
OP 07
×0.98V
REF
+0.01V
REF
= 0.502V
REF
255
127
255
1
-15V
V
GND
REFL
×0.98V
REF
+0.01V
REF
= 0.498V
REF
VOUT = -0.02V
V
R
F
(
R ) - V
F I
R +
DPP
I
V
=
OUT
×0.98V
REF
+0.01V
REF
= 0.014V
REF
VOUT = -4.86V
VOUT = -4.90V
R
I
255
0
For R = R
I
F
×0.98V
REF
+0.01V
REF
= 0.010V
REF
255
V
= 2V
- V
OUT
DPP I
Bipolar DPP Output
V+
I > 2mA
+5V
R
R
I
F
+15V
V
REF
= 5.00V
–
V
V
V
V
DD
REFH
REFL
DD
REFH
V
OUT
+
CONTROL
& DATA
CONTROL
& DATA
CAT523
LT 1029
CAT523
OP 07
-15V
V
GND
V
GND
REFL
R
F
R
I
V
= (1 +
) V
DPP
OUT
Digitally Trimmed Voltage Reference
Amplified DPP Output
28 ÷ 32V
15kΩ
10µF
10kΩ
1N5231B
5.1V
V
DD
V
REFH
CONTROL
& DATA
CAT523
+
–
MPT3055EL
V
GND
REFL
LM 324
OUTPUT
4.02kΩ
0 - 25V
@ 1A
10µF
35V
1.00kΩ
Digitally Controlled Voltage Reference
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
9
Doc. No. MD-2005 Rev. I
CAT523
Not Recommended for New Design
+5V
+V
REF
+5V
V
REF
V
V
REFH
DD
V
DD
V
REFH
127R
C
127R
C
FINE ADJUST
DPP
FINE ADJUST
DPP
+
(+V
) - (V
)
OFFSET
REF
R
R
=
C
0
1µA
CAT523
CAT523
+
+V
(-V
) + (V )
OFFSET
REF
R
R
C
0
R
C
=
COARSE ADJUST
DPP
1µA
COARSE ADJUST
DPP
+
–
V
OFFSET
GND
V
REFL
GND
V
REFL
+V
V
OFFSET
+
–
-V
REF
V
REF
256 x 1µA
R
=
C
-V
Fine adjust gives ±1 LSB change in V
OFFSET
when V
OFFSET
= V /2
REF
Coarse-Fine Offset Control by Averaging DPP
Outputs for Dual Power Supply Systems
Coarse-Fine Offset Control by Averaging DPP
Outputs for Single Power Supply Systems
+5V
2.2kΩ
4.7µF
V
V
REFH
LM385-2.5
DD
I
= 2 - 255mA
SINK
+15V
DPP1
+
1mA steps
2N7000
–
+5V
10kΩ
10kΩ
39Ω 1W
CONTROL
& DATA
CAT523
39Ω 1W
DPP2
+
–
5µA steps
2N7000
GND
V
REFL
5MΩ
5MΩ
3.9kΩ
10kΩ
10kΩ
–
+
TIP30
-15V
Current Sink with 4 Decades of Resolution
Doc. No. MD-2005 Rev. I
10
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
Not Recommended for New Design
CAT523
+15V
51kΩ
+
TIP29
–
10kΩ
10kΩ
+5V
V
V
REFH
DD
5MΩ
5MΩ
39Ω 1W
39Ω 1W
DPP1
–
+
CONTROL
& DATA
BS170P
CAT523
1mA steps
5MΩ
5MΩ
3.9kΩ
DPP2
–
+
GND
V
REFL
BS170P
5µA steps
LM385-2.5
-15V
I
= 2 ÷ 255mA
SOURCE
Current Source with 4 Decades of Resolution
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
11
Doc. No. MD-2005 Rev. I
CAT523
Not Recommended for New Design
PACKAGE OUTLINE DRAWINGS
PDIP 14-Lead (L)(1)(2)
SYMBOL
MIN
3.56
0.38
2.92
0.36
1.15
0.21
18.67
7.62
6.10
NOM
MAX
A
A1
A2
b
5.33
3.30
0.45
4.95
0.55
1.77
0.35
19.68
8.25
7.11
E1
b1
c
1.52
0.26
D
19.05
7.87
E
E1
e
6.35
D
2.54 BSC
eB
L
7.88
2.99
10.92
3.81
TOP VIEW
3.30
E
A2
A1
A
L
c
e
b
b1
eB
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC standard MS-001.
Doc. No. MD-2005 Rev. I
12
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
Not Recommended for New Design
CAT523
SOIC 14-Lead (W)(1)(2)
SYMBOL
MIN
NOM
MAX
1.75
0.25
0.51
0.25
8.75
6.20
4.00
A
A1
b
1.35
0.10
0.33
0.19
8.55
5.80
3.80
c
D
E
E1
e
8.65
6.00
E1
E
3.90
1.27 BSC
h
0.25
0.40
0º
0.50
1.27
8º
L
θ
PIN#1 IDENTIFICATION
TOP VIEW
h
D
θ
A
c
e
b
L
A1
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC standard MS-012.
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
13
Doc. No. MD-2005 Rev. I
CAT523
Not Recommended for New Design
EXAMPLE OF ORDERING INFORMATION
Prefix
Device # Suffix
CAT
523
W
I
T2
Optional
Company ID
Temperature Range
I = Industrial (-40ºC to 85ºC)
Tape & Reel
T: Tape & Reel
2: 2000/Reel
Product
Number
523
Package
L: PDIP
W: SOIC
Notes:
(1) All packages are RoHS compliant (Lead-free, Halogen-free).
(2) Standard lead finish is Matte-Tin.
(3) This device used in the above example is a CAT523WI-T2 (SOIC, Industrial Temperature, Tape & Reel).
ORDERING PART NUMBER
CAT523LI
CAT523WI
Doc. No. MD-2005 Rev. I
14
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
Not Recommended for New Design
REVISION HISTORY
CAT523
Date
Revision Description
16-Mar-04
D
Updated Potentiometer Characteristics
Updated Functional Diagram
12-Jul-04
E
Updated Potentiometer Characteristics
Added Note 3 under Potentiometer/AC Characteristics tables
Add Package Outline Drawings
26-Jul-07
08-Oct-07
F
Updated Example of Ordering Information
Added MD- to document number
Change title
Update Writing to Memory
G
15-Jul-08
H
I
Add “Not Recommended for New Design” to the top of all pages
Change logo and fine print to ON Semiconductor
24-Nov-08
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to
any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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Email: orderlit@onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
15
Doc. No. MD-2005 Rev. I
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