CH7005C-V_技术文档

CH7005C

CHRONTEL

Digital PC to TV Encoder with Macrovision^TM

Features

General Description

• Supports Macrovision^TM7.X anti-copy protection

• Function compatible with CH7004

Chrontel’s CH7005 digital PC to TV encoder is a stand-

alone integrated circuit which provides a PC 99 compliant

solution for TV output. Suggested application use with the

Intel I740.* It provides a universal digital input port to

accept a pixel data stream from a compatible VGA

controller (or equivalent) and converts this directly into

NTSC or PAL TV format.

• Universal digital interface accepts YCrCb (CCIR601

or 656) or RGB (15,16 or 24-bit) video data in both

non-interlaced and interlaced formats

• TrueScale ^TMrendering engine supports undescam

operations for various graphic resolutions† ¥

• Enhanced text sharpness and adaptive flicker removal

with up to 5-lines of filtering†

• Enhanced dot crawl control and area reduction

This circuit integrates a digital NTSC/PAL encoder with

9-bit DAC interface, and new adaptive flicker filter, and

high accuracy low-jitter phase locked loop to create

outstanding quality video. Through its TrueScale^TM

scaling and deflickering engine, the CH7005 supports full

vertical and horizontal underscan capability and operates

in 5 different resolutions including 640x480 and 800x600.

2

• Fully programmable through I C port

• Supports NTSC, NTSC-EIA (Japan), and PAL (B, D,

G, H, I, M and N) TV formats

A new universal digital interface along with full

programmability make the CH7005 ideal for system-level

PC solutions. All features are software programmable

through a standard I²C port, to enable a complete PC

solution using a TV as the primary display.

• Provides Composite, S-Video and SCART outputs

• Auto-detection of TV presence

• Supports VBI pass-through

• Programmable power management

• 9-bit video DAC outputs

• Complete Windows and DOS driver software

• Offered in 44-pin PLCC, 44-pin TQFP

† Patent number 5,781,241

¥ Patent number 5,914,753

LINE

YUV-RGB CONVERTER

MEMORY

RGB-YUV

CONVERTER

TRUE SCALE

DIGITAL

Y/R

SCALING &

DEFLICKERING

ENGINE

NTSC/PAL

ENCODER

& FILTERS

D[15:0]

TRIPLE

DAC

INPUT

C/G

INTERFACE

PIXEL DATA

CVBS/B

RSET

SYSTEM CLOCK

2

TIMING & SYNC

GENERATOR

I C REGISTER &

PLL

CONTROL BLOCK

SC

SD

RESET*

XCLK

DS/BCO

P-OUT

H

XI

V

XO/FIN CSYNC

Figure 1: Functional Block Diagram

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*Intel I740 is a Trademark of Intel Corp

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CHRONTEL

CH7005C

D[3]

D[4]

7

39

38

37

36

35

34

33

32

31

30

29

XO/FIN

XI

8

D[5]

9

AVDD

DVDD

RESET*

DGND

SC

D[6]

10

11

12

13

14

15

16

17

DVDD

D[7]

CHRONTEL

CH7005

D[8]

DGND]

D[9]

SD

VDD

D[10]

D[11]

RSET

GND

Figure 2: 44-Pin PLCC

2

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CHRONTEL

CH7005C

1

D[3]

33

32

31

30

29

28

27

26

25

24

23

XO/FIN

2

D[4]

D[5]

XI

3

AVDD

4

D[6]

DVDD

CHRONTEL

CH7005

5

DVDD

D[7]

RESET*

ADDR

6

DGND

7

D[8]

SC

8

DGND]

D[9]

SD

9

VDD

10

11

D[10]

D[11]

RSET

GND

Figure 3: 44-Pin TQFP

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CH7005C

Table 1. Pin Descriptions

44-Pin

PLCC

44-Pin

TQFP

Type

Symbol

Description

Digital Pixel Inputs

21-15

13-12,

10-4

15,14,

13,12,

11,10,

9,7,6,

4,3,

2,1,

44,43,

42

In

D15-D0

These pins accept digital pixel data streams with either 8, 12, or 16-bit

multiplexed or 16-bit non-multiplexed formats, determined by the input

mode setting (see Registers and Programming section). Inputs D0 - D7

are used when operating in 8-bit multiplexed mode. Inputs D0 - D11

are used when operating in 12-bit mode. Inputs D0 - D15 are used

when operating in 16-bit mode. The data structure and timing

sequence for each mode is described in the section on Digital Input

Port.

Pixel Clock Output

43

37

Out

P-OUT

The CH7005, operating in master mode, provides a pixel data clocking

signal to the VGA controller. This clock will only be provided in master

clock modes and will be tri-stated otherwise. This pin provides the pixel

clock output signal (adjustable as 1X,2X or 3x) to the VGA controller

(see the section on Digital Video Interface, Registers and Programming

for more details). The capacitive loading on this pin should be kept to a

minimum.

Pixel Clock Input

1

39

In

XCLK

To operate in a pure master mode, the P-OUT signal should be

connected to the XCLK input pin. To operate in a pseudo-master mode,

the P-OUT clock is used as a reference frequency, and a signal locked

to this output (at 1X, 1/2X, or 1/3X the P-OUT frequency) is input to the

XCLK pin. To operate in slave mode, the CH7005 accepts an external

pixel clock input at this pin. The capacitive loading on this pin should be

kept to a minimum.

Vertical Sync Input/Output

3

2

41

40

35

In/Out

V

H

This pin accepts the vertical sync signal from the VGA controller, or

outputs a vertical sync to the VGA controller. The capacitive loading on

this pin should kept to a minimum.

Horizontal Sync Input/Output

This pin accepts the horizontal sync from the VGA controller, or outputs

a horizontal sync to the VGA controller. The capacitive loading on this

pin should be kept to a minimum.

Data/Start (input) / Buffered Clock (output)

41

DS/BCO

When configured as an input, the rising edge of this signal identifies the

first active pixel of data for each active line.

When configured as an output this pin provides a buffered clock output.

The output clock can be selected using the BCO register (17h) (see

Registers and Programming).

Crystal Input

38

39

32

33

In

XI

A parallel resonance 14.31818 MHz (± 50 ppm) crystal should be

attached between XI and XO/FIN. However, if an external CMOS clock

is attached to XO/FIN, XI should be connected to ground.

Crystal Output or External Fref

XO/FIN

A 14.31818 MHz (± 50 ppm) crystal may be attached between XO/FIN

and XI. An external CMOS compatible clock can be connected to

XO/FIN as an alternative.

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CH7005C

Table 1. Pin Descriptions

44-Pin

PLCC

44-Pin

TQFP

Type

Symbol

Description

Reference Resistor

30

28

24

22

In

RSET

A 360 W resistor with short and wide traces should be attached

between RSET and ground. No other connections should be made to

this pin.

Luminance Output

Out

Y/R

C/G

A 75 W termination resistor with short traces should be attached

between Y and ground for optimum performance. In normal operating

modes other than SCART and RGB bypass, this pin outputs the

composite video signal. In SCART and RGB Bypass modes, this pin

outputs the red signal.

Chrominance Output

27

26

21

20

A 75 W termination resistor with short traces should be attached

between C and ground for optimum performance. In normal operating

modes other than SCART and RGB bypass, this pin outputs the

composite video signal. In SCART and RGB Bypass modes, this pin

outputs the green signal.

Composite Video Output

CVBS/B

A 75 W termination resistor with short traces should be attached

between CVBS and ground for optimum performance. In normal

operating modes other than SCART and RGB bypass, this pin outputs

the composite video signal. In SCART and RGB Bypass modes, this pin

outputs the blue signal.

Composite Sync Output

23

32

33

35

40

17

26

27

29

34

Out

In/Out

In

CSYNC

SD

A 75 W termination resistor with short traces should be attached

between CSYNC and ground for optimum performance. In SCART

mode, this pin outputs the composite sync signal.

Serial Data (External pull-up required)

2

This pin functions as the serial data pin of the I C interface port (see the

2

I C Port Operation section for details). This pin uses the DVDD supply

and is not 5V tolerant.

Serial Clock (Internal pull-up)

SC

2

This pin functions as the serial clock pin of the I C interface port (see

2

the I C Port Operation section for details). This pin uses the DVDD

supply and is not 5V tolerant.

Reset Input

In

Reset*

AGND

When this pin is low, the CH7005 is held in the power-on reset

condition. When this pin is high, the device operates normally and

reset is controlled through the I C register.

2

Analog ground

Power

This pin provides the ground reference for the analog section of the

CH7005, and MUST be connected to the system ground, to prevent

latchup. Refer to the Application Information section for information on

proper supply decoupling.

Analog Supply Voltage

37

31

25

Power

AVDD

VDD

This pins supplies the 5V power to the analog section of the CH7005.

DAC Power Supply

This pins supplies the 5V power to CH7005’s internal DAC’s.

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CH7005C

Table 1. Pin Descriptions

44-Pin

PLCC

44-Pin

TQFP

Type

Symbol

Description

DAC Ground

29, 25

19,23

Power

GND

These pins provide the ground reference for CH7005’s internal DACs.

For information on proper supply decoupling, please refer to the

Application Information section.

Digital Supply Voltage

44, 36,

22, 11

5,16,

30,38

Power

DVDD

DGND

These pins supply the 3.3V power to the digital section of CH7005.

Digital Ground

42, 34,

24, 14

8,18,

28,36

These pins provide the ground reference for the digital section of

CH7005, and MUST be connected to the system ground to prevent

latchup.

R (Red) Component Output

N/A

Out

R

G

B

This pin provides the analog Red component of the digital RGB input in

the RGB Pass-Through mode.

G (Green) Component Output

This pin provides the analog Green component of the digital RGB input

in the RGB Pass-Through mode.

B (Blue) Component Output

This pin provides the analog Blue component of the digital RGB input in

the RGB Pass-Through mode.

Digital Video Interface

The CH7005 digital video interface provides a flexible digital interface between a computer graphics controller and

the TV encoder IC, forming the ideal quality/cost configuration for performing the TV-output function. This digital

interface consists of up to 16 data signals and 4 control signals, all of which are subject to programmable control

through the CH7005 register set. This interface can be configured as 8, 12 or 16-bit inputs operating in either

multiplexed mode or 16-bit input operation in demultiplexed mode. It will also accept either YCrCb or RGB (15, 16

or 24-bit) data formats and will accept both non-interlaced and interlaced data formats. A summary of the input data

format modes is as follows:

Table 2. Input Data Formats

Bus

Transfer Mode

Color Space and Depth

Format Reference

Width

16-bit

15-bit

16-bit

8-bit

Non-multiplexed

2X-multiplexed

3X-multiplexed

2X-multiplexed

RGB 16-bit

RGB 15-bit

YCrCb (24-bit)

RGB 15-bit

RGB 16-bit

RGB 24-bit

YCrCb (24-bit)

RGB 24

5-6-5 each word

5-5-5 each word

CbY0,CrY1...(CCIR656 style)

5-5-5 over two bytes

8-bit

5-6-5 over two bytes

8-bit

8-8-8 over three bytes

8-bit

Cb,Y0,Cr,Y1,(CCIR656 style)

8-8-8 over two words - ‘C’ version

8-8-8 over two words - ‘I’ version

8-8,8X over two words

12-bit

16-bit

RGB 24

RGB 24 (32)

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CH7005C

The clock and timing signals used to latch and process the incoming pixel data is dependent upon the clock mode.

The CH7005 can operate in either master (the CH7004 generates a pixel frequency which is either returned as a

phase-aligned pixel clock or used directly to latch data), or slave mode (the graphics chip generates the pixel clock).

The pixel clock frequency will change depending upon the active image size (e.g., 640x480 or 800x600), the desired

output format (NTSC or PAL), and the amount of scaling desired. The pixel clock may be requested to be 1X, 2X,

or 3X the pixel data rate (subject to a 100MHz frequency limitation). In the case of a 1X pixel clock the CH7005

will automatically use both clock edges, if a multiplexed data format is selected.

Sync Signals: Horizontal and vertical sync signals will normally be supplied by the VGA controller, but may be

selected to be generated by the CH7005. In the case of CCIR656 style input (IDF = 1 or 9), embedded sync may

also be used. (In each case, the period of the horizontal sync should be equal to the duration of the pixel clock, time

the first value of the (Total Pixels/line x Total Lines/Frame) column of Table 16 on page 31 (Display Mode

Register 00H description). The leading edge of the horizontal sync is used to determine the start of each line. The

Vertical sync signal must be able to be set to the second value in the (Total Pixels/Line x Total Lines/Frame) column

of Table 16 on page 31.)

Master Clock Mode: The CH7005 generates a clock signal (output at the P-OUT pin) which will be used by the

VGA controller as a frequency reference. The VGA controller will then generate a clock signal which will be input

via the XCLK input. This incoming signal will be used to latch (and de-multiplex, if required) incoming data. The

XCLK input clock rate must match the input data rate, and the P-OUT clock can be requested to be 1X, 2X or 3X

the pixel data rate. As an alternative, the P-OUT clock signal can also be used as the input clock signal (connected

directly to the XCLK input) to latch the incoming data. If this mode is used, the incoming data must meet setup and

hold times with respect to the XCLK input (with the only internal adjustment being XCLK polarity).

Slave Clock Mode: The VGA controller will generate a clock which will be input to the XCLK pin (no clock

signal will be output on the P-OUT pin). This signal must match the input data rate, must occur at 1X, 2X or 3X the

pixel data rate, and will be used to latch (and de-multiplex if required) incoming data. Also, the graphics IC

transmits back to the TV encoder the horizontal and vertical timing signals, and pixel data, each of which must meet

the specified setup and hold times with respect to the pixel clock.

Pixel Data: Active pixel data will be expected after a programmable number pixels times the multiplex rate after

the leading edge of Horizontal Sync. In other words, specifying the horizontal back porch value (as a pixel count),

plus horizontal sync width, will determine when the chip will begin to sample pixels.

Non-multiplexed Mode

In the 15/16-bit mode shown in Figure 4, the pixel data bus represents a 15/16-bit non-multiplexed data stream,

which contains either RGB or YCrCb formatted data. When operating in RGB mode, each 15/16-bit Pn value will

contain a complete pixel encoded in either 5-6-5 or 5-5-5 format. When operating in YCrCb mode, each 16-bit Pn

word will contain an 8-bit Y (luminance) value on the upper 8 bits, and an 8-bit C (color difference) value on the

lower 8 bits. The color difference will be transmitted at half the data rate of the luminance data, with the sequence-

being set as Cb followed by Cr. The Cb and Cr data will be cosited with the Y value transmitted with the Cb value,

with the data sequence described in Table 3. The first active pixel is SAV pixels after the leading edge of horizon-

tal sync, where SAV is a bus-controlled register.

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CHRONTEL

CH7005C

t_HSW

HSYNC

t

PH 1

P1

t_P

t_PH

t_HD

POut/

t

XCLK

SP1

SAV

AVR

t

HP1

t_SP

t

P^H2^P

P3

P4

P5

P2b

P0

P1

Pixel

Data

P0a

P0b

P1a

P1b

P2a

Figure 4: Non-multiplexed Data Transfers

When IDF = 1, (YCrCb 16-bit mode), H and V sync signals can be embedded into the data stream. In this mode, the

embedded sync will be similar to the CCIR656 convention (not identical, since that convention is for 8-bit data

streams), and the first byte of the ‘video timing reference code’ will be assumed to occur when a Cb sample would

occur – if the video stream was continuous. This is delineated in Table 4 below.

Table 3. YCrCb Non-multiplexed Mode with Embedded Syncs

IDF#

1

Format

YCrCb 16-bit

Pixel#

Bus Data

P0

0

1

P1

S[7]

S[6]

S[5]

S[4]

S[3]

S[2]

S[1]

S[0]

0

P2

P3

P4

P5

P6

P7

D[15]

D[14]

D[13]

D[12]

D[11]

D[10]

D[9]

D[8]

D[7]

D[6]

D[5]

Y0[7]

Y0[6]

Y0[5]

Y0[4]

Y0[3]

Y0[2]

Y0[1]

Y0[0]

Cb0[7]

Cb0[6]

Cb0[5]

Cb0[4]

Cb0[3]

Cb0[2]

Cb0[1]

Cb0[0]

Y1[7]

Y1[6]

Y1[5]

Y1[4]

Y1[3]

Y1[2]

Y1[1]

Y1[0]

Cr0[7]

Cr0[6]

Cr0[5]

Cr0[4]

Cr0[3]

Cr0[2]

Cr0[1]

Cr0[0]

Y2[7]

Y2[6]

Y2[5]

Y2[4]

Y2[3]

Y2[2]

Y2[1]

Y2[0]

Cb2[7]

Cb2[6]

Cb2[5]

Cb2[4]

Cb2[3]

Cb2[2]

Cb2[1]

Cb2[0]

Y3[7]

Y3[6]

Y3[5]

Y3[4]

Y3[3]

Y3[2]

Y3[1]

Y3[0]

Cr2[7]

Cr2[6]

Cr2[5]

Cr2[4]

Cr2[3]

Cr2[2]

Cr2[1]

Cr2[0]

Y4[7]

Y4[6]

Y4[5]

Y4[4]

Y4[3]

Y4[2]

Y4[1]

Y4[0]

Cb4[7]

Cb4[6]

Cb4[5]

Cb4[4]

Cb4[3]

Cb4[2]

Cb4[1]

Cb4[0]

Y5[7]

Y5[6]

Y5[5]

Y5[4]

Y5[3]

Y5[2]

Y5[1]

Y5[0]

Cr4[7]

Cr4[6]

Cr4[5]

Cr4[4]

Cr4[3]

Cr4[2]

Cr4[1]

Cr4[0]

D[4]

D[3]

D[2]

D[1]

D[0]

In this mode, the S[7-0] byte contains the following data:

S[6]

S[5]

S[4]

=

F

V

H

=

1 during field 2, 0 during field 1

1 during field blanking, 0 elsewhere

1 during EAV (the synchronization reference at the end of active video)

0 during SAV (the synchronization reference at the start of active video)

Bits S[7] and S[3-0] are ignored.

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CH7005C

Multiplexed Mode

Each rising edge (or each rising and falling edge) of the XCLK signal will latch data from the graphics chip. The

multiplexed input data formats are shown in Figure 5 and 6. The Pixel Data bus represents an 8, 12, or 16-bit

multiplexed data stream, which contains either RGB or YCrCb formatted data. In IDF settings of 2, 4, 5, 7, 8 and 9,

the input data rate is 2X PCLK, and each pair of Pn values (e.g., P0a and P0b) will contain a complete pixel,

encoded as shown in the tables below. When IDF = 6, the input data rate is 3X PCLK, and each triplet of Pn values

(e.g., P0a, P0b and P0c) will contain a complete pixel, encoded as shown in the tables below. When the input is

YCrCb, the color-difference data will be transmitted at half the data rate of the luminance data, with the sequence

being set as Cb, Y, Cr, Y where Cb0,Y0,Cr0 refers to co-sited luminance and color-difference samples — and the

following Y1 byte refers to the next luminance sample, per CCIR656 standards. However, the clock frequency is

dependent upon the current mode, (not 27MHz, as specified in CCIR656).

t_HSW

HS

t_P2

t_PH2

t_HD

XCLK

DEC = 0

t_SP2

t_HP2

XCLK

DEC = 1

t_SP2

t_HP2

t_SP2

t_HP2

D[15:0]

P0a

P0b

P1a

P1b

P2a

P2b

Figure 5: Multiplexed Pixel Data Transfer Mode

Table 4. RGB 8-bit Multiplexed Mode

IDF#

7

8

Format

RGB 5-6-5

RGB 5-5-5

Pixel#

Bus Data

P0a

P0b

P1a

P1b

P0a

P0b

x

P1a

G1[2]

P1b

x

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

G0[2]

G0[1]

G0[0]

B0[4]

B0[3]

B0[2]

B0[1]

B0[0]

R0[4]

R0[3]

R0[2]

R0[1]

R0[0]

G0[5]

G0[4]

G0[3]

G1[2]

G1[1]

G1[0]

B1[4]

B1[3]

B1[2]

B1[1]

B1[0]

R1[4]

R1[3]

R1[2]

R1[1]

R1[0]

G1[5]

G1[4]

G1[3]

G0[2]

G0[1]

G0[0]

B0[4]

B0[3]

B0[2]

B0[1]

B0[0]

R0[4]

R0[3]

R0[2]

R0[1]

R0[0]

G0[4]

G0[3]

G1[1]

G1[0]

B1[4]

B1[3]

B1[2]

B1[1]

B1[0]

R1[4]

R1[3]

R1[2]

R1[1]

R1[0]

G1[4]

G1[3]

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CH7005C

Table 5. RGB 12-bit Multiplexed Mode

IDF#

4

5

Format

12-bit RGB (12-12)

Pixel#

P0a

P0b

P1a

P1b

P0a

P0b

P1a

P1b

Bus Data

D[11]

D[10]

D[9]

D[8]

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

G0[3]

G0[2]

G0[1]

G0[0]

B0[7]

B0[6]

B0[5]

B0[4]

B0[3]

B0[2]

B0[1]

B0[0]

R0[7]

R0[6]

R0[5]

R0[4]

R0[3]

R0[2]

R0[1]

R0[0]

G0[7]

G0[6]

G0[5]

G0[4]

G1[3]

G1[2]

G1[1]

G1[0]

B1[7]

B1[6]

B1[5]

B1[4]

B1[3]

B1[2]

B1[1]

B1[0]

R1[7]

R1[6]

R1[5]

R1[4]

R1[3]

R1[2]

R1[1]

R1[0]

G1[7]

G1[6]

G1[5]

G1[4]

G0[4]

G0[3]

G0[2]

B0[7]

B0[6]

B0[5]

B0[4]

B0[3]

G0[0]

B0[2]

B0[1]

B0[0]

R0[7]

R0[6]

R0[5]

R0[4]

R0[3]

G0[7]

G0[6]

G0[5]

R0[2]

R0[1]

R0[0]

G0[1]

G1[4]

G1[3]

G1[2]

B1[7]

B1[6]

B1[7]

B1[4]

B1[3]

G1[0]

B1[2]

B1[1]

B1[0]

R1[7]

R1[6]

R1[5]

R1[4]

R1[3]

G1[7]

G1[6]

G1[5]

R1[2]

R1[1]

R1[0]

G1[1]

Table 6. RGB 16-bit Muliplexed Mode

IDF#

2

Format

16-bit RGB (16-8)

Pixel#

P0a

P0b

P1a

P1b

Bus Data

D[15]

D[14]

D[13]

D[12]

D[11]

D[10]

D[9]

D[8]

D[7]

D[6]

D[5]

G0[7]

G0[6]

G0[5]

G0[4]

G0[3]

G0[2]

G0[1]

G0[0]

B0[7]

B0[6]

B0[5]

B0[4]

B0[3]

B0[2]

B0[1]

B0[0]

A0[7]

A0[6]

A0[5]

A0[4]

A0[3]

A0[2]

A0[1]

A0[0]

R0[7]

R0[6]

R0[5]

R0[4]

R0[3]

R0[2]

R0[1]

R0[0]

G1[7]

G1[6]

G1[5]

G1[4]

G1[3]

G1[2]

G1[1]

G1[0]

B1[7]

B1[6]

B1[5]

B1[4]

B1[3]

B1[2]

B0[1]

B0[0]

R1[7]

R1[6]

R1[5]

R1[4]

R1[3]

R1[2]

R1[1]

R1[0]

A1[7]

A1[6]

A1[5]

A1[4]

A1[3]

A1[2]

A1[1]

A1[0]

D[4]

D[3]

D[2]

D[1]

D[0]

Note: The AX[7:0] data is ignored.

Table 7. YCrCb Multiplexed Mode

IDF#

Format

9

YCrCb 8-bit

Pixel#

P0a

P0b

P1a

P1b

P2a

P2b

P3a

P3b

Bus Data

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

Cb0[7]

Cb0[6]

Cb0[5]

Cb0[4]

Cb0[3]

Cb0[2]

Cb0[1]

Cb0[0]

Y0[7]

Y0[6]

Y0[5]

Y0[4]

Y0[3]

Y0[2]

Y0[1]

Y0[0]

Cr0[7]

Y1[7]

Y1[6]

Y1[5]

Y1[4]

Y1[3]

Y1[2]

Y1[1]

Y1[0]

Cb2[7]

Cb2[6]

Cb2[5]

Cb2[4]

Cb2[3]

Cb2[2]

Cb2[1]

Cb2[0]

Y2[7]

Y2[6]

Y2[5]

Y2[4]

Y2[3]

Y2[2]

Y2[1]

Y2[0]

Cr2[7]

Cr2[6]

Cr2[5]

Cr2[4]

Cr2[3]

Cr2[2]

Cr2[1]

Cr2[0]

Y3[7]

Y3[6]

Y3[5]

Y3[4]

Y3[3]

Y3[2]

Y3[1]

Y3[0]

Cr0[6]

Cr0[5]

Cr0[4]

Cr0[3]

Cr0[2]

Cr0[1]

Cr0[0]

10

201-0000-025 Rev 2.1, 8/2/99

CHRONTEL

CH7005C

When IDF = 9 (YCrCb 8-bit mode), H and V sync signals can be embedded into the data stream. In this mode, the

embedded sync will follow the CCIR656 convention, and the first byte of the “video timing reference code” will be

assumed to occur when a Cb sample would occur if the video stream was continuous. This is delineated in Table 8

shown below.

Table 8. YCrCb Multiplexed Mode with Embedded Syncs

IDF#

9

Format

YCrCb 8-bit

Pixel#

Bus Data

P0a

FF

P0b

0

P1a

0

P1b

P2a

P2b

P3a

P3b

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

S[7]

S[6]

S[5]

S[4]

S[3]

S[2]

S[1]

S[0]

Cb2[7]

Cb2[6]

Cb2[5]

Cb2[4]

Cb2[3]

Cb2[2]

Cb2[1]

Cb2[0]

Y2[7]

Y2[6]

Y2[5]

Y2[4]

Y2[3]

Y2[2]

Y2[1]

Y2[0]

Cr2[7]

Cr2[6]

Cr2[5]

Cr2[4]

Cr2[3]

Cr2[2]

Cr2[1]

Cr2[0]

Y3[7]

Y3[6]

Y3[5]

Y3[4]

Y3[3]

Y3[2]

Y3[1]

Y3[0]

In this mode the S[7.0} contains the following data:

S[6]

S[5]

S[4]

=

F

V

H

=

1 during field 2, 0 during field 1

1 during field blanking, 0 elsewhere

1 during EAV (the synchronization reference at the end of active video)

0 during SAV (the synchronization reference at the start of active video)

Bits S[7] and S[3-0] are ignored.

t_HSW

HSYNC

t_P3

t_PH3

t_HD

POut/

XCLK

t_SP3

t_HP3

P0c

Pixel

Data

P0a

P0b

P1a

P1b

P1c

D[7:0]

Figure 6: Multiplexed Pixel Data Transfer Mode (IDF = 6)

Table 9. RGB 8-bit Multiplexed Mode (24-bit Color)

IDF#

6

Format

Pixel#

Bus Data

RGB 8-bit

P0a

P0b

P0c

P1a

P1b

P1c

P2a

P2b

P2c

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

B0[7]

B0[6]

B0[5]

B0[4]

B0[3]

B0[2]

B0[1]

B0[0]

G0[7]

G0[6]

G0[5]

G0[4]

G0[3]

G0[2]

G0[1]

G0[0]

R0[7]

R0[6]

R0[5]

R0[4]

R0[3]

R0[2]

R0[1]

R0[0]

B1[7]

B1[6]

B1[5]

B1[4]

B1[3]

B1[2]

B1[1]

B1[0]

G1[7]

G1[6]

G1[5]

G1[4]

G1[3]

G1[2]

G1[1]

G1[0]

R1[7]

R1[6]

R1[5]

R1[4]

R1[3]

R1[2]

R1[1]

R1[0]

B2[7]

B2[6]

B2[5]

B2[4]

B2[3]

B2[2]

B2[1]

B2[0]

G2[7]

G2[6]

G2[5]

G2[4]

G2[3]

G2[2]

G2[1]

G2[0]

R2(7)

R2(6)

R2(5)

R2(4)

R2(3)

R2(2)

R2(1)

R2(0)

201-0000-025 Rev 2.1, 8/2/99

11

CHRONTEL

CH7005C

Functional Description

The CH7005 is a TV-output companion chip to graphics controllers providing digital output in either YUV or RGB

format. This solution involves both hardware and software elements which work together to produce an optimum

TV screen image based on the original computer generated pixel data. All essential circuitry for this conversion are

integrated onchip. Onchip circuitry includes memory, memory control, scaling, PLL, DAC, filters, and NTSC/PAL

encoder. All internal signal processing, including NTSC/PAL encoding, is performed using digital techniques to

ensure that the high-quality video signals are not affected by drift issues associated with analog components. No

additional adjustment is required during manufacturing.

CH7005 is ideal for PC motherboards, web browsers, or VGA add-in boards where a minimum of discrete support

components (passive components, parallel resonance 14.31818 MHz crystal) are required for full operation.

Architectural Overview

The CH7005 is a complete TV output subsystem which uses both hardware and software elements to produce an

image on TV which is virtually identical to the image that would be displayed on a monitor. Simply creating a

compatible TV output from a VGA input involves a relatively straightforward process. This process includes a

standard conversion from RGB to YUV color space, converting from a non-interlaced to an interlaced frame

sequence, and encoding the pixel stream into NTSC or PAL compliant format. However, creating an optimum

computer-generated image on a TV screen involves a highly sophisticated process of scaling, deflickering, and

filtering. This results in a compatible TV output that displays a sharp and subtle image, of the right size, with

minimal artifacts from the conversion process.

As a key part of the overall system solution, the CH7005 software establishes the correct framework for the VGA

input signal to enable this process. Once the display is set to a supported resolution (either 640x480 or 800x600),

the CH7005 software may be invoked to establish the appropriate TV output display. The software then programs

the various timing parameters of the VGA controller to create an output signal that will be compatible with the

chosen resolution, operating mode, and TV format. Adjustments performed in software include pixel clock rates,

total pixels per line, and total lines per frame. By performing these adjustments in software, the CH7005 can render

a superior TV image without the added cost of a full frame buffer memory – normally used to implement features

such as scaling and full synchronization.

The CH7005 hardware accepts digital RGB or YCrCb inputs, which are latched in synchronization with the pixel

clock. These inputs are then color-space converted into YUV in 4-2-2 format, and stored in a line buffer memory.

The stored pixels are fed into a block where scan-rate conversion, underscan scaling and 2-line, 3-line, 4-line and 5-

line vertical flicker filtering are performed. The scan-rate converter transforms the VGA horizontal scan-rate to

either NTSC or PAL scan rates; the vertical flicker filter eliminates flicker at the output while the underscan scaling

reduces the size of the displayed image to fit onto a TV screen. The resulting YUV signals are filtered through

digital filters to minimize aliasing problems. The digital encoder receives the filtered signals and transforms them to

composite and S-Video outputs, which are converted by the three 9-bit DACs into analog outputs.

Color Burst Generation*

The CH7005 allows the subcarrier frequency to be accurately generated from a 14.31818 MHz crystal oscillator,

leaving the subcarrier frequency independent of the sampling rate. As a result, the CH7005 may be used with any

VGA chip (with an appropriate digital interface) since the CH7005 subcarrier frequency can be generated without

being dependent on the precise pixel rates of VGA controllers. This feature is a significant benefit, since even a

± 0.01% subcarrier frequency variation may be enough to cause some television monitors to lose color lock.

In addition, the CH7005 has the capability to genlock the color burst signal to the VGA horizontal sync frequency,

which enables a fully synchronous system between the graphics controller and the television. When genlocked, the

CH7005 can also stop “dot crawl” motion (for composite mode operation in NTSC modes) to eliminate the

annoyance of moving borders. Both of these features are under programmable control through the register set.

Display Modes

The CH7005 display mode is controlled by three independent factors: input resolution, TV format, and scale factor,

which are programmed via the display mode register. It is designed to accept input resolutions of 640x480,

800x600, 640x400 (including 320x200 scan-doubled output), 720x400, and 512x384.

12

* Patent number 5,874,846

201-0000-025 Rev 2.1, 8/2/99

CHRONTEL

CH7005C

Display Modes (continued)

It is disigned to support output to either NTSC or PAL television formats. The CH7005 provides interpolated scaling

with selectable factors of 5:4, 1:1, 7:8, 5:6, 3:4 and 7:10 in order to support adjustable overscan or underscan

operation when displayed on a TV. This combination of factors results in a matrix of useful operating modes which

are listed in detail in Table 10.

Table 10. CH7005 Display Modes

TVFormat

Standard

Input

(active)

Scale

Factor

Active

TV Lines

Percent (1)

Overscan

Pixel

Clock

Horizontal

Total

Vertical

Total

Resolution

640x480

800x600

640x400

720x400

512x384

1:1

7:8

5:6

3:4

7:10

10%

(3%)

(8%)

16%

4%

(3%)

16%

(8%)

(19%)

16%

(8%)

10%

(11%)

NTSC

480

420

400

500

450

420

500

400

350

500

400

480

384

24.671

28.196

30.210

39.273

43.636

47.832

21.147

26.434

30.210

23.790

29.455

20.140

24.671

784

800

1040

1064

840

945

936

800

784

525

600

630

700

750

420

525

600

420

525

420

525

5:4

1:1

7:8

5:4

1:1

5:4

1:1

640x480

800x600

640x400

720x400

512x384

5:4

1:1

5:6

1:1

5:6

3:4

5:4

1:1

5:4

1:1

5:4

1:1

600

480

400

600

500

450

500

400

500

400

480

384

14%

(8%)

(29%)

14%

(4%)

(15%)

(4%)

(29%)

(4%)

(29%)

(8%)

21.000

26.250

31.500

29.500

36.000

39.000

25.000

31.500

28.125

34.875

21.000

26.250

840

944

960

500

625

750

625

750

836

500

625

500

625

500

625

PAL

936

1000

1008

1125

1116

840

(35%)

840

(1) Note:Percent underscan is a calculated value based on average viewable lines on each TV format, assuming an average TV over-

scan of 10%. (Negative values) indicate modes which are operating in underscan.

For NTSC: 480 active lines - 10% (overscan) = 432 viewable lines (average)

For PAL: 576 active lines - 10% (overscan) = 518 viewable lines (average)

The inclusion of multiple levels of scaling for each resolution have been created to enable optimal use of the

CH7005 for different application needs. In general, underscan (modes where percent overscan is negative provides

an image that is viewable in its entirety on screen; it should be used as the default for most applications (e.g.,

viewing text screens, operating games, running productivity applications and working within Windows).

Overscanning provides an image that extends past the edges of the TV screen, exactly like normal television

programs and movies appear on TV, and is only recommended for viewing movies or video clips coming from the

computer. In addition to the above mode table, the CH7005 also support interlaced input modes, both in CCIR 656

and proprietary formats (see Display Mode Register section.)

Flicker Filter and Text Enhancement

The CH7005 integrates an advanced 2-line, 3-line, 4-line and 5-line (depending on mode) vertical deflickering filter

circuit to help eliminate the flicker associated with interlaced displays. This flicker circuit provides an adaptive

filter algorithm for implementing flicker reduction with selections of high, medium or low flicker content for both

luma and chroma channels (see register descriptions). In addition, a special text enhancement circuit incorporates

201-0000-025 Rev 2.1, 8/2/99

13

CHRONTEL

CH7005C

Display Modes (continued)

additional filtering for enhancing the readability of text. These modes are fully programmable via I²C under the

flicker filter register.

Internal Voltage Reference

An onchip bandgap circuit is used in the DAC to generate a reference voltage which, in conjunction with a reference

resistor at pin RSET, and register controlled divider, sets the output ranges of the DACs. The CH7005 bandgap

reference voltage is 1.235 volts nominal for NTSC or PAL-M, or 1.317 volts nominal (for PAL or NTSC-J), which

is determined by IDF register bit 6 (DACG bit). The recommended value for the reference resistor RSET is 360

ohms (though this may be adjusted in order to achieve a different output level). The gain setting for DAC output is

th

1/48 . Therefore, for each DAC, the current output per LSB step is determined by the following equation:

I

= V(RSET)/RSET reference resistor * 1/GAIN

LSB

For DACG=0, this is: I

For DACG=1, this is: I

= 1.235/360 * 1/48 = 71.4 mA (nominal)

= 1.317/360 * 1/48 = 76.2 mA (nominal)

LSB

Power Management

The CH7005 supports five operating states including Normal [On], Power Down, Full Power Down, S-Video Off,

and Composite Off to provide optimal power consumption for the application involved. Using the programmable

power down modes accessed over the I²C port, the CH7005 may be placed in either Normal state, or any of the four

power managed states, as listed below (see “Power Management Register” under the Register Descriptions section

for programming information). To support power management, a TV sensing function (see “Connection Detect

Register” under the Register Descriptions section) is provided, which identifies whether a TV is connected to either

S-Video or composite. This sensing function can then be used to enter into the appropriate operating state (e.g., if

TV is sensed only on composite, the S-Video Off mode could be set by software).

Table 11. Power Management

Operating State

Normal (On):

Functional Description

In the normal operating state, all functions and pins are active

Power Down:

In the power-down state, most pins and circuitry are disabled.The DS/BCO pin

will continue to provide either the VCO divided by K3, or 14.318 MHz out when

selected as an output, and the P-OUT pin will continue to output a clock

reference when in master clock mode.

S-Video Off:

Power is shut off to the unused DACs associated with S-Video outputs.

Composite Off:

In Composite-off state, power is shut off to the unused DAC associated with

CVBS output.

2

Full Power Down:

In this power-down state, all but the I C circuits are disabled. This places the

CH7005 in its lowest power consumption mode.

Luminance and Chrominance Filter Options

The CH7005 contains a set of luminance filters to provide a controllable bandwidth output on both CVBS and S-

Video outputs. All values are completely programmable via the Video Bandwidth Register. For all graphs shown,

the horizontal axis is frequency in MHz, and the vertical axis is attenuation in dBs. The composite luminance and

chrominance video bandwidth output is shown in Table 12.

Macrovision^TMAnti-copy Protection

The CH7005 implements the Macrovision 7.X anti-copy protection process. This process changes the encoded

output of the NTSC/PAL signals to inhibit recording on VCR devices while not affecting viewing on a TV. The

parameters that control this process are fully programmable and can be described by Chrontel only after a suitable

Non-Disclosure Agreement has been executed between Macrovision^TM, Inc. and the customer.

14

201-0000-025 Rev 2.1, 8/2/99

CHRONTEL

CH7005C

VBI Pass-Through Support

The CH7005 provides the ability to pass-through data with minimal filtering, on vertical blanking lines 10-21 for

Intercast or close captioned applications (see register descriptions).

Table 12. Video Bandwidth

Mode

Chrominance

Luminance Bandwidth with Sin(X) /X (MHz)

CVBS

YCV

S-Video

CBW[1:0]

YSV[1:0], YPEAK = 0

YSV[1:0], YPEAK = 1

00

01

10

11

00

01

1X

00

01

1X

0

1

0

1

2

3

4

5

6

7

0.62

0.78

0.53

0.65

0.83

1.03

0.70

0.87

0.74

0.93

0.63

0.78

0.89

0.62

0.78

0.93

0.64

0.74

0.79

0.77

0.95

1.02

0.77

0.86

0.94

0.71

0.47

0.38

0.68

0.85

0.58

0.71

0.91

1.13

0.77

0.95

0.81

1.02

0.68

0.86

0.98

0.68

0.85

1.02

0.71

0.81

0.87

0.85

1.03

1.12

0.85

0.94

1.03

0.78

0.51

0.41

0.80

1.00

0.68

0.83

1.07

1.32

0.90

1.12

0.95

1.20

0.80

1.00

1.15

0.80

1.00

1.20

0.83

0.95

1.02

1.00

1.22

1.32

0.99

1.11

1.21

0.91

0.60

0.48

0.95

1.18

0.81

0.99

1.27

1.57

1.07

1.33

1.13

1.42

0.95

1.19

1.36

0.95

1.18

1.42

0.98

1.13

1.21

1.18

1.44

1.56

1.18

1.31

1.44

1.08

0.71

0.57

2.26

2.82

1.93

2.36

3.03

3.75

2.56

3.17

2.69

3.39

2.28

2.84

3.25

2.26

2.82

3.39

2.35

2.70

2.89

2.82

3.44

3.73

2.82

3.13

3.43

2.58

1.70

1.37

3.37

4.21

2.87

3.52

4.51

5.59

3.81

4.72

4.01

5.05

3.39

4.24

4.84

3.37

4.21

5.05

3.50

4.02

4.31

4.20

5.13

5.56

4.20

4.66

5.11

3.85

2.53

2.04

2.26

2.82

1.93

2.36

3.03

3.75

2.56

3.17

2.69

3.39

2.28

2.84

3.25

2.26

2.82

3.39

2.35

2.70

2.89

2.82

3.44

3.73

2.82

3.13

3.43

2.58

1.70

1.37

3.37

4.21

2.87

3.52

4.51

5.59

3.81

4.72

4.01

5.05

3.39

4.24

4.84

3.37

4.21

5.05

3.50

4.02

4.31

4.20

5.13

5.56

4.20

4.66

5.11

3.85

2.53

2.04

5.23

6.53

4.46

5.46

7.00

8.68

5.92

7.33

6.22

7.84

5.26

6.58

7.52

5.23

6.53

7.84

5.43

6.24

6.68

6.53

7.97

8.63

6.52

7.24

7.94

5.97

3.92

3.17

2.57

3.21

2.19

2.68

3.44

4.27

2.91

3.60

3.06

3.85

2.59

3.23

3.70

2.57

3.21

3.85

2.67

3.07

3.29

3.21

3.92

4.24

3.20

3.56

3.90

2.94

1.93

1.56

4.44

5.56

3.79

4.64

5.95

7.38

5.04

6.23

5.29

6.67

4.48

5.59

6.39

4.44

5.56

6.67

4.62

5.30

5.68

5.55

6.77

7.34

5.54

6.16

6.75

5.08

3.34

2.69

5.23

6.53

4.46

5.46

7.00

8.68

5.92

7.33

6.22

7.84

5.26

6.58

7.52

5.23

6.53

7.84

5.43

6.24

6.68

6.53

7.97

8.63

6.52

7.24

7.94

5.97

3.92

3.17

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

The composite luminance and chrominance frequency response is depicted in Figures 7 through 9.

201-0000-025 Rev 2.1, 8/2/99

15

CHRONTEL

CH7005C

Luminance and Chrominance Filter Options (continued)

0

-6

6

-12

12

-1₁8₈

_<<_{i >}i>

(YCVdB

)

_nn

YCVdB

-24

24

-

30

-36

36

-42

42

0

1

2

3

4

5

6

7

8

9

10

11

12

10

11

12

7

8

5

6

4

0

f

n , i

6

n,i

6

10

Figure 7: Composite Luminance Frequency Response (YCV = 0)

0

-6

-12

-18

-24

-30

<i >

YSVdB

<i>

(YSVdB

)

n

-36

-42

0

9

8

10

11

12

3

5

7

4

1

2

6

n, i

f

6

10

Figure 8: S-Video Luminance Frequency Response (YSV = 1X, YPEAK = 0)

16

201-0000-025 Rev 2.1, 8/2/99

CHRONTEL

CH7005C

Luminance and Chrominance Filter Options (continued)

0

6

-6

-1¹2²

18

-18

<i>

UVfirdB

n

)

<i>

(UVfirdB

n

24

-24

30

-30

36

-36

42

-42

⁰0

1¹

2

3

4

5

6

7

8

9

10

11

12

5

6

f

n, i

n,i

6

10

Figure 9: Chrominance Frequency Response

201-0000-025 Rev 2.1, 8/2/99

17

CHRONTEL

CH7005C

NTSC and PAL Operation

Composite and S-Video outputs are supported in either NTSC or PAL format. The general parameters used to

characterize these outputs are listed in Table 13 and shown in Figure 10. (See Figure 13 through 18 for illustrations

of composite and S-Video output waveforms.)

CCIR624-3 Compliance

The CH7005 is predominantly compliant with the recommendations called out in CCIR624-3. The following are the

only exceptions to this compliance:

• The frequencies of Fsc, Fh, and Fv can only be guaranteed in master or pseudo-master modes, not in slave mode

when the graphics device generates these frequencies.

• It is assumed that gamma correction, if required, is performed in the graphics device which establishes the color

reference signals.

• All modes provide the exact number of lines called out for NTSC and PAL modes respectively, except mode 21,

which outputs 800x600 resolution, scaled by 3:4, to PAL format with a total of 627 lines (vs. 625).

• Chroma signal frequency response will fall within 10% of the exact recommended value.

• Pulse widths and rise/fall times for sync pulses, front/back porches, and equalizing pulses are designed to

approximate CCIR624-3 requirements, but will fall into a range of values due to the variety of clock frequencies

used to support multiple operating modes

Table 13. NTSC/PAL Composite Output Timing Parameters (in mS)

Level (mV)

Duration (uS)

NTSC

Symbol

Description

NTSC

PAL

Front Porch

Horizontal Sync

Breezeway

Color Burst

Back Porch

Black

1.49 - 1.51

4.69 - 4.72

0.59 - 0.61

2.50 - 2.53

1.55 - 1.61

0.00 - 7.50

37.66 - 52.67

0.00 - 7.50

1.48 - 1.51

4.69 - 4.71

0.88 - 0.92

2.24 - 2.26

2.62 - 2.71

0.00 - 8.67

34.68 - 52.01

0.00 - 8.67

A

B

C

D

E

F

287

0

300

0

287

340

300

Active Video

Black

G

H

For this table and all subsequent figures, key values are:

Note:

1. RSET = 360 ohms; V(RSET) = 1.235V; 75 ohms doubly terminated load.

2. Durations vary slightly in different modes due to the different clock frequencies used.

3. Active video and black (F, G, H) times vary greatly due to different scaling ratios used in different modes.

4. Black times (F and H) vary with position controls.

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201-0000-025 Rev 2.1, 8/2/99

CHRONTEL

CH7005C

A

B

C

D

E

F

G

H

Figure 10: NTSC / PAL Composite Output

SSTTAARRTT

OOFF

VVSSYYNNCC

AANNAALLOOGG

Start of

field 1

FFIEIELLDD 11

523

552200 552211 552222 5522

524

9

66

12

99

10

77

525

11

88

3

552255

1

33 55224

2

4

11

4

22

5

336

447

558

Pre-equalizing

pulse interval

Post-equalizing

pulse interval

Vertical sync

pulse interval

Reference

sub-carrier phase

color field 1

Line

vertical

AANNAALLOOGG

FFIEIELLDD 22

interval

t +V

1

262

263

264

270

261

265

267

268

269

271

272

225588 225599 226600 226611 226622 226633 226644 226655 226666 226677 226688 226699 227700 227711 227722

273

274

275

266

START

OF

VSYNC

Start of

field 2

Reference

ANALOG

FIELD 1

sub-carrier phase

t +V

2

color field 2

523

10

12

9

524

521

11

8

6

3

2

524

7

4

8

5

9

6

525

522

4

1

5

2

520

523

1

Start of

field 3

525

3

7

Reference

ANALOG

^subF^-cIE^arL^riD^{er p}2^hase

t +V

3

color field 3

263

260

264

261

274

271

261

258

262

259

269

266

270

267

273

270

272

269

262

265

2

6

3

2

6

4

7

2

6

68

5

2

27

6

1

8

227725

Start of

field 4

Reference

sub-carrier phase

color field 4

Figure 11: Interlaced NTSC Video Timing

201-0000-025 Rev 2.1, 8/2/99

19

CHRONTEL

CH7005C

START

OF

VSYNC

ANALOG

FIELD 1

620 621

622 623

624 625

1

2

3

4

5

6

7

8

9

10

ANALOG

FIELD 2

308 309 310 311 312 313

314 315

316 317 318 319 320 321 322 323

ANALOG

FIELD 3

620 621 622 623 624 625

1

2

3

4

5

6

7

8

9

10

ANALOG

FIELD 4

308 309 310 311 312 313

314 315

316 317 318 319 320 321 322 323

BURST

BLANKING

4

3

INTERVALS

°

BURST PHASE = REFERENCE PHASE = 135 R

°

ELATIVE TO U

BURST PHASE = REFERENCE PHASE = 135 RELATIVE TO U

PAL SWITCH = 0, +V COMPONENT

2

1

°

BURST PHASE = REFERENCE PHASE+90 = 225 RELATIVE TO U

°

BURST PHASE = REFERENCE PHASE+90 = 225 RELATIVE TO U

PAL SWITCH = 1, - V COMPONENT

Figure 12: Interlaced PAL Video Timing

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CHRONTEL

CH7005C

Color bars:

Color/Level

mA

V

White

Yellow

26.66

24.66

1.000

0.925

Cyan

Green

21.37

19.37

0.801

0.726

Magenta

Red

16.22

14.22

0.608

0.533

Blue

Black

11.08

9.08

0.415

0.340

Blank

7.65

0.287

Sync

0.00

0.000

Figure 13: NTSC Y (Luminance) Output Waveform (DACG = 0)

Color bars:

Color/Level

mA

V

White

Yellow

26.75

24.62

1.003

0.923

Cyan

Green

21.11

18.98

0.792

0.712

Magenta

Red

15.62

13.49

0.586

0.506

Blue

10.14

8.00

0.380

0.300

Blank/ Black

Sync

0.00

0.000

Figure 14: PAL Y (Luminance) Video Output Waveform (DACG = 1)

201-0000-025 Rev 2.1, 8/2/99

21

CHRONTEL

CH7005C

Color bars:

Color/Level

mA

V

Cyan/Red

Green/Magenta 25.01

25.80

0.968

0.938

Yellow/Blue

22.44

0.842

Peak Burst

Blank

18.08

14.29

0.678

0.536

Peak Burst

10.51

0.394

3.579545 MHz Color Burst

(9 cycles)

Yellow/Blue

6.15

0.230

Green/Magenta

Cyan/Red

3.57

2.79

0.134

0.105

Figure 15: NTSC C (Chrominance) Video Output Waveform (DACG = 0)

Color bars:

Color/Level

mA

V

Cyan/Red

Green/Magenta 26.68

27.51

1.032

1.000

Yellow/Blue

23.93

0.897

Peak Burst

Blank

19.21

15.24

0.720

0.572

Peak Burst

11.28

0.423

4.433619 MHz Color Burst

(10 cycles)

Yellow/Blue

6.56

0.246

Green/Magenta

Cyan/Red

3.81

2.97

0.143

0.111

Figure 16: PAL C (Chrominance) Video Output Waveform (DACG = 1)

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201-0000-025 Rev 2.1, 8/2/99

CHRONTEL

CH7005C

Color/Level

mA

V

Color bars:

Peak Chrome 32.88

1.233

White

26.66

1.000

Peak Burst

11.44

0.429

Black

Blank

9.08

7.65

0.340

0.281

Peak Burst

Sync

4.45 0.145

0.00 0.000

3.579545 MHz Color Burst

(9 cycles)

Figure 17: Composite NTSC Video Output Waveform (DACG = 0)

mA

Color/Level

V

Color bars:

Peak Chrome 33.31

1.249

White

26.75

1.003

Peak Burst

Blank/Black

11.97

8.00

0.449

0.300

Peak Burst

Sync

4.04

0.00

0.151

0.000

4.433619 MHz Color Burst

(10 cycles)

Figure 18: Composite PAL Video Output Waveform (DACG = 1)

201-0000-025 Rev 2.1, 8/2/99

23

CHRONTEL

CH7005C

I²C Port Operation

The CH7005 contains a standard I²C control port, through which the control registers can be written and read. This

port is comprised of a two-wire serial interface, pins SD (bidirectional) and SC, which can be connected directly to

the SDB and SCB buses as shown in Figure 19.

The Serial Clock line (SC) is input only and is driven by the output buffer of the master device (also shown in

Figure 19). The CH7005 acts as a slave, and generation of clock signals on the bus is always the responsibility of

the master device. When the bus is free, both lines are HIGH. The output stages of devices connected to the bus

must have an open-drain or open-collector to perform the wired-AND function. Data on the bus can be transferred

up to 400 kbit/s.

+DVDD

R_P

SDB (Serial Data Bus)

SCB (Serial Clock Bus)

SD

SC

DATAN2

OUT

MASTER

DATAN2

OUT

DATAN2

OUT

SCLK

OUT

FROM

MASTER

DATA IN

MASTER

SCLK

IN1

DATA

IN1

SCLK

IN2

DATA

IN2

BUS MASTER

SLAVE

Figure 19: Connection of Devices to the Bus

Electrical Characteristics for Bus Devices

The electrical specifications of the bus devices’ inputs and outputs and the characteristics of the bus lines connected

to them are shown in Figure 19. A pull-up resistor (R_P) must be connected to a 3.3V ± 10% supply. The CH7005 is

a device with input levels related to DVDD.

Maximum and minimum values of pull-up resistor (R )

P

The value of R depends on the following parameters:

P

• Supply voltage

• Bus capacitance

• Number of devices connected (input current + leakage current = I

)

input

The supply voltage limits the minimum value of resistor R due to the specified minimum sink current of 2mA at

P

VOL

= 0.4 V for the output stages:

max

R >= (V – 0.4) / 2 (R in kW)

P

DD

P

The bus capacitance is the total capacitance of wire, connections and pins. This capacitance limits the maximum

value of R due to the specified rise time. The equation for RP is shown below:

P

3

R <= 10 /C (where: R is in kW and C, the total capacitance, is in pF)

P

The maximum HIGH level input current of each input/output connection has a specified maximum value of 10 mA.

Due to the desired noise margin of 0.2V for the HIGH level, this input current limits the maximum value of R .

DD

P

The R limit depends on V and is shown below:

P

DD

R <= (100 x V )/ I

(where: R is in kW and I

is in mA)

input

P

DD input

P

24

201-0000-025 Rev 2.1, 8/2/99

CHRONTEL

CH7005C

Transfer Protocol

Both read and write cycles can be executed in “Alternating” and “Auto-increment” modes. Alternating mode

expects a register address prior to each read or write from that location (i.e., transfers alternate between address and

data). Auto-increment mode allows you to establish the initial register location, then automatically increments the

register address after each subsequent data access (i.e., transfers will be address, data data data...). A basic serial port

transfer protocol is shown in Figure 20 and described below.

SD

2

I C

1 - 8

CH7

1 - 8

9

8

9

SC

Stop

Condition

Start

Condition

Data

ACK

Device ID

R/W*

ACK

Data₁

ACK

n

CH7005

acknowledge

Figure 20: Serial Port Transfer Protocol

1. The transfer sequence is initiated when a high-to-low transition of SD occurs while SC is high; this is the

“START” condition. Transitions of address and data bits can only occur while SC is low.

2. The transfer sequence is terminated when a low-to-high transition of SD occurs while SC is high; this is the

“STOP” condition.

3. Upon receiving the first START condition, the CH7005 expects a Device Address Byte (DAB) from the

master device. The value of the device address is shown in the DAB data format below.

4. After the DAB is received, the CH7005 expects a Register Address Byte (RAB) from the master. The

format of the RAB is shown in the RAB data format below (note that B7 is not used).

Device Address Byte (DAB)

B7

1

B6

1

B5

1

B4

0

B3

1

B2

0

B1

1

B0

R/W

Read/Write Indicator

“0”: master device will write to the CH7005 at the register location specified by the address

AR[5:0]

“1”: master device will read from the CH7005 at the register location specified by the

address AR[5:0].

Register Address Byte (RAB)

B0

B7

1

B6

B5

B4

B3

B2

B1

AutoInc

AR[5]

AR[4]

AR[3]

AR[2]

AR[1]

AR[0]

201-0000-025 Rev 2.1, 8/2/99

25

CHRONTEL

CH7005C

Transfer Protocols (continued)

AutoInc

Register Address Auto-Increment - to facilitate sequential R/W of registers.

“1”: Auto-Increment enabled (auto-increment mode).

Write: After writing data into a register, the Address Register will automatically be

incremented by one.

Read: Before loading data from a register to the on-chip temporary register (getting ready to

be serially read), the Address Register will automatically be incremented by one.

However, for the first read after an RAB, the Address Register will not be changed.

“0”: Auto-Increment disabled (alternating mode).

Write: After writing data into a register, the Address Register will remain unchanged until a

new RAB is written.

Read: Before loading data from a register to the on-chip temporary register (getting ready to

be serially read), the Address Register will remain unchanged.

AR[5:0]

Specifies the Address of the Register to be Accessed.

This register address is loaded into the Address Register of the CH7005. The R/W access, which

follows, is directed to the register specified by the content stored in the Address Register.

The following two sections describe the operation of the serial interface for the four combinations of R/W = 0,1 and

AutoInc = 0,1.

CH7005 Write Cycle Protocols (R/W = 0)

Data transfer with acknowledge is required. The acknowledge-related clock pulse is generated by the master-

transmitter. The master-transmitter releases the SD line (HIGH) during the acknowledge clock pulse. The slave-

receiver must pull down the SD line, during the acknowledge clock pulse, so that it remains stable LOW during the

HIGH period of the clock pulse. The CH7005 always acknowledges for writes (see Figure 21). Note that the

resultant state on SD is the wired-AND of data outputs from the transmitter and receiver.

SD Data Output

By Master-Transmitter

not acknowledge

SD Data Output

By the CH7005

acknowledge

SC from

Master

1

2

8

9

clock pulse for

Start

Condition

acknowledgment

Figure 21: Acknowledge on the Bus

Figure 22 shows two consecutive alternating write cycles for AutoInc = 0 and R/W = 0. The byte of information,

following the Register Address Byte (RAB), is the data to be written into the register specified by AR[5:0]. If

AutoInc = 0, then another RAB is expected from the master device, followed by another data byte, and so on.

26

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CHRONTEL

CH7005C

CH7005

acknowledge

SD

2

I C

1 - 8

1 - 7

8

9

SC

Start

Condition

Stop

Condition

Device ID R/W*

ACK

RAB

ACK

Data

ACK

RAB

ACK

Data

ACK

Note: The acknowledge is from the CH7005 (slave).

Figure 22: Alternating Write Cycles

If AutoInc = 1, then the register address pointer will be incremented automatically and subsequent data bytes will be

written into successive registers without providing an RAB between each data byte. An Auto-increment write cycle

is shown in Figure 23.

.

CH7005

acknowledge

SD

SC

2

I C

1 - 7

1 - 8

8

9

Start

Condition

Stop

Condition

Device ID R/W*

ACK

RAB

ACK

Data

ACK

Data

n+1

ACK

n

Note: The acknowledge is from the CH7005 (slave).

Figure 23: Auto-Increment Write Cycle

When the auto-increment mode is enabled (AutoInc is set to 1), the register address pointer continues to increment

for each write cycle until AR[5:0] = 3F (3F is the address of the Address Register). The next byte of information

represents a new auto-sequencing “Starting address,” which is the address of the register to receive the next byte.

The auto-sequencing then resumes based on this new “Starting address.” The auto-increment sequence can be

terminated any time by either a “STOP” or “RESTART” condition. The write operation can be terminated with a

“STOP” condition.

CH7005 Read Cycle Protocols (R/W = 1)

If a master-receiver is involved in a transfer, it must signal the end of data to the slave-transmitter by not generating

an acknowledge on the last byte that was clocked out of the slave. The slave-transmitter CH7005 releases the data

line to allow the master to generate the STOP condition or the RESTART condition.

To read the content of the registers, the master device starts by issuing a “START” condition (or a “RESTART”

condition). The first byte of data, after the START condition, is a DAB with R/W = 0. The second byte is the RAB

with AR[5:0], containing the address of the register that the master device intends to read from in AR[5:0]. The

master device should then issue a “RESTART” condition (“RESTART” = “START,” without a previous “STOP”

condition). The first byte of data, after this RESTART condition, is another DAB with R/W=1, indicating the

master’s intention to read data hereafter. The master then reads the next byte of data (the content of the register

specified in the RAB). If AutoInc = 0, then another RESTART condition, followed by another DAB with R/W = 0

and RAB, is expected from the master device. The master device then issues another RESTART, followed by

another DAB. After that, the master may read another data byte, and so on. In summary, a RESTART condition,

followed by a DAB, must be produced by the master before each of the RAB, and before each of the data read

events. Two consecutive alternating read cycles are shown in Figure 24.

201-0000-025 Rev 2.1, 8/2/99

27

CHRONTEL

CH7005C

Transfer Protocols (continued)

.

CH7005

acknowledge

Master

SD

does not

acknowledge

2

I C

1 - 8

1 - 7

8

9

10

1 - 7

8

9

10

SC

Start

Condition

Device ID R/W* ACK

RAB

ACK Restart

Condition

Device ID R/W* ACK

Data

ACK

Restart

1

Condition

Master does

not acknowledge

CH7005

acknowledge

CH7005

acknowledge

CH7005

acknowledge

2

I C

1 - 8

1 - 7

8

9

10

1 - 7

8

9

Stop

Condition

DeviceID

R/W* ACK

RAB

ACK

Restart DeviceID R/W* ACK

Condition

Data

ACK

2

Figure 24: Alternating Read Cycle

If AutoInc = 1, then the address register will be incremented automatically and subsequent data bytes can be read

from successive registers, without providing a second RAB

Master does

not acknowledge

just before Stop

condition

CH7005

acknowledge

CH7005

acknowledge

CH7005

acknowledge

Master

acknowledge

SD

2

I C

1 - 8

1 - 7

8

9

10

1 - 7

8

9

SC

Start

Condition

Stop

Condition

Device ID R/W* ACK RAB

ACK Restart Device ID R/W* ACK Data

Condition

ACK

Data

n+1

ACK

n

Figure 25: Auto-increment Read Cycle

When the auto-increment mode is enabled (AutoInc is set to 1), the Address Register will continue incrementing for

each read cycle. When the content of the Address Register reaches 2A, it will wrap around and start from 00h again.

The auto increment sequence can be terminated by either a “STOP” or “RESTART” condition. The read operation

can be terminated with a “STOP” condition. Figure 25 shows an auto-increment read cycle terminated by a STOP

or RESTART condition.

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201-0000-025 Rev 2.1, 8/2/99

CHRONTEL

CH7005C

Registers and Programming

The CH7005 is a fully programmable device, providing for full functional control through a set of registers accessed

from the I²C port. The CH7005 contains a total of 37 registers, which are listed in Table 14 and described in detail

under Register Descriptions. Detailed descriptions of operating modes and their effects are contained in the previ-

ous section, Functional Description. An addition (+) sign in the Bits column below signifies that the parameter con-

tains more than 8 bits, and the remaining bits are located in another register.

Table 14. Register Map

Register

Display Mode

Symbol

DMR

FFR

VBW

IDF

Address

00H

Bits

Functional Summary

Display mode selection

8

Flicker Filter

01H

6

Flicker filter mode selection

Video Bandwidth

Input Data Format

Clock Mode

03H

7

Luma and chroma filter bandwidth selection

Data format and bit-width selections

Sets the clock mode to be used

Active video delay setting

04H

7

CM

06H

8

Start Active Video

Position Overflow

Black Level

SAV

PO

07H

8+

3

08H

MSB bits of position values

BLR

HPR

09H

8

Black level adjustment input latch clock edge select

0AH

8+

Enables horizontal movement of displayed image on

TV

Horizontal Position

Vertical Position

VPR

0BH

8+

Enables vertical movement of displayed image on

TV

SPR

PMR

CDR

CE

0DH

0EH

4

Determines the horizontal and vertical sync polarity

Enables power saving modes

Sync Polarity

Power Management

Connection Detect

Contrast Enhancement

PLL M and N extra bits

PLL-M Value

5

10H

4

Detection of TV presence

11H

3

Contrast enhancement setting

MNE

PLLM

PLLN

BCO

FSCI

13H

5

Contains the MSB bits for the M and N PLL values

Sets the PLL M value - bits (7:0)

14H

8+

6

PLL-N Value

15H

Sets the PLL N value - bits (7:0)

Buffered Clock

17H

Determines the clock output at pin 41

Determines the subcarrier frequency

Subcarrier Frequency

Adjust

18H -1FH

4 or 8

each

PLL and Memory Control

CIV Control

PLLC

CIVC

CIV

20H

21H

6

Controls for the PLL and memory sections

Control of CIV value

5

Calculated Fsc Increment

Value

22H -

24H

8 each

Readable register containing the calculated

subcarrier increment value

Version ID

Test

VID

TR

25H

8

Device version number

26H -

29H

30

Reserved for test (details not included herein)

Address

AR

3FH

6

Current register being addressed

201-0000-025 Rev 2.1, 8/2/99

29

CHRONTEL

CH7005C

Register Descriptions (continued)

2

Table 15. I C Alternate Register Map (Note: Macrovision^TMcontrols available only by special arrangement)

Register

00H

01H

02H

03H

04H

05H

06H

07H

08H

09H

0AH

0BH

0CH

0DH

0EH

0FH

10H

11H

12H

13H

14H

15H

16H

17H

18H

19H

1AH

1BH

1CH

1DH

1EH

1FH

20H

21H

22H

23H

24H

25H

26H

27H

28H

29H

3FH

Bit 7

Bit 6

Bit 5

IRO

Bit 4

VOS1

FC0

Bit 3

VOS0

FY1

Bit 2

SR2

FY0

Bit 1

SR1

FT1

Bit 0

SR0

FT0

IR2

IR1

FC1

FLFF

CVBW

DACG

CBW1

CBW0

YPEAK

IDF3

YSV1

IDF2

YSV0

IDF1

YCV

IDF0

RGBBP

CFRB

SAV7

M/S*

Reserved

SAV5

MCP

XCM1

SAV3

XCM0

SAV2

SAV8

BL2

PCM1

SAV1

HP8

PCM0

SAV0

VP8

SAV6

SAV4

BL7

HP7

VP7

BL6

HP6

VP6

BL5

HP5

VP5

BL4

HP4

VP4

BL3

HP3

VP3

BL1

BL0

HP2

HP1

HP0

VP0

VP2

VP1

DES

SYO

PD2

VSP

PD1

HSP

PD0

SCART

Reset*

YT

CT

CVBST

CE1

SENSE

CE0

CE2

SNE

M4

SPE

M3

N9

M2

N2

N8

M1

N1

M8

M0

N0

M7

N7

M6

N6

M5

N5

N4

N3

SHF2

SHF1

SHF0

FSCI31

FSCI27

FSCI23

FSCI19

FSCI15

FSCI11

FSCI7

FSCI3

PLLS

SCO2

FSCI30

FSCI26

FSCI22

FSCl18

FSCl14

FSCl10

FSCI6

FSCI2

PLL5VD

ClVH1

CIV18

CIV10

CIV2

SCO1

FSCI29

FSCI25

FSCI21

FSCl17

FSCl13

FSCl9

FSCI5

FSCI1

PLL5VA

ClVH0

CIV17

CIV9

SCO0

FSCI28

FSCI24

FSCI20

FSCl16

FSCI12

FSCI8

FSCI4

FSCI0

MEM5V

AClV

P-OUTP

DSEN

PLLCPl

PLLCAP

CIV25

CIV20

CIV12

CIV4

CIV24

CIV19

CIV11

CIV3

CIV23

CIV15

CIV7

VID7

TS3

CIV22

CIV14

CIV6

VID6

TS2

CIV21

CIV13

CIV5

VID5

TS1

CIV16

CIV8

CIV1

CIVO

VID4

VID3

VID2

VID1

VID0

TS0

RSA

BST

NST

TE

MS2

MS1

MSO

MTD

YLM8

YLM1

CLM1

AR1

CLM8

YLM0

CLM0

AR0

YLM7

YLM6

YLM5

CLM5

AR5

YLM4

CLM4

AR4

YLM3

CLM3

AR3

YLM2

CLM2

AR2

CLM7

CLM6

reserved

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CH7005C

Register Descriptions (continued)

Display Mode Register

Address: 00H

Bits: 8

Bit:

7

6

5

4

3

2

1

0

IR2

IR1

IR0

VOS1

VOS0

SR2

SR1

R/W

1

SR0

Symbol:

Type:

R/W

0

R/W

1

R/W

1

R/W

0

R/W

1

R/W

0

R/W

0

Default:

This register provides programmable control of the CH7005 display mode, including input resolution (IR[2:0]),

output TV standard (VOS[1:0]), and scaling ratio (SR[2:0]). The mode of operation is determined according to the

table below (default is 640x480 input, NTSC output, 7/8’s scaling).

Table 16. Display Modes

Input Data

Format

(Active

Total

Pixels/Line

x Total

Output

Format

VOS

[1:0]

SR

[2:0]

Pixel Clock

(MHz)

Mode

0

IR[2:0]

000

001

010

011

100

101

110

Video)

Lines/Frame

Scaling

5/4

1/1

5/4

1/1

5/4

1/1

5/4

1/1

5/4

1/1

5/4

1/1

7/8

5/4

1/1

5/6

1/1

7/8

5/6

1/1

5/6

3/4

5/6

3/4

7/10

1/1

00

01

00

01

00

01

00

01

00

01

00

01

00

01

000

001

000

001

000

001

000

001

010

001

000

001

010

000

001

011

001

010

011

001

011

100

011

100

101

001

512x384

720X400

720x400

640x400

640x480

800x600

720x576

720x480

800x500

640X400

840x500

840x625

800x420

784x525

1125X500

1116x625

945x420

936x525

1000x500

1008x625

840x420

840x525

840x600

840x500

840x625

840x750

784x525

784x600

800x630

944x625

960x750

936x836

1040x630

1040x700

1064x750

864x625

858x525

1135x625

910X525

PAL

21.000000

26.250000

20.139860

24.671329

28.125000

34.875000

23.790210

29.454545

25.000000

31.5000000

21.146853

26.433566

30.209790

21.000000

26.250000

31.5000000

24.671329

28.195804

30.209790

29.500000

36.0000000

39.000000

39.272727

43.636364

47.832168

13.500000

17.734375

14.318182

1

PAL

2

NTSC

PAL

3

4

5

PAL

6

NTSC

PAL

7

8

9

PAL

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25*

26*

27*

28*

NTSC

PAL

NTSC

PAL

NTSC

PAL

NTSC

PAL

NTSC

* Interlaced modes of operation. (For those modes, some functions will be bypassed. For details, please contact the

application department.)

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CHRONTEL

CH7005C

Register Descriptions (continued)

00

01

10

11

VOS[1:0]

PAL

NTSC

PAL-M

NTSC-J

Output Format

Flicker Filter Register

Symbol: FFR

Address: 01H

Bits: 6

Bit:

7

6

5

4

3

2

1

0

FC1

R/W

1

FC0

R/W

1

FY1

R/W

0

FY0

R/W

0

FT1

R/W

1

FT0

R/W

0

Symbol:

Type:

Default:

The flicker filter register provides for adjusting the operation of the various filters used in rendering the on-screen

image. Adjusting settings between minimal and maximal values enables optimization between sharpness and flicker

content. The FC[1:0] bits determine the settings for the chroma channel. The FT[1:0] bits determine the settings for

the text enhancement circuit. The FY[1:0] bits determine the settings for the luma channel. In addition, the Chroma

channel filtering includes a setting to enable the chroma dot crawl reduction circuit.

Note: When writing to register O1H, FY[1:0] is bits 3:2. FT[1:0] is bits 1:0. When reading from the register O1H, FY

[1:0] is bits 1:0 and FT[1:0] is bits 3:2.

Table 17. Flicker Filter Settings

FY[1:0]

00

Settings for Luma Channel

Minimal Flicker Filtering

Slight Flicker Filtering

Maximum Flicker Filtering

Invalid

01

10

11

FT[1:0]

00

Settings for Text Enhancement Circuit

Maximum Text Enhancement

Slight Text Enhancement

Minimum Text Enhancement

Invalid

01

10

11

FC[1:0]

00

Settings for Chroma Channel

Minimal Flicker Filtering

01

Slight Flicker Filtering

10

Maximum Flicker Filtering

Enable Chroma DotCrawl Reduction

11

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CH7005C

Register Descriptions (continued)

Symbol: VBW

Video Bandwidth Register

Address: 03H

Bits: 7

Bit:

7

6

5

4

3

2

1

0

FLFF

R/W

0

CVBW

R/W

0

CBW1

R/W

0

CBW0

R/W

0

YPEAK

R/W

0

YSV1

R/W

0

YSV0

R/W

0

YCV

R/W

0

Symbol:

Type:

Default:

This register enables the selection of alternative filters for use in the luma and chroma channels. There are currently

four filter options defined for the chroma channel, 4 filter options in the S-Video luma channel and two filter options

in the composite luma channel. The Table 18 and 19 below show the various settings.

Table 18. Luma Filter Bandwidth

YCV

Luma Composite Video Filter Adjust

Low bandwidth

0

1

High bandwidth

YSV[1:0]

Luma S-Video Filter Adjust

00

Low bandwidth

01

Medium bandwidth

10

High bandwidth

11

Reserved (decode this and handle the same as 10)

Disables the Y-peaking circuit

Disables the peaking filter in luma S-Video channel

Enables the peaking filter in luma S-Video channel

YPEAK

0

1

Table 19. Chroma Filter Bandwidth

CBW[1:0]

0 0

Chroma Filter Adjust

Low bandwidth

0 1

Medium bandwidth

Med-high bandwidth

High bandwidth

1 0

1 1

Bit 6 (CVBW) outputs the S-Video luma signal on both the S-Video luma output and the CVBS output. A "1" in this

location enables the output of a black and white image on composite, thereby eliminating the degrading effects of

the color signal (such as dot crawl or false colors), which is useful for viewing text with high accuracy.

Bit 7 (FLFF) controls the flicker filter used in the 7/10’s scaling modes. In these scaling modes, setting FLFF to 1

causes a five line flicker filter to be used. The default setting of 0 uses a four line flicker filter.

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CHRONTEL

CH7005C

Register Descriptions (continued)

Input Data Format Register

Symbol: IDF

Address: 04H

Bits: 7

Bit:

7

6

5

4

3

2

1

0

DACG

RGBBP

IDF3

IDF2

IDF1

IDF0

Symbol:

Type:

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Default:

This register sets the variables required to define the incoming pixel data stream.

Table 20. Input Data Format

IDF[3:0]

0000

Description

16-bit non-multiplexed RGB (16-bit color, 565) input

0001

16-bit non-multiplexed YCrCb (24-bit color) input (Y non-multiplexed, CrCb multiplexed)

16-bit multiplexed RGB (24-bit color) input

0010

0011

15-bit non-multiplexed RGB (15-bit color, 555) input

0100

12-bit multiplexed RGB (24-bit color) input (“C” multiplex scheme)

12-bit multiplexed RGB2 (24-bit color) input (“I” multiplex scheme)

8-bit multiplexed RGB (24-bit color, 888) input

0101

0110

0111

8-bit multiplexed RGB (16-bit color, 565) input

1000

8-bit multiplexed RGB (15-bit color, 555) input

1001-1111

8-bit multiplexed YCrCb (24-bit color) input (Y, Cr and Cb are multiplexed)

RGBBP (bit 5): Setting this bit enables the RGB pass-through mode. Setting this bit to a 1 causes the input RGB

signal to be directly output at the DACs (subject to a pipeline delay). If RGBBP=0, the bypass mode is disabled.

DACG (bit 6): This bit controls the gain of the D/A converters. When DACG=0, the nominal DAC current is 71

mA, which provides the correct levels for NTSC and PAL-M. When DACG=1, the nominal DAC current is 76mA,

which provides the correct levels for PAL and NTSC-J.

Clock Mode Register

Symbol: CM

Address: 06H

Bits: 8

Bit:

7

6

5

4

3

2

1

0

CFRB

R/W

0

M/S*

R/W

0

Reserved

MCP

R/W

1

XCM1

R/W

0

XCM0

R/W

0

PCM1

R/W

0

PCM0

R/W

0

Symbol:

Type:

R/W

0

Default:

The setting of the clock mode bits determines the clocking mechanism used in the CH7005. The clock modes are

shown in the table below. PCM controls the frequency of the pixel clock, and XCM identifies the frequency of the

XCLK input clock.

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CH7005C

Register Descriptions (continued)

Note: For what was formerly defined as the master mode, the user must now externally connect the P-OUT clock to the

XCLK input pin. Although it is possible to set the XCM [1:0] and PCM[1:0] values independent of the input data format,

there are only certain combinations of input data format, XCM and PCM, that will result in valid data being demultiplexed

at the input of the device. Refer to the “Input Data Format Register” for these combinations.

Note: Display modes 25 and 26 must use a 2X multiplexed input data format and a 2X XCLK. Display modes 27

and 28 must use a 1X XCLK input data format.

Table 21. Input Data Format Register

XCM[1:0]

PCM[1:0]

XCLK

1X

P-OUT

1X

Input Data Modes Supported

0, 1, 2, 3, 4, 5, 7, 8, 9

2, 4, 5, 7, 8, 9

00

01

1X

00

01

1X

00

01

1X

00

01

1X

2X

1X

3X

2X

1X

2X

2, 4, 5, 7, 8, 9

2X

3X

2, 4, 5, 7, 8, 9

3X

1X

6

3X

2X

3X

The Clock Mode Register also contains the following bits:

•

MCP (bit 4) determines which edge of the pixel clock output will be used to latch input data. Zero selects the

negative edge, one selects the positive edge.

•

M/S* (bit 6) determines whether the device operates in master or slave clock mode. In master mode (1), the

14.31818MHz clock is used as a frequency reference to the PLL. In slave mode (0) the XCLK input is used as

a reference to the PLL, and is divided by the value specified by XCM[1:0]. The divide by N and M are forced

to one.

•

CFRB (bit 7) sets whether the chroma subcarrier free-runs, or is locked to the video signal. One causes the

subcarrier to lock to the TV vertical rate, and should be used when the ACIV bit is set to zero. Zero causes the

subcarrier to free-run, and should be used when the ACIV bit is set to one.

Start Active Video Register

Symbol: SAV

Address: 07H

Bits: 8

Bit:

7

6

5

4

3

2

1

0

SAV7

R/W

0

SAV6

R/W

0

SAV5

R/W

0

SAV4

R/W

0

SAV3

R/W

0

SAV2

R/W

0

SAV1

R/W

0

SAV0

R/W

0

Symbol:

Type:

Default:

This register sets the delay in pixel increments from leading edge of horizontal sync, or the rising edge of data start,

to the start of active video. The entire bit field SAV[8:0] is comprised of this register SAV[7:0], plus the MSB value

contained in the position overflow register, bit SAV8. This is decoded as a whole number of pixels, which can be set

anywhere between 0 and 511 pixels. Therefore, in any 2X clock mode, the number of 2X clocks from the leading

edge of sync to the first active data must be a multiple of two clocks. In any 3X clock mode, the number of 3X

clocks from the leading edge of sync to the first active data must be a multiple of three clocks. When using the

DS/BCO pin as a data start input, this register should be set to decimal value 11.

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CHRONTEL

CH7005C

Register Descriptions (continued)

Position Overflow Register

Symbol: PO

Address: 08H

Bits: 3

Bit:

7

6

5

4

3

2

1

0

SAV8

HP8

VP8

Symbol:

Type:

R/W

0

R/W

0

R/W

0

Default:

This position overflow register contains the MSB values for the SAV, HP, and VP values, as follows:

•

VP8 (bit 0) is the MSB of the vertical position value (see explanation under “Vertical Position Register”).

HP8 (bit 1) is the MSB of the horizontal position value (see explanation under “Horizontal Position

Register”).

•

SAV8 (bit 2) is the MSB of the start of active video value (see explanation under “Start Active Video

Register”).

Black Level Register

Symbol: BLR

Address: 09H

Bits: 8

Bit:

7

6

5

4

3

2

1

0

BL7

R/W

0

BL6

R/W

1

BL5

R/W

1

BL4

R/W

1

BL3

R/W

1

BL2

R/W

1

BL1

R/W

1

BL0

R/W

1

Symbol:

Type:

Default:

This register sets the black level. The luminance data is added to this black level, which must be set between 90 and

208, with the default value being 127. Recommended values for NTSC and PAL-M are 127, 105 for PAL and 100

for NTSC-J.

Horizontal Position Register

Symbol: HPR

Address: 0AH

Bits: 8

Bit:

7

6

5

4

3

2

1

0

HP7

HP6

HP5

HP4

HP3

HP2

HP1

HP0

Symbol:

Type:

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Default:

The horizontal position register is used to shift the displayed TV image in a horizontal direction (left or right) to

achieve a horizontally centered image on screen. The entire bit field, HP[8:0] is comprised of this register HP[7:0]

plus the MSB value contained in the position overflow register, bit HP8. Increasing this value moves the displayed

image position RIGHT; decreasing this value moves the displayed image position LEFT. Each increment moves the

image position by 4 input pixels.

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Register Descriptions (continued)

Vertical Position Register

Symbol: VPR

Address: 0BH

Bits: 8

Bit:

7

6

5

4

3

2

1

0

VP7

VP6

VP5

VP4

VP3

VP2

VP1

VP0

Symbol:

Type:

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Default:

This register is used to shift the displayed TV image in a vertical direction (up or down) to achieve a vertically cen-

tered image on screen. This bit field, VP[8:0] represents the TV line number (relative to the VGA vertical sync)

used to initiate the generation and insertion of the TV vertical interval (i.e., the first sequence of equalizing pulses).

Increasing values delay the output of the TV vertical sync, causing the image position to move UP on the TV screen.

Decreasing values, therefore, move the image position DOWN. Each increment moves the image position by one

TV lines (approximately 4 input lines). The maximum value that should be programmed into the VP[8:0] value is

the number of TV lines minus one, divided by two (262, 312 or 313). When panning the image up, the number

should be increased until (TVLPF-1) /2 is reached; the next step should be to reset the register to zero. When pan-

ning the image down the screen, the VP[8:0] value should be decremented until the value zero is reached. The next

step should set the register to (TVLPF-1) /2, and then decrementing can continue. If this value is programmed to a

number greater than (TV lines per frame-1) /2, a TV vertical SYNC will not be generated.

Sync Polarity Register

Symbol: SPR

Address: 0DH

Bits: 4

Bit:

7

6

5

4

3

2

1

0

DES

SYO

VSP

HSP

Symbol:

Type:

R/W

0

R/W

0

R/W

0

R/W

0

Default:

This register provides selection of the synchronization signal input to, or output from, the CH7005.

•

HSP (bit 0) is Horizontal Sync Polarity - an HSP value of zero means the horizontal sync is active low and a

value of one means the horizontal sync is active high.

VSP (bit 1) is Vertical Sync Polarity - a VSP value of zero means the vertical sync is active low and a value of

one means the vertical sync is active high.

SYO (bit 2) is Sync Direction - a SYO value of zero means that H and V sync are input to the CH7005. A

value of one means that H and V sync are output from the CH7005.

DES (bit 3) is Detect Embedded Sync - a DES value of zero means that H and V sync will be obtained from

the direct pin inputs. A DES value of one means that H and V sync will be detected from the embedded codes

on the pixel input stream. Note that this will only be valid for the YCrCb input modes.

Note: When sync direction is set to be an output, horizontal sync will use a fixed pulse width of 64 pixels and vertical

sync will use a fixed pulse width of 1 line.

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37

CHRONTEL

CH7005C

Register Descriptions (continued)

Power Management Register

Symbol: PMR

Address: 0EH

Bits: 5

Bit:

7

6

5

4

3

2

1

0

SCART

Reset*

PD2

PD1

PD0

Symbol:

Type:

R/W

0

R/W

1

R/W

0

R/W

1

R/W

1

Default:

This register provides control of the power management functions, a software reset (ResetB), and the SCART output

enable. The CH7005 provides programmable control of its operating states, as described in the table below.

Table 22. Power Management

PD[2:0]

Operating State

Composite Off

Power Down

Functional Description

CVBS DAC is powered down

000

001

Most pins and circuitry are disabled (except for the buffered clock outputs

which are limited to the 14MHz output and VCO divided output when the

DS/BCO pin is selected to be an output).

010

011

S-Video Off

S-Video DACs are powered down

All circuits and pins are active.

Normal (On)

2

1XX

Full Power Down

All circuitry is powered down, except I C circuit.

Reset* (bit 3) is soft reset. Setting this bit to 0 will reset all circuitry requiring a power on reset, except for this bit

2

itself and the I C state machines. After reset, this bit should be set back to 1 for normal operation to continue.

SCART (bit 4) is the SCART enable. Setting SCART = 0 means the CH7005 will operate normally, outputting Y/C

and CVBS from the three DACs. SCART=1 enables SCART output, which will cause R, G and B to be output from

the DACs and composite sync from the CSYNC pin.

Note: For complete details regarding the operation of these modes, see the Power Management in Functional Description

sections.

Connection Detect Register

Symbol: CDR

Address: 10H

Bits: 4

Bit:

7

6

5

4

3

2

1

0

YT

R

0

CT

R

CVBST

SENSE

Symbol:

Type:

R

0

W

0

Default:

The Connection Detect Register provides a means to sense the connection of a TV to either S-Video or Composite

video outputs. The status bits, YT, CT, and CVBST correspond to the DAC outputs for S-Video (Y and C outputs)

and Composite video (CVBS), respectively. However, the values contained in these status bits are NOT VALID

until a sensing procedure is performed. Use of this register requires a sequence of events to enable the sensing of

outputs, then reading out the applicable status bits. The detection sequence works as follows:

1. Ensure the power management register Bits 2-0 is set to 011(normal mode).

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CH7005C

Register Descriptions (continued)

2. Set the SENSE bit to a 1. This forces a constant current output onto the Y, C, and CVBS outputs. Note that

during SENSE = 1, these 3 analog outputs are at steady state and no TV synchronization pulses are asserted.

3. Reset the SENSE bit to 0. This triggers a comparison between the voltage sensed on these analog outputs

and the reference value expected (V

= 1.235V). If the measured voltage is below this threshold

threshold

value, it is considered connected, if it is above this voltage it is considered unconnected. During this step,

each of the three status bits corresponding to individual analog outputs will be set if they are NOT

connected.

4. Read the status bits. The status bits, Y, C, and CVBST (corresponding to S-Video Y and C outputs and

composite video) now contain valid information which can be read to determine which outputs are

connected to a TV. Again, a “0” indicates a valid connection, a “1” indicates an unconnected output.

Contrast Enhancement Register

Symbol: CE

Address: 11H

Bits: 3

Bit:

7

6

5

4

3

2

1

0

CE2

CE1

CE0

Symbol:

Type:

R/W

0

R/W

1

R/W

1

Default:

This register provides control of the contrast enhancement feature of the CH7005, according to the table below. At

a setting of 000, the video signal will be pulled towards the maximum black level. As the value of CE[2:0] is

increased, the amount that the signal is pulled towards black is decreased until unity gain is reached at a setting of

011. From this point on, the video signal is pulled towards the white direction, with the effect increasing with

increasing settings of CE[2:0].

Table 23. Contrast Enhancement Function

CE[2:0]

000

Description (all gains limited to 0-255)

Contrast enhancement gain 3 Y = (5/4)*(Y -102) = Enhances Black

out

in

001

Contrast enhancement gain 2 Y = (9/8)*(Y -57)

out in

010

Contrast enhancement gain 1 Y = (17/16)*(Y -30)

out in

011

Normal mode Y = (1/1)*(Yin-0) = Normal Contrast

out

100

Contrast enhancement gain 1 Y = (17/16)*(Y -0)

out in

101

Contrast enhancement gain 2 Y = (9/8)*(Y -0)

out in

110

Contrast enhancement gain 3 Y = (5/4)*(Y -0)

out in

111

Contrast enhancement gain 4 Y = (3/2)*(Y -0) = Enhances White

out in

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CHRONTEL

CH7005C

Register Descriptions (continued)

256

224

192

160

128

96

64

32

0

32

64

96

128

160

192

224 256

Figure 26: Luma Transfer Function at different contrast enhancement settings.

PLL Overflow Register

Symbol: MNE

Address: 13H

Bits: 5

Bit:

7

6

5

4

3

2

1

0

Reserved

N9

R/W

0

N8

R/W

0

M8

R/W

0

Symbol:

Type:

R/W

0

R/W

0

Default:

The PLL Overflow Register contains the MSB bits for the ‘M’ and ‘N’ values, which will be described in the PLL-

M and PLL-N registers, respectively. The reserved bits should not be written to.

PLL M Value Register

Symbol: PLLM

Address: 14H

Bits: 8

Bit:

7

6

5

4

3

2

1

0

M7

R/W

0

M6

R/W

1

M5

R/W

0

M4

R/W

0

M3

R/W

0

M2

R/W

0

M1

R/W

0

M0

R/W

1

Symbol:

Type:

Default:

The PLL M value register determines the division factor applied to the frequency reference clock before it is input to

the PLL phase detector when the CH7005 is operating in master or pseudo-master clock mode. In slave mode, an

external pixel clock is used instead of the frequency reference, and the division factor is determined by the

XCM[3:0] value. This register contains the lower 8 bits of the complete 9-bit M value.

40

201-0000-025 Rev 2.1, 8/2/99

CHRONTEL

Register Descriptions (continued)

CH7005C

PLL N Value Register

Symbol: PLLN

Address: 15H

Bits: 8

Bit:

7

6

5

4

3

2

1

0

N7

R/W

1

N6

R/W

0

N5

R/W

0

N4

R/W

0

N3

R/W

0

N2

R/W

0

N1

R/W

0

N0

R/W

0

Symbol:

Type:

Default:

The PLL N value register determines the division factor applied to the VCO output before being applied to the PLL

phase detector, when the CH7005 is operating in master or pseudo-master mode. In slave mode, the value of ‘N’ is

always 1. This register contains the lower 8 bits of the complete 10-bit N value. The pixel clock generated in a

master and pseudo-master modes is calculated according to the equation below:

Fpixel = Fref* [(N+2) / (M+2)]

When using a 14.318 MHz frequency reference, the required M and N values for each mode are shown in the table

below

Table 24. M and N Values for Each Mode

Mode

VGA Resolution, TV

Standard, Scaling Ratio

N 10-

bits

M 9-

bits

Mode

VGA Resolution, TV

Standard, Scaling Ratio

N 10-

bits

M 9-

bits

15

16

17

18

19

20

21

22

23

24

25

26

27

28

640X480, PAL, 5:6

640X480, NTSC, 1:1

640X480, NTSC, 7:8

640X480, NTSC, 5:6

800X600, PAL, 1:1

800X600, PAL, 5:6

800X600, PAL, 3:4

800X600, NTSC, 5:6

800X600, NTSC, 3:4

800X600, NTSC, 7:10

720X576, PAL, 1:1

720X480, NTSC, 1:1

800X500, PAL, 1:1

640X400, NTSC, 1:1

9

3

63

89

313

33

103

33

19

89

33

197

2

0

1

512x384, PAL, 5:4

512x384, PAL, 1:1

512X384, NTSC, 5:4

512X384, NTSC, 1:1

720X400, PAL, 5:4

720X400, PAL, 1:1

720X400, NTSC, 5:4

720X400, NTSC, 1:1

640X400, PAL, 5:4

640X400, PAL, 1:1

640X400, NTSC, 5:4

640x400, NTSC, 1:1

640X400, NTSC, 7:8

640X480, PAL, 5:4

640X480, PAL, 1:1

20

9

13

4

110

126

190

647

86

89

63

26

138

63

33

61

3

2

126

110

53

3

4

5

339

106

70

284

94

6

7

62

8

108

9

302

31

9

63

11

89

13

4

10

11

12

13

14

94

31

22

242

2

190

20

9

Buffered Clock Output Register

Symbol: BCO

Address: 17H

Bits: 6

Bit:

7

6

5

4

3

2

1

0

SHF2

SHF1

R/W

0

SHF0

SCO2

SCO1

SCO0

R/W

0

Symbol:

Type:

R/W

0

R/W

0

R/W

0

R/W

0

Default:

When this pin is selected to be an output, the buffered clock output register determines which clock is selected to be

output at the DS/BCO clock output pin and what frequency value is output when a VCO derived signal is out-

put.The tables below show the possible outputs.

201-0000-025 Rev 2.1, 8/2/99

41

CHRONTEL

CH7005C

Register Descriptions (continued)

Table 25. Clock Output Selection

SCO[2:0]

000

Buffered Clock Output

14MHz crystal

001

(for test use only)

010

VCO divided by K3 (see Table 26)

Field ID signal

011

100

(for test use only)

101

(for test use only)

110

TV horizontal sync (for test use only)

TV vertical sync (for test use only)

111

Table 26. K3 Selection

SHF[2:0]

000

K3

2.5

3.5

4

010

011

100

4.5

5

101

110

6

111

7

Subcarrier Value Registers

Symbol: FSCI

Address: 18H - 1FH

Bits: 4 or 8 each

Bit:

7

6

5

4

3

2

1

0

FSCI#

R/W

FSCI#

R/W

FSCI#

R/W

FSCI#

R/W

Symbol:

Type:

Default:

The lower four bits of registers 18H through 1FH contain a 32-bit value which is used as an increment value for the

ROM address generation circuitry. The bit locations are specified as the following:

Register

18H

19H

1AH

1BH

1CH

1DH

1EH

Contents

FSCI[31:28]

FSCI[27:24]

FSCI[23:20]

FSCI[19:16]

FSCI[15:12]

FSCI[11:8]

FSCI[7:4]

1FH

FSCI[3:0]

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201-0000-025 Rev 2.1, 8/2/99

CHRONTEL

Register Descriptions (continued)

CH7005C

When the CH7005 is operating in the master clock mode, the tables below should be used to set the FSCI registers.

When using these values, the ACIV bit in register 21H should be set to “0” and the CFRB bit in register 06H should

be set to “1”.

Table 27. FSCI Values (525-Line Modes)

NTSC

“Normal Dot Crawl”

NTSC

“No Dot Crawl”

PAL-M

“Normal Dot Crawl

Mode

2

763,363,328

623,153,737

574,429,782

463,962,517

646,233,505

516,986,804

452,363,454

623,153,737

545,259,520

508,908,885

521,957,831

469,762,048

428,554,851

569,408,543

1,073,741,824

763,366,524

623,156,346

574,432,187

463,964,459

646,236,211

5165,988,968

452,365,347

623,156,346

545,261,803

508,911,016

521,960,016

469,764,015

438,556,645

569,410,927

1,073,746,319

762,524,467

622,468,953

573,798,541

463,452,668

645,523,358

516,418,687

451,866,351

622,468,953

544,660,334

508,349,645

521,384,251

469,245,826

428,083,911

568,782,819

1,072,561,888

3

6

7

10

11

12

16

17

18

22

23

24

26

28

Table 28. FSCI Values (625-Line Modes)

PAL

PAL-N

Mode

0

“Normal Dot Crawl”

806,021,060

644,816,848

601,829,058

485,346,014

677,057,690

537,347,373

806,021,060

644,816,848

537,347,373

645,499,916

528,951,320

488,262,757*

705,268,427

1,073,747,879

“Normal Dot Crawl”

651,209,077

520,967,262

486,236,111

392,125,896

547,015,625

434,139,385

651,209,077

520,967,262

434,139,385

521,519,134

427,355,957

394,482,422

569,807,942

867,513,766

1

4

5

8

9

13

14

15

19

20

21

25

27

When the CH7005 is operating in the slave clock mode, the ACIV bit in register 21H should be set to “1” and the

CFRB bit in register 06H should be set to “0”.

*Note: For reduced corss-color and cross-luminance artifacts, a value of 488,265,597 can be used with CFRB = "0"

& ACIV = "0".

201-0000-025 Rev 2.1, 8/2/99

43

CHRONTEL

CH7005C

Register Descriptions (continued)

Symbol:

Address: 1BH

Bits: 8

Bit:

7

6

5

4

3

2

1

0

P-OUTP

R/W

0

FSCI19

R/W

0

FSCI18

R/W

0

FSCI17

R/W

0

FSCI16

R/W

0

Symbol:

Type:

Default:

Note: P-OUTP (bit 4) is used to invert the P-OUT signal.

Symbol:

Address: 1CH

Bits: 6

Bit:

7

6

5

4

3

2

1

0

DSEN

FSCI15

FSCI14

FSCI13

FSCI12

Symbol:

Type:

R/W

1

R/W

0

R/W

0

R/W

0

R/W

0

Default:

Note: DSEN (bit4) controls the BCO / Data Start I/O pin. When this bit is low, the pin continues to operate as the BCO

pin described in the BCO register description. When this bit is high, the pin becomes an input for the Data Start signal.

PLL Control Register

Symbol: PLLC

Address: 20H

Bits: 6

Bit:

7

6

5

4

3

2

1

0

PLLCPI

R/W

0

PLLCAP

R/W

0

PLLS

R/W

1

PLL5VD

R/W

0

PLL5VA

R/W

1

MEM5V

R/W

0

Symbol:

Type:

Default:

The following PLL and memory controls are available through the PLL control register:

MEM5V

PLL5VA

PLL5VD

PLLS

MEM5V is set to 1 when the memory supply is 5 volts. The default value of 0 is used when the

memory supply is 3.3 volts.

PLL5VA is set to 1 when the phase-locked loop analog supply is 5 volts (default). A value of 0 is

used when the phase-locked loop analog supply is 3.3 volts.

PLL5VD is set to 1 when the phase-locked loop digital supply is 5 volts. A value of 0 is used when

the phase-locked loop digital supply is 3.3 volts (default).

PLLS controls the number of stages used in the PLL. When the PLL5VA is 1 (5V analog PLL

supply) PLLS should be 1, and seven stages are used. When PLL5VA is 0 (3.3V analog PLL

supply) PLLS should be 0, and five stages are used.

PLLCAP

PLLCPI

PLLCAP controls the loop filter capacitor of the PLL. A recommended listing of PLLCAP vs.

Mode is shown below

PLLCHI controls the charge pump current of the PLL. The default value should be used.

44

201-0000-025 Rev 2.1, 8/2/99

CHRONTEL

CH7005C

Register Descriptions (continued)

Table 29. PLL Capacitor Setting

Mode

PLLCAP

Value

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

201-0000-025 Rev 2.1, 8/2/99

45

CHRONTEL

CH7005C

Register Descriptions (continued)

CIV Control Register

Symbol: CIVC

Address: 21H

Bits: 5

Bit:

7

6

5

4

3

2

1

0

CIV25

CIV24

CIVH1

R/W

0

CIVH0

R/W

0

ACIV

R/W

1

Symbol:

Type:

R

0

R

0

Default:

The following controls are available through the CIV control register:

ACIV

When the automatic calculated increment value is 1, the number calculated and present at the CIV

registers will automatically be used as the increment value for subcarrier generation, removing the

need for the user to read the CIV value and write in a new FSCI value. Whenever this bit is set to

1, the subcarrier generation must be forced to free-run mode.

These bits control the hysteresis circuit which is used to calculate the CIV value.

See descriptions in the next section.

CIVH[1:0]

CIV[25:24]

Calculated Increment Value Register

Symbol: CIV

Address: 22H - 24H

Bits: 8

Bit:

7

6

5

4

3

2

1

0

CIV#

Symbol:

Type:

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

Default:

The CIV registers 22H through 24H contain a 26-bit value, which is the calculated increment value that should be

used as the upper 26 bits of FSCI. This value is determined by a comparison of the pixel clock and the 14MHz

clock. The bit locations and calculation of CIV are specified as the following:

Register

21H

22H

23H

24H

Contents

CIV[25:24]

CIV[23:16]

CIV[15:8]

CIV[7:0]

Version ID Register

Symbol: VID

Address: 25H

Bits: 8

Bit:

7

6

5

4

3

2

1

0

VID7

VID6

R

VID5

R

VID4

R

VID3

R

VID2

R

VID1

R

VID0

R

Symbol:

Type:

R

0

1

0

1

0

Default:

This read-only register contains a 8-bit value indicating the identification number assigned to this version of the

CH7005. The default value shown is pre-programmed into this chip and is useful for checking for the correct

version of this chip, before proceeding with its programming.

46

201-0000-025 Rev 2.1, 8/2/99

CHRONTEL

CH7005C

Register Descriptions (Continued)

Address Register

Symbol: AR

Address: 3FH

Bits: 6

Bit:

7

6

5

4

3

2

1

0

AR5

AR4

AR3

AR2

AR1

AR0

Symbol:

Type:

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

Default:

The Address Register points to the register currently being accessed.

Electrical Specifications

Table 30. Absolute Maximum Ratings

Symbol

Description

relative to GND

Min

- 0.5

Typ

Max

Units

V

7.0

V

DD

1

Input voltage of all digital pins

GND - 0.5

VDD + 0.5

Analog output short circuit duration

Ambient operating temperature

Storage temperature

T

Indefinite

Sec

° C

SC

T

- 55

- 65

125

150

220

AMB

TSTOR

TJ

Junction temperature

Vapor phase soldering (one minute)

TVPS

Notes:

1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the

device. These are stress ratings only. Functional operation of the device at these or any other conditions

above those indicated under the normal operating condition of this specification is not recommended.

Exposure to absolute maximum rating conditions for extended periods my affect reliability.

2. The device is fabricated using high-performance CMOS technology. It should be handled as an

ESDsensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5V

can induce destructive latch.

Table 31. Recommended Operating Conditions

Symbol

VDD

Description

DAC power supply voltage

Min

Typ

5.00

3.3

Max

5.25

3.6

Units

4.75

V

AVDD

DVDD

RL

Analog supply voltage

Digital supply voltage

Output load to DAC outputs

37.5

W

201-0000-025 Rev 2.1, 8/2/99

47

CHRONTEL

CH7005C

o

Table 32. Electrical Characteristics (Operating Conditions: TA = 0 C - 70 C, VDD = 5V ± 5%)

Symbol

Description

Video D/A resolution

Min

Typ

9

Max

Unit

Bits

mA

%

9

Full scale output current

Video level error

33.89

10

VDD & AVDD (5V) current (simultaneous

S-Video & composite outputs)

105

40

mA

DVDD (3.3V) current

mA

Note: RSET = 360 W, VREF = 1.235V, and NTSC CCIR601 operation.

Table 33. Timing - TV Encoder

Symbol

Description

Pixel Clock Period

Min

Typ

Max

Unit

t

20

8

50

25

60

25

nS

P1

PH1

Pixel Clock High Time

Pixel Clock Duty Cycle (t

Pixel Clock Period

nS

%

tdc1

/t

)

40

10

50

PH1 P1

t

nS

%

P2

Pixel Clock High Time

Pixel Clock Duty Cycle (t

Pixel Clock Period

PH2

tdc2

/t

)

40

10

60

17

PH2 P2

t

nS

%

P3

Pixel Clock High Time

Pixel Clock Duty Cycle (t

PH3

tdc3

/t

)

40

60

PH3 P3

Table 34. Digital Inputs / Outputs

Symbol

Description

SD Output

Test Condition

IOL = 2.0 mA

Min

Typ

Max

Unit

V

0.4

V

SDOL

Low Voltage

SD Input

V

2.7

VDD + 0.5

1.4

V

IICIH

High Voltage

SD Input

V

GND-0.5

2.5

IICIL

Low Voltage

D[0-15] Input

High Voltage

D[0-15] Input

Low Voltage

P-OUT Output

High Voltage

P-OUT Output

Low Voltage

V

DVDD+0.5

0.8

DATAIH

V

GND-0.5

2.8

DATAIL

V

IOL = - 400 mA

P-OUTOH

V

IOL = 3.2 mA

0.2

P-OUTOL

Note:

1. V_IIC-refers to I2C pins SD and SC.

2. V_DATA- refers to all digital pixel and clock inputs.

3. V_SD- refers to I2C pin SD as an output.

4. V_P-OUT- refers to pixel data output Time - Graphics.

48

201-0000-025 Rev 2.1, 8/2/99

CHRONTEL

CH7005C

Table 35. Timing Graphics

Symbol

Description

Min

Typ

Max

17

Unit

t

Horizontal Sync Pulse Width

1

2

t

p

HSW

t

Pixel Clock to Horizontal Leading Edge Delay

Setup time from Pixel Data to Pixel Clock

nS

HD

t

SP1, SP2, SP3

t

Hold time from Pixel Clock to Pixel Data

2

nS

PH1, HP2, PH3

ORDERING INFORMATION

Part number

CH7005C-V

CH7005C-T

Package type

Number of pins

Voltage supply

3V/5V

PLCC

44

TQFP

3V/5V

Chrontel

2210 O’Toole Avenue

San Jose, CA 95131-1326

Tel: (408) 383-9328

Fax: (408) 383-9338

www.chrontel.com

E-mail: sales@chrontel.com

Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE

SPECIFIC WRITTEN CONSENT OF Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used as directed can reasonably

expect to result in personal injury or death. Chrontel reserves the right to make changes at any time without notice to improve and supply the best possible product and is not

responsible and does not assume any liability for misapplication or use outside the limits specified in this document. We provide no warranty for the use of our products and assume no

liability for errors contained in this document. Printed in the U.S.A.

201-0000-025 Rev 2.1, 8/2/99

49


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