CH7007A-T [ETC]
DIGITAL PC TO TV ENCODER WITH MACROVISION; 数码电脑使用Macrovision电视编码器型号: | CH7007A-T |
厂家: | ETC |
描述: | DIGITAL PC TO TV ENCODER WITH MACROVISION |
文件: | 总49页 (文件大小:277K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CH7007A
Digital PC to TV Encoder with MacrovisionTM
CHRONTEL
Features
General Description
• Supports MacrovisionTM 7.X anti-copy protection
• Support for low voltage interface to VGA controller
Chrontel’s CH7007 digital PC to TV encoder is a stand-
alone integrated circuit which provides a PC 99 compliant
solution for TV output. Suggested application use with the
Intel 810 chipset and Intel 810E chipset.* It provides a
universal digital input port to accept a pixel data stream
from a compatible VGA controller (or equivalent) and
converts this directly into NTSC or PAL TV format.
• Universal digital interface accepts YCrCb (CCIR656)
or RGB (15, 16 or 24-bit multiplexed) video data in
both non-interlaced and interlaced formats
• TrueScale TM rendering engine supports underscan
operations for various graphic resolutions† ¥
• Enhanced text sharpness and adaptive flicker removal
with up to 5-lines of filtering†
• Enhanced dot crawl control and area reduction
• Fully programmable through I2C port
This circuit integrates a digital NTSC/PAL encoder with
9-bit DAC interface, and new adaptive flicker filter, and
high accuracy low-jitter phase locked loop to create
outstanding quality video. Through its TrueScaleTM
scaling and deflickering engine, the CH7007 supports full
vertical and horizontal underscan capability and operates
in 5 different resolutions including 640x480 and 800x600.
• Supports NTSC, NTSC-EIA (Japan), and PAL (B, D,
G, H, I, M and N) TV formats
A new universal digital interface along with full
programmability make the CH7007 ideal for system-level
PC solutions. All features are software programmable
• Provides Composite, S-Video and SCART outputs
• Auto-detection of TV presence
2
through a standard IC port, to enable a complete PC
• Programmable power management
• 9-bit video DAC outputs
solution using a TV as the primary display.
• Complete Windows and DOS driver software
• Offered in 44-pin PLCC, 44-pin TQFP
† Patent number 5,781,241
¥ Patent number 5,914,753
LINE
YUV-RGB CONVERTER
MEMORY
RGB-YUV
CONVERTER
TRUE SCALE
DIGITAL
Y/R
SCALING &
DEFLICKERING
NTSC/PAL
ENCODER
& FILTERS
D[11:0]
TRIPLE
DAC
INPUT
ENGINE
C/G
INTERFACE
PIXEL DATA
CVBS/B
ISET
SYSTEM CLOCK
I2C REGISTER &
CONTROL BLOCK
TIMING & SYNC
GENERATOR
GPIO[1:0]
PLL
SC
SD
RESET*
XCLK*
H
XO
DS/BCO
CSYNC P-OUT
V
XI/FIN
Figure 1: Functional Block Diagram
201-0000-002 Rev. 2.7, 08/23/2000 *Intel 810 and Intel 810E are Trademarks of Intel Corp
1
CHRONTEL
CH7007A
D[1]
D[2]
7
39
38
37
36
35
34
33
32
31
30
29
XO
8
XI/FIN
AVDD
DVDD
RESET*
DGND
SC
D[3]
9
D[4]
10
11
12
13
14
15
16
17
DVDD
D[5]
CHRONTEL
CH7007
D[6]
DGND]
D[7]
SD
VDD
ISET
GND
D[8]
D[9]
Figure 2: 44-Pin PLCC
2
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CHRONTEL
CH7007A
D[1]
D[2]
D[3]
D[4]
1
33
32
31
30
29
28
27
26
25
24
23
XO
2
XI/FIN
AVDD
DVDD
RESET*
DGND
SC
3
4
DVDD
D[5]
5
CHRONTEL
CH7007
6
D[6]
7
DGND]
D[7]
8
SD
9
VDD
D[8]
10
11
ISET
GND
D[9]
Figure 3: 44-Pin TQFP
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CHRONTEL
CH7007A
Table 1. Pin Descriptions
44-Pin
PLCC
44-Pin
TQFP
Type
Symbol
Description
1
2
39
40
Reference Voltage Input
In/Out
VREF
The VREF pin inputs a reference voltage of DVDD2/2. The signal is
derived externally through a resistor divider and decoupling capacitor,
and will be used as a reference level for data and sync inputs.
External Clock Input
In
XCLK
This input along with XCLK* will form a differential clock input. For
applications where a differential clock is not available, the XCLK* pin
should be connected to the VREF pin.
External Clock Input*
3
4
41
42
In
XCLK*
H
See XCLK description
Horizontal Sync Input/Output
In/Out
When the SYO bit is low, this pin accepts a horizontal sync input. The
level is 0 to DVDD2, with VREF as the threshold level.
When the SYO bit is high, the device will output a horizontal sync pulse.
The output is driven from the DVDD supply.
Vertical Sync Input/Output
5
43
In/Out
V
When the SYO bit is low, this pin accepts a vertical sync input. The level
is 0 to DVDD2 with VREF as the threshold level.
When the SYO bit is high, the device will output a vertical sync pulse.
The output is driven from the DVDD supply.
Data [0] through Data [11] Inputs
6-10,12-
13,15-19
44,1-4,6-
7,9-13
In
D[0]-D[11]
These pins accept 12 data inputs from the graphics controller. The level
is 0 to DVDD2, with VREF as the threshold level.
General Purpose Input/Output [0-1] and Internal pull-up
20-21
14-15
In/Out
GPIO[0]
GPIO[1]
These pins provide general purpose I/O’s controlled via the IIC bus,
registers 1Bh and 1Ch, bits 7 and 6. The internal pull-up is to the DVDD
supply.
Composite Sync Output
23
17
Out
Out
CSYNC
A 75 W termination resistor with short traces should be attached
between CSYNC and ground for optimum performance. In SCART
mode, this pin outputs the composite sync signal.
Composite Video Output/Blue Output
26
20
CVBS/B
A 75 W termination resistor with short traces should be attached
between CVBS and ground for optimum performance. In normal
operating modes other than SCART, this pin outputs the composite
video signal. In SCART mode, this pin outputs the blue signal.
27
21
Out
C/G
Chroma Output/Green Output
A 75 W termination resistor with short traces should be attached
between C and ground for optimum performance. In normal operating
modes other than SCART, this pin outputs the chroma video signal. In
SCART mode, this pin outputs the green signal.
Luma Output / Red Output
28
30
22
24
Out
Y/R
A 75 W termination resistor with short traces should be attached
between Y and ground for optimum performance. In normal operating
modes other than SCART, this pin outputs the luma video signal. In
SCART mode, this pin outputs the red signal.
Current Set Resistor Input
In
ISET
This pin sets the DAC current. A 360 ohm resistor should be
connected between this pin and GND using short and wide traces.
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CHRONTEL
CH7007A
Table 1. Pin Descriptions
44-Pin
PLCC
44-Pin
TQFP
Type
Symbol
Description
Serial Data Input/Output
32
33
35
26
27
29
In/Out
SD
This pin functions as the serial data pin of the I2C interface port, and
uses the DVDD supply.
(see the I2C Port Operation section for details)
Serial Clock Input
In
In
SC
This pin functions as the serial clock pin of the I2C interface port, and
uses the DVDD supply.
(see the I2C Port Operation section for details)
Reset* Input
RESET*
When this pin is low, the CH7007 is held in the power-on reset
condition. When this pin is high, the device operates normally and reset
2
is controlled through the I C register.
Crystal Input/External Reference Input
38
39
41
32
33
35
In
XI/FIN
XO
A parallel resonance 14.31818MHz crystal should be attached
between this pin and XO. However, an external CMOS clock can be
attached to XI/FIN.
Crystal Output
Out
A parallel resonance 14.31818MHz +20ppm crystal should be
attached between this pin and XI/FIN. However, if an external CMOS
clock is attached to XI/FIN, XO should not be connected.
Data start (input)/Buffered Clock (output)
In/Out
DS/BCO
In normal operating modes, when configured as an input, the rising
edge of this signal identifies the first active pixel of data for each
active line. The level is 0 to DVDD2, with VREF as the threshold level.
When configured as an output this pin provides a buffered clock
output, driven by the DVDD supply. The output clock can be selected
using the BCO register (17th) (see Registers and Programing).
43
37
Out
P-OUT
Pixel Clock Output
This pin provides a pixel clock signal to the VGA controller (adjustable as
1X, 2X and 3X) and is driven from the DVDD2 supply. This clock will only
be provided in master clock modes, and will be tri-stated otherwise, (see
the section on Digital Video Interface and Registers and Programming
for more details). The capacitive loading on this pin should be kept to a
minimum.
Digital Supply Voltage
Digital Ground
11,22,36
5,16,30
Power
Power
DVDD
DGND
14,24,34,
42
8,18,28,
36
DAC
25,29
31
19,23
25
Power
Power
Power
Power
Power
GND
VDD
DAC Supply Voltage
PLL Supply Voltage
PLL Ground
37
31
AVDD
AGND
DVDD2
40
34
I/O SUPPLY VOLTAGE
44
38
Digital supply voltage for the P-OUT
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CHRONTEL
CH7007A
Digital Video Interface
The CH7007 digital video interface provides a flexible digital interface between a computer graphics
controller and the TV encoder IC forming the ideal quality/cost configuration for performing the TV-output
function. This digital interface consists of up to 12 data signals and 4 control signals, all of which are
subject to programmable control through the CH7007 register set. This interface can be configured as 8
or 12-bit inputs operating in multiplexed mode. It will also accept either YCrCb or RGB (15, 16 or 24-bit
color depth) data formats and will accept both non-interlaced and interlaced data formats. A summary of
the input data format modes is as follows:
Table 2. Input Data Formats
Bus
Transfer Mode
Color Space and Depth
Format Reference
Width
8-bit
8-bit
2X-multiplexed
2X-multiplexed
2X-multiplexed
2X-multiplexed
2X-multiplexed
RGB 15-bit
RGB 16-bit
YCrCb (24-bit)
RGB 24
5-5-5 over two bytes
5-6-5 over two bytes
8-bit
Cb,Y0,Cr,Y1,(CCIR656 style)
8-8-8 over two words - ‘C’ version
8-8-8 over two words - ‘I’ version
12-bit
12-bit
RGB 24
The clock and timing signals used to latch and process the incoming pixel data is dependent upon the clock mode.
The CH7007 can operate in either master (the CH7007 generates a pixel frequency which is either returned as a
phase-aligned pixel clock or used directly to latch data), or slave mode (the graphics chip generates the pixel clock).
The pixel clock frequency will change depending upon the active image size (e.g., 640x480 or 800x600), the desired
output format (NTSC or PAL), and the amount of scaling desired. The pixel clock may be requested to be 1X, 2X or
3X the pixel data rate (subject to a 100MHz frequency limitation). In the case of a 1X pixel clock the CH7007 will
automatically use both clock edges, if a multiplexed data format is selected.
Sync Signals: Horizontal and vertical sync signals will normally be supplied by the VGA controller, but may be
selected to be generated by the CH7007. In the case of CCIR656 style input (IDF = 9), embedded sync may also be
used. In each case, the period of the horizontal sync should be equal to the duration of the pixel clock, times the first
value of the (Total Pixels/line x Total Lines/Frame) column of Table13 on page 29 (Display Mode Register 00H
description). The leading edge of the horizontal sync is used to determine the start of each line. The Vertical sync
signal must be able to be set to the second value in the (Total Pixels/Line x Total Lines/Frame) column of Table13
on page 29.
Master Clock Mode: The CH7007 generates a clock signal (output at the P-OUT pin) which will be used by the
VGA controller as a frequency reference. The VGA controller will then generate a clock signal which will be input
via the XCLK input. This incoming signal will be used to latch (and de-multiplex, if required) incoming data. The
XCLK input clock rate must match the input data rate, and the P-OUT clock can be requested to be 1X, 2X or 3X
the pixel data rate. As an alternative, the P-OUT clock signal can also be used as the input clock signal (connected
directly to the XCLK input) to latch the incoming data. If this mode is used, the incoming data must meet setup and
hold times with respect to the XCLK input (with the only internal adjustment being XCLK polarity).
Slave Clock Mode: The VGA controller will generate a clock which will be input to the XCLK pin (no clock signal
will be output on the P-OUT pin). This signal must match the input data rate, must occur at 1X, 2X or 3X the pixel
data rate, and will be used to latch (and de-multiplex if required) incoming data. Also, the graphics IC transmits
back to the TV encoder the horizontal and vertical timing signals, and pixel data, each of which must meet the
specified setup and hold times with respect to the pixel clock.
Pixel Data: Active pixel data will be expected after a programmable numberpixels times the multiplex rate after the
leading edge of Horizontal Sync. In other words, specifying the horizontal back porch value (as a pixel count), plus
horizontal sync width, will determine when the chip will begin to sample pixels.
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CHRONTEL
CH7007A
Input Data Formats
The XCLK and XCLK* signals are used to latch data from the graphics chip. Data can be latched coincident with
the rising edge of XCLK, falling edge of XCLK, or both edges, depending upon register settings of XCM and MCP.
The input data format is shown in Figure4. The Pixel Data bus represents an 8 or 12-bit multiplexed data stream,
which contains either RGB or YCrCb formatted data. In IDF settings of 4, 5, 7, 8 and 9, the input data rate is 2X
pixel clock, and each pair of Pn values (e.g., P0a and P0b) will contain a complete pixel, encoded as shown in the
tables below. When the input is YCrCb, the color-difference data will be transmitted at half the data rate of the lumi-
nance data, with the sequence being set as Cb0, Y0, Cr0, Y1 where Cb0,Y0,Cr0 refers to co-sited luminance and
color-difference samples — and the following Y1 byte refers to the next luminance sample, per CCIR656 standards.
However, the clock frequency is dependent upon the current mode, not 27MHz, as specified in CCIR656.
HS
SAV
(DSEN=0)
DS / BCO
XCLK (XCM=01)
XCLK* (XCM=01)
XCLK (XCM=00)
XCLK* (XCM=00)
D[11:0]
P0a
P0b
P1a
P1b
P2a
P2b
When DSEN=1(bit 4 of register 1Ch), SAV should be set to 11d.
Figure 4: Non-multiplexed Data Transfers
Table 3. RGB 8-bit Multiplexed Mode
IDF#
7
8
Format
RGB 5-6-5
RGB 5-5-5
Pixel#
Bus Data
P0a
P0b
P1a
P1b
P0a
P0b
x
P1a
G1[2]
P1b
x
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
G0[2]
G0[1]
G0[0]
B0[4]
B0[3]
B0[2]
B0[1]
B0[0]
R0[4]
R0[3]
R0[2]
R0[1]
R0[0]
G0[5]
G0[4]
G0[3]
G1[2]
G1[1]
G1[0]
B1[4]
B1[3]
B1[2]
B1[1]
B1[0]
R1[4]
R1[3]
R1[2]
R1[1]
R1[0]
G1[5]
G1[4]
G1[3]
G0[2]
G0[1]
G0[0]
B0[4]
B0[3]
B0[2]
B0[1]
B0[0]
R0[4]
R0[3]
R0[2]
R0[1]
R0[0]
G0[4]
G0[3]
G1[1]
G1[0]
B1[4]
B1[3]
B1[2]
B1[1]
B1[0]
R1[4]
R1[3]
R1[2]
R1[1]
R1[0]
G1[4]
G1[3]
201-0000-002 Rev. 2.7, 08/23/2000
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CHRONTEL
CH7007A
Table 4. RGB 12-bit Multiplexed Mode
IDF#
4
5
Format
12-bit RGB (12-12)
12-bit RGB (12-12)
Pixel#
P0a
P0b
P1a
P1b
P0a
P0b
P1a
P1b
Bus Data
D[11]
D[10]
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
G0[3]
G0[2]
G0[1]
G0[0]
B0[7]
B0[6]
B0[5]
B0[4]
B0[3]
B0[2]
B0[1]
B0[0]
R0[7]
R0[6]
R0[5]
R0[4]
R0[3]
R0[2]
R0[1]
R0[0]
G0[7]
G0[6]
G0[5]
G0[4]
G1[3]
G1[2]
G1[1]
G1[0]
B1[7]
B1[6]
B1[5]
B1[4]
B1[3]
B1[2]
B1[1]
B1[0]
R1[7]
R1[6]
R1[5]
R1[4]
R1[3]
R1[2]
R1[1]
R1[0]
G1[7]
G1[6]
G1[5]
G1[4]
G0[4]
G0[3]
G0[2]
B0[7]
B0[6]
B0[5]
B0[4]
B0[3]
G0[0]
B0[2]
B0[1]
B0[0]
R0[7]
R0[6]
R0[5]
R0[4]
R0[3]
G0[7]
G0[6]
G0[5]
R0[2]
R0[1]
R0[0]
G0[1]
G1[4]
G1[3]
G1[2]
B1[7]
B1[6]
B1[7]
B1[4]
B1[3]
G1[0]
B1[2]
B1[1]
B1[0]
R1[7]
R1[6]
R1[5]
R1[4]
R1[3]
G1[7]
G1[6]
G1[5]
R1[2]
R1[1]
R1[0]
G1[1]
Table 5. YCrCb Multiplexed Mode
IDF#
9
Format
YCrCb 8-bit
Pixel#
P0a
P0b
P1a
P1b
P2a
P2b
P3a
P3b
Bus Data
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
Cb0[7]
Cb0[6]
Cb0[5]
Cb0[4]
Cb0[3]
Cb0[2]
Cb0[1]
Cb0[0]
Y0[7]
Y0[6]
Y0[5]
Y0[4]
Y0[3]
Y0[2]
Y0[1]
Y0[0]
Cr0[7]
Y1[7]
Y1[6]
Y1[5]
Y1[4]
Y1[3]
Y1[2]
Y1[1]
Y1[0]
Cb2[7]
Cb2[6]
Cb2[5]
Cb2[4]
Cb2[3]
Cb2[2]
Cb2[1]
Cb2[0]
Y2[7]
Y2[6]
Y2[5]
Y2[4]
Y2[3]
Y2[2]
Y2[1]
Y2[0]
Cr2[7]
Cr2[6]
Cr2[5]
Cr2[4]
Cr2[3]
Cr2[2]
Cr2[1]
Cr2[0]
Y3[7]
Y3[6]
Y3[5]
Y3[4]
Y3[3]
Y3[2]
Y3[1]
Y3[0]
Cr0[6]
Cr0[5]
Cr0[4]
Cr0[3]
Cr0[2]
Cr0[1]
Cr0[0]
8
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CH7007A
When IDF = 9, (YCrCb 8-bit mode), H and V sync signals can be embedded into the data stream. In this mode, the
embedded sync will be similar to the CCIR656 convention, and the first byte of the ‘video timing reference code’
will be assumed to occur when a Cb sample would occur – if the video stream was continuous. This is delineated in
Table 6 shown below.
Table 6. YCrCb Multiplexed Mode with Embedded Syncs
IDF#
9
Format
YCrCb 8-bit
Pixel#
Bus Data
P0a
1
1
1
1
1
1
1
1
P0b
0
0
0
0
0
0
0
0
P1a
0
0
0
0
0
0
0
0
P1b
P2a
P2b
P3a
P3b
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
S[7]
S[6]
S[5]
S[4]
S[3]
S[2]
S[1]
S[0]
Cb2[7]
Cb2[6]
Cb2[5]
Cb2[4]
Cb2[3]
Cb2[2]
Cb2[1]
Cb2[0]
Y2[7]
Y2[6]
Y2[5]
Y2[4]
Y2[3]
Y2[2]
Y2[1]
Y2[0]
Cr2[7]
Cr2[6]
Cr2[5]
Cr2[4]
Cr2[3]
Cr2[2]
Cr2[1]
Cr2[0]
Y3[7]
Y3[6]
Y3[5]
Y3[4]
Y3[3]
Y3[2]
Y3[1]
Y3[0]
In this mode, the S[7:0] byte contains the following data:
S[6]
S[5]
S[4]
=
=
=
F
V
H
=
=
=
1 during field 2, 0 during field 1
1 during field blanking, 0 elsewhere
1 during EAV (the synchronization reference at the end of active video)
0 during SAV (the synchronization reference at the start of active video)
Bits S[7] and S[3-0] are ignored.
201-0000-002 Rev. 2.7, 08/23/2000
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CHRONTEL
CH7007A
Functional Description
The CH7007 is a TV-output companion chip to graphics controllers providing digital output in either YCrCb or
RGB format. This solution involves both hardware and software elements which work together to produce an
optimum TV screen image based on the original computer generated pixel data. All essential circuitry for this
conversion are integrated on chip. On chip circuitry includes memory, memory control, scaling, PLL, DAC, filters
and NTSC/PAL encoder. All internal signal processing, including NTSC/PAL encoding, is performed using digital
techniques to ensure that the high-quality video signals are not affected by drift issues associated with analog
components. No additional adjustment is required during manufacturing.
CH7007 is ideal for PC motherboards, web browsers or VGA add-in boards where a minimum of discrete support
components (passive components, parallel resonance 14.31818 MHz crystal) are required for full operation.
Architectural Overview
The CH7007 is a complete TV output subsystem which uses both hardware and software elements to produce an
image on TV which is virtually identical to the image that would be displayed on a monitor. Simply creating a
compatible TV output from a VGA input involves a relatively straightforward process. This process includes a
standard conversion from RGB to YUV color space, converting from a non-interlaced to an interlaced frame
sequence, and encoding the pixel stream into NTSC or PAL compliant format. However, creating an optimum
computer-generated image on a TV screen involves a highly sophisticated process of scaling, deflickering, and
filtering. This results in a compatible TV output that displays a sharp and subtle image, of the right size, with
minimal artifacts from the conversion process.
As a key part of the overall system solution, the CH7007 software establishes the correct framework for the VGA
input signal to enable this process. Once the display is set to a supported resolution (either 640x480 or 800x600), the
CH7007 software may be invoked to establish the appropriate TV output display. The software then programs the
various timing parameters of the VGA controller to create an output signal that will be compatible with the chosen
resolution, operating mode, and TV format. Adjustments performed in software include pixel clock rates, total
pixels per line, and total lines per frame. By performing these adjustments in software, the CH7007 can render a
superior TV image without the added cost of a full frame buffer memory – normally used to implement features
such as scaling and full synchronization.
The CH7007 hardware accepts digital RGB or YCrCb inputs, which are latched in synchronization with the pixel
clock. These inputs are then color-space converted into YUV in 4-2-2 format, and stored in a line buffer memory.
The stored pixels are fed into a block where scan-rate conversion, underscan scaling and 2-line, 3-line, 4-line or 5-
line vertical flicker filtering are performed. The scan-rate converter transforms the VGA horizontal scan-rate to
either NTSC or PAL scan rates; the vertical flicker filter eliminates flicker at the output while the underscan scaling
reduces the size of the displayed image to fit onto a TV screen. The resulting YUV signals are filtered through
digital filters to minimize aliasing problems. The digital encoder receives the filtered signals and transforms them to
composite andS-Video outputs, which are converted by the three 9-bit DACs into analog outputs.
Color Burst Generation*
The CH7007 allows the subcarrier frequency to be accurately generated from a 14.31818 MHz crystal oscillator,
leaving the subcarrier frequency independent of the sampling rate. As a result, the CH7007 may be used with any
VGA chip (with an appropriate digital interface) since the CH7007 subcarrier frequency can be generated without
being dependent on the precise pixel rates of VGA controllers. This feature is a significant benefit, since even a
±0.01% subcarrier frequency variation may be enough to cause some television monitors to lose color lock.
In addition, the CH7007 has the capability to genlock the color burst signal to the VGA horizontal sync frequency,
which enables a fully synchronous system between the graphics controller and the television. When genlocked, the
CH7007 can also stop “dot crawl” motion (for composite mode operation in NTSC modes) to eliminate the
annoyance of moving borders. Both of these features are under programmable control through the register set.
Display Modes
The CH7007 display mode is controlled by three independent factors: input resolution, TV format, and scale factor,
which are programmed via the display mode register. It is designed to accept input resolutions of 640x480, 800x600,
640x400 (including 320x200 scan-doubled output), 720x400 and 512x384.
201-0000-002 Rev. 2.7, 08/23/2000
* Patent number 5,874,846
10
CHRONTEL
CH7007A
Display Modes (continued)
It is designed to support output to either NTSC or PAL television formats. The CH7007 provides interpolated
scaling with selectable factors of 5:4, 1:1, 7:8, 5:6, 3:4 and 7:10 in order to support adjustable overscan or underscan
operation when displayed on a TV. This combination of factors results in a matrix of useful operating modes which
are listed in detail in Table 7.
Table 7. CH7007 Display Modes
TV Format
Standard
Input
(active)
Scale
Factor
Active
TV Lines
Percent (1)
Overscan
Pixel
Clock
Horizontal
Total
Vertical
Total
Resolution
640x480
640x480
640x480
800x600
800x600
800x600
640x400
640x400
640x400
720x400
720x400
512x384
512x384
1:1
7:8
5:6
5:6
10%
(3%)
(8%)
16%
4%
(3%)
16%
(8%)
(19%)
16%
(8%)
10%
(11%)
NTSC
NTSC
NTSC
NTSC
NTSC
NTSC
NTSC
NTSC
NTSC
NTSC
NTSC
NTSC
NTSC
480
420
400
500
450
420
500
400
350
500
400
480
384
24.671
28.196
30.210
39.273
43.636
47.832
21.147
26.434
30.210
23.790
29.455
20.140
24.671
784
784
525
600
630
630
700
750
420
525
600
420
525
420
525
800
1040
1040
1064
840
840
840
945
936
800
784
3:4
7:10
5:4
1:1
7:8
5:4
1:1
5:4
1:1
640x480
640x480
640x480
800x600
800x600
800x600
640x400
640x400
720x400
720x400
512x384
512x384
5:4
1:1
5:6
1:1
5:6
3:4
5:4
1:1
5:4
1:1
5:4
1:1
600
480
400
600
500
450
500
400
500
400
480
384
14%
(8%)
(29%)
14%
21.000
26.250
31.500
29.500
36.000
39.000
25.000
31.500
28.125
34.875
21.000
26.250
840
840
840
500
625
750
625
750
836
500
625
500
625
500
625
PAL
PAL
PAL
PAL
PAL
PAL
PAL
PAL
PAL
PAL
PAL
PAL
944
(4%)
(15%)
(4%)
(29%)
(4%)
(29%)
(8%)
(35%)
960
936
1000
1008
1125
1116
840
840
(1) Note: Percent underscan is a calculated value based on average viewable lines on each TV format, assuming an average TV over-
scan of 10%. (Negative values) indicate modes which are operating in underscan.
For NTSC: 480 active lines - 10% (overscan) = 432 viewable lines (average)
For PAL: 576 active lines - 10% (overscan) = 518 viewable lines (average)
The inclusion of multiple levels of scaling for each resolution have been created to enable optimal use of the
CH7007 for different application needs. In general, underscan (modes where percent overscan is negative) provides
an image that is viewable in its entirety on screen; it should be used as the default for most applications (e.g.,
viewing text screens, operating games, running productivity applications and working within Windows).
Overscanning provides an image that extends past the edges of the TV screen, exactly like normal television
programs and movies appear on TV, and is only recommended for viewing movies or video clips coming from the
computer. In addition to the above mode table, the CH7007 also support interlaced input modes, both in CCIR 656
and proprietary formats (see Display Mode Register section).
Flicker Filter and Text Enhancement
The CH7007 integrates an advanced 2-line, 3-line, 4-line and 5-line (depending on mode) vertical deflickering filter
circuit to help eliminate the flicker associated with interlaced displays. This flicker circuit provides an adaptive filter
algorithm for implementing flicker reduction with selections of high, medium or low flicker content for both luma
and chroma channels (see register descriptions). In addition, a special text enhancement circuit incorporates
201-0000-002 Rev. 2.7, 08/23/2000
11
CHRONTEL
CH7007A
Display Modes (continued)
additional filtering for enhancing the readability of text. These modes are fully programmable via I2C under the
flicker filter register.
Internal Voltage Reference
An on chip bandgap circuit is used in the DAC to generate a reference voltage which, in conjunction with a
reference resistor at pin ISET, and register controlled divider, sets the output ranges of the DACs. The CH7007
bandgap reference voltage is 1.235 volts nominal for NTSC or PAL-M, or 1.317 volts nominal for PAL or NTSC-J,
which is determined by IDF register bit 6 (DACG bit). The recommended value for the reference resistor from ISET
to ground is 360 ohms (though this may be adjusted in order to achieve a different output level). The gain setting for
DAC output is 1/48th. Therefore, for each DAC, the current output per LSB step is determined by the following
equation:
ILSB = V(ISET)/ISET reference resistor * 1/GAIN
For DACG=0, this is: ILSB = 1.235/360 * 1/48 = 71.4 mA (nominal)
For DACG=1, this is: ILSB = 1.317/360 * 1/48 = 76.2 mA (nominal)
Power Management
The CH7007 supports five operating states including Normal [On], Power Down, Full Power Down, S-Video Off
and Composite Off to provide optimal power consumption for the application involved. Using the programmable
power down modes accessed over the I2C port, the CH7007 may be placed in either Normal state, or any of the four
power managed states, as listed below (see “Power Management Register” under theRegister Descriptions section
for programming information). To support power management, a TV sensing function (see “Connection Detect
Register” under the Register Descriptions section) is provided, which identifies whether a TV is connected to either
S-Video or composite. This sensing function can then be used to enter into the appropriate operating state (e.g., if
TV is sensed only on composite, the S-Video Off mode could be set by software).
Table 8. Power Management
Operating State
Normal (On):
Functional Description
In the normal operating state, all functions and pins are active.
Power Down:
In the power-down state, most pins and circuitry are disabled.The DS/BCO pin
will continue to provide either the VCO divided by K3, or 14.318 MHz out when
selected as an output, and the P-OUT pin will continue to output a clock
reference when in master clock mode.
S-Video Off:
Power is shut off to the unused DACs associated with S-Video outputs.
Composite Off:
In Composite-off state, power is shut off to the unused DAC associated with
CVBS output.
2
Full Power Down:
In this power-down state, all but the I C circuits are disabled. This places the
CH7007 in its lowest power consumption mode.
Luminance and Chrominance Filter Options
The CH7007 contains a set of luminance filters to provide a controllable bandwidth output on both CVBS and S-
Video outputs. All values are completely programmable via the Video Bandwidth Register. For all graphs shown,
the horizontal axis is frequency in MHz, and the vertical axis is attenuation in dBs. The composite luminance and
chrominance video bandwidth output is shown in Table 9.
MacrovisionTM Anti-copy Protection
The CH7007 implements the Macrovision 7.X anti-copy protection process. This process changes the encoded
output of the NTSC/PAL signals to inhibit recording on VCR devices while not affecting viewing on a TV. The
parameters that control this process are fully programmable and can be described by Chrontel only after a suitable
Non-Disclosure Agreement has been executed between MacrovisionTM, Inc. and the customer.
12
201-0000-002 Rev. 2.7, 08/23/2000
CHRONTEL
CH7007A
Table 9. Video Bandwidth
Mode
Chrominance
Luminance Bandwidth with Sin(X) /X (MHz)
CVBS
YCV
S-Video
YSV[1:0], YPEAK = 0
S-Video
YSV[1:0], YPEAK = 1
CBW[1:0]
00
01
10
11
0
1
00
01
1X
00
01
1X
0
0.62
0.78
0.53
0.65
0.83
1.03
0.70
0.87
0.74
0.93
0.63
0.78
0.89
0.62
0.78
0.93
0.64
0.74
0.79
0.77
0.95
1.02
0.77
0.86
0.94
0.71
0.71
0.68
0.85
0.58
0.71
0.91
1.13
0.77
0.95
0.81
1.02
0.68
0.86
0.98
0.68
0.85
1.02
0.71
0.81
0.87
0.85
1.03
1.12
0.85
0.94
1.03
0.78
0.78
0.80
1.00
0.68
0.83
1.07
1.32
0.90
1.12
0.95
1.20
0.80
1.00
1.15
0.80
1.00
1.20
0.83
0.95
1.02
1.00
1.22
1.32
0.99
1.11
1.21
0.91
0.91
0.95
1.18
0.81
0.99
1.27
1.57
1.07
1.33
1.13
1.42
0.95
1.19
1.36
0.95
1.18
1.42
0.98
1.13
1.21
1.18
1.44
1.56
1.18
1.31
1.44
1.08
1.08
2.26
2.82
1.93
2.36
3.03
3.75
2.56
3.17
2.69
3.39
2.28
2.84
3.25
2.26
2.82
3.39
2.35
2.70
2.89
2.82
3.44
3.73
2.82
3.13
3.43
2.58
2.58
3.37
4.21
2.87
3.52
4.51
5.59
3.81
4.72
4.01
5.05
3.39
4.24
4.84
3.37
4.21
5.05
3.50
4.02
4.31
4.20
5.13
5.56
4.20
4.66
5.11
3.85
3.85
2.26
2.82
1.93
2.36
3.03
3.75
2.56
3.17
2.69
3.39
2.28
2.84
3.25
2.26
2.82
3.39
2.35
2.70
2.89
2.82
3.44
3.73
2.82
3.13
3.43
2.58
2.58
3.37
4.21
2.87
3.52
4.51
5.59
3.81
4.72
4.01
5.05
3.39
4.24
4.84
3.37
4.21
5.05
3.50
4.02
4.31
4.20
5.13
5.56
4.20
4.66
5.11
3.85
3.85
5.23
6.53
4.46
5.46
7.00
8.68
5.92
7.33
6.22
7.84
5.26
6.58
7.52
5.23
6.53
7.84
5.43
6.24
6.68
6.53
7.97
8.63
6.52
7.24
7.94
5.97
5.97
2.57
3.21
2.19
2.68
3.44
4.27
2.91
3.60
3.06
3.85
2.59
3.23
3.70
2.57
3.21
3.85
2.67
3.07
3.29
3.21
3.92
4.24
3.20
3.56
3.90
2.94
2.94
4.44
5.56
3.79
4.64
5.95
7.38
5.04
6.23
5.29
6.67
4.48
5.59
6.39
4.44
5.56
6.67
4.62
5.30
5.68
5.55
6.77
7.34
5.54
6.16
6.75
5.08
5.08
5.23
6.53
4.46
5.46
7.00
8.68
5.92
7.33
6.22
7.84
5.26
6.58
7.52
5.23
6.53
7.84
5.43
6.24
6.68
6.53
7.97
8.63
6.52
7.24
7.94
5.97
5.97
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
The composite luminance and chrominance frequency response is depicted in Figures 5through 7.
201-0000-002 Rev. 2.7, 08/23/2000
13
CHRONTEL
CH7007A
Luminance and Chrominance Filter Options (continued)
0
-6
-1
2
-18
(YCVdB<i>
)
n
-2
4
-
30
-36
-42
0
1
2
2
3
4
5
9
10
11
12
6
7
8
fn,i
6
10
Figure 5: Composite Luminance Frequency Response (YCV = 0)
0
-6
-12
-18
-24
-30
<i>
(YSVdB
)
n
-36
-42
0
9
10
1
3
4
5
7
8
11
12
2
6
n ,i
f
6
10
Figure 6: S-Video Luminance Frequency Response (YSV = 1X, YPEAK = 0)
14
201-0000-002 Rev. 2.7, 08/23/2000
CHRONTEL
CH7007A
Luminance and Chrominance Filter Options(continued)
0
-6
-12
-18
(UVfirdB<i>
)
n
-24
-30
-36
-42
0
1
12
2
3
4
5
9
10
11
6
fn,i
6
10
Figure 7: Chrominance Frequency Response
201-0000-002 Rev. 2.7, 08/23/2000
15
CHRONTEL
CH7007A
NTSC and PAL Operation
Composite and S-Video outputs are supported in either NTSC or PAL format. The general parameters used to
characterize these outputs are listed in Table10 and shown in Figure8. (See Figures 11 through 16 for illustrations
of composite and S-Video output waveforms).
CCIR624-3 Compliance
The CH7007 is predominantly compliant with the recommendations called out in CCIR624-3. The following are the
only exceptions to this compliance:
• The frequencies of Fsc, Fh, and Fv can only be guaranteed in master mode, not in slave mode when the graphics
device generates these frequencies.
• It is assumed that gamma correction, if required, is performed in the graphics device which establishes the color
reference signals.
• All modes provide the exact number of lines called out for NTSC and PAL modes respectively, except mode 21,
which outputs 800x600 resolution, scaled by 3:4, to PAL format with a total of 627 lines (vs. 625).
• Chroma signal frequency response will fall within 10% of the exact recommended value.
• Pulse widths and rise/fall times for sync pulses, front/back porches, and equalizing pulses are designed to
approximate CCIR624-3 requirements, but will fall into a range of values due to the variety of clock frequencies
used to support multiple operating modes.
Table 10. NTSC/PAL Composite Output Timing Parameters (in mS)
Symbol
Description
Level (mV)
Duration (uS)
NTSC
NTSC
PAL
PAL
1.48 - 1.51
4.69 - 4.71
0.88 - 0.92
2.24 - 2.26
2.62 - 2.71
0.00 - 8.67
34.68 - 52.01
0.00 - 8.67
Front Porch
Horizontal Sync
Breezeway
Color Burst
Back Porch
Black
1.49 - 1.51
4.69 - 4.72
0.59 - 0.61
2.50 - 2.53
1.55 - 1.61
0.00 - 7.50
37.66 - 52.67
0.00 - 7.50
A
B
C
D
E
F
287
0
300
0
287
287
287
340
340
340
300
300
300
300
300
300
Active Video
Black
G
H
For this table and all subsequent figures, key values are:
Note:
1. ISET = 360 ohms; V(ISET) = 1.235V; 75 ohms doubly terminated load.
2. Durations vary slightly in different modes due to the different clock frequencies used.
3. Active video and black (F, G, H) times vary greatly due to different scaling ratios used in different modes.
4. Black times (F and H) vary with position controls.
16
201-0000-002 Rev. 2.7, 08/23/2000
CHRONTEL
CH7007A
A
B
C
D
E
F
G
H
Figure 8: NTSC / PAL Composite Output
SSTTAARRTT
OF
VSYNC
ANALOG
Start of
field 1
523
524
525
9
10
12
3
11
1
2
4
5
6
7
8
Pre-equalizing
pulse interval
Post-equalizing
pulse interval
Vertical sync
pulse interval
Reference
sub-carrier phase
color field 1
Line
ANALOG
vertical
interval
t1+V
263
262
264
270
261
265
267
268
269
271
272
273
274
275
266
START
Start of
field 2
Reference
sub-carrier phase
t2+V
color field 2
523
10
12
524
6
11
2
7
8
9
5
2
5
1
Start of
3
4
5
field 3
Reference
sub-carrier phase
t3+V
color field 3
263
264
274
261
262
269
270
273
265
266
267
268
271
2
7
2
275
Start of
field 4
Reference
sub-carrier phase
color field 4
Figure 9: Interlaced NTSC Video Timing
201-0000-002 Rev. 2.7, 08/23/2000
17
CHRONTEL
CH7007A
START
OF
VSYNC
FIELD 1
620
621
622
623
624
625
1
2
3
4
5
6
7
8
9
10
FIELD 2
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
FIELD 3
620621
622623624
625
1
2
3
4
5
6
7
8
9
10
FIELD 4
308
309
323
310
311
312
313
314
315
316
317
318
319
320
321
322
BURST
BLANKING
4
3
INTERVALS
2
1
Figure 10: Interlaced PAL Video Timing
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201-0000-002 Rev. 2.7, 08/23/2000
CHRONTEL
CH7007A
Color bars:
Color/Level
mA
V
White
Yellow
26.66
24.66
1.000
0.925
Cyan
Green
21.37
19.37
0.801
0.726
Magenta
Red
16.22
14.22
0.608
0.533
Blue
Black
11.08
9.08
0.415
0.340
Blank
7.65
0.287
Sync
0.00
0.000
Figure 11: NTSC Y (Luminance) Output Waveform (DACG = 0)
Color bars:
Color/Level
mA
V
White
Yellow
26.75
24.62
1.003
0.923
Cyan
Green
21.11
18.98
0.792
0.712
Magenta
Red
15.62
13.49
0.586
0.506
Blue
10.14
8.00
0.380
0.300
Blank/ Black
Sync
0.00
0.000
Figure 12: PAL Y (Luminance) Video Output Waveform (DACG = 1)
201-0000-002 Rev. 2.7, 08/23/2000
19
CHRONTEL
CH7007A
Color bars:
Color/Level
mA
V
Cyan/Red
Green/Magenta 25.01
25.80
0.968
0.938
Yellow/Blue
22.44
0.842
Peak Burst
Blank
18.08
14.29
0.678
0.536
Peak Burst
10.51
0.394
3.579545 MHz Color Burst
(9 cycles)
Yellow/Blue
6.15
0.230
Green/Magenta 3.57
Cyan/Red 2.79
0.134
0.105
Figure 13: NTSC C (Chrominance) Video Output Waveform (DACG = 0)
Color bars:
Color/Level
mA
V
Cyan/Red
Green/Magenta 26.68
27.51
1.032
1.000
Yellow/Blue
23.93
0.897
Peak Burst
Blank
19.21
15.24
0.720
0.572
Peak Burst
11.28
0.423
4.433619 MHz Color Burst
(10 cycles)
Yellow/Blue
6.56
0.246
Green/Magenta
Cyan/Red
3.81
2.97
0.143
0.111
Figure 14: PAL C (Chrominance) Video Output Waveform (DACG = 1)
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201-0000-002 Rev. 2.7, 08/23/2000
CHRONTEL
CH7007A
Color/Level
mA
V
Color bars:
Peak Chrome 32.88
1.233
White
26.66
1.000
Peak Burst
11.44
0.429
Black
Blank
9.08
7.65
0.340
0.281
Peak Burst
4.45
0.145
3.579545 MHz Color Burst
(9 cycles)
Sync
0.00 0.000
Figure 15: Composite NTSC Video Output Waveform (DACG = 0)
mA
Color/Level
V
Color bars:
Peak Chrome 33.31
1.249
White
26.75
1.003
Peak Burst
Blank/Black
11.97
8.00
0.449
0.300
Peak Burst
Sync
4.04
0.00
0.151
0.000
4.433619 MHz Color Burst
(10 cycles)
Figure 16: Composite PAL Video Output Waveform (DACG = 1)
201-0000-002 Rev. 2.7, 08/23/2000
21
CHRONTEL
CH7007A
I2C Port Operation
The CH7007 contains a standard I2C control port, through which the control registers can be written and read. This
port is comprised of a two-wire serial interface, pins SD (bidirectional) and SC, which can be connected directly to
the SDB and SCB buses as shown in Figure17.
The Serial Clock line (SC) is input only and is driven by the output buffer of the master device (also shown in
Figure17). The CH7007 acts as a slave, and generation of clock signals on the bus is always the responsibility of
the master device. When the bus is free, both lines are HIGH. The output stages of devices connected to the bus
must have an open-drain or open-collector to perform the wired-AND function. Data on the bus can be transferred
up to 400 kbit/s.
+DVDD
R
P
SDB (Serial Data Bus)
SCB (Serial Clock Bus)
SD
SC
DATAN2
OUT
MASTER
DATAN2
OUT
DATAN2
OUT
SCLK
OUT
FROM
MASTER
DATA IN
MASTER
SCLK
IN1
DATA
IN1
SCLK
IN2
DATA
IN2
BUS MASTER
SLAVE
SLAVE
Figure 17: Connection of Devices to the Bus
Electrical Characteristics for Bus Devices
The electrical specifications of the bus devices’ inputs and outputs and the characteristics of the bus lines connected
to them are shown in Figure17. A pull-up resistor (RP) must be connected to a 3.3V ± 10% supply. The CH7007 is
a device with input levels related to DVDD.
Maximum and minimum values of pull-up resistor (RP)
The value of RP depends on the following parameters:
• Supply voltage
• Bus capacitance
• Number of devices connected (input current + leakage current = Iinput
)
The supply voltage limits the minimum value of resistor RP due to the specified minimum sink current of 2mA at
VOLmax = 0.4 V for the output stages:
RP >= (VDD – 0.4) / 2 (RP in kW)
The bus capacitance is the total capacitance of wire, connections and pins. This capacitance limits the maximum
value of RP due to the specified rise time. The equation for RP is shown below:
RP <= 103/C (where: RP is in kW and C, the total capacitance, is in pF)
The maximum HIGH level input current of each input/output connection has a specified maximum value of 10 mA.
Due to the desired noise margin of 0.2VDD for the HIGH level, this input current limits the maximum value of RP.
The RP limit depends on VDD and is shown below:
RP <= (100 x VDD)/ Iinput (where: RP is in kW and Iinput is in mA)
22
201-0000-002 Rev. 2.7, 08/23/2000
CHRONTEL
CH7007A
Transfer Protocol
Both read and write cycles can be executed in “Alternating” and “Auto-increment” modes. Alternating mode
expects a register address prior to each read or write from that location (i.e., transfers alternate between address and
data). Auto-increment mode allows you to establish the initial register location, then automatically increments the
register address after each subsequent data access (i.e., transfers will be address, data...). A basic serial port transfer
protocol is shown in Figure18 and described below.
SD
2
I C
CH7007
1 - 8
1 - 8
8
9
9
9
SC
Stop
Condition
Start
Condition
Device ID
R/W*
ACK
Data
ACK
Data
ACK
1
n
CH7007
CH7007
CH7007
acknowledge
acknowledge
acknowledge
Figure 18: Serial Port Transfer Protocol
1. The transfer sequence is initiated when a high-to-low transition of SD occurs while SC is high; this is the
“START” condition. Transitions of address and data bits can only occur while SC is low.
2. The transfer sequence is terminated when a low-to-high transition of SD occurs while SC is high; this is the
“STOP” condition.
3. Upon receiving the first START condition, the CH7007 expects a Device Address Byte (DAB) from the
master device. The value of the device address is shown in the DAB data format below.
4. After the DAB is received, the CH7007 expects a Register Address Byte (RAB) from the master. The
format of the RAB is shown in the RAB data format below (note that B7 is not used).
Device Address Byte (DAB)
B7
B6
B5
B4
B3
B2
B1
B0
1
1
1
0
1
0
1
R/W
R/W
Read/Write Indicator
“0”: master device will write to the CH7007 at the register location specified by the address
AR[5:0]
“1”: master device will read from the CH7007 at the register location specified by the
address AR[5:0].
Register Address Byte (RAB)
B0
B7
B6
B5
B4
B3
B2
B1
1
AutoInc
AR[5]
AR[4]
AR[3]
AR[2]
AR[1]
AR[0]
201-0000-002 Rev. 2.7, 08/23/2000
23
CHRONTEL
CH7007A
Transfer Protocols (continued)
AutoInc
Register Address Auto-Increment - to facilitate sequential R/W of registers.
“1”: Auto-Increment enabled (auto-increment mode).
Write: After writing data into a register, the Address Register will automatically be
incremented by one.
Read: Before loading data from a register to the on-chip temporary register (getting ready to
be serially read), the Address Register will automatically be incremented by one.
However, for the first read after an RAB, the Address Register will not be changed.
“0”: Auto-Increment disabled (alternating mode).
Write: After writing data into a register, the Address Register will remain unchanged until a
new RAB is written.
Read: Before loading data from a register to the on-chip temporary register (getting ready to
be serially read), the Address Register will remain unchanged.
AR[5:0]
Specifies the Address of the Register to be Accessed.
This register address is loaded into the Address Register of the CH7007. The R/W access, which
follows, is directed to the register specified by the content stored in the Address Register.
The following two sections describe the operation of the serial interface for the four combinations of R/W = 0,1 and
AutoInc = 0,1.
CH7007 Write Cycle Protocols (R/W = 0)
Data transfer with acknowledge is required. The acknowledge-related clock pulse is generated by the master-
transmitter. The master-transmitter releases the SD line (HIGH) during the acknowledge clock pulse. The slave-
receiver must pull down the SD line, during the acknowledge clock pulse, so that it remains stable LOW during the
HIGH period of the clock pulse. The CH7007 always acknowledges for writes (see Figure19). Note that the
resultant state on SD is the wired-AND of data outputs from the transmitter and receiver.
SD Data Output
By Master-Transmitter
not acknowledge
SD Data Output
By the CH7007
acknowledge
SC from
Master
1
2
8
9
clock pulse for
Start
Condition
acknowledgment
Figure 19: Acknowledge on the Bus
Figure 20 shows two consecutive alternating write cycles for AutoInc = 0 and R/W = 0. The byte of information,
following the Register Address Byte (RAB), is the data to be written into the register specified by AR[5:0]. If
AutoInc = 0, then another RAB is expected from the master device, followed by another data byte, and so on.
24
201-0000-002 Rev. 2.7, 08/23/2000
CHRONTEL
CH7007A
CH7007
CH7007
CH7007
CH7007
CH7007
acknowledge
acknowledge
acknowledge
acknowledge
acknowledge
SD
I2C
1 - 7
8
9
1 - 8
9
1 - 8
9
1 - 8
9
1 - 8
9
SC
Start
Condition
Stop
Condition
Device ID R/W*
ACK
RAB
ACK
Data
ACK
RAB
ACK
Data
ACK
Note: The acknowledge is from the CH7007 (slave).
Figure 20: Alternating Write Cycles
If AutoInc = 1, then the register address pointer will be incremented automatically and subsequent data bytes will be
written into successive registers without providing an RAB between each data byte. An Auto-increment write cycle
is shown in Figure21.
.
CH7007
CH7007
CH7007
CH7007
acknowledge
acknowledge
acknowledge
acknowledge
SD
SC
I2C
1 - 7
1 - 8
1 - 8
1 - 8
8
9
9
9
9
Start
Condition
Stop
Condition
Device ID
R/W*
ACK
RAB
ACK
Data
ACK
Data
n+1
ACK
n
n
Note: The acknowledge is from the CH7007 (slave).
Figure 21: Auto-Increment Write Cycle
When the auto-increment mode is enabled (AutoInc is set to 1), the register address pointer continues to increment
for each write cycle until AR[5:0] = 3F (3F is the address of the Address Register). The next byte of information
represents a new auto-sequencing “Starting address”, which is the address of the register to receive the next byte.
The auto-sequencing then resumes based on this new “Starting address”. The auto-increment sequence can be
terminated any time by either a “STOP” or “RESTART” condition. The write operation can be terminated with a
“STOP” condition.
CH7007 Read Cycle Protocols (R/W = 1)
If a master-receiver is involved in a transfer, it must signal the end of data to the slave-transmitter by not generating
an acknowledge on the last byte that was clocked out of the slave. The slave-transmitter CH7007 releases the data
line to allow the master to generate the STOP condition or the RESTART condition.
To read the content of the registers, the master device starts by issuing a “START” condition (or a “RESTART”
condition). The first byte of data, after the START condition, is a DAB with R/W = 0. The second byte is the RAB
with AR[5:0], containing the address of the register that the master device intends to read from in AR[5:0]. The
master device should then issue a “RESTART” condition (“RESTART” = “START”, without a previous “STOP”
condition). The first byte of data, after this RESTART condition, is another DAB with R/W=1, indicating the
master’s intention to read data hereafter. The master then reads the next byte of data (the content of the register
specified in the RAB). If AutoInc = 0, then another RESTART condition, followed by another DAB with R/W = 0
and RAB, is expected from the master device. The master device then issues another RESTART, followed by
another DAB. After that, the master may read another data byte, and so on. In summary, a RESTART condition,
followed by a DAB, must be produced by the master before each of the RAB, and before each of the data read
events. Two consecutive alternating read cycles are shown in Figure22.
201-0000-002 Rev. 2.7, 08/23/2000
25
CHRONTEL
CH7007A
Transfer Protocols (continued)
.
CH7007
CH7007
CH7007
acknowledge
acknowledge
acknowledge
Master
SD
does not
acknowledge
2
I2C
I C
1 - 7
8
9
1 - 8
9
10
1 - 7
8
9
1 - 8
9
10
SC
Start
Condition
Device ID R/W* ACK
RAB
ACK Restart
Condition
Device ID R/W* ACK
Data
ACK
Restart
Condition
1
1
Master does
not acknowledge
CH7007
acknowledge
CH7007
acknowledge
CH7007
acknowledge
2
I C
I2C
1 - 8
1 - 8
1 - 7
8
9
9
10
1 - 7
8
9
9
Stop
Condition
Device ID
R/W*
ACK
RAB
ACK
Restart Device ID R/W*
Condition
ACK
Data
ACK
2
2
Figure 22: Alternating Read Cycle
If AutoInc = 1, then the address register will be incremented automatically and subsequent data bytes can be read
from successive registers, without providing a second RAB.
Master does
not acknowledge
just before Stop
condition
CH7007
acknowledge
CH7007
acknowledge
CH7007
acknowledge
Master
acknowledge
SD
I2C
1 - 8
1 - 8
1 - 8
1 - 7
8
9
9
10
1 - 7
8
9
9
9
SC
Start
Condition
Stop
Condition
Device ID R/W* ACK RAB
ACK Restart Device ID R/W* ACK
Condition
Data
ACK
Data
n+1
ACK
n
n
Figure 23: Auto-increment Read Cycle
When the auto-increment mode is enabled (AutoInc is set to 1), the Address Register will continue incrementing for
each read cycle. When the content of the Address Register reaches 2A, it will wrap around and start from 00h again.
The auto increment sequence can be terminated by either a “STOP” or “RESTART” condition. The read operation
can be terminated with a “STOP” condition. Figure23 shows an auto-increment read cycle terminated by a STOP
or RESTART condition.
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201-0000-002 Rev. 2.7, 08/23/2000
CHRONTEL
CH7007A
Registers and Programming
The CH7007 is a fully programmable device, providing for full functional control through a set of registers accessed
from the I2C port. The CH7007 contains a total of 37 registers, which are listed in Table 11 and described in detail
under Register Descriptions. Detailed descriptions of operating modes and their effects are contained in the previous
section, Functional Description. An addition (+) sign in the Bits column below signifies that the parameter contains
more than 8 bits, and the remaining bits are located in another register.
Table 11. Register Map
Register
Display Mode
Symbol
DMR
FFR
Address
00H
Bits
Functional Summary
Display mode selection
8
Flicker Filter
01H
6
Flicker filter mode selection
Video Bandwidth
Input Data Format
Clock Mode
VBW
IDF
03H
8
Luma and chroma filter bandwidth selection
Data format and bit-width selections
04H
6
CM
06H
8
Sets the clock mode to be used
Active video delay setting
Start Active Video
SAV
07H
8+
Position Overflow
Black Level
PO
08H
3
MSB bits of position values
BLR
HPR
09H
8
Black level adjustment input latch clock edge select
0AH
8+
Enables horizontal movement of displayed image on
TV
Horizontal Position
Vertical Position
VPR
SPR
0BH
0DH
8+
4
Enables vertical movement of displayed image on
TV
Determines the horizontal and vertical sync polarity
Sync Polarity
Power Management
Connection Detect
Contrast Enhancement
PLL M and N extra bits
PLL-M Value
PMR
CDR
CE
0EH
10H
5
Enables power saving modes
4
Detection of TV presence
11H
3
Contrast enhancement setting
MNE
PLLM
PLLN
BCO
FSCI
13H
5
Contains the MSB bits for the M and N PLL values
Sets the PLL M value - bits (7:0)
Sets the PLL N value - bits (7:0)
Determines the clock output at pin 41
Determines the subcarrier frequency
14H
8+
8+
6
PLL-N Value
15H
Buffered Clock
17H
Subcarrier Frequency
Adjust
18H -1FH
4 or 8
each
PLL and Memory Control
CIV Control
PLLC
CIVC
CIV
20H
21H
6
Controls for the PLL and memory sections
Control of CIV value
5
Calculated Fsc Increment
Value
21H -
24H
8 each
Readable register containing the calculated
subcarrier increment value
Version ID
Test
VID
TR
25H
8
Device version number
26H -
29H
30
Reserved for test (details not included herein)
Address
AR
3FH
6
Current register being addressed
201-0000-002 Rev. 2.7, 08/23/2000
27
CHRONTEL
CH7007A
Register Descriptions (continued)
Table 12. I2C Alternate Register Map (Note: MacrovisionTM controls available only by special arrangement)
Register
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
3FH
Bit 7
Bit 6
Bit 5
IRO
FC1
Bit 4
VOS1
FC0
Bit 3
VOS0
FY1
Bit 2
SR2
FY0
Bit 1
SR1
FT1
Bit 0
SR0
FT0
IR2
IR1
FLFF
CVBW
DACG
CBW1
CBW0
YPEAK
IDF3
YSV1
IDF2
YSV0
IDF1
YCV
IDF0
Reserved
CFRB
SAV7
M/S*
Reserved
SAV5
MCP
XCM1
SAV3
XCM0
SAV2
SAV8
BL2
PCM1
SAV1
HP8
BL1
PCM0
SAV0
VP8
SAV6
SAV4
BL7
HP7
VP7
BL6
HP6
VP6
BL5
HP5
VP5
BL4
HP4
VP4
BL3
HP3
VP3
BL0
HP2
HP1
VP1
HP0
VP0
VP2
DES
SYO
PD2
VSP
PD1
HSP
PD0
SCART
Reset*
YT
CT
CVBST
CE1
SENSE
CE0
CE2
Reserved
M4
Reserved
M3
N9
M2
N2
N8
M1
N1
M8
M0
N0
M7
N7
M6
N6
M5
N5
N4
N3
SHF2
SHF1
SHF0
FSCI31
FSCI27
FSCI23
FSCI19
FSCI15
FSCI11
FSCI7
FSCI3
PLLS
SCO2
FSCI30
FSCI26
FSCI22
FSCl18
FSCl14
FSCl10
FSCI6
FSCI2
PLL5VD
ClVH1
CIV18
CIV10
CIV2
SCO1
FSCI29
FSCI25
FSCI21
FSCl17
FSCl13
FSCl9
FSCI5
FSCI1
PLL5VA
ClVH0
CIV17
CIV9
SCO0
FSCI28
FSCI24
FSCI20
FSCl16
FSCI12
FSCI8
FSCI4
FSCI0
MEM5V
AClV
GPIOIN1
GOENB1
GPIOIN0
GOENB0
DVDD2
DSM
P-OUTP
DSEN
PLLCPl
PLLCAP
CIV25
CIV20
CIV12
CIV4
CIV24
CIV19
CIV11
CIV3
CIV23
CIV15
CIV7
VID7
TS3
CIV22
CIV14
CIV6
VID6
TS2
CIV21
CIV13
CIV5
VID5
TS1
CIV16
CIV8
CIV1
CIVO
VID4
VID3
VID2
VID1
VID0
TS0
RSA
BST
NST
TE
MS2
MS1
MSO
MTD
YLM8
YLM1
CLM1
AR1
CLM8
YLM0
CLM0
AR0
YLM7
YLM6
YLM5
CLM5
AR5
YLM4
CLM4
AR4
YLM3
CLM3
AR3
YLM2
CLM2
AR2
CLM7
CLM6
Reserved
Reserved
28
201-0000-002 Rev. 2.7, 08/23/2000
CHRONTEL
CH7007A
Register Descriptions (continued)
Display Mode Register
Symbol: DMR
Address: 00H
Bits: 8
Bit:
7
6
5
4
3
2
1
0
IR2
R/W
0
IR1
R/W
1
IR0
R/W
1
VOS1
R/W
0
VOS0
R/W
1
SR2
R/W
0
SR1
R/W
1
SR0
R/W
0
Symbol:
Type:
Default:
This register provides programmable control of the CH7007 display mode, including input resolution (IR[2:0]),
output TV standard (VOS[1:0]), and scaling ratio (SR[2:0]). The mode of operation is determined according to the
table below (default is 640x480 input, NTSC output, 7/8’s scaling).
Table 13. Display Modes
Input Data
Format
(Active
Total
Pixels/Line
x Total
Output
Format
VOS
[1:0]
SR
[2:0]
Pixel Clock
(MHz)
Mode
0
IR[2:0]
000
000
000
000
001
001
001
001
010
010
010
010
010
011
Video)
Lines/Frame
Scaling
5/4
1/1
5/4
1/1
5/4
1/1
5/4
1/1
5/4
1/1
5/4
1/1
7/8
5/4
1/1
5/6
1/1
7/8
5/6
1/1
5/6
3/4
5/6
3/4
7/10
1/1
1/1
00
00
01
01
00
00
01
01
00
00
01
01
01
00
00
00
01
01
01
00
00
00
01
01
01
00
01
000
001
000
001
000
001
000
001
010
001
000
001
010
000
001
011
001
010
011
001
011
100
011
100
101
001
001
512x384
512x384
512x384
512x384
720X400
720x400
720x400
720x400
640x400
640x400
640x400
640x400
640x400
640x480
640x480
640x480
640x480
640x480
640x480
800x600
800x600
800x600
800x600
800x600
800x600
720x576
720x480
840x500
840x625
800x420
784x525
1125X500
1116x625
945x420
936x525
1000x500
1008x625
840x420
840x525
840x600
840x500
840x625
840x750
784x525
784x600
800x630
944x625
960x750
936x836
1040x630
1040x700
1064x750
864x625
858x525
PAL
21.000000
26.250000
20.139860
24.671329
28.125000
34.875000
23.790210
29.454545
25.000000
31.5000000
21.146853
26.433566
30.209790
21.000000
26.250000
31.5000000
24.671329
28.195804
30.209790
29.500000
36.0000000
39.000000
39.272727
43.636364
47.832168
13.500000
13.500000
1
PAL
2
NTSC
NTSC
PAL
3
4
5
PAL
6
NTSC
NTSC
PAL
7
8
9
PAL
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25*
26*
NTSC
NTSC
NTSC
PAL
011
PAL
011
PAL
011
NTSC
NTSC
NTSC
PAL
011
011
100
100
100
100
100
100
101
101
PAL
PAL
NTSC
NTSC
NTSC
PAL
NTSC
* Interlaced modes of operation. (For those modes, some functions will be bypassed. For details, please contact the
application department.)
201-0000-002 Rev. 2.7, 08/23/2000
29
CHRONTEL
CH7007A
Register Descriptions (continued)
00
01
10
11
VOS[1:0]
PAL
NTSC
PAL-M
NTSC-J
Output Format
Flicker Filter Register
Symbol: FFR
Address: 01H
Bits: 6
Bit:
7
6
5
4
3
2
1
0
FC1
R/W
1
FC0
R/W
1
FY1
R/W
0
FY0
R/W
0
FT1
R/W
1
FT0
R/W
0
Symbol:
Type:
Default:
The flicker filter register provides for adjusting the operation of the various filters used in rendering the on-screen
image. Adjusting settings between minimal and maximal values enables optimization between sharpness and flicker
content. The FC[1:0] bits determine the settings for the chroma channel. The FT[1:0] bits determine the settings for
the text enhancement circuit. The FY[1:0] bits determine the settings for the luma channel. In addition, the Chroma
channel filtering includes a setting to enable the chroma dot crawl reduction circuit.
Note: When writing to register O1H, FY[1:0] is bits 3:2. FT[1:0] is bits 1:0. When reading from the register O1H, FY
[1:0] is bits 1:0 and FT[1:0] is bits 3:2.
Table 14. Flicker Filter Settings
FY[1:0]
00
Settings for Luma Channel
Minimal Flicker Filtering
Slight Flicker Filtering
Maximum Flicker Filtering
Invalid
01
10
11
FT[1:0]
00
Settings for Text Enhancement Circuit
Maximum Text Enhancement
Slight Text Enhancement
Minimum Text Enhancement
Invalid
01
10
11
FC[1:0]
00
Settings for Chroma Channel
Minimal Flicker Filtering
01
Slight Flicker Filtering
10
Maximum Flicker Filtering
Enable Chroma DotCrawl Reduction
11
30
201-0000-002 Rev. 2.7, 08/23/2000
CHRONTEL
CH7007A
Register Descriptions (continued)
Symbol: VBW
Video Bandwidth Register
Address: 03H
Bits: 8
Bit:
7
6
5
4
3
2
1
0
FLFF
CVBW
CBW1
CBW0
YPEAK
YSV1
YSV0
YCV
Symbol:
Type:
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Default:
This register enables the selection of alternative filters for use in the luma and chroma channels. There are currently
four filter options defined for the chroma channel, four filter options in the S-Video luma channel and two filter
options in the composite luma channel. The Tables 15 and 16 below show the various settings.
Table 15. Luma Filter Bandwidth
YCV
Luma Composite Video Filter Adjust
Low bandwidth
0
1
High bandwidth
YSV[1:0]
Luma S-Video Filter Adjust
Low bandwidth
00
01
Medium bandwidth
10
High bandwidth
11
Reserved
YPEAK
Disables the Y-peaking circuit
Disables the peaking filter in luma s-video channel
Enables the peaking filter in luma s-video channel
0
1
Table 16. Chroma Filter Bandwidth
CBW[1:0]
0 0
Chroma Filter Adjust
Low bandwidth
0 1
Medium bandwidth
Med-high bandwidth
High bandwidth
1 0
1 1
Bit 6 (CVBW) outputs the S-Video luma signal on both the S-Video luma output and the CVBS output. A 1 in this
location enables the output of a black and white image on composite video, thereby eliminating the degrading
effects of the color signal (such as dot crawl or false colors), which is useful for viewing text with high accuracy.
Bit 7 (FLFF) controls the flicker filter used in the 7/10’s scaling modes. In these scaling modes, setting FLFF to 1
causes a five line flicker filter to be used. The default setting of 0 uses a four line flicker filter.
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CHRONTEL
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Register Descriptions (continued)
Input Data Format Register
Symbol: IDF
Address: 04H
Bits: 6
Bit:
7
6
5
4
3
2
1
0
DACG
R/W
0
Reserved
IDF3
R/W
0
IDF2
R/W
0
IDF1
R/W
0
IDF0
R/W
0
Symbol:
Type:
R/W
0
Default:
This register sets the variables required to define the incoming pixel data stream.
Table 17. Input Data Format
IDF[3:0]
0000
Description
Not available
Not available
Not available
Not available
0001
0010
0011
0100
0101
0110
12-bit multiplexed RGB (24-bit color) input (“C” multiplex scheme)
12-bit multiplexed RGB (24-bit color) input (“I” multiplex scheme)
Not available
0111
8-bit multiplexed RGB (16-bit color, 565) input
1000
1001-1111
8-bit multiplexed RGB (15-bit color, 555) input
8-bit multiplexed YCrCb (24-bit color) input (Y, Cr and Cb are multiplexed)
Reserved (bit 5): This bit should be set to 0.
DACG (bit 6): This bit controls the gain of the D/A converters. When DACG=0, the nominal DAC current is 71
mA, which provides the correct levels for NTSC and PAL-M. When DACG=1, the nominal DAC current is 76mA,
which provides the correct levels for PAL and NTSC-J.
Clock Mode Register
Symbol: CM
Address: 06H
Bits: 8
Bit:
7
6
5
4
3
2
1
0
CFRB
R/W
0
M/S*
R/W
0
Reserved
MCP
R/W
1
XCM1
R/W
0
XCM0
R/W
0
PCM1
R/W
0
PCM0
R/W
0
Symbol:
Type:
R/W
0
Default:
The setting of the clock mode bits determines the clocking mechanism used in the CH7007. The clock modes are
shown in the table below. PCM controls the frequency of the P-OUT clock, and XCM identifies the frequency of the
XCLK input clock.
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Register Descriptions (continued)
Note: Although it is possible to set the XCM [1:0] and PCM[1:0] values independent of the input data format, there are
only certain combinations of input data format, XCM and PCM, that will result in valid data being demultiplexed at the
input of the device. Refer to the “Input Data Format Register” for these combinations.
Note: Display modes 25 and 26 must use a 2X multiplexed input data format and a 2X XCLK.
Table 18. Clock Mode Register
XCM[1:0]
PCM[1:0]
XCLK
1X
P-Out
1X
Input Data Modes Supported
4, 5, 7, 8, 9
00
00
00
01
01
01
00
01
1X
00
01
1X
1X
2X
4, 5, 7, 8, 9
1X
3X
4, 5, 7, 8, 9
2X
1X
4, 5, 7, 8, 9
2X
2X
4, 5, 7, 8, 9
2X
3X
4, 5, 7, 8, 9
The Clock Mode Register also contains the following bits:
•
MCP (bit 4) determines which edge of the pixel clock output will be used to latch input data. Zero selects the
negative edge, one selects the positive edge.
•
M/S* (bit 6) determines whether the device operates in master or slave clock mode. In master mode (1), the
14.31818MHz clock is used as a frequency reference to the PLL. In slave mode (0) the XCLK input is used as
a reference to the PLL, and is divided by the value specified by XCM[1:0]. The divide by N and M are forced
to one.
•
CFRB (bit 7) sets whether the chroma subcarrier free-runs, or is locked to the video signal. One causes the
subcarrier to lock to the TV vertical rate, and should be used when the ACIV bit is set to zero. Zero causes the
subcarrier to free-run, and should be used when the ACIV bit is set to one.
Start Active Video Register
Symbol: SAV
Address: 07H
Bits: 8
Bit:
7
6
5
4
3
2
1
0
SAV7
SAV6
SAV5
SAV4
SAV3
SAV2
SAV1
SAV0
Symbol:
Type:
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Default:
This register sets the delay in pixel increments from leading edge of horizontal sync, or the rising edge of data start,
to the start of active video. The entire bit field SAV[8:0] is comprised of this register SAV[7:0], plus the MSB value
contained in the position overflow register, bit SAV8. This is decoded as a whole number of pixels, which can be set
anywhere between 0 and 511 pixels. Therefore, in any 2X clock mode, the number of 2X clocks from the leading
edge of sync to the first active data must be a multiple of two clocks. In any 3X clock mode, the number of 3X
clocks from the leading edge of sync to the first active data must be a multiple of three clocks. When using the
DS/BCO pin as a data start input, this register should be set to decimal value 11.
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CHRONTEL
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Register Descriptions (continued)
Position Overflow Register
Symbol: PO
Address: 08H
Bits: 3
Bit:
7
6
5
4
3
2
1
0
SAV8
R/W
0
HP8
R/W
0
VP8
R/W
0
Symbol:
Type:
Default:
This position overflow register contains the MSB values for the SAV, HP and VP values, as follows:
•
•
VP8 (bit 0) is the MSB of the vertical position value (see explanation under “Vertical Position Register”).
HP8 (bit 1) is the MSB of the horizontal position value (see explanation under “Horizontal Position
Register”).
•
SAV8 (bit 2) is the MSB of the start of active video value (see explanation under “Start Active Video
Register”).
Black Level Register
Symbol: BLR
Address: 09H
Bits: 8
Bit:
7
6
5
4
3
2
1
0
BL7
BL6
BL5
BL4
BL3
BL2
BL1
BL0
Symbol:
Type:
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Default:
This register sets the black level. The luminance data is added to this black level, which must be set between 90 and
208, with the default value being 127. Recommended values for NTSC and PAL-M are 127, 105 for PAL and 100
for NTSC-J.
Horizontal Position Register
Symbol: HPR
Address: 0AH
Bits: 8
Bit:
7
6
5
4
3
2
1
0
HP7
HP6
HP5
HP4
HP3
HP2
HP1
HP0
Symbol:
Type:
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Default:
The horizontal position register is used to shift the displayed TV image in a horizontal direction (left or right) to
achieve a horizontally centered image on screen. The entire bit field, HP[8:0] is comprised of this register HP[7:0]
plus the MSB value contained in the position overflow register, bit HP8. Increasing this value moves the displayed
image position RIGHT; decreasing this value moves the displayed image position LEFT. Each increment moves the
image position by 4 input pixels.
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Register Descriptions (continued)
Vertical Position Register
Symbol: VPR
Address: 0BH
Bits: 8
Bit:
7
6
5
4
3
2
1
0
VP7
VP6
VP5
VP4
VP3
VP2
VP1
VP0
Symbol:
Type:
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Default:
This register is used to shift the displayed TV image in a vertical direction (up or down) to achieve a vertically cen-
tered image on screen. This bit field, VP[8:0] represents the TV line number (relative to the VGA vertical sync)
used to initiate the generation and insertion of the TV vertical interval (i.e., the first sequence of equalizing pulses).
Increasing values delay the output of the TV vertical sync, causing the image position to move UP on the TV screen.
Decreasing values, therefore, move the image position DOWN. Each increment moves the image position by one
TV lines (approximately 4 input lines). The maximum value that should be programmed into the VP[8:0] value is
the number of TV lines minus one, divided by two (262, 312 or 313). When panning the image up, the number
should be increased until (TVLPF-1) /2 is reached; the next step should be to reset the register to zero. When pan-
ning the image down the screen, the VP[8:0] value should be decremented until the value zero is reached. The next
step should set the register to (TVLPF-1) /2, and then decrementing can continue. If this value is programmed to a
number greater than (TV lines per frame-1) /2, a TV vertical SYNC will not be generated.
Sync Polarity Register
Symbol: SPR
Address: 0DH
Bits: 4
Bit:
7
6
5
4
3
2
1
0
DES
R/W
0
SYO
R/W
0
VSP
R/W
0
HSP
R/W
0
Symbol:
Type:
Default:
This register provides selection of the synchronization signal input to, or output from, the CH7007.
•
•
•
•
HSP (bit 0) is Horizontal Sync Polarity - an HSP value of zero means the horizontal sync is active low and a
value of one means the horizontal sync is active high.
VSP (bit 1) is Vertical Sync Polarity - a VSP value of zero means the vertical sync is active low and a value of
one means the vertical sync is active high.
SYO (bit 2) is Sync Direction - a SYO value of zero means that H and V sync are input to the CH7007. A
value of one means that H and V sync are output from the CH7007.
DES (bit 3) is Detect Embedded Sync - a DES value of zero means that H and V sync will be obtained from
the direct pin inputs. A DES value of one means that H and V sync will be detected from the embedded codes
on the pixel input stream. Note that this will only be valid for the YCrCb input modes.
Note: When sync direction is set to be an output, horizontal sync will use a fixed pulse width of 64 pixels and vertical
sync will use a fixed pulse width of 1 line.
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CHRONTEL
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Register Descriptions (continued)
Power Management Register
Symbol: PMR
Address: 0EH
Bits: 5
Bit:
7
6
5
4
3
2
1
0
SCART
Reset*
PD2
PD1
PD0
Symbol:
Type:
R/W
0
R/W
1
R/W
1
R/W
0
R/W
1
Default:
This register provides control of the power management functions, a software reset (Reset*) and the SCART output
enable. The CH7007 provides programmable control of its operating states, as described in the table below.
Table 19. Power Management
PD[2:0]
Operating State
Composite Off
Power Down
Functional Description
CVBS DAC is powered down.
000
001
Most pins and circuitry are disabled (except for the buffered clock outputs
which are limited to the 14MHz output and VCO divided outputs).
010
011
S-Video Off
S-Video DACs are powered down.
All circuits and pins are active.
Normal (On)
Full Power Down
2
1XX
All circuitry is powered down except I C circuit.
Reset* (bit 3) is soft reset. Setting this bit will reset all circuitry requiring a power on reset, except for this bit itself
and the I2C state machines.
SCART (bit 4) is the SCART enable. Setting SCART = 0 means the CH7007 will operate normally, outputting Y/C
and CVBS from the three DACs. SCART=1 enables SCART output, which will cause R, G and B to be output from
the DACs and composite sync from the CSYNC pin.
Note: For complete details regarding the operation of these modes, see the Power Management in Functional Description
sections.
Connection Detect Register
Symbol: CDR
Address: 10H
Bits: 4
Bit:
7
6
5
4
3
2
1
0
YT
CT
CVBST
SENSE
Symbol:
Type:
R
0
R
0
R
0
W
0
Default:
The Connection Detect Register provides a means to sense the connection of a TV to either S-Video or Composite
video outputs. The status bits, YT, CT, and CVBST correspond to the DAC outputs for S-Video (Y and C outputs)
and Composite video (CVBS), respectively. However, the values contained in these status bits are NOT VALID
until a sensing procedure is performed. Use of this register requires a sequence of events to enable the sensing of
outputs, then reading out the applicable status bits. The detection sequence works as follows:
1. Ensure the power management register bits 2-0 are set to 011 (normal mode).
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CH7007A
Register Descriptions (continued)
2. Ensure that the XCLK and XCLK* input pins are receiving clock signals (alternatively, XCLK* can be
connected to the VREF pin).
3. Set the SENSE bit to a 1. This forces a constant current output onto the Y, C, and CVBS outputs. Note that
during SENSE = 1, these 3 analog outputs are at steady state and no TV synchronization pulses are asserted.
4. Reset the SENSE bit to 0. This triggers a comparison between the voltage sensed on these analog outputs
and the reference value expected (Vthreshold = 1.235V). If the measured voltage is below this threshold
value, it is considered connected, if it is above this voltage it is considered unconnected. During this step,
each of the three status bits corresponding to individual analog outputs will be set if they are NOT
connected.
5. Read the status bits. The status bits Y, C and CVBST (corresponding to S-Video Y and C outputs and
composite video) now contain valid information which can be read to determine which outputs are
connected to a TV. Again, a “0” indicates a valid connection, a “1” indicates an unconnected output.
Contrast Enhancement Register
Symbol: CE
Address: 11H
Bits: 3
Bit:
7
6
5
4
3
2
1
0
CE2
CE1
CE0
Symbol:
Type:
R/W
0
R/W
1
R/W
1
Default:
This register provides control of the contrast enhancement feature of the CH7007, according to the table below. At a
setting of 000, the video signal will be pulled towards the maximum black level. As the value of CE[2:0] is
increased, the amount that the signal is pulled towards black is decreased until unity gain is reached at a setting of
011. From this point on, the video signal is pulled towards the white direction, with the effect increasing with
increasing settings of CE[2:0].
Table 20. Contrast Enhancement Function
CE[2:0]
000
Description (all gains limited to 0-255)
Contrast enhancement gain 3 Y = (5/4)*(Y -102) = Enhances Black
out
in
001
Contrast enhancement gain 2 Y = (9/8)*(Y -57)
out in
010
Contrast enhancement gain 1 Y = (17/16)*(Y -30)
out in
011
Normal mode Y = (1/1)*(Yin-0) = Normal Contrast
out
100
Contrast enhancement gain 1 Y = (17/16)*(Y -0)
out in
101
Contrast enhancement gain 2 Y = (9/8)*(Y -0)
out in
110
111
Contrast enhancement gain 3 Y = (5/4)*(Y -0)
out in
Contrast enhancement gain 4 Y = (3/2)*(Y -0) = Enhances White
out
in
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CHRONTEL
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Register Descriptions (continued)
256
224
192
160
128
96
64
32
0
0
32
64
96
128
160
192
224 256
Figure 24: Luma Transfer Function at different contrast enhancement settings.
PLL Overflow Register
Symbol: MNE
Address: 13H
Bits: 5
Bit:
7
6
5
4
3
2
1
0
Reserved
Reserved
N9
N8
M8
Symbol:
Type:
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Default:
The PLL Overflow Register contains the MSB bits for the’M’ and ’N’ values, which will be described in the PLL-M
and PLL-N registers, respectively. The reserved bits should not be written to.
PLL M Value Register
Symbol: PLLM
Address: 14H
Bits: 8
Bit:
7
6
5
4
3
2
1
0
M7
R/W
0
M6
R/W
1
M5
R/W
0
M4
R/W
0
M3
R/W
0
M2
R/W
0
M1
R/W
0
M0
R/W
1
Symbol:
Type:
Default:
The PLL M value register determines the division factor applied to the frequency reference clock before it is input to
the PLL phase detector when the CH7007 is operating in master mode. In slave mode, an external pixel clock is
used instead of the frequency reference, and the division factor is determined by the XCM[1:0] value. This register
contains the lower 8 bits of the complete 9-bit M value.
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Register Descriptions (continued)
PLL N Value Register
Symbol: PLLN
Address: 15H
Bits: 8
Bit:
7
6
5
4
3
2
1
0
N7
R/W
1
N6
R/W
0
N5
R/W
0
N4
R/W
0
N3
R/W
0
N2
R/W
0
N1
R/W
0
N0
R/W
0
Symbol:
Type:
Default:
The PLL N value register determines the division factor applied to the VCO output before being applied to the PLL
phase detector, when the CH7007 is operating in master mode. In slave mode, the value of ‘N’ is always 1. This
register contains the lower 8 bits of the complete 10-bit N value. The pixel clock generated in a master mode and is
calculated according to the equation below:
Fpixel = Fref* [(N+2) / (M+2)]
When using a 14.318 MHz frequency reference, the required M and N values for each mode are shown in the table
below
Table 21. M and N Values for Each Mode
Mode
VGA Resolution, TV
Standard, Scaling Ratio
N 10-
bits
M 9-
bits
Mode
VGA Resolution, TV
Standard, Scaling Ratio
N 10-
bits
M 9-
bits
14
15
16
17
18
19
20
21
22
23
24
25
26
640x480, PAL, 1:1
640X480, PAL, 5:6
640X480, NTSC, 1:1
640X480, NTSC, 7:8
640X480, NTSC, 5:6
800X600, PAL, 1:1
800X600, PAL, 5:6
800X600, PAL, 3:4
800X600, NTSC, 5:6
800X600, NTSC, 3:4
800X600, NTSC, 7:10
720X576, PAL, 1:1
720X480, NTSC, 1:1
9
4
3
0
1
512x384, PAL, 5:4
512x384, PAL, 1:1
512X384, NTSC, 5:4
512X384, NTSC, 1:1
720X400, PAL, 5:4
720X400, PAL, 1:1
720X400, NTSC, 5:4
720X400, NTSC, 1:1
640X400, PAL, 5:4
640X400, PAL, 1:1
640X400, NTSC, 5:4
640x400, NTSC, 1:1
640X400, NTSC, 7:8
640X480, PAL, 5:4
20
9
13
4
9
89
63
26
138
63
33
61
3
110
126
190
647
86
63
63
89
313
33
103
33
19
89
33
33
2
126
110
53
3
4
5
339
106
70
6
284
94
7
8
108
9
62
9
63
11
302
31
10
11
12
13
94
22
89
13
31
190
20
Buffered Clock Output Register
Symbol: BCO
Address: 17H
Bits: 6
Bit:
7
6
5
4
3
2
1
0
SHF2
SHF1
R/W
0
SHF0
SCO2
SCO1
SCO0
R/W
0
Symbol:
Type:
R/W
0
R/W
0
R/W
0
R/W
0
Default:
When this pin is selected to be an output, the buffered clock output register determines which clock is selected to be
output at the DS/BCO clock output pin and what frequency value is output when a VCO derived signal is output.
The tables below show the possible outputs.
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CHRONTEL
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Register Descriptions (continued)
Table 22. Clock Output Selection
SCO[2:0]
000
Buffered Clock Output
14MHz crystal
001
(for test use only)
010
VCO divided by K3 (seeTable23)
Field ID signal
011
100
(for test use only)
101
(for test use only)
110
TV horizontal sync (for test use only)
TV vertical sync (for test use only)
111
Table 23. K3 Selection
SHF[2:0]
000
K3
2.5
3.5
4
010
011
100
4.5
5
101
110
6
111
7
Subcarrier Value Registers
Symbol: FSCI
Address: 18H - 1FH
Bits: 4 or 8 each
Bit:
7
6
5
4
3
2
1
0
FSCI#
FSCI#
FSCI#
FSCI#
Symbol:
Type:
R/W
R/W
R/W
R/W
Default:
The lower four bits of registers 18H through 1FH contain a 32-bit value which is used as an increment value for the
ROM address generation circuitry. The bit locations are specified as the following:
Register
18H
19H
1AH
1BH
1CH
1DH
1EH
Contents
FSCI[31:28]
FSCI[27:24]
FSCI[23:20]
FSCI[19:16]
FSCI[15:12]
FSCI[11:8]
FSCI[7:4]
1FH
FSCI[3:0]
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CHRONTEL
Register Descriptions (continued)
CH7007A
When the CH7007 is operating in the master clock mode, the tables below should be used to set the FSCI registers.
When using these values, the ACIV bit in register 21H should be set to “0” and the CFRB bit in register 06H should
be set to “1”.
Table 24. FSCI Values (525-Line Modes)
NTSC
“Normal Dot Crawl”
NTSC
“No Dot Crawl”
PAL-M
“Normal Dot Crawl”
Mode
2
763,363,328
623,153,737
574,429,782
463,962,517
646,233,505
516,986,804
452,363,454
623,153,737
545,259,520
508,908,885
521,957,831
469,762,048
428,554,851
569,408,543
763,366,524
623,156,346
574,432,187
463,964,459
646,236,211
5165,988,968
452,365,347
623,156,346
545,261,803
508,911,016
521,960,016
469,764,015
438,556,645
569,410,927
762,524,467
622,468,953
573,798,541
463,452,668
645,523,358
516,418,687
451,866,351
622,468,953
544,660,334
508,349,645
521,384,251
469,245,826
428,083,911
568,782,819
3
6
7
10
11
12
16
17
18
22
23
24
26
Table 25. FSCI Values (625-Line Modes)
PAL
PAL-N
Mode
0
“Normal Dot Crawl”
806,021,060
644,816,848
601,829,058
485,346,014
677,057,690
537,347,373
806,021,060
644,816,848
537,347,373
645,499,916
528,951,320
488,262,757*
705,268,427
“Normal Dot Crawl”
651,209,077
520,967,262
486,236,111
392,125,896
547,015,625
434,139,385
651,209,077
520,967,262
434,139,385
521,519,134
427,355,957
394,482,422
569,807,942
1
4
5
8
9
13
14
15
19
20
21
25
When the CH7007 is operating in the slave clock mode, the ACIV bit in register 21H should be set to “1” and the
CFRB bit in register 06H should be set to “0”.
*Note: For reduced cross-color and cross-luminance artifacts, a value of 488,265,597 can be used with CFRB = "0"
& ACIV = "0".
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CHRONTEL
CH7007A
Register Descriptions (continued)
Symbol:
Address: 1BH
Bits: 8
Bit:
7
6
5
4
3
2
1
0
GPIOIN1
GPIOIN0
DVDD2
R/W
0
P-OUTP
FSCI19
R/W
0
FSCI18
R/W
0
FSCI17
R/W
0
FSCI16
R/W
0
Symbol:
Type:
R/W
0
R/W
0
R/W
0
Default:
Register 1BH, bit 4 (P-OUTP) controls the polarity of the P-OUT pin.
Register 1BH, bit 5 controls the P-OUT drive level, and should be set to 0 when DVDD2 is 1.8V, and set
to 1 when DVDD2 is 3.3V.
Register 1BH, bits 7 and 6 control the GPIO pins. When the corresponding GOENB bits are low, these
registers values are driven out of the GPIO pins. When the corresponding GOENB bits are high, these
registers values can be read to determine the level forced into the GPIO pins.
Symbol:
Address: 1CH
Bits: 6
Bit:
7
6
5
4
3
2
1
0
GOENB1
GOENB0
DSM
R/W
1
DSEN
R/W
1
FSCI15
R/W
0
FSCI14
R/W
0
FSCI13
R/W
0
FSCI12
R/W
0
Symbol:
Type:
R/W
1
R/W
1
Default:
Register 1CH, bit 4 controls whether the Data Start pin or the Horizontal Sync pin is used to determine the
start of active video. When this bit is low, the pin continues to operate as the BCO pin described in the
BCO register section. When this bit is high the pin becomes an input for the Data Start signal. A value of
0 is recommended if H syn is used as a reference to active video and the DSM bit5 also need to be set to
0.
Register 1CH, bit 5 determines how the Data Start input is used. A value of 0 is recommended, if DSEN
bit4 is set to 0.
Register 1CH, bits 7and 6 control the GPIO pins direction. When a GOENB bit is low, the corresponding
GPIO pin is an output pin. When a GOENB bit is high, the corresponding GPIO pin can be read to deter-
mine the level forced into it.
42
201-0000-002 Rev. 2.7, 08/23/2000
CHRONTEL
CH7007A
Register Descriptions (continued)
PLL Control Register
Symbol: PLLC
Address: 20H
Bits: 6
Bit:
7
6
5
4
3
2
1
0
PLLCPI
R/W
0
PLLCAP
PLLS
R/W
1
PLL5VD
PLL5VA
R/W
1
MEM5V
R/W
0
Symbol:
Type:
R/W
0
R/W
0
Default:
The following PLL and memory controls are available through the PLL control register:
MEM5V
PLL5VA
PLL5VD
PLLS
MEM5V should be set to 0 when DVDD is 3.3 volts, and 1 when DVDD is 5 volts.
PLL5VA is set to 1 when AVDD is 5 volts.
PLL5VD is set to 1 when DVDD is 5 volts. A value of 0 is used when DVDD is 3.3 volts (default).
When the PLL5VA is 1 PLLS should be 1. When PLL5VA is 0 PLLS should be 0.
PLLCAP
PLLCAP controls the loop filter capacitor of the PLL. A recommended listing of PLLCAP vs
Mode is shown below.
PLLCPI
The default value should be used.
201-0000-002 Rev. 2.7, 08/23/2000
43
CHRONTEL
CH7007A
Register Descriptions (continued)
Table 26. PLL Capacitor Setting
Mode
PLLCAP
Value
0
1
1
1
1
0
1
0
1
1
0
1
1
1
0
1
1
1
0
0
0
0
1
0
1
1
0
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
44
201-0000-002 Rev. 2.7, 08/23/2000
CHRONTEL
CH7007A
CIV Control Register
Symbol: CIVC
Address: 21H
Bits: 5
Bit:
7
6
5
4
3
2
1
0
CIV25
CIV24
CIVH1
CIVH0
ACIV
Symbol:
Type:
R
0
R
0
R/W
0
R/W
0
R/W
1
Default:
The following controls are available through the CIV control register:
ACIV
When the automatic calculated increment value is 1, the number calculated and present at the CIV
registers will automatically be used as the increment value for subcarrier generation, removing the
need for the user to read the CIV value and write in a new FSCI value. Whenever this bit is set to
1, the subcarrier generation must be forced to free-run mode (CFRB = 0).
CIVH[1:0]
CIV[25:24]
These bits control the hysteresis circuit which is used to calculate the CIV value.
See descriptions in the next section.
Calculated Increment Value Register
Symbol: CIV
Address: 22H - 24H
Bits: 8
Bit:
7
6
5
4
3
2
1
0
CIV#
CIV#
CIV#
CIV#
CIV#
CIV#
CIV#
CIV#
Symbol:
Type:
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Default:
The CIV registers 22H through 24H contain a 26-bit value, which is the calculated increment value that should be
used as the upper 26 bits of FSCI. This value is determined by a comparison of the pixel clock and the 14MHz
clock. The bit locations and calculation of CIV are specified as the following:
Register
21H
22H
23H
24H
Contents
CIV[25:24]
CIV[23:16]
CIV[15:8]
CIV[7:0]
Version ID Register
Symbol: VID
Address: 25H
Bits: 8
Bit:
7
6
5
4
3
2
1
0
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Symbol:
Type:
R
0
R
1
R
0
R
1
R
0
R
0
R
0
R
0
Default:
This read-only register contains a 8-bit value indicating the identification number assigned to this version of the
CH7007. The default value shown is pre-programmed into this chip and is useful for checking for the correct
version of this chip, before proceeding with its programming.
201-0000-002 Rev. 2.7, 08/23/2000
45
CHRONTEL
CH7007A
Address Register
Symbol: AR
Address: 3FH
Bits: 6
Bit:
7
6
5
4
3
2
1
0
Reserved
Reserved
AR5
AR4
AR3
AR2
AR1
AR0
Symbol:
Type:
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
Default:
The Address Register points to the register currently being accessed.
46
201-0000-002 Rev. 2.7, 08/23/2000
CHRONTEL
CH7007A
Electrical Specifications
Table 27. Absolute Maximum Ratings
Symbol
Description
relative to GND
Min
- 0.5
Typ
Max
Units
V
7.0
V
DD
1
Input voltage of all digital pins
GND - 0.5
VDD + 0.5
V
Sec
°C
TSC
TAMB
TSTOR
TJ
Analog output short circuit duration
Ambient operating temperature
Storage temperature
Indefinite
- 55
- 65
85
150
150
220
°C
Junction temperature
°C
Vapor phase soldering (one minute)
TVPS
°C
Notes:
1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the
device. These are stress ratings only. Functional operation of the device at these or any other conditions
above those indicated under the normal operating condition of this specification is not recommended.
Exposure to absolute maximum rating conditions for extended periods my affect reliability.
2. The device is fabricated using high-performance CMOS technology. It should be handled as an ESD
sensitive device. Voltage on any signal pin that exceeds the power supply voltages by more than ± 0.5V can
induce destructive latch.
Table 28. Recommended Operating Conditions
Symbol
VDD
Description
DAC power supply voltage
Min
4.75
4.75
3.1
Typ
5.00
5.00
3.3
Max
5.25
5.25
3.6
Units
V
AVDD
DVDD
DVDD2
Analog supply voltage
Digital supply voltage
Digital supply voltage (P-OUT pin) VGA controller
interface = 1.8V
1.7
1.8
1.9
V
Digital supply voltage (P-OUT pin) VGA controller
interface = 3.3V
3.1
3.3
3.6
DVDD2
RL
V
Output load to DAC outputs
37.5
W
Table 29. Electrical Characteristics (Operating Conditions: TA = 0oC - 70oC, VDD = 5V ± 5%)
Video D/A resolution
Full scale output current
Video level error
9
9
9
Bits
mA
%
33.89
10
VDD & AVDD (5V) current (simultaneous S-Video
& composite outputs)
105
mA
DVDD (3.3V) current
45
4
mA
mA
DVDD2 (1.8V) current (15pF load)
201-0000-002 Rev. 2.7, 08/23/2000
47
CHRONTEL
CH7007A
Timing Information
V
OH
P-OUT
V
OL
t36
t38
t39
t39
V
OH
XCLK
V
OL
V
OH
XCLK*
V
OL
t37
V
OH
D[11:0]
P0a
P0b
P1a
P1b P2a
P2b
V
OL
t37
t40
V
OH
DS
V
OL
t37
t40
V
OH
H
64 P-OUT
V
OL
V
OH
V
1 VGA
Line
V
OL
t40
t40
DVDD
CK
(Internal Clock)
DGND
DVDD
CKB
(Internal Clock)
DGND
DVDD
PCLKX
(Internal Clock)
DGND
Symbol
VOH
Parameter
Output High level of interface signals
Min
Typ
Max
Unit
DVDD2 - 0.2
DVDD2 + 0.2
V
V
VOL
Output Low level of interface signals
(P-OUT = VREF) to (XCLK = XCLK*) Delay
Setup and Hold time:
Differential Clock: (XCLK = XCLK*) to (D[11:0], H, V & DS = VREF)
Single-ended Clock: (XCLK =VREF) to (D[11:0], H, V & DS = VREF)
-0.2
2
0.2
9
t36
nS
nS
1.5
t37
t38
XCLK & XCLK* rise/fall time w/15pF load
P-OUT rise/fall time w/15pF load, VREF = 1.65 V
D[11:0], H, V & DW rise/fall time w/15pF load
Digital I/O Supply Voltage
1
3
3
2
7
nS
nS
nS
V
t39
t40
DVDD2
1.7
3.6
48
201-0000-002 Rev. 2.7, 08/23/2000
CHRONTEL
CH7007A
Table 30. Digital Inputs / Outputs
Symbol
Description
SD Output
Test Condition
IOL = 2.0 mA
Min
Typ
Max
Unit
V
0.4
V
SDOL
Low Voltage
SD Input
V
2.7
VDD + 0.5
1.4
V
V
V
V
V
V
IICIH
IICIL
High Voltage
SD Input
V
GND-0.5
Vref+0.25
GND-0.5
2.8
Low Voltage
V
DATAIH
V
DATAIL
D[0-11] Input
High Voltage
D[0-11] Input
Low Voltage
P-OUT Output
High Voltage
DVDD+0.5
Vref-0.25
V
IOL = - 400 mA
P-OUTOH
P-OUTOL
V
P-OUT Output
Low Voltage
IOL = 3.2 mA
0.2
Note:
V IIC -refers to I2C pins SD and SC.
V DATA - refers to all digital pixel and clock inputs.
V SD - refers to I2C pin SD as an output.
V P-OUT- refers to pixel data output Time - Graphics.
ORDERING INFORMATION
Part number
CH7007A-V
CH7007A-T
Package type
PLCC
Number of pins
Voltage supply
3V/5V
44
44
TQFP
3V/5V
Chrontel
2210 O’Toole Avenue
San Jose, CA 95131-1326
Tel: (408) 383-9328
Fax: (408) 383-9338
www.chrontel.com
E-mail: sales@chrontel.com
Ó1998 Chrontel, Inc. All Rights Reserved.
Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE
SPECIFIC WRITTEN CONSENT OF Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used as directed can reasonably
expect to result in personal injury or death. Chrontel reserves the right to make changes at any time without notice to improve and supply the best possible product and is not
responsible and does not assume any liability for misapplication or use outside the limits specified in this document. We provide no warranty for the use of our products and assume no
liability for errors contained in this document. Printed in the U.S.A.
201-0000-002 Rev. 2.7, 08/23/2000
49
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