CL10K50SQC240-2X [ETC]

FPGA ; FPGA产品将打


型号：	CL10K50SQC240-2X
厂家：	ETC
描述：	FPGA FPGA产品将打
文件：	总18页 (文件大小：195K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LIBERATOR

CL10K50S

Key Features

u Fully Compatible to the Altera^®FLEX^®10KS Family

u Prototype Your System With Altera FPGAs

u Seamlessly Migrate Production To Clear Logic

u No ASIC Engineering, No NRE, And No Test Vector

Development

u Very Fast, Dense Signal Routing Using Vertical Link

Interconnect

u "Gate Array" Option Eliminates Configuration EPROMs

u Fabricated Using 0.25 Micron CMOS Process

u Very Low Power Consumption (Active And Standby)

u High Density

50,000 Usable Gates

2,880 Logic Elements

40,960 RAM Bits

254 Maximum User I/O Pins

CL10KE Product Family Overview

CL10K50E

CL10K50S

CL10K200E

CL10K200S

Parameter

CL10K30E

CL10K100E

Typical Gates

30,000

50,000

100,000

200,000

(Logic and RAM)

Maximum System Gates

Logic Elements

119,000

1,728

199,000

2,880

257,000

4,992

513,000

9,984

Embedded Array Blocks

Total RAMBits

24,576

220

40,960

254

49,152

338

98,304

470

Max User I/O pins

Speed Grades

-1, -2, -3

144-pin TQFP

208-pin PQFP

240-pin PQFP

256-pin FBGA

356-pin SBGA

484-pin FBGA

208-pin PQFP

240-pin PQFP

256-pin FBGA

356-pin SBGA

484-pin FBGA

240-pin PQFP

356-pin SBGA

484-pin FBGA

600-pin SBGA

672-pin FBGA

144-pin TQFP

208-pin PQFP

256-pin FBGA

484-pin FBGA

Packages

10KEtbl 01

May 2001

Page 1

LIBERATOR CL10K50S (PRELIMINARY)

The LIBERATOR CL10KS family offers you all of the time-to-

Description

market benefits of designing with programmable logic. Simply

use Altera FLEX 10KS FPGAs to prototype and verify the design.

Then, take five minutes to submit the bitstream using Clear

Logic's web site! Within eight weeks, your system can be in

volume production using compatible Clear Logic devices.

LIBERATOR technology frees you to completely design,

prototype, and verify your custom logic using Altera FLEX 10KS

products. Clear Logic's innovative technology eliminates NRE

costs, test vector development, ordering minimums, and long lead

times. No re-simulation or re-layout is required, because Clear

Logic offers an architecture that is exactly compatible to the

functionality of the FPGA prototype. Clear Logic's NoFault^®test

technology ensures complete test coverage through the use of

special scan test registers.

The LIBERATOR family is based upon an array of logic

elements. Each logic element contains a configurable look-up

table for combinatorial functions and a register for sequential

operations. Eight logic elements in a group form a block. Logic

functions and signal routing are defined by Clear Logic's

proprietary vertical metal links.

Laser-based configuration allows quick-turn prototyping and

eliminates NRE costs for photomasks. Inherent CL10KS family

performance benefits include extremely consistent propagation

delays, reduced power consumption, and improved immunity to

noise and upset events.

Configuration

The "Gate Array" configuration mode eliminates the need for

external EPROMs or software configuration. The LIBERATOR

device is already factory-configured when it is shipped. When

using the device in the "Gate Array" mode, it powers up fully

configured. In this mode, if the customer selects INIT_DONE

option, this pin will always be high.

Page 2

LIBERATOR CL10K50S (PRELIMINARY)

Additional

Information

For further information on designing with the LIBERATOR

family, please refer to these documents:

u AN-01: Requesting a First Article. This document provides

instructions on how to request first articles by submitting a

bitstream file to Clear Logic's web site.

u AN-02: Clear Logic Packaging Guide. This document provides

specifications and drawings for packages used by the CL10K

family and other Clear Logic devices.

u AN-13: LIBERATOR -- A New Way To Design. This document

describes the most efficient path for custom logic designs up

to 200K gates using FPGA design techniques and going to

production with Clear Logic.

u AN-14: CL10K Technology White Paper. This document

outlines the technologies employed by the LIBERATOR

family.

u AN-15: LIBERATOR System Configuration. This document

contains a detailed discussion of all aspects of configuring

CL10K-based systems.

u AN-16: Introduction to the Clear Logic Verilog Model

Generator. Clear Logic now has Verilog models of your FPGA

converted design. Learn what it is and how it can help you.

u AN-17: Clear Logic LIBERATOR Design Models. This

document outlines the capabilities and freedom available in

the Clear Logic Verilog and VHDL design models.

u AN-18: Debugging Designs Using Clear Logic Models. This

document shows the enhanced troubleshooting capabilities

that the Clear Logic LIBERATOR Verilog/VHDL design

models bring to the system debugging process.

Page 3

LIBERATOR CL10K50S (PRELIMINARY)

Block Diagram

Embedded Array Block (EAB)

I/O Element

IOE IOE IOE IOE

IOE IOE

IOE

(IOE)

IOE

Logic Array

Column

Interconnect

EAB

Logic Building

Block (LBB)

IOE

Logic Element (LE)

IOE

EAB

Row

Local Interconnect

Interconnect

Logic

Array

10KE drw 01

IOE IOE

IOE IOE IOE IOE

Logical Memory Array (LMA)

Page 4

LIBERATOR CL10K50S (PRELIMINARY)

Pin Configuration

Pin Name

144-Pin TQFP

208-Pin PQFP

240-Pin PQFP

MSEL0

108

107

124

123

MSEL1

nSTATUS

nCONFIG

DCLK

105

155

121

179

107

CONF_DONE

INIT_DONE

nCE

106

154

178

nCEO

nWS

142

141

144

143

206

204

208

207

238

236

240

239

nRS

nCS

RDYnBSY

CLKUSR

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0

116

114

113

112

111

110

109

108

166

164

162

161

159

158

157

156

190

188

186

185

183

182

181

180

10K50S tbl 01A

Page 5

LIBERATOR CL10K50S (PRELIMINARY)

Pin Configuration

Pin Name

144-Pin TQFP

208-Pin PQFP

240-Pin PQFP

TDI

105

153

177

TDO

TCK

TMS

TRST

Dedicated Inputs

Dedicated Clock Pins

DEV_CLRn

54, 56, 124, 126

55, 125

122

78, 80, 182, 184

79, 183

180

90, 92, 210, 212

91, 211

209

DEV_OE

128

186

213

6, 23, 35, 43, 76, 106, 109,

117, 137, 145, 181

5, 27, 47, 96, 122, 130, 150,

170

VCCINT

6, 25, 52, 53, 75, 93, 123

5, 22, 34, 42, 66, 84, 98, 110, 16, 37, 57, 77, 112, 140, 160,

VCCIO

5, 24, 45, 61, 71, 94, 115, 134

118, 138, 146, 165, 178, 194

189, 205, 224

VCC_CKLK

20, 21, 32, 33, 48, 49, 59, 72, 10, 22, 32, 42, 52, 69, 85, 93,

15, 16, 40, 50, 58, 66, 84, 85,

103, 104, 127, 129, 139

GNDINT

82, 91, 123, 124, 129, 130,

151, 152, 171, 185, 188, 201

104, 125, 135, 145, 155, 165,

176, 197, 216, 232

GND_CKLK

No Connect

Total user I/O Pins

102

147

189

10K50S tbl 01B

Page 6

LIBERATOR CL10K50S (PRELIMINARY)

Pin Configuration

Pin Name

256-Pin FBGA

356-Pin SBGA

484-Pin FBGA

MSEL0

MSEL1

nSTATUS

nCONFIG

DCLK

T16

D24

W19

AC5

CONF_DONE

INIT_DONE

nCE

C15

G16

AC24

T24

F18

K19

AC2

nCEO

B16

B14

C14

A16

A15

G14

D15

AC22

AE24

AE23

AD24

AD23

U22

E19

nWS

E17

nRS

F17

nCS

D19

D18

RDYnBSY

CLKUSR

DATA7

K17

AA24

AF4

G18

DATA6

AD8

DATA5

AE5

DATA4

AD6

DATA3

AF2

DATA2

AD5

DATA1

AD4

DATA0

AD3

TDI

AC3

TDO

C16

B15

P15

R16

B9, E8, M9, R9

A9, L8

AC23

AD25

D22

F19

TCK

E18

TMS

U18

V19

TRST

D23

Dedicated Inputs

Dedicated Clock Pins

A13, B14, AF14, AE13

A14, AF13

E12, H11, R12, V11

D12, P11

10K50S tbl 01C

Page 7

LIBERATOR CL10K50S (PRELIMINARY)

Pin Configuration

Pin Name

256-Pin FBGA

356-Pin SBGA

AD13

484-Pin FBGA

DEV_CLRn

G11

F12

DEV_OE

VCCINT

AE14

C11, C15, H14, J8, J10, J12,

J15, L9, L10, L13, M10, M13,

M14, N12, P8, P10, P15, R14,

V5, W21, Y8, AA12

E11, F5, F7, F9, F12, H6, J7,

J10, J11, K9, L5,L7, L12, M11,

A1, A26, C14, C26, D5, F1,

H22, J1, M26, N1, T26, U5,

AA1, AD26, AF1, AF26

A6, A13, B5, E1, G1, G15, H9,

H20, J11, J13, K9, K11, K14,

K20, L14, M9, N3, N9, N11,

N14, N20, P13, R1, R9, T3,

T15, T22, V22, AB13

A7, A23, B3, C15, D25, F4,

H24, K5, M23, P2, T25, V2,

W22, AB1, AC25, AD18MAF3,

AF7, AF16

D12, E6, F8, F10, G6, G8, G11,

H11, J6, K6, K8, K11, L10, M6,

N12

VCCIO

VCC_CKLK

C14

P12

A1, A8, A22, B1, B2, B17, B21,

B22, C2, C21, E21, G3, G21,

A2, A10, A20, B1, B13, B22,

B25, B26, C2, C9, C13, C25, H2, H8, H15, J9, J14, J20, K3,

H23, J26, K1, M1, N26, R1, K10, K12, K13, L11, L12, M11,

R26, T1, U26, W1, AD2, AD14, M12, M20, N10, N13, P9, P14,

AD20, AE1, AE2, AE7, AE25, R8, R15, R22, T1, V3, W20, Y1,

E5, E12, F6, F11, G7, G9, G10,

H8, H9, J8, J9, K7, K10, L6,

L11, M5, M12

GND

AE26, AF11, AF19, AF25

Y2, Y3, Y21, Y22, AA1, AA6,

AA22, AB11, AB16

GND_CKLK

B13

W11

A2, A3. A4. A5, A7, A9, A11,

A12, A14, A15, A20, A21, B3,

B4, B9, B10, B12, B16, B19,

B20, C1, C6, C9, C10, C12,

C13, C14, C16, C17, C22, D1,

D2, D3, D20, D21, E2, E3,

E20, E22, F1, F2, F20, F21,

G2, G20, G22, J1, J2, J3, J21,

K1, K2, K22, L1, L2, L20, L22,

M2, M3, M22, N1, N2, N21,

N22, P3, P20, P21, P22, R2,

R3, R21, T2, T20, T21, U1, U2,

U3, U20, U21, U22, V2, V20,

W1, W2, W22, Y4, Y9, Y12,

Y13, Y16, Y19, Y20, AA2, AA3,

AA4, AA9, AA11, AA13, AA15,

AA21, AB1, AB2, AB3, AB4,

AB5, AB7, AB8, AB9, AB12,

AB15, AB17, AB18, AB19,

AB20, AB21, AB22

D1, E2, E22, E25, F5, F23,

F26, G3, G22. G25, H4, H5, J2,

J4, J23, J24, K2, K3, K25, K26,

L2, L23, L26, M2, M5, M22,

M25, N4, N25, P1, P5, P22,

P23, R5, T22, U2, U3, U23,

U24, V4, W3, W4, W24, W26,

Y2, Y5, AA3, AA22, AA25, AB3,

AB5, AB22, AB24, AB26

No Connect

Total user I/O Pins

191

220

254

10K50S tbl 01D

Page 8

LIBERATOR CL10K50S (PRELIMINARY)

DC Electrical Specifications

Absolute Maximum Ratings

Symbol

Parameter

Conditions

Min

-0.5

-2.0

-25

Max

3.6

Unit

V_CC

Supply Voltage

DC Input Voltage^[1]

5.75

I_OUT

T_STG

T_AMB

T_J

DC Output Current, per Pin

Storage Temperature

Ambient Temperature

Junction Temperature

°C

No Bias

-65

150

135

Under Bias

-65

10KEtbl 02

[2]

Recommended Operating Conditions

Symbol

Parameter

Conditions

Min

Max

Unit

V_CCINT

Supply Voltage, Internal Logic and Input Buffers

Commercial Grade Devices

2.375

2.625

Industrial Grade Devices

V_CCIO

DC Input Voltage for 3.3VOperation

Commercial Grade Devices

Industrial Grade Devices

3.00

3.60

V_CCIO

DC Input Voltage for 2.5VOperation

Commercial Grade Devices

Industrial Grade Devices

2.375

2.625

Input Voltage

-0.5

5.75

V_O

T_A

Output Voltage

VCCIO

Operating Temperature

Commercial Temperature Range

Industrial Temperature Range

-40

°C

t_R

t_F

Input Signal Rise Time

Input Signal Fall Time

10KEtbl 03B

Page 9

LIBERATOR CL10K50S (PRELIMINARY)

DC Electrical Specifications cont.

DC Electrical Characteristics (over the operating range)

Typ^[3]

Symbol

Parameter

Input HIGH Voltage

Input LOW Voltage

Conditions

Min

Max

5.75

Unit

Lower of

1.7 or 0.5

x V_CCINT

-0.5

2.4

0.3 x V_CCIO

3.3-VHigh-Level TTL Output

Voltage

I_OH= -8 mADC, V_CCIO= 3.00 V

I_OH= -0.1 mADC, V_CCIO= 3.00 V

3.3-VHigh-Level CMOS

Output Voltage

V_CCIO-0.2

3.3-VHigh-Level PCI Output

Voltage

I_OH= -0.5 mADC, V_CCIO= 3 to 3.60 V 0.9 x V_CCIO

V_OH

I_OH= -0.1 mADC, V_CCIO= 2.30 V

I_OH= -1 mADC, V_CCIO= 2.30 V

I_OH= -2 mADC, V_CCIO= 2.30 V

I_OL= 9 mADC, V_CCIO= 3.00 V

I_OL= 0.1 mADC, V_CCIO= 3.00 V

I_OL= 1.5 mADC, V_CCIO= 3 to 3.60 V

I_OL= 0.1 mADC, V_CCIO= 2.30 V

I_OL= 1 mADC, V_CCIO= 2.30 V

I_OL= 2 mADC, V_CCIO= 2.30 V

2.1

2.0

1.7

2.5-VHigh-Level Output

Voltage

3.3-VLow-Level TTL Output

Voltage

0.45

0.2

3.3-VLow-Level CMOS

Output Voltage

3.3-VLow-Level PCI Output

Voltage

0.1 x V_CCIO

0.2

V_OL

2.5-VLow-Level Output

Voltage

0.4

0.7

I_IN

I_OZ

Input Leakage Current

Output Leakage Current

Standby Current

V = 5.3Vto -0.3V

-10

µA

V_O= 5.3Vto -0.3V

I_CC0

V = GND, No Load

10KEtbl 04

Capacitance^[4]

Symbol

C_IN

Parameter

Input Capacitance

Output Capacitance

Conditions

Min

Max

Unit

V = 0 V, f = 1.0 MHz

C_OUT

V_OUT= 0 V, f = 1.0 MHz

10KEtbl 05

Page 10

LIBERATOR CL10K50S (PRELIMINARY)

AC Electrical Specifications

I/O Element Timing Parameters ^[5]

Speed: -1

Speed: -2

Speed: -3

Symbol

Parameter

Min

Max

Min

Max

Min

Max Unit

t_IOD

IOE Register Data Delay

2.4

0.3

0.2

0.5

2.8

0.3

0.2

0.6

3.8

t_IOC

IOE Register Control Signal Delay

IOE Register Clock to Output Delay

0.5

0.3

0.8

t_IOCO

t_IOCOMBIOE Combinatorial Delay

t_IOSUIOE Register Setup Time Before Clock

t_IOH

2.2

0.5

2.6

0.6

3.5

0.8

IOE Register Hold Time After Clock

IOE Register Clear Delay

t_IOCLR

0.2

1.1

0.2

1.3

0.3

1.8

Output Buffer and Pad Delay

t_OD1

t_OD2

t_OD3

Slow Slew Rate = off, VCCIO = V_CCINT

Output Buffer and Pad Delay

Slow Slew Rate = off, VCCIO = Low Voltage

0.6

3.0

0.9

3.5

1.6

4.8

Output Duffer and Pad Delay

Slow Slew Rate = on

[6]

t_ZX

1.1

1.3

1.8

1.6

Output Buffer Disable Delay

t_ZX1

[6]

Slow Slew Rate = off, VCCIO = V_CCINT

Output Buffer Disable Delay

Slow Slew Rate = off, VCCIO = Low

t_ZX2

0.6

3.0

0.9

3.5

1.6

4.8

Voltage^[6]

Output Buffer Disable Delay

Slow Slew Rate = on^[6]

t_ZX3

IOE Input Pad and Buffer to IOE Register

Delay

t_INREG

t_IOFD

5.0

3.0

5.9

3.6

8.0

4.8

IOE Register Feedback Delay

IOE Input Pad and Buffer to Interconnect

Delay

t_INCOMB

10KEtbl 06A

Page 11

LIBERATOR CL10K50S (PRELIMINARY)

AC Electrical Specifications cont.

External Timing Parameters^[4]

Speed: -1

Speed: -2

Speed: -3

Symbol

Parameter

Min

Max

Min

Max

Min

Max Unit

Three Row Interconnects, and Four Local

Interconnects

t_DRR

8.5

10.0

13.5

Setup Time with Global Clock at IOE

t_INSU

3.0

3.6

4.8

t_INH

Hold time with Global Clock at IOE Register

0.0

2.0

0.0

2.0

0.0

2.0

t_OUTCOOutput Data Hold Time After Clock

3.5

4.5

7.1

10KEtbl 07C

Logic Element Timing Parameters^[5]

Speed: -1

Speed: -2

Speed: -3

Symbol

t_LUT

Parameter

Look-up Table Delay for Data-in

Look-up Table Delay for Carry-in

Min

Max

0.6

Min

Max

0.8

Min

Max Unit

1.1

0.8

t_CLUT

0.5

0.6

Look-up Table Delay for LE Register

Feedback

t_RLUT

0.7

0.8

1.1

t_PACKEDData-in to Packed Register Delay

0.5

0.6

0.2

0.5

0.2

0.8

0.5

0.6

0.7

0.2

0.5

0.2

0.9

0.6

0.8

0.9

0.3

0.8

0.3

1.2

0.8

0.7

t_EN

LE Register Enable Delay

Carry-in to Carry-out Delay

Data-in to Carry-out Delay

t_CICO

t_CGEN

t_CGENRLE Register Feedback to Carry-out Delay

t_CASC

t_C

Cascade Chain Routing Ddelay

LE Register Control Signal Delay

LE Register Clock-to-output Delay

Combinatorial Delay

t_CO

t_COMB

t_SU

LE Register Setup Time Before Clock

LE Register Hold Time After Clock

LE Register Preset Delay

LE Register Clear Delay

0.5

0.9

0.6

1.1

0.8

1.5

t_H

t_PRE

t_CLR

t_CH

0.5

0.6

0.8

Clock High Time

2.0

2.5

3.0

t_CL

Clock Low Time

10KEtbl 08A

Page 12

LIBERATOR CL10K50S (PRELIMINARY)

AC Electrical Specifications cont.

Interconnect Timing Parameters^[5]

Speed: -1

Speed: -2

Speed: -3

Symbol

Parameter

Min

Max

Min

Max

Min

Max Unit

Delay from dedicated input pin to IOE control

input

t_DIN2IOE

4.1

0.9

1.8

3.9

0.9

0.1

4.6

1.0

1.9

4.6

1.0

0.1

5.9

Delay from dedicated input pin to LE or EAB

control input

t_DIN2LE

1.3

2.3

6.2

1.3

0.2

Delay from dedicated input or clock pin to LE

or EAB data

t_DIN2DATA

t_DCLK2IOEDelay from dedicated clock pin to IOE clock

Delay from dedicated clock pin to LE or EAB

t_DCLK2LE

clock

t_SAMELABDelay from an LE to LE in same LAB

Delay for driving a row IOE, LE or EAB to a

t_SAMEROW

1.3

1.8

row IOE, LE or EAB in the same row

t_SAMECOLUMNDelay from an LE to IOE in the same column

0.7

2.0

3.3

3.8

0.1

0.8

2.1

3.4

4.1

0.1

1.5

3.3

5.1

5.3

0.2

Delay for driving a column IOE, LE or EAB to

t_DIFFROW

an LE or EAB in a different row

Delay for driving a row IOE or EAB to an LE or

EAB in a different row

t_TWOROWS

Delay from an LE to IOE control signal via the

peripheral contol bus

t_LEPERIPH

Delay from an LE carry-out signal to an LE

t_LABCARRY

carry-in signal in a different LAB

Delay from an LE cascade-out signal to an

t_LABCASC

0.3

0.5

LE cascade-in signal in a different LAB

10KEtbl 09C

Page 13

LIBERATOR CL10K50S (PRELIMINARY)

AC Electrical Specifications cont.

EAB Timing Parameters^[5]

Speed: -1

Speed: -2

Speed: -3

Symbol

Parameter

Min

Max

Min

Max

Min

Max Unit

Delay from Data or Address to EAB for

Combinatorial Input

t_EABDATA1

1.7

0.6

1.1

0.4

2.0

0.7

1.3

0.4

2.7

Delay from Data or Address to EAB for

Registered Input

t_EABDATA2

0.9

1.8

0.6

t_EABWE1WE Delay to EAB for Combinatorial Input

t_EABWE2WE Delay to EAB for Registered Input

t_EABCLKEAB Register Clock Delay

t_EABCOEAB Register Clock-to-output Delay

t_EABBYPASSBypass Register Delay

0.0

0.3

0.5

0.0

0.3

0.6

0.0

0.5

0.8

t_EABSU

t_EABH

t_AA

EAB Register Setup Time

EAB Register Hold Time

Address Access Delay

Write Pulse Width

0.9

0.4

1.0

0.4

1.4

0.6

3.2

3.8

5.1

t_WP

2.5

0.9

2.9

1.0

3.9

1.4

Data Setup Time Before Falling Edge of

Write Pulse

t_WDSU

t_WDH

t_WASU

t_WAH

Data Hold Time After Falling Edge of Write

Pulse

0.1

1.7

1.8

0.1

2.0

2.1

0.2

2.7

2.9

Address Setup Time Before Rising Edge of

Write Pulse

Address Hold After Falling Edge of Write

Pulse

t_WO

t_DD

Write Enable to Date Output Delay

Data-in to Date-out Delay

2.5

0.5

2.9

0.6

3.9

0.8

t_EABOUTData-out Delay

t_EABCH

t_EABCL

Clock High Time

Clock Low Time

1.5

2.0

2.5

10KEtbl 10A

Page 14

LIBERATOR CL10K50S (PRELIMINARY)

AC Electrical Specifications cont.

EAB Timing Parameters^[5]

Speed: -1

Speed: -2

Speed: -3

Symbol

Parameter

Min

Max

Min

Max

Min

Max Unit

t_EABAA

EAB Address Access Delay

6.4

7.6

10.2

t_EABRCCOMBEAB Asynchronous Read Cycle Time

t_EABRCREGEAB Synchronous Read Cycle Time

t_EABWPEAB Write Pulse Width

6.4

4.4

2.5

6.0

6.8

7.6

5.1

2.9

7.0

7.8

10.2

7.0

3.9

t_EABWCCOMBEAB Asynchronous Write Cycle Time

t_EABWCREGEAB Synchronous Write Cycle Time

9.5

10.6

t_EABDD

EAB Data-in to Data-out Delay

5.7

0.8

6.7

0.9

9.0

1.3

EAB Clock-to-output Delay Using Output

Registers

t_EABDATACO

EAB Data/Address Setup Time Using Input

t_EABDATASU

1.5

0.0

1.3

0.0

1.7

0.0

1.4

0.0

2.3

0.0

2.0

0.0

EAB Data/Address Hold Time Using Input

t_EABDATAH

t_EABWESUEAB WE Setup When Using Input Register

EAB WE Hold Time When Using Input

t_EABWESH

EAB Data Setup Time to Falling Edge of

t_EABWDSU

1.5

0.0

3.0

0.5

1.7

0.0

3.6

0.5

2.3

0.0

4.8

0.8

Write Pulse When Not Using Input Registers

EAB Data Hold Time After Falling Edge of

t_EABWDH

Write Pulse When Not Using Input Registers

EAB Address Setup Time to Rising Edge of

t_EABWASU

Write Pulse When Not Using Input Registers

EAB Address Hold Time After Falling Edge

t_EABWAHof Write Pulse When Not Using Input

Registers

t_EABWOEAB WE to Data Output Delay

5.1

6.0

8.1

10KEtbl 11A

Page 15

LIBERATOR CL10K50S (PRELIMINARY)

AC Electrical Specifications cont.

External Bidirectional Timing Parameters^[5]

Speed: -1

Speed: -2

Speed: -3

Symbol

Parameter

Min

Max

Min

Max

Min

Max Unit

Setup for Bi-directional Pins with Global

Clock at Adjacent LE Registers

t_INSUBIDIR

1.5

2.2

0.0

2.0

3.6

0.0

2.0

Hold Time for Bi-directional Pins with Global

Glock at Adjacent LE Registers

t_INHBIDIR

t_OUTCOBIDIR

t_XZBIDIR

0.0

2.0

Clock-to-output Delay for Bi-directional Pins

with Global Clock at IOE Register

3.5

5.8

4.7

4.5

6.3

5.3

7.1

8.0

7.2

Synchronous IOE Output Buffer Disable

Delay

Synchronous IOE Output Buffer Disable

Delay, Slow Slew Rate = off

t_ZXBIDIR

10KEtbl 12C

AC Test Conditions

(A)

(B)

All Input Pulses

481 Ω

V_CCIO

3.0V

90%

10%

90%

OUTPUT

10%

35 pF

5 pF

481 Ω

GND

Includes jig

capacitance

Includes jig

capacitance

≤ 3ns

10KE drw 02

A: Test fixture set-up A is for general testing.

B: Test fixture set-up B is for high Z testing (t_ZX#).

Notes to Tables

1. During transitions, inputs may undershoot to -2.0V or overshoot to 5.75V for

periods shorter than 20ns. Otherwise, minimum DC input voltage is -0.5V.

2. Device inputs may be driven before V_CCINTand V_CCIOare powered.

3. Typical values are at V_CCof 3.3 volts and ambient temperature of 25 ºC.

4. Guaranteed but not tested. Characterized initially, and after any design changes

which may affect these parameters.

5. Internal timing delays are based on characterization, and cannot be explicitly

tested. Internal timing parameters should be used for performance estimation

only.

6. Use AC Test Conditions set-up B for these parameters.

Revision History

02 Dec. 2000:

22 May 2001:

Created new document

Corrected VCCINT table

Page 16

LIBERATOR CL10K50S (PRELIMINARY)

Ordering Information

Part Number

CL10K50STC144-3

CL10K50STC144-2

CL10K50STC144-2X*

CL10K50STC144-1

CL10K50STC144-1X*

CL10K50SQC208-3

CL10K50SQC208-2

CL10K50SQC208-2X*

CL10K50SQC208-1

CL10K50SQC208-1X*

CL10K50SQI208-2

CL10K50SQC240-3

CL10K50SQC240-2

CL10K50SQC240-2X*

CL10K50SQC240-1

CL10K50SQC240-1X*

CL10K50SFC256-4

CL10K50SFC256-3

CL10K50SFC256-2

CL10K50SFC256-2X*

CL10K50SFC256-1

CL10K50SFC256-1X*

Temperature Range

Package Type

Speed

-3

Altera Equivalent

EPF10K50STC144-3

EPF10K50STC144-2

EPF10K50STC144-2X

EPF10K50STC144-1

EPF10K50STC144-1X

EPF10K50SQC208-3

EPF10K50SQC208-2

EPF10K50SQC208-2X

EPF10K50SQC208-1

EPF10K50SQC208-1X

EPF10K50SQI208-2

EPF10K50SQC240-3

EPF10K50SQC240-2

EPF10K50SQC240-2X

EPF10K50SQC240-1

EPF10K50SQC240-1X

EPF10K50SFC256-4

EPF10K50SFC256-3

EPF10K50SFC256-2

EPF10K50SFC256-2X

EPF10K50SFC256-1

Commercial

144-pin TQFP

-2

-1

Commercial

208-pin Plastic QFP

-3

-2

-1

Industrial

-2

Commercial

240-pin Plastic QFP

-3

-2

-1

Commercial

256-pin FBGA

-4

-3

-2

-1

EPF10K50SFC256-1X

10K50S tbl 02A

* Contact your local Clear Logic Representative for availability.

Page 17

LIBERATOR CL10K50S (PRELIMINARY)

Ordering Information

Part Number

CL10K50SBC356-3

CL10K50SBC356-2

CL10K50SBC356-2X*

CL10K50SBC356-1

CL10K50SBC356-1X*

CL10K50SFC484-3

CL10K50SFC484-2

CL10K50SFC484-2X*

CL10K50SFC484-1

CL10K50SFC484-1X*

CL10K50SFI484-2

Temperature Range

Package Type

Speed

Altera Equivalent

EPF10K50SBC356-3

EPF10K50SBC356-2

EPF10K50SBC356-2X

EPF10K50SBC356-1

EPF10K50SBC356-1X

EPF10K50SFC484-3

EPF10K50SFC484-2

EPF10K50SFC484-2X

EPF10K50SFC484-1

EPF10K50SFC484-1X

Commercial

356-pin SBGA

-3

-2

-1

-3

-2

-1

-2

Commercial

484-pin FBGA

Industrial

EPF10K50SFI484-2

10K50S tbl 02B

* Contact your local Clear Logic Representative for availability.

Page 18

CL10K50SQC240-2X [ETC]

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