CLC410AJ-QML [ETC]
Current-Feedback Operational Amplifier ; 电流反馈运算放大器\n
| 型号： | CLC410AJ-QML |
| 厂家： | 
ETC |
| 描述： | Current-Feedback Operational Amplifier
|
| 文件： | 总11页 (文件大小：73K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MICROCIRCUIT DATA SHEET
Original Creation Date: 11/03/98
Last Update Date: 07/19/99
MNCLC410A-X REV 0A0
Last Major Revision Date: 05/06/99
FAST SETTLING, VIDEO OP AMP WITH DISABLE
General Description
The current-feedback CLC410 is a fast-settling, wideband, monolithic op amp with fast
disable/enable feature. Designed for low-gain applications (Av = +1 to +8), the CLC410
consumes only 160mW of power (180mW max) yet provides a -3dB bandwidth of 200MHz (Av = +2)
and 0.05% settling in 12ns (15ns max). Plus, the disable feature provides fast turn-on
(100ns) and turn-off (200ns). In addition, the CLC410 offers both high performance and
stability without compensation, even at a gain of +1.
The CLC410 provides a simple, high-performance solution for video switching and
distribution applications, especially where analog buses benefit from use of the disable
function to "multiplex" signals onto the bus. Differential gain/phase of 0.01%/0.01
provide high fidelity and the 70mA output current offers ample drive capability.
The CLC410's fast settling, low distortion, and high drive capabilities make it an ideal
ADC driver. The low 160mW quiescent power consumption and very low 40mW disabled power
consumption suggest use where power is critical and/or "system off" power consumption must
be minimized.
Industry Part Number
NS Part Numbers
CLC410A
CLC410AJ-QML
Prime Die
UB1286C
Controlling Document
5962-9060001PA
Processing
Subgrp Description
Temp (oC)
MIL-STD-883, Method 5004
1
Static tests at
+25
2
Static tests at
+125
-55
3
Static tests at
4
Dynamic tests at
Dynamic tests at
Dynamic tests at
Functional tests at
Functional tests at
Functional tests at
Switching tests at
Switching tests at
Switching tests at
+25
Quality Conformance Inspection
5
+125
-55
6
MIL-STD-883, Method 5005
7
+25
8A
8B
9
+125
-55
+25
10
11
+125
-55
1
MICROCIRCUIT DATA SHEET
MNCLC410A-X REV 0A0
Features
- -3dB bandwidth of 200MHz
- 0.05% settling in 12ns
- Low power, 160mW (40mW disabled)
- Low distortion, -60dBc at 20MHz
- Fast disable (200ns)
- Differential gain/phase: 0.01%/0.01 deg
- +1 to +8 closed-loop gain range
Applications
- Video switching and distribution
- Analog bus driving (with disable)
- Low power "standby" using disable
- Fast, precision A/D conversion
- D/A current-to-voltage conversion
- IF processors
- High-speed communications
2
MICROCIRCUIT DATA SHEET
MNCLC410A-X REV 0A0
(Absolute Maximum Ratings)
(Note 1)
Supply Voltage (Vs)
+7V dc
70mA
+Vs
Output Current (Iout)
Common Mode Input Voltage (Vcm)
Differential Input Voltage (Vid)
Disable Input Voltage (D I S pin)
Applied Output Voltage when Disabled
5V
+Vs
+Vs
Maximum Power Dissipation (Pd)
(Note 2)
1.2W
Lead Temperature (soldering, 10 seconds)
Junction Temperature (Tj)
+300 C
+175 C
Storage Temperature
-65 C to +150 C
Thermal Resistance
Junction -to-ambient (ThetaJA)
Ceramic DIP
(Still Air)
(500 LFPM)
(ThetaJC)
TBD
TBD
Junction -to-case
Ceramic DIP
Package Weight
(Typical)
Ceramic DIP
TBD
ESD Tolerance
(Note 3)
ESD Rating
1000V
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur.
Operating Ratings are conditions for which the device is functional, but do not
guarantee specific performance limits. For guaranteed specifications and test
conditions see the Electrical Characteristics. The guaranteed specifications apply
only for the test conditions listed. Some performance characteristics may degrade
when the device is not operated under the listed test conditions.
Note 2: The maximum power dissipation must be derated at elevated temperatures and is
dictated by Tjmax (maximum junction temperature), ThetaJA (package junction to
ambient thermal resistance), and TA (ambient temperature). The maximum allowable
power dissipation at any temperature is Pdmax = (Tjmax - TA) / ThetaJA or the number
given in the Absolute Maximum Ratings, whichever is lower.
Note 3: Human body model, 100pF discharged through 1.5K Ohms.
3
MICROCIRCUIT DATA SHEET
MNCLC410A-X REV 0A0
Recommended Operating Conditions
Supply Voltage (Vs)
+5V dc
+1 to +8
-55 C to +125 C
Gain Range (Av)
Ambient Operating Temperature Range (Ta)
4
MICROCIRCUIT DATA SHEET
MNCLC410A-X REV 0A0
Electrical Characteristics
AC/DC PARAMETERS: ELECTRICAL CHARACTERISTICS
(The following conditions apply to all the following parameters, unless otherwise specified.)
DC: Vs = +5V dc, Av = +2, load resistance (Rl = 100Ohms), feedback resistance (Rf) = 250Ohms, gain setting
resistance (Rg) = 250Ohms. -55 C < Ta < +125 C (Note 3).
PIN-
NAME
SUB-
SYMBOL
+Iin
PARAMETER
CONDITIONS
NOTES
MIN
-20
MAX UNIT
GROUPS
Input Bias
+20
uA
uA
uA
uA
uA
mV
mV
mV
1, 2
Current
(noninverting)
-36
+36
3
1
2
3
1
2
3
-Iin
Vio
Input Bias
Current
(Inverting)
-20
+20
-30
+30
-36
+36
Input Offset
Voltage
Rs = 50 Ohms
-5.0
-9.0
-8.2
-100
-200
-100
-200
-40
+5.0
+9.0
+8.2
+100
+200
+100
+200
+40
Tc (+Iin)
Tc (-Iin)
Average +Input
Bias Current
Drift
1
1
1
1
1
nA/C 2
nA/C 3
nA/C 2
nA/C 3
uV/C 2, 3
Average -Input
Bias Current
Drift
Tc (Vio)
Is
Average Offset
Voltage Drift
Supply Current
No Load
18
mA
dB
dB
1, 2,
3
PSRR
CMRR
SSBW
Power Supply
Rejection Ratio
Vs+ = +4.5V to +5.0V, Vs- = -4.5V to
-5.0V
45
45
1, 2,
3
Common Mode
Rejection Ratio
Vcm = +1 V
1
1, 2,
3
Small Signal
Bandwidth
-3 dB bandwidth, Vout < 0.5 Vpp
150
120
150
MHz 4
MHz 5
MHz 6
2
2
GFPL
GFPH
GFR
Gain Flatness
Peaking Low
At 0.1 Mhz to 40 MHz
At > 40 MHz
0.3
0.4
0.5
0.7
1
dB
dB
dB
dB
dB
dB
dB
4
2
2
5, 6
Gain Flatness
Peaking High
4
5, 6
Gain Flatness
Rolloff
At 0.1 Mhz to 75 MHz
4
5
6
2
2
1.3
1
5
MICROCIRCUIT DATA SHEET
MNCLC410A-X REV 0A0
Electrical Characteristics
AC/DC PARAMETERS: ELECTRICAL CHARACTERISTICS(Continued)
(The following conditions apply to all the following parameters, unless otherwise specified.)
DC: Vs = +5V dc, Av = +2, load resistance (Rl = 100Ohms), feedback resistance (Rf) = 250Ohms, gain setting
resistance (Rg) = 250Ohms. -55 C < Ta < +125 C (Note 3).
PIN-
NAME
SUB-
GROUPS
SYMBOL
HD2
PARAMETER
CONDITIONS
2 Vpp at 20 MHz
NOTES
MIN
MAX UNIT
-45
Second Harmonic
Distortion
dBc 4
2
2
-45
-40
-50
-50
-154
dBc 5
dBc 6
HD3
SNF
Third Harmonic
Distortion
2 Vpp at 20 MHz
At > 1 MHz
dBc 4
2
1
dBc 5, 6
dBm 4, 6
Noise Floor
(1Hz)
1
-156
dBm 5
(1Hz)
INV
Integrated Noise At 1 MHz to 200 Mhz
1
1
1
1
57
uV
uV
uV
V
1
2
3
63
54
Vdis
Ven
DISABLE voltage
to disable
0.5
1, 2,
3
DISABLE voltage
to enable
1
1
1
1
3.2
4.0
2.3
250
V
1
2
3
V
V
Idis
Ien
DISABLE current
to disable
uA
1, 2,
3
DISABLE current
to enable
1
1
1
1
1
1
60
uA
dB
ns
ns
ns
ns
1, 2,
3
OSD
Off Isolation
Disable Time
Enable Time
At 10 Mhz
55
4, 5,
6
Toff
Ton
> 50 dB attenuation at 10 Mhz
1000
200
2.4
10
4, 5,
6
4, 5,
6
TRS
Rise and Fall
Time
0.5 V Step
5 V Step
9, 10,
11
TRL
Rise and Fall
Time
9, 10,
11
+Rin
Input Resistance
1
1
1
1
100
kOhm 1, 2
kOhm 3
50
50
30
Iout
Output Current
mA
mA
1, 2
3
6
MICROCIRCUIT DATA SHEET
MNCLC410A-X REV 0A0
Electrical Characteristics
AC/DC PARAMETERS: ELECTRICAL CHARACTERISTICS(Continued)
(The following conditions apply to all the following parameters, unless otherwise specified.)
DC: Vs = +5V dc, Av = +2, load resistance (Rl = 100Ohms), feedback resistance (Rf) = 250Ohms, gain setting
resistance (Rg) = 250Ohms. -55 C < Ta < +125 C (Note 3).
PIN-
NAME
SUB-
SYMBOL
Vout
PARAMETER
CONDITIONS
NOTES
MIN
2.8
MAX UNIT
GROUPS
Output Voltage
Swing
Rl = 100 Ohms
2
2
1
V
V
4, 5
2.3
430
6
SR
ts
Slew Rate
Measured +1 V with +3 V step, Av = +2
2 V step at 0.1% of the fixed value
2 V step at 0.05% of the fixed value
0.5 V step
V/uS 4, 5,
6
Settling Time
1
1
13
15
ns
9, 10,
11
ns
9, 10,
11
OS
Overshoot
1
1
10
15
%
%
9, 10
11
Note 1: If not tested, shall be guaranteed to the limits specified in table 1 herein.
Note 2: Group A sample tested only.
Note 3: The algebraic convention, whereby the most negative value is a minimum and most
positive is a maximum, is used in this table. Negative current shall be defined as
convential current flow out of a device terminal.
7
MICROCIRCUIT DATA SHEET
MNCLC410A-X REV 0A0
Graphics and Diagrams
GRAPHICS#
DESCRIPTION
07081HRA3
J08ARL
CERDIP (J), 8 LEAD (B/I CKT)
CERDIP (J), 8 LEAD (P/P DWG)
CERDIP (J), 8 LEAD (PINOUT)
P000416A
See attached graphics following this page.
8
DIS
+V
1
2
3
4
8
7
6
5
Offset Adjust
V
INV
CC
V
V
OUT
NON-INV
N/C
-V
CC
CLC410J
8 - LEAD DIP
CONNECTION DIAGRAM
TOP VIEW
P000416A
MIL/AEROSPACE OPERATIONS
2900 SEMICONDUCTOR DRIVE
SANTA CLARA, CA 95050
MICROCIRCUIT DATA SHEET
MNCLC410A-X REV 0A0
Revision History
Rev ECN # Rel Date Originator Changes
0A0
M0003072 07/19/99
Shaw Mead
Initial MDS Release
9
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