CMT2110AW-ESR [ETC]
Low-Cost 240 â 960 MHz OOK Transmitter;
| 型号： | CMT2110AW-ESR |
| 厂家： | 
ETC |
| 描述： | Low-Cost 240 â 960 MHz OOK Transmitter |
| 文件： | 总25页 (文件大小：781K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMT2110/17AW
Low-Cost 240 – 960 MHz OOK Transmitter
Features
Applications
Embedded EEPROM
Low-Cost Consumer Electronics Applications
Home and Building Automation
Remote Fan Controllers
Very Easy Development with RFPDK
All Features Programmable
Frequency Range:
Infrared Transmitter Replacements
Industrial Monitoring and Controls
Remote Lighting Control
240 to 480 MHz (CMT2110AW)
240 to 960 MHz (CMT2117AW)
OOK Modulation
Wireless Alarm and Security Systems
Remote Keyless Entry (RKE)
Symbol Rate: 0.5 to 30 ksps
Output Power: -10 to +13 dBm
Supply Voltage: 1.8 to 3.6 V
Current Consumption: 12.4 mA @ +10 dBm
Sleep Current: < 20 nA
Ordering Information
FCC / ETSI Compliant
Part Number
CMT2110AW-ESR
CMT2117AW-ESR
Frequency
433.92 MHz
868.35 MHz
Package
SOT23-6
SOT23-6
MOQ
RoHS Compliant
3,000 pcs
3,000 pcs
6-pin SOT23-6 Package
More Ordering Info: See Page 20
Descriptions
The CMT2110/17AW devices are ultra low-cost, highly
flexible, high performance, single-chip OOK transmitters for
various 240 to 960 MHz wireless applications. The
CMT2110AW covers the frequency range from 240 to 480
MHz while the CMT2117AW covers the 240 to 960 MHz
frequency range. They are part of the CMOSTEK
NextGenRFTM family, which includes a complete line of
transmitters, receivers and transceivers. With very low
current consumption, the device modulates and transmits
the data which is sent from the host MCU. An embedded
EEPROM allows the frequency, output power and other
features to be programmed into the chip using the
CMOSTEK USB Programmer and RFPDK. Alternatively, in
stock products of 433.92/868.35 MHz are available for
immediate demands without the need of EEPROM
programming. The CMT2110/17AW uses a 1-pin crystal
oscillator circuit with the required crystal load capacitance
integrated on-chip to minimize the number of external
components. The CMT2110/17AW transmitter together with
the CMT221x receiver enables an ultra low cost RF link.
SOT23-6
6
5
4
1
2
3
VDD
XTAL
GND
RFO
CLK
DATA
CMT2110/17AW
Copyright © By CMOSTEK
Rev 1.2 | Page 1/25
www.hoperf.com
CMT2110/17AW
Typical Application
CMT2110/17AW
X1
VDD VDD
C0
1
2
3
6
5
4
ANT
J1
VDD
XTAL
VDD
RFO
CLK
1
2
3
4
L1
DATA
CLK
L2
U1
GND
C1
C2
Note: Connector J1 is for
EEPROM Programming
DATA
CLK
DATA
Figure 1. CMT2110/17AW Typical Application Schematic
Table 1. BOM of 433.92/868.35 MHz Low-Cost Application
Value
Designator
Descriptions
Unit
Manufacturer
433.92 MHz
868.35 MHz[1]
CMT2110/17AW, Low-Cost 240 – 960 MHz
U1
-
-
CMOSTEK
OOK Transmitter
26
X1
C0
C1
C2
L1
L2
±20 ppm, SMD32*25 mm crystal
±20%, 0402 X7R, 25 V
MHz
uF
EPSON
0.1
Murata GRM15
Murata GRM15
Murata GRM15
Murata LQG18
Murata LQG18
±5%, 0402 NP0, 50 V
82
9
82
3.9
100
8.2
pF
±5%, 0402 NP0, 50 V
pF
±5%, 0603 multi-layer chip inductor
±5%, 0603 multi-layer chip inductor
180
27
nH
nH
Note:
[1]. The 868.35 MHz Application is for CMT2117AW only.
Table 2. Product Selection Table
Max Output
Embedded
EEPROM
Product
Frequency
240-480 MHz
240-960 MHz
Modulation
Tx Current Consumption
Power
13.4 mA
CMT2110AW
CMT2117AW
OOK
+13 dBm
√
√
(+10 dBm @ 433.92 MHz)
15.5 mA
OOK
+13 dBm
(+10 dBm @ 868.35 MHz)
Rev 1.2 | Page 2/25
www.hoperf.com
CMT2110/17AW
Abbreviations
Abbreviations used in this data sheet are described below
AN
Application Notes
PA
Power Amplifier
Personal Computer
Printed Circuit Board
Phase Noise
BOM
BSC
Bill of Materials
PC
Basic Spacing between Centers
PCB
EEPROM
Electrically Erasable Programmable Read-Only PN
Memory
RCLK
Reference Clock
Radio Frequency
ESD
ESR
ETSI
Electro-Static Discharge
Equivalent Series Resistance
European Telecommunications Standards
Institute
RF
RFPDK
RoHS
Rx
RF Product Development Kit
Restriction of Hazardous Substances
Receiving, Receiver
Small-Outline Transistor
Symbol Rate
FCC
Max
MCU
Min
Federal Communications Commission
Maximum
SOT
SR
Microcontroller Unit
Minimum
TWI
Two-wire Interface
Transmission, Transmitter
Typical
Tx
MOQ
NP0
OBW
OOK
Minimum Order Quantity
Negative-Positive-Zero
Occupied Bandwidth
On-Off Keying
Typ
USB
XO/XOSC
XTAL
Universal Serial Bus
Crystal Oscillator
Crystal
Rev 1.2 | Page 3/25
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CMT2110/17AW
Table of Contents
1. Electrical Characteristics............................................................................................................................................ 5
1.1 Recommended Operating Conditions ................................................................................................................... 5
1.2 Absolute Maximum Ratings................................................................................................................................... 5
1.3 Transmitter Specifications..................................................................................................................................... 6
1.4 Crystal Oscillator................................................................................................................................................... 7
2. Pin Descriptions .......................................................................................................................................................... 8
3. Typical Performance Characteristics......................................................................................................................... 9
4. Typical Application Schematics ............................................................................................................................... 10
4.1 Low-Cost Application Schematic......................................................................................................................... 10
4.2 FCC/ETSI Compliant Application Schematic....................................................................................................... 11
5. Functional Descriptions............................................................................................................................................ 12
5.1 Overview............................................................................................................................................................. 12
5.2 Modulation, Frequency and Symbol Rate ........................................................................................................... 12
5.3 Embedded EEPROM and RFPDK ...................................................................................................................... 13
5.4 Power Amplifier................................................................................................................................................... 14
5.5 PA Ramping........................................................................................................................................................ 14
5.6 Crystal Oscillator and RCLK................................................................................................................................ 15
6. Working States and Transmission Control Interface ............................................................................................. 16
6.1 Working States.................................................................................................................................................... 16
6.2 Transmission Control Interface ........................................................................................................................... 16
6.2.1 Tx Enabled by DATA Pin Rising Edge...................................................................................................... 17
6.2.2 Tx Enabled by DATA Pin Falling Edge..................................................................................................... 17
6.2.3 Two-wire Interface.................................................................................................................................... 17
7. Ordering Information................................................................................................................................................. 20
8. Package Outline......................................................................................................................................................... 21
9. Top Marking ............................................................................................................................................................... 22
9.1 CMT2110/17AW Top Marking............................................................................................................................. 22
10. Other Documentations.............................................................................................................................................. 23
11. Document Change List.............................................................................................................................................. 24
12. Contact Information .................................................................................................................................................. 25
Rev 1.2 | Page 4/25
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CMT2110/17AW
1. Electrical Characteristics
VDD = 3.3 V, TOP = 25 ℃, FRF = 433.92 MHz, output power is +10 dBm terminated in a matched 50 Ω impedance, unless
otherwise noted.
1.1 Recommended Operating Conditions
Table 3. Recommended Operation Conditions
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Operation Voltage Supply
Operation Temperature
Supply Voltage Slew Rate
VDD
TOP
1.8
-40
1
3.6
85
V
℃
mV/us
1.2 Absolute Maximum Ratings
Table 4. Absolute Maximum Ratings[1]
Parameter
Supply Voltage
Symbol
Conditions
Min
Max
3.6
Unit
V
VDD
VIN
-0.3
-0.3
-40
-50
Interface Voltage
Junction Temperature
Storage Temperature
Soldering Temperature
ESD Rating
VDD + 0.3
125
V
TJ
℃
TSTG
TSDR
150
℃
Lasts at least 30 seconds
Human Body Model (HBM)
@ 85 ℃
255
℃
-2
2
kV
mA
Latch-up Current
Note:
-100
100
[1]. Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
Caution! ESD sensitive device. Precaution should be used when handling the device in order
to prevent permanent damage.
Rev 1.2 | Page 5/25
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CMT2110/17AW
1.3 Transmitter Specifications
Table 5. Transmitter Specifications
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
CMT2110AW
CMT2117AW
FRF ≤ 480 MHz
FRF > 480 MHz
240
240
480
960
MHz
MHz
Hz
Frequency Range[1]
FRF
198
398
+13
-10
1
Synthesizer Frequency
Resolution
FRES
Hz
Maximum Output Power
Minimum Output Power
Output Power Step Size
PA Ramping Time[2]
POUT(Max)
POUT(Min)
PSTEP
dBm
dBm
dB
tRAMP
0
1024
us
0 dBm, 50% duty cycle
+10 dBm, 50% duty cycle
+13 dBm, 50% duty cycle
0 dBm, 50% duty cycle
+10 dBm, 50% duty cycle
+13 dBm, 50% duty cycle
6.7
13.4
17.4
8.0
mA
Current Consumption
@ 433.92 MHz
IDD433.92
mA
mA
mA
Current Consumption
@ 868.35 MHz
IDD868.35
15.5
19.9
20
mA
mA
Sleep Current
ISLEEP
SR
nA
Symbol Rate
0.5
30
ksps
us
Frequency Tune Time
tTUNE
370
-81
-83
-92
-97
-107
-75
-77
-86
-91
-101
-52
-60
-67
-55
60
100 kHz offset from FRF
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBm
dBm
dBm
dBm
dB
200 kHz offset from FRF
Phase Noise @ 433.92
MHz
PN433.92
400 kHz offset from FRF
600 kHz offset from FRF
1.2 MHz offset from FRF
100 kHz offset from FRF
200 kHz offset from FRF
Phase Noise @ 868.35
MHz
PN868.35
400 kHz offset from FRF
600 kHz offset from FRF
1.2 MHz offset from FRF
H2433.92
H3433.92
H2868.35
H3868.35
2nd harm @ 867.84 MHz, +13 dBm POUT
3rd harm @ 1301.76 MHz, +13 dBm POUT
2nd harm @ 1736.7 MHz, +13 dBm POUT
3rd harm @ 2605.05 MHz, +13 dBm POUT
Harmonics Output for
433.92 MHz[3]
Harmonics Output for
868.35 MHz[3]
OOK Extinction Ration
Notes:
[1]. The frequency range is continuous over the specified range.
[2]. 0 and 2n us, n = 0 to 10, when set to “0”, the PA output power will ramp to its configured value in the shortest possible
time.
[3]. The harmonics output is measured with the application shown as Figure 10.
Rev 1.2 | Page 6/25
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CMT2110/17AW
1.4 Crystal Oscillator
Table 6. Crystal Oscillator Specifications
Parameter
Symbol
Conditions
Min
Typ
26
Max
Unit
MHz
ppm
pF
Crystal Frequency[1]
Crystal Tolerance[2]
Load Capacitance[3]
Crystal ESR
FXTAL
26
26
±20
CLOAD
Rm
12
20
60
Ω
XTAL Startup Time[4]
tXTAL
400
us
Notes:
[1]. The CMT2110/17AW can directly work with external 26 MHz reference clock input to XTAL pin (a coupling capacitor is
required) with amplitude 0.3 to 0.7 Vpp.
[2]. This is the total tolerance including (1) initial tolerance, (2) crystal loading, (3) aging, and (4) temperature dependence.
The acceptable crystal tolerance depends on RF frequency and channel spacing/bandwidth.
[3]. The required crystal load capacitance is integrated on-chip to minimize the number of external components.
[4]. This parameter is to a large degree crystal dependent.
Rev 1.2 | Page 7/25
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CMT2110/17AW
2. Pin Descriptions
6
5
4
1
2
3
VDD
RFO
CLK
XTAL
GND
DATA
Figure 2. CMT2110/17AW Pin Assignments
Table 7. CMT2110/17AW Pin Descriptions
Pin Number
Name
I/O
Descriptions
26 MHz single-ended crystal oscillator input or
External 26 MHz reference clock input
Ground
1
2
XTAL
GND
I
I
Data input to be transmitted or
Data pin to access the embedded EEPROM
Pulled down internally to GND when configured as Transmission Enabled by
DATA Pin Falling Edge and used as input pin
Pulled up internally to VDD when configured as Transmission Enabled by DATA
Pin Rising Edge and used as input pin
3
DATA
IO
Clock pin to control the device
4
CLK
I
Clock pin to access the embedded EEPROM
Pulled up internally to VDD
5
6
RFO
VDD
O
I
Power amplifier output
Power supply input
Rev 1.2 | Page 8/25
www.hoperf.com
CMT2110/17AW
3. Typical Performance Characteristics
Phase Noise @ 868.35 MHz
Phase Noise
15
5
20
13.0 dBm
@ 868.35 MHz
13.2 dBm
@ 433.92 MHz
10
-5
0
-10
-20
-30
-15
-25
-35
-45
-55
-65
-55.9 dBm
@ 869.55 MHz
-40
-55.0 dBm
@ 435.12 MHz
-50
-60
432.42 432.72 433.02 433.32 433.62 433.92 434.22 434.52 434.82 435.12 435.42
866.85 867.1 867.35 867.6 867.85 868.1 868.35 868.6 868.85 869.1 869.35 869.6 869.85
Frequency (MHz) RBW = 10 kHz
Frequency (MHz) (RBW = 10 kHz)
Figure 3. Phase Noise, FRF = 433.92 MHz,
Figure 4. Phase Noise, FRF = 868.35 MHz,
POUT = +13 dBm, Unmodulated
POUT = +13 dBm, Unmodulated
Spectrum of Various PA Ramping Options
OOK Spectrum, SR = 9.6 ksps
10
0
10
0
128 us
64 us
32 us
16 us
8 us
-10
-20
-30
-40
-50
-10
-20
-30
-40
-50
4 us
433.18
433.37
433.55
433.74
433.92
434.11
434.29
434.48
434.66
433.17
433.37
433.57
433.77
433.97
434.17
434.37
434.57
Frequency (MHz)
Frequency (MHz)
Figure 5. OOK Spectrum, SR = 9.6 ksps,
POUT = +10 dBm, tRAMP = 32 us
Figure 6. Spectrum of PA Ramping,
SR = 9.6 ksps, POUT = +10 dBm
Spectrum of Various PA Ramping Options
POUT vs. VDD
10
0
14
1024 us
512 us
256 us
12
10
8
SR = 1.2 ksps
128 us
64 us
32 us
-10
-20
-30
-40
-50
0 dBm
6
+10 dBm
+13 dBm
4
2
0
-2
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
433.17
433.37
433.57
433.77
433.97
434.17
434.37
434.57
Frequency (MHz)
Supply Voltage VDD (V)
Figure 8. Spectrum of PA Ramping,
SR = 1.2 ksps, POUT = +10 dBm
Figure 7. Output Power vs. Supply
Voltages, FRF = 433.92 MHz
Rev 1.2 | Page 9/25
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CMT2110/17AW
4. Typical Application Schematics
4.1 Low-Cost Application Schematic
CMT2110/17AW
X1
VDD VDD
C0
1
2
3
6
5
4
ANT
J1
VDD
XTAL
GND
VDD
RFO
CLK
1
2
3
4
L1
DATA
CLK
L2
U1
C1
C2
Note: Connector J1 is for
EEPROM Programming
DATA
CLK
DATA
Figure 9. Low-Cost Application Schematic
Notes:
1. Connector J1 is a must for the CMT2110/17AW EEPROM access during development or manufacture.
2. The general layout guidelines are listed below. For more design details, please refer to “AN101 CMT211xA Schematic and
PCB Layout Design Guideline”
Use as much continuous ground plane metallization as possible.
Use as many grounding vias (especially near to the GND pins) as possible to minimize series parasitic inductance
between the ground pour and the GND pins.
Avoid using long and/or thin transmission lines to connect the components.
Avoid placing the nearby inductors in the same orientation to reduce the coupling between them.
Place C0 as close to the CMT2110/17AW as possible for better filtering.
3. The table below shows the BOM of 433.92/868.35 MHz Low-Cost Application. For the BOM of 315/915 MHz application,
please refer to “AN101 CMT211xA Schematic and PCB Layout Design Guideline”.
Table 8. BOM of 433.92/868.35 MHz Low-Cost Application
Value
Designator
Descriptions
Unit
Manufacturer
433.92 MHz
868.35 MHz[1]
CMT2110/17AW, Low-Cost 240 – 960 MHz
OOK Transmitter
U1
-
-
CMOSTEK
26
X1
C0
±20 ppm, SMD32*25 mm crystal
±20%, 0402 X7R, 25 V
MHz
uF
EPSON
0.1
Murata GRM15
Murata GRM15
Murata GRM15
Murata LQG18
Murata LQG18
C1
±5%, 0402 NP0, 50 V
82
9
82
3.9
100
8.2
pF
C2
±5%, 0402 NP0, 50 V
pF
L1
±5%, 0603 multi-layer chip inductor
±5%, 0603 multi-layer chip inductor
180
27
nH
nH
L2
Note:
[1]. The 868.35 MHz Application is for CMT2117AW only.
Rev 1.2 | Page 10/25
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CMT2110/17AW
4.2 FCC/ETSI Compliant Application Schematic
CMT2110/17AW
X1
VDD
VDD
C0
1
2
3
6
5
4
ANT
J1
VDD
XTAL
VDD
RFO
CLK
VDD
1
2
3
4
L1
DATA
CLK
L2
L3
C2
GND
U1
GND
C1
C3
Note: Connector J1 is for
EEPROM Programming
DATA
DATA
CLK
Figure 10. FCC/ETSI Compliant Application Schematic
Notes:
1. Connector J1 is a must for the CMT2110/17AW EEPROM access during development or manufacture.
2. The general layout guidelines are listed below. For more design details, please refer to “AN101 CMT211xA Schematic and
PCB Layout Design Guideline”.
Use as much continuous ground plane metallization as possible.
Use as many grounding vias (especially near to the GND pins) as possible to minimize series parasitic inductance
between the ground pour and the GND pins.
Avoid using long and/or thin transmission lines to connect the components.
Avoid placing the nearby inductors in the same orientation to reduce the coupling between them.
Place C0 as close to the CMT2110/17AW as possible for better filtering.
3. The table below shows the BOM of 433.92/868.35 MHz FCC/ETSI Compliant Application. For the BOM of 315/915 MHz
application, please refer to “AN101 CMT211xA Schematic and PCB Layout Design Guideline”.
Table 9. BOM of 433.92/868.35 MHz FCC/ETSI Compliant Application
Value
Designator
Descriptions
Unit
Manufacturer
433.92 MHz 868.35 MHz[1]
CMT2110/17AW, Low-Cost 240 – 960 MHz
OOK Transmitter
-
-
U1
CMOSTEK
X1
C0
±20 ppm, SMD32*25 mm crystal
±20%, 0402 X7R, 25 V
26
MHz
uF
EPSON
0.1
Murata GRM15
Murata GRM15
Murata GRM15
Murata GRM15
Murata LQG18
Murata LQG18
Murata LQG18
C1
±5%, 0402 NP0, 50 V
68
15
68
9.1
8.2
100
8.2
8.2
pF
C2
±5%, 0402 NP0, 50 V
pF
C3
±5%, 0402 NP0, 50 V
15
pF
L1
±5%, 0603 multi-layer chip inductor
±5%, 0603 multi-layer chip inductor
±5%, 0603 multi-layer chip inductor
180
36
nH
nH
nH
L2
L3
18
Note:
[1]. The 868.35 MHz Application is for CMT2117AW only.
Rev 1.2 | Page 11/25
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CMT2110/17AW
5. Functional Descriptions
VDD
LDOs
GND
POR
Bandgap
XOSC
VCO
XTAL
PFD/CP
Loop Filter
RFO
PA
Fractional-N
DIV
Ramp
Control
EEPROM
OOK Modulator
CLK
Interface and Digital Logic
DATA
Figure 11. CMT2110/17AW Functional Block Diagram
5.1 Overview
The CMT2110/17AW is an ultra low-cost, highly flexible, high performance, single-chip OOK transmitter for various 240 to 960
MHz wireless applications. The CMT2110AW covers the frequency range from 240 to 480 MHz while the CMT2117 covers the
240 to 960 MHz frequency range. They are part of the CMOSTEK NextGenRFTM family, which includes a complete line of
transmitters, receivers and transceivers. The chip is optimized for the low system cost, low power consumption, battery
powered application with its highly integrated and low power design.
The functional block diagram of the CMT2110/17AW is shown in the figure above. The CMT2110/17AW is based on direct
synthesis of the RF frequency, and the frequency is generated by a low-noise fractional-N frequency synthesizer. It uses a
1-pin crystal oscillator circuit with the required crystal load capacitance integrated on-chip to minimize the number of external
components. Every analog block is calibrated on each Power-on Reset (POR) to the highly accurate reference voltage
internally. The calibration can help the chip to finely work under different temperatures and supply voltages. The
CMT2110/17AW uses the DATA pin for the host MCU to send in the data. The input data will be modulated and sent out by a
highly efficient PA which output power can be configured from -10 to +13 dBm in 1 dB step size. RF Frequency, PA output
power and other product features can be programmed into the embedded EEPROM by the RFPDK and USB Programmer.
This saves the cost and simplifies the product development and manufacturing effort. Alternatively, in stock products of
433.92/868.35 MHz are available for immediate demands with no need of EEPROM programming. The CMT2110/17AW
operates from 1.8 to 3.6 V so that it can finely work with most batteries to their useful power limits. Working under 3.3 V supply
voltage when transmitting signal at +10 dBm power, it only consumes 13.4 mA at 433.92 MHz and 15.5 mA at 868.35 MHz.
5.2 Modulation, Frequency and Symbol Rate
The CMT2110/17AW supports OOK modulation with the symbol rate up to 30 ksps. The CMT2110AW covers the frequency
range from 240 to 480 MHz, while the CMT2117AW covers the frequency range from 240 to 960 MHz, including the license
free ISM frequency band around 315 MHz, 433.92 MHz, 868.35 MHz and 915 MHz. The device contains a high spectrum
purity low power fractional-N frequency synthesizer with output frequency resolution better than 198 Hz when the frequency is
lower than 480 MHz, and the frequency resolution is 397 Hz when the frequency is higher than 480 MHz. See the table below
for the modulation, frequency and symbol rate specifications.
Rev 1.2 | Page 12/25
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CMT2110/17AW
Table 10. Modulation, Frequency and Symbol Rate
Parameter
Value
Unit
Modulation
OOK
240 to 480
240 to 960
198
-
Frequency (CMT2110AW)
Frequency (CMT2117AW)
Frequency Resolution (FRF ≤ 480 MHz)
Frequency Resolution (FRF > 480 MHz)
Symbol Rate
MHz
MHz
Hz
Hz
397
0.5 to 30
ksps
5.3 Embedded EEPROM and RFPDK
The RFPDK (RF Products Development Kit) is a very user-friendly software tool delivered for the user configuring the
CMT2110/17AW in the most intuitional way. The user only needs to fill in/select the proper value of each parameter and click
the “Burn” button to complete the chip configuration. No register access and control is required in the application program. See
the figure below for the accessing of the EEPROM and Table 11 for the summary of all the configurable parameters of the
CMT2110/17AW in the RFPDK.
CMT2110/17AW
RFPDK
EEPROM
CLK
CMOSTEK USB
Programmer
Interface
DATA
Figure 12. Accessing Embedded EEPROM
For more details of the CMOSTEK USB Programmer and the RFPDK, please refer to “AN103 CMT211xA-221xA One-Way RF
Link Development Kits Users Guide”. For the detail of CMT2110/17AW configurations with the RFPDK, please refer to “AN102
CMT2110/17A Configuration Guideline”.
Table 11. Configurable Parameters in RFPDK
Category
Parameters
Descriptions
Default
Mode
Frequency
To input a desired transmitting radio frequency in the
Basic
Advanced
Basic
433.92 MHz
(CMT2110AW) range from 240 to 480 MHz. The step size is 0.001 MHz.
Frequency To input a desired transmitting radio frequency in the
868.35 MHz
+13 dBm
15 pF
(CMT2117AW) range from 240 to 960 MHz. The step size is 0.001 MHz.
Advanced
Basic
To select a proper transmitting output power from -10
Tx Power
RF Settings
dBm to +14 dBm, 1 dBm margin is given above +13 dBm.
Advanced
Basic
On-chip XOSC load capacitance options: from 10 to 22
Xtal Cload
pF.
Advanced
To control PA output power ramp up/down time, options
PA Ramping
0 us
Advanced
Advanced
are 0 and 2n us (n from 0 to 10).
Start condition of a transmitting cycle, by Data Pin
Data Pin
Rising Edge
Data Pin
Start by
Rising/Falling Edge.
Transmitting
Settings
Stop condition of a transmitting cycle, by Data Pin
Stop by
Holding Low
for 20 ms
Advanced
Holding Low for 20 to 90 ms.
Rev 1.2 | Page 13/25
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CMT2110/17AW
5.4 Power Amplifier
A highly efficient single-ended Power Amplifier (PA) is integrated in the CMT2110/17AW to transmit the modulated signal out.
Depending on the application, the user can design a matching network for the PA to exhibit optimum efficiency at the desired
output power for a wide range of antennas, such as loop or monopole antenna. Typical application schematics and the
required BOM are shown in “Chapter 4 Typical Application Schematic”. For the schematic, layout guideline and the other
detailed information please refer to “AN101 CMT211xA Schematic and PCB Layout Design Guideline”.
The output power of the PA can be configured by the user within the range from -10 dBm to +13 dBm in 1 dB step size using
the CMOSTEK USB Programmer and RFPDK.
5.5 PA Ramping
When the PA is switched on or off quickly, its changing input impedance momentarily disturbs the VCO output frequency. This
process is called VCO pulling, and it manifests as spectral splatter or spurs in the output spectrum around the desired carrier
frequency. By gradually ramping the PA on and off, PA transient spurs are minimized. The CMT2110/17AW has built-in PA
ramping configurability with options of 0, 1, 2, 4, 8, 16, 32, 64, 128, 256, 512 and 1024 us, as shown in Figure 13. When the
option is set to “0”, the PA output power will ramp up to its configured value in the shortest possible time. The ramp down time
is identical to the ramp up time in the same configuration.
CMOSTEK recommends that the maximum symbol rate should be no higher than 1/2 of the PA ramping “rate”, as shown in the
formula below:
1
tRAMP
)
SRMax ≤ 0.5 * (
In which the PA ramping “rate” is given by (1/tRAMP). In other words, by knowing the maximum symbol rate in the application,
the PA ramping time can be calculated by:
1
tRAMP ≤ 0.5 * (
)
SRMAX
The user can select one of the values of the tRAMP in the available options that meet the above requirement. If somehow the
tRAMP is set to be longer than “0.5 * (1/SRMax)”, it will possibly bring additional challenges to the OOK demodulation of the Rx
device. For more detail of calculating tRAMP, please refer to “AN102 CMT2110/17A Configuration Guideline”.
0 us
1 us
2 us
4 us
8 us
512 us
1024 us
Time
Logic 1
Logic 0
Time
Figure 13. PA Ramping Time
Rev 1.2 | Page 14/25
www.hoperf.com
CMT2110/17AW
5.6 Crystal Oscillator and RCLK
The CMT2110/17AW uses a 1-pin crystal oscillator circuit with the required crystal load capacitance integrated on-chip. Figure
14 shows the configuration of the XTAL circuitry and the crystal model. The recommended specification for the crystal is 26
MHz with ±20 ppm, ESR (Rm) < 60 Ω, load capacitance CLOAD ranging from 12 to 20 pF. To save the external load capacitors, a
set of variable load capacitors CL is built inside the CMT2110/17AW to support the oscillation of the crystal.
The value of load capacitors is configurable with the CMOSTEK USB Programmer and RFPDK. To achieve the best
performance, the user only needs to input the desired value of the XTAL load capacitance CLOAD of the crystal (can be found in
the datasheet of the crystal) to the RFPDK, then finely tune the required XO load capacitance according to the actual XO
frequency. Please refer to “AN103 CMT211xA-221xA One-Way RF Link Development Kits Users Guide” for the method of
choosing the right value of CL.
Crystal Model
CMT2110/17AW
CMT2110/17AW
Cc
XTAL
XTAL
RCLK
26 MHz
Rm
0. 3 –0. 7 Vpp
Cm
Lm
C0
CL
CL
Figure 14. XTAL Circuitry and Crystal Model
Figure 15. RCLK Circuitry
If a 26 MHz RCLK (reference clock) is available in the system, the user can directly use it to drive the CMT2110/17AW by
feeding the clock into the chip via the XTAL pin. This further saves the system cost due to the removal of the crystal. A coupling
capacitor is required if the RCLK is used. The recommended amplitude of the RCLK is 0.3 to 0.7 Vpp on the XTAL pin. Also,
the user should set the internal load capacitor CL to its minimum value. See Figure 15 for the RCLK circuitry.
Rev 1.2 | Page 15/25
www.hoperf.com
CMT2110/17AW
6. Working States and Transmission Control Interface
6.1 Working States
The CMT2110/17AW has 4 different working states: SLEEP, XO-STARTUP, TUNE and TRANSMIT.
SLEEP
When the CMT2110/17AW is in the SLEEP state, all the internal blocks are turned off and the current consumption is
minimized to 20 nA typically.
XO-STARTUP
After detecting a valid control signal on DATA pin, the CMT2110/17AW goes into the XO-STARTUP state, and the internal XO
starts to work. The valid control signal can be a rising or falling edge on the DATA pin, which can be configured on the RFPDK.
The host MCU has to wait for the tXTAL to allow the XO to get stable. The tXTAL is to a large degree crystal dependent. A typical
value of tXTAL is provided in Table 12.
TUNE
The frequency synthesizer will tune the CMT2110/17AW to the desired frequency in the time tTUNE. The PA can be turned on to
transmit the incoming data only after the TUNE state is done, before that the incoming data will not be transmitted. See Figure
16 and Figure 17 for the details.
TRANSMIT
The CMT2110/17AW starts to modulate and transmit the data coming from the DATA pin. The transmission can be ended in 2
methods: firstly, driving the DATA pin low for tSTOP time, where the tSTOP can be configured from 20 to 90 ms on the RFPDK;
secondly, issuing SOFT_RST command over the two-wire interface, this will stop the transmission in 1 ms. See section 6.2.3
for details of the two-wire interface.
Table 12. Timing in Different Working States
Parameter
Symbol
tXTAL
Min
Typ
400
370
Max
Unit
us
XTAL Startup Time [1]
Time to Tune to Desired Frequency
tTUNE
us
Hold Time After Rising Edge
tHOLD
10
20
ns
Time to Stop The Transmission[2]
tSTOP
90
ms
Notes:
[1]. This parameter is to a large degree crystal dependent.
[2]. Configurable from 20 to 90 ms in 10 ms step size.
6.2 Transmission Control Interface
The CMT2110/17AW uses the DATA pin for the host MCU to send in data for modulation and transmission. The DATA pin can
be used as pin for EEPROM programming, data transmission, as well as controlling the transmission. The transmission can be
started by detecting rising or falling edge on the DATA pin, and stopped by driving the DATA pin low for tSTOP as shown in the
table above. Besides communicating over the DATA pin, the host MCU can also communicate with the device over the
two-wire interface, so that the transmission is more robust, and consumes less current.
Please note that the user is recommended to use the Tx Enabled by DATA pin Rising Edge, which is described in Section
6.2.1.
Rev 1.2 | Page 16/25
www.hoperf.com
CMT2110/17AW
6.2.1 Tx Enabled by DATA Pin Rising Edge
As shown in the Figure 16, once the CMT2110/17AW detects a rising edge on the DATA pin, it goes into the XO-STARTUP
state. The user has to pull the DATA pin high for at least 10 ns (tHOLD) after detecting the rising edge, as well as wait for the sum
of tXTAL and tTUNE before sending any useful information (data to be transmitted) into the chip on the DATA pin. The logic state of
the DATA pin is “Don't Care” from the end of tHOLD till the end of tTUNE. In the TRANSMIT state, PA sends out the input data after
they are modulated. The user has to pull the DATA pin low for tSTOP in order to end the transmission.
SLEEP
SLEEP
XO-STARTUP TUNE
TRANSMIT
STATE
t
TUNE
t
XTAL
t
STOP
0
Rising Edge
0
Don’t Care
Valid Transmitted Data
RF Signals
1
DATA pin
PA out
t
HOLD
Figure 16. Transmission Enabled by DATA Pin Rising Edge
6.2.2 Tx Enabled by DATA Pin Falling Edge
As shown in the Figure 17, once the CMT2110/17AW detects a falling edge on the DATA pin, it goes into XO-STARTUP state
and the XO starts to work. During the XO-STARTUP state, the DATA pin needs to be pulled low. After the XO is settled, the
CMT2110/17AW goes to the TUNE state. The logic state of the DATA pin is “Don't Care” during the TUNE state. In the
TRANSMIT state, PA sends out the input data after they are modulated. The user has to pull the DATA pin low for tSTOP in order
to end the transmission. Before starting the next transmit cycle, the user has to pull the DATA pin back to high.
TRANSMIT
SLEEP
SLEEP XO-STARTUP TUNE
STATE
t
TUNE
t
STOP
0
t
XTAL
Falling Edge
Don’t Care
1
0
1
Valid Transmitted Data
RF Signals
DATA pin
PA out
Figure 17. Transmission Enabled by DATA Pin Falling Edge
6.2.3 Two-wire Interface
For power-saving and reliable transmission purposes, the CMT2110/17AW is recommended to communicate with the host
MCU over a two-wire interface (TWI): DATA and CLK. The TWI is designed to operate at a maximum of 1 MHz. The timing
requirement and data transmission control through the TWI are shown in this section.
Rev 1.2 | Page 17/25
www.hoperf.com
CMT2110/17AW
Table 13. TWI Requirements
Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Digital Input Level High
Digital Input Level Low
CLK Frequency
VIH
VIL
0.8
VDD
VDD
kHz
ns
0.2
FCLK
tCH
10
1,000
CLK High Time
500
500
CLK Low Time
tCL
ns
CLK delay time for the first falling edge of the
TWI_RST command, see Figure 20
The data delay time from the last CLK rising
edge of the TWI command to the time DATA
return to default state
CLK Delay Time
tCD
20
15,000
15,000
ns
DATA Delay Time
tDD
ns
DATA Setup Time
DATA Hold Time
tDS
tDH
From DATA change to CLK falling edge
From CLK falling edge to DATA change
20
ns
ns
200
CLK
tCH
tCL
t
DS DH
t
DATA
Figure 18. Two-wire Interface Timing Diagram
Once the device is powered up, TWI_RST and SOFT_RST should be issued to make sure the device works in SLEEP state
robustly. On every transmission, TWI_RST and TWI_OFF should be issued before the transmission to make sure the TWI
circuit functions correctly. TWI_RST and SOFT_RST should be issued again after the transmission for the device going back to
SLEEP state reliably till the next transmission. The operation flow with TWI is shown as the figure below.
Reset TWI
One Transmission Cycle
One Transmission Cycle
(1) - TWI_RST
(2) - SOFT_RST
(1) - TWI_RST
(2) - TWI_OFF
(1) - TWI_RST
(2) - SOFT_RST
(1) - TWI_RST
(2) - TWI_OFF
(1) - TWI_RST
(2) - SOFT_RST
TRANSMISSION
TRANSMISSION
Figure 19. CMT2110/17AW Operation Flow with TWI
Table 14. TWI Commands Descriptions
Descriptions
Command
Implemented by pulling the DATA pin low for 32 clock cycles and clocking in 0x8D00, 48 clock cycles in total.
It only resets the TWI circuit to make sure it functions correctly. The DATA pin cannot detect the
Rising/Falling edge to trigger transmission after this command, until the TWI_OFF command is issued.
TWI_RST
Notes:
1.
2.
Please ensure the DATA pin is firmly pulled low during the first 32 clock cycles.
When the device is configured as Transmission Enabled by DATA Pin Falling Edge, in order to issue
the TWI_RST command correctly, the first falling edge of the CLK should be sent tCD after the DATA
falling edge, which should be longer than the minimum DATA setup time 20 ns, and shorter than 15 us,
Rev 1.2 | Page 18/25
www.hoperf.com
CMT2110/17AW
Command
Descriptions
as shown in Figure 20.
3.
When the device is configured as Transmission Enabled by DATA Pin Rising Edge, the default state of
the DATA is low, there is no tCD requirement, as shown in Figure 21.
Implemented by clocking in 0x8D02, 16 clock cycles in total.
TWI_OFF
It turns off the TWI circuit, and the DATA pin is able to detect the Rising/Falling edge to trigger transmission
after this command, till the TWI_RST command is issued. The command is shown as Figure 22.
Implemented by clocking in 0xBD01, 16 clock cycles in total.
It resets all the other circuits of the chip except the TWI circuit. This command will trigger internal calibration
for getting the optimal device performance. After issuing the SOFT_RST command, the host MCU should
wait 1 ms before sending in any new command. After that, the device goes to SLEEP state. The command is
shown as Figure 23.
SOFT_RST
32 clock cycles
16 clock cycles
CLK
…
…
t
CD
tDD
1
0
0x8D00
1
DATA
Figure 20. TWI_RST Command When Transmission Enabled by DATA Pin Falling Edge
32 clock cycles
16 clock cycles
CLK
…
…
0
0x8D00
0
DATA
Figure 21. TWI_RST Command When Transmission Enabled by DATA Pin Rising Edge
16 clock cycles
16 clock cycles
CLK
…
CLK
…
t
DD
t
DD
Default
State
Default
State
DATA
0x8D02 (TWI_OFF)
DATA
0xBD01 (SOFT_RST)
Figure 22. TWI_OFF Command
Figure 23. SOFT_RST Command
The DATA is generated by the host MCU on the rising edge of CLK, and is sampled by the device on the falling edge. The CLK
should be pulled up by the host MCU during the TRANSMISSION shown in Figure 19. The TRANSMISSION process should
refer to Figure 16 or Figure 17 for its timing requirement, depending on the “Start By” setting configured on the RFPDK.
The device will go to SLEEP state by driving the DATA low for tSTOP, or issuing SOFT_RST command. A helpful practice for the
device to go to SLEEP is to issue TWI_RST and SOFT_RST commands right after the useful data is transmitted, instead of
waiting the tSTOP, this can save power significantly.
Rev 1.2 | Page 19/25
www.hoperf.com
CMT2110/17AW
7. Ordering Information
Table 15. CMT2110/17AW Ordering Information
Package
Type
Package
Option
Operating
MOQ /
Part Number
Descriptions
Condition
1.8 to 3.6 V,
-40 to 85 ℃
1.8 to 3.6 V,
-40 to 85 ℃
Multiple
Low-Cost 240-480 MHz
OOK Transmitter
CMT2110AW-ESR[1]
SOT23-6
SOT23-6
Tape & Reel
Tape & Reel
3,000
3,000
Low-Cost 240-960 MHz
OOK Transmitter
CMT2117AW-ESR[1]
Notes:
[1]. “E” stands for extended industrial product grade, which supports the temperature range from -40 to +85 ℃.
“S” stands for the package type of SOT23-6.
“R” stands for the tape and reel package option, the minimum order quantity (MOQ) for this option is 3,000 pieces.
The default frequency for CMT2110AW-ESR is 433.92 MHz, for CMT2117AW-ESR is 868.35 MHz, for the other
settings, please refer to the Table 11 of Page 13.
Visit www.cmostek.com/products to know more about the product and product line.
Contact sales@cmostek.com or your local sales representatives for more information.
Rev 1.2 | Page 20/25
www.hoperf.com
CMT2110/17AW
8. Package Outline
The 6-pin SOT23-6 illustrates the package details for the CMT2110/17AW. Table 16 lists the values for the dimensions shown
in the illustration.
e1
e
0.25
L
E1
E
c
b
θ
D
A
A2
A3
A1
Figure 24. 6-Pin SOT23-6
Table 16. 6-Pin SOT23-6 Package Dimensions
Size (millimeters)
Symbol
Min
—
Typ
—
Max
1.35
0.15
1.20
0.75
0.48
0.20
3.12
3.00
1.80
A
A1
A2
A3
b
0.04
1.00
0.55
0.38
0.08
2.72
2.60
1.40
—
1.10
0.65
—
C
—
D
2.92
2.80
1.60
0.95 BSC
1.90 BSC
—
E
E1
e
e1
L
0.30
0
0.60
8°
θ
—
Rev 1.2 | Page 21/25
www.hoperf.com
CMT2110/17AW
9. Top Marking
9.1 CMT2110/17AW Top Marking
6
5
4
6
5
4
0 A
7 A
① ② ③
① ② ③
1
2
3
1
2
3
Figure 25. CMT2110AW (Left) and CMT2117AW (Right) Top Marking
Table 17. CMT2110/17AW Top Marking Explanation
Top Mark:
0A①②③ / 7A①②③
Mark Method:
Font Size:
Laser
0.6 mm, right-justified
0, represents CMT2110AW
1st letter:
7, represents CMT2117AW
2nd letter:
A: represents revision A
3rd – 5th letter:
①②③: Internal reference for data code tracking, assigned by the assembly house
Rev 1.2 | Page 22/25
www.hoperf.com
CMT2110/17AW
10.Other Documentations
Table 18. Other Documentations for CMT2110/17AW
Brief
Name
Descriptions
Details of CMT2110/13/17/19AW PCB schematic and layout
design rules, RF matching network and other application
layout design related issues.
CMT211xA Schematic and PCB Layout
Design Guideline
AN101
Details of configuring CMT2110/17AW features on the
RFPDK.
AN102
AN103
CMT2110/17A Configuration Guideline
User’s Guides for CMT211xAW and CMT221xAW
Development Kits, including Evaluation Board and
Evaluation Module, CMOSTEK USB Programmer and the
RFPDK.
CMT211xA-221xA One-Way RF Link
Development Kits Users Guide
Rev 1.2 | Page 23/25
www.hoperf.com
CMT2110/17AW
11.Document Change List
Table 19. Document Change List
Rev. No.
Chapter
Description of Changes
Initial released version
Date
0.7
All
2014-03-04
0
1
3
4
5
Add Ordering Information in first page
Update Table 5
Update the title of Figure8/9
0.8
2014-04-05
Update the BOM of Typical Application Schematics
Update Section 5.3 Embedded EEPROM and RFPDK Add Section
5.5 PA Ramping
1
3
0
Update Table 5
0.85
0.9
2014-04-08
2014-06-14
Update Figure 4
Update ordering Information in first page
Update Description
5
7
Update 5.3, add Table 11
Update chapter 7. Ordering information
1.0
1.1
1.2
-
-
2014-06-30
2015-01-16
2015-01-23
All
6
Add product CMT2117AW to the datasheet
Add Section 6.2.3
6
Update Section 6.2.3
Rev 1.2 | Page 24/25
www.hoperf.com
CMT2110/17AW
12.Contact Information
Hope Microelectronics Co., Ltd.
Address: 2/F,Building3,Pingshan Private Enterprise science and Technology Park,Xili Town,Nanshan District,Shenzhen,China
Tel: +86-755-82973805
Fax: +86-755-82973550
Email: sales@hoperf.com
hoperf@gmail.com
Website: http://www.hoperf.com
http://www.hoperf.cn
Copyright. CMOSTEK Microelectronics Co., Ltd. All rights are reserved.
The information furnished by CMOSTEK is believed to be accurate and reliable. However, no responsibility is assumed for
inaccuracies and specifications within this document are subject to change without notice. The material contained herein is
the exclusive property of CMOSTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior
written permission of CMOSTEK. CMOSTEK products are not authorized for use as critical components in life support
devices or systems without express written approval of CMOSTEK. The CMOSTEK logo is a registered trademark of
CMOSTEK Microelectronics Co., Ltd. All other names are the property of their respective owners.
Rev 1.2 | Page 25/25
www.hoperf.com
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