COIC5130A [ETC]
Programmable Reed-Solomon Error Correction Encoder and Decoder; 可编程的里德 - 所罗门纠错编码器和解码
| 型号： | COIC5130A |
| 厂家： | 
ETC |
| 描述： | Programmable Reed-Solomon Error Correction Encoder and Decoder |
| 文件： | 总20页 (文件大小：291K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
COic5130A
Specifications
Preliminary Device Specification
t = 0 to 10, 320Mbs,
Introduction
Programmable Reed-Solomon
Error Correction Encoder and Decoder
The COic5130A contains both a high data rate programmable
Reed-Solomon encoder and a separate decoder that will process
blocks of up to 255 eight bit symbols to provide corrections (T) of
up to 10 errors per code block at data rates up to 320 Mbs. The
encoder output code block will contain the unaltered original data
symbols followed by the generated parity symbols. The decoder
input will contain the received data symbols including errors that
may be introduced during transmission.Decoder output will be a
completely corrected block or will be marked as non-correctable
and the block will be outputted as received without any changes.
For information on separate encoder refer to the COic5127A data sheet.
For information on separate decoder refer to the COiC5128A data sheet.
The encoder and decoder can be operated independent of each
other. Either or both may active at one time. As the devices have
separate clocks, the encoder and decoder may operate at different
data rates.
The 128-pin mqfp device is manufactured using an 0.5micron
CMOS technology by a ISO 9000 certified facility. This part is
functionally compatible with the COic5125A, COic5126A,
COic5127A and COic5128A and also theAMPEX 1295125-01 and
1295126, but includes features not found in the Ampex devices.
~
Optic
Co~
■
■
■
■
1742 Sand Hill Road, Suite 303, Palo Alto, CA 94304
Tel: (650)321-3390
Fax: (650) 322-8569
Email: sales@co-optic.com
Web: www.co-optic.com
©1998, Co-Optic, Inc. All rights reserved. Specifications subject to change without notice.
COic5130A Specifications
2
~
Optic
Co~
Encoder Functional Description
• Requires only one ( byte ) clock. Input and output data are at one
byte per symbol clock for each the encoder and decoder
The COic5130A contains an encoder that will provide ( N, N-r ) Reed-
Solomon forward error correction encoding of blocks of eight bit sym-
bols.The number of parity symbols ( r ) may be from 0 to 20 , 0 in Pass
Through Mode,and the number of symbols in a block ( N ) from r+1 to
255. At the decoder two parity bytes will be used for each untagged
symbol error correction and one parity byte used for a location identi-
fied error (erasure ) correction. This will provide correction of up to 10
errors ( E ) or up to 20 erasures ( e ) or a combination as long as 2E + e
</= r.
• Code provides choice of 0 to 20 parity bytes per block
• Provides Pass Through ( no parity ) mode switching on the fly
• Processing latency of only 3 symbol clocks
• Allows code rate changes on the fly
• ISO 9000 certified manufacturing
• 128-pin metal quad flat pack
• Vdd 4.5 to 5.5 volts operation
The encoder can encode data at rates from 0 to 40 million symbols per
second ( 320 Mbs ) These devices implement the primitive polynomial
Px = x8+ x4 + x3 + x2 + x0 and the generator polynomial
• - 40 to + 85 degrees C operation
r-1
G ( x) = II ( x - µ i )
i =0
Encoder Initialization
Before operations the encoder must be initialized to define the number
of parity symbols ( r ).
which are compatible with SMPTE D-1/D-2,ANSI ID1/ID2, MIL- STD-
2179A, DVB, DDS, DAVIC, and DSL standards.
To initialize the binary value of r/2 ( 0 to 10 ) is placed in TA0 - TA3 (TA0
is least significant ) while Reset and EnlnA are held low for four symbol
clock periods.Reset is then brought and held high for two symbol clock
periods. The inputs on TA0 - TA3 can then be released and the section
can start normal operation.
Controls are provided to :
1. tri-state the output data bus
2. disable the input data
3. select the output data source
(input data bus or parity generator)
Any TAx pin that is not used must be held low or connected to ground.
Encoder Functional Block Diagram
Encoding
To encode a block of symbols the enable in line ( EnlnA) and enable out
line ( EnOutA ) are brought high coincident with the leading edge of
first data symbol clock in a new block and remain high until all of the
data symbols are clocked into the encoder section and k-3 symbols out
onto the Dout bus. There is a processing latency ( delay ) of three clock
cycles between the data in ( DinA ) and the data out ( DoutA.).The data
ready signal ( RdyA ) is EnlnA delayed by three clock cycles.
Din (7.0)
1
0
1
0
Encoder
Dout (7.0)
En Out
En Out
At the leading edge of the clockA pulse after the last data symbol has
been placed into the encoder, EnlnA and EnOutA are brought low. This
will fill the parity generator will zeros. EnlnA and EnOutA are held low
for ( r ) clock cycles which inputs zeros into the encoder while out-
putting the parity code symbols which are appended to the data sym-
bols to form the output data stream. After at least r clock cycles EnlnA
and EnOutA are brought high to start the next block.
T (3.0)
TriEn
Reset
Clock
Control
Rty
Encoder Features
• Supports 8 bit symbol Reed-Solomon codes ( N, N- r ) with
0 < r < 20 and r+1 < N < 255,N= symbols per block including par-
ity, r = number of parity bytes (NOTE: r is often called 2t)
The output data bus ( DoutA ) may be put into a high impedance state
by bringing the TriEnA high. This will not effect the operation of the
encoder except to disable the output bus.
• Encoding rates from 0 to 320 Mbs with 0 to 40 Mhz symbol clock
When the input enable ( EnlnA) is low, zeros will be clocked into the
encoder input. This can be used to prevent spurious data from being
encoded.
• Implements SMPTE D-1/D-2 Digital Video Standards, DVBS Digital
Video,ANSI ID-1/ID-2, and Mil -STD-2179A coding polynomials
COic5130A Specifications
3
~
Optic
Co~
The number of data symbols ( k ) of succeeding blocks can be changed
as desired at any time. This will change the code rate for the blocks, but
to change the correction power ( r ) the section must be re-initialized.
This can also be done at any time,but any blocks in process at that time
will be lost.
COic5128 decoder as well as the T=5 AMPEX 1295126-01. It includes
features not found in that device, and using r = 20 corrects up to 10
errors per block.
r-1
Devices use the generator polynomial : G ( x) = Õ ( x - µ i )
i=0
Encoder Duplex Operation
Half Duplex operation can be achieved on a single bi-directional chan-
nel at a maximum transmission rate equal toone half of the symbol
clock. Allowing for transmission and circuit switching delays, data can
be switched from the unit encoder to the decoder on any symbol
boundary. External data switching and control circuits will be required
to control data flow and device enables.
Decoder Functional Block Diagram
DIN7 - DIN0
FIFO
DOUT7- DOUT0
Error Locator
& Evaluator
Error
Correct
MAG7- MAG0
LOC
Full duplex at full clock rate can be implemented but requires two data
carriers or echo cancellation.
CLK
Encoder Pass Through Mode
DATARDY
CORR
Control
Any number of symbols can be passed through the encoder without any
encoding if the Enable In (EnlnA) is held high and enable out ( EnOutA)
is held low while the symbols are clocked into the section. This will
allow the maximum data transfer rate, but will not provide any error
correction (t=0 ). To end pass through mode operation EnlnA must be
brought high,which will start the encoding process.This must be at the
beginning of a block for correct operations. Pass through mode may be
invoked at any time but any blocks in process when this mode is start-
ed will not be encoded properly and will not be able to be decoded.
DATAEN
RESET
SHORT1
P0 - P4
ENABIN
STATEN
SHORT2
Decoder Features
• Supports 8 bit symbol Reed Solomon codes ( N,N-r ) with 0 < r < 20
and N < 255, N= symbols per block including parity, r = number of
parity symbols (Note: r is often called 2t)
Decoder Functional Description
COic5130A includes a high data rate programmable Forward Error
Correction devices that can decode Reed-Solomon code blocks of up to
255 eight bit data symbols. It provides corrections of up to 10 symbol
errors per block at data rates up to 320 Mbs. Blocks with more errors
than are correctable are so flagged with data outputted as received ( no
corrections ).Note:blocks must contain at least 8 parity symbols,except
when operating in bypass mode.
• Corrects up to 10 errors per block
• COic5128A has 3 selectable latencies:
Default ( Ampex / AHA ) = 2N + 5r + 33 clock cycles with a
minimum block length of 5r + 15
Latency 1 = 2N + 2r + 13 clock cycles with a minimum block
length of 2r + 13
Latency 2 = 3N /2 +3r/2 + 15 clock cycles with a minimum
block length of 3r/2 + 15
• Contains complete decoder device. No external memory or control
required after initialization
The decoder input code block will contain the transmitted data and par-
ity symbols, including corruption by channel noise ( errors ).A symbol
error is corrected the same regardless of the number of incorrect bits in
the symbol and decoding time is the same regardless of the number of
errors in a block. Decoder output data will be corrected data plus cor-
rected parity or block error data. Error location and correction data is
also provided. No clock other than the data clock is required.Input and
output are one byte per clock cycle.
• Data rates up to 40 MBS ( 320 Mbs ) with 0 to 40 Mhz symbol clock
• End of Block flag eases applications
• Input and output data are at the identical rate and operates on data
clock only
• Provides Pass Through Mode ( no correction ) switching on-the-fly
• Latency is constant regardless of error patterns
COic5130A uses the primitive polynomial Px = x 8 + x4 + x 3 + x2 +
x0 which complies with SMPTE D-1 / D-2 Digital Video Standards,
DVB,DBS, DAVIC, DSL, ANSI ID-1 / ID-2, and MIL STD 2179A. The
COic5130A is functionally compatible with the COic5127 encoder and
• Allows code rate change ( less data, same parity ) on-the-fly
COic5130A Specifications
4
~
Optic
Co~
• Provides complete error location and correction information
• Flags uncorrectable blocks
regular data block may be used for this step but to prevent possible loss
of data a block using dummy symbols of any value is recommended.
• 4.5 to 5.5 volt operation
Selecting the value of P
• -40 to + 85 degrees C operation range (extended range available)
• ISO 9000 certified manufacturing
The value of P determines the number of parity bytes that can be used
(decoded) before a block is flagged as uncorrectable. The decoder will
always use all of the parity bytes available to correct a block regardless
of the value of P, which is usually set equal to r (the number of parity
bytes) but P can be less or more than r.
Decoder Functional Description
The device contains a decoder that will provide ( N,N-r ) Reed-Solomon
forward error correction decoding of blocks of eight bit symbols. The
number of parity symbols (r ) may be from 8 to 20, 0 in Pass Through
Mode, and the number of symbols in a block ( N ) up to 255 . Two par-
ity bytes will be used for each symbol error correction. This device will
provide correction of up to 10 symbol errors ( E ) as long as 2E </= r.It
will provide the number of corrections made in each block. Symbol
errors are processed the same regardless of the number of incorrect bits
in the symbol. Processing latency is the same regardless of the number
of errors, including zero, in a block. The device can decode at data rates
from 0 to 40 million symbols per second ( 320 Mbs ) and two or more
devices can be used together ( see Application Brief for Reed-Solomon
FEC ) to process data at higher rates.
1. If P equals r the device will properly correct all blocks where 2E </=
r and mark all other blocks as uncorrectable. This option is almost
always used.
2. If P is less than r the device will use all of the parity bytes to correct
the block but will mark corrected blocks as uncorrected if P < 2E < r.
In this case the error status bytes must be checked to determine if
correction was actually achieved. This feature can be used to detect
more errors than can be corrected, but must be used with care.
3. If P is more than r normal correction will take place but the device
will not provide uncorrectable block flags and may pass on to the out-
put unflagged uncorrected data blocks . THIS SETTING HAS NO
VALUE AND SHOULD NOT BE USED.
Encoder Initialization
4. If P is more than 20 the decoder will pass all information directly to
the data output without any corrections. THIS SETTING HAS NO
VALUE AND SHOULD NOT BE USED.
Before operations the device must be initialized to define N, r, P ( the
number of parity symbols that can be used ( decoded ) before a block is
determined uncorrectable ) and to set the block error information
report (status) output.A two step process is used.
The value of P may be changed at any time,but any blocks in process at
the time of the change may not be properly flagged if uncorrectable.
Step One: Set the level of OptLn to the desired level and maintain
throughtout all operations.While the binary value of P is held on the P
control bus,Reset and DataEn are held low for at least four symbol clock
cycles and then Reset is brought high and held high for at least two more
symbol clock cycles.At the same time the StatEn line is held high if the
decoder block error information bytes ( status ) output are desired and
low if not.Note that the decoder will output corrected parity bytes in the
space formerly used by parity which are not used by block error infor-
mation (status) bytes. Symbols of any value can be used for this step.
Minimum Block Lengths
Minimum block lengths and latency are a function of the number of
parity bytes used in a code. OptLn must be set at the start of initializa-
tion and held at the correct level throughout operations. The device
must repeat Initialization if OptLn is to be changed
The COic5130A allows three different equations to determine the mini-
mum block lengths.When pin 16 is low and pin 9 LOW or NC the default
equation is Minimum Block Length = 5r + 15 bytes.When pin 9 is held
at High and pin 16 is low level Latency1 is invoked and the minimum
block length equation is changed to (2r + 13) bytes. If pin 16 is high
Latency 2 is invoked and the minimum block length is 3r/2 + 15 regar-
dles of the level of pin 9.
Step Two : With Reset high a normal block processing procedure is used
to set up values of N, r, and k ( N-r ). The Enabln is brought high with
the first data symbol and held high throughout the decoding secession.
Also at the beginning of the block DataEn is brought high at the leading
edge of the first symbol clock pulse and held high while the data sym-
bols are being clocked into the device, that is N-r symbol clock pluses.
DataEn is brought low with the first parity symbol and held low for r
symbol clock cycles while the parity symbols are clocked in. DataEn‚s
going high again marks the end of parity and the start of the next block.
Reset will remain high throughout step 2 and normal use until a new
reset cycle is desired. This step will set up the device timing for all fol-
lowing blocks until the device is reinitialized or an alternate length
block with fewer data symbols ( see Alternate Block Length ) is used.A
Decoder Latency
The time that is required for the data to flow through the device is called
latency and is measured in symbol clock cycles. The devices can be
operated with any of three latencies, under the control of OpLan1,pin 9
and OpLan2, pin 16. Latencies are a function of the block length and
correction level, but unaffected by error patterns. The default latency
(pin 9 and 16 both low) is equal to 2N + 5r + 33 symbol clock cycles,
COic5130A Specifications
5
~
Optic
Co~
which is compatible with the Ampex 1295126-01 device.When pin 9 is
held to High level and pin 16 is low Latency 1 is invoked and the equa-
tion is changed to 2N +2r + 13 symbol clock cycles. Latency 2 is
involked if pin 16 is high regardless of the level of pin 9 and the equa-
tion is 3n/2 +3r/2 +15. Effects of optional shorter latency and mini-
mum code length ( OptLn ) : The combination of the shorter code and
latency can result in considerable increase in effective data transfer. In
most new designs the Latency1 or Latency 2 option will provide the best
operations.
StatEN
If StatEn has been set high the first two parity bytes will be replaced
with error information. Byte 1 will show FXXEEEEE and Byte 2 will
show FXXTTTTT where:
F = block Not Correctable if high, block was Corrected if low.
EEEEE = Erasure count will be 0.
TTTTT = Total number of corrections made in the block.
If the block was not correctable ( F bit is high ) E and T values will be
meaningless. If StatEn is low all of the corrected parity symbols will be
clocked out of the decoder.
Example:If a desired code is ( 64,48 ) r= 16,the default minimum block
length ( 5r + 33 ) is 95 bytes which requires 31 " filler " bytes to be
inserted in each block., a loss of over 33 % of the channel effectiveness.
Decoder Error Information Output
The latency ( 2N+5r+33 ) is 313 clock cycles.With OptLn2 invoked the
minimum block length is 39 bytes , which does not require any filler
bytes so there is no loss of channel effectiveness. The latency is 135
clock cycles.
In order to help optimize the application ECC function, detailed error
information for each block is also available while the decoder data out-
put is in process. It is not necessary to use this information for proper
operation the part.
Decoding
If the symbol being outputed from the decoder has been corrected
ErLoc (pin 24) will go high.The pattern used to correct that symbol will
apprear on CMag 0 -CMag7 pins at the same time.Note that the error is
actually the logical inverse of the correction. (The user must provide
external storage and processing of this information as the COic5130
does not store these error location or correction information outputs.If
the decoder detects more than r/2 errors ErLoc will remain low
throughout the block as no changes will be made. The UnCorr line or
Status bytes must be monitored to flag this condition.
After the COic5130A is initialized it can begin decoding incoming
blocks. It is a good idea, but not absolutely necessary, to pass at least as
many dummy symbols as the latency through the device before actual
data is used in order to clear out any spurious information in the unit.
Although it is not recommended, block of data can be used to initialize
the device can be made up of valid data, if step one has been complet-
ed.
To decode, the Enabln is brought high and held high throughout the
decoding secession.At the beginning of a code block DataEn is brought
high at the leading edge of the first symbol clock pulse and held high
while the data symbols are being clocked into the device, that is N-r
symbol clock pluses. DataEn is brought low with the first parity symbol
and held low for r symbol clock cycles while the parity symbols are
clocked into the decoder. DataEn‚s going highagain marks the end of
parity and the start of the next block.
Decoder Pass Through Mode ( r =0 )
Any number of symbols can be passed through the decoder without any
changes (corrections) if the Enable In ( Enabln ) is held low while sym-
bols are clocked into the device. The input symbols, data and parity if
any, will be passed unchanged to the output ( Dout ) after the number
of symbol clocks needed for processing latency. In this mode there will
normally not be any parity symbols. That will allow transfer of data
symbols at the maximum rate,but will not provide any error correction
(t=0).
The first data symbol is placed on the Dout bus, the DatRdy line will go
high and the unit will begin to output data symbols when the number
of symbol clocks required for processing latency are complete. At the
end of N-r symbols the DatRdy line goes low and parity symbols are
outputted
To end Pass Through Mode operation Enabln must be brought high,
which will start the decoding process. This must be at the beginning of
a block for correct operations. Pass Through Mode may be invoked at
any time but any blocks in process when this mode is started will not be
decoded properly.
Correct
Correct pin --- goes high as the block starts being outputted if the block
contains corrected symbols or low if the block is outputted as it was
received due to either 0 or more than r errors in the block.
EnOBk
UnCorr
When the last byte of a block is outputted EnOBK pin 22 will go to the
high level for one clock period.
If the block cannot be corrected UnCorr,pin --- will go to the high level.
This will occurr as the block being processed starts to be outputted.
COic5130A Specifications
Encoder Output Timing
6
~
Optic
Co~
T
T
T
T
ckw
ckr
ckw
ckf
Clock
Input
T
ck
T
T
ih
Output
isu
T
sd
Encoder Initialization
Before operation the encoder must be initialized to define the number of parity symbols (r).
To initialize the binary value of r/2,(0 to 10) is placed in T0 – T3 (T0 is least significant ) while RESET and ENIN are held low for four sym-
bol clock periods. RESET is then brought high for two symbol clock periods. The inputs on T0 – T3 can then be released and the encoder
can start normal operation. Any TX pin that is not used must be held low or connected to ground.
Decoder Output Timing
T
T
T
T
ckw
ckr
ckw
ckf
Clock
Input
T
ck
T
T
ih
Output
isu
T
sd
Decoder Initialization
Certain architectural and mathematical properties of this device are not hard wired and must be set up during the initialization control
sequence. These properties include:
1. The overall message block length (N)
2. The number of data bytes (K)
3. The total number of check bytes (R)
4. The number of check bytes allocated for correction only (P)
5. Whether the first check byte output positions are used for status bytes or check bytes (STATEN)
6. Whether to use AMPEX compatible, non-compatible, or short timing (SHORT1, SHORT2)
COic5130A Specifications
7
~
Optic
Co~
These properties must be initialized before normal operation can begin.There are two distinct phases of the initialization process.In phase
one, the values of P, STATEN and SHORT1 and SHORT2 are initialized.In phase two, the first message block through the device is used to
set the valuesof N, K and R.
The phase one sequence consists of at least 4 clock cycles in which RESET is held LOW followed by at least 2 clock cycles during which
RESET is held HIGH.RESET must then remain HIGH for all subsequent operations or else an unwanted initialization sequence will ensue.
The desired values of STATEN and P4 - P0 must be maintained during the first phase of initialization. The desired value of SHORT1 and
SHORT2 must be maintained during all the phases of operation of the device. DATAEN must be held LOW during the entire six clock
sequence or unintended processing of spurious messages may occur.
Decoder Initialization Control Sequence Timing
RESET
At least 4 clock cycles
At least 2 clock cycles
P4-P0
STATEN
DATAEN
ENABIN
Initialization
Message
The rising edge of DATAEN at the end of the phase one initialization sequence marks the beginning of the first message block,which is the
beginning of phase two of the initialization process. DATAEN has the role of initializing the parameters of N, K and R. DATAEN has a dif-
ferent function on all subsequent blocks until an initialization sequence is begun once again. As the first message block passes through the
device,DATAEN is held HIGH for K clock cycles and then LOW for R clock cycles. DATAEN going high again marks the first byte of the sec-
ond block and implies the end of the phase two initialization sequence. DATAEN has thus defined R,K and N for all subsequent blocks until
another initialization sequence is performed.
Decoder Message Input Timing
DIN7 - DIN0
K Data Bytes
R Parity Bytes
DATAEN
ENABIN
COic5130A Specifications
8
~
Optic
Co~
Message Decoding
During message decoding the device clocks in the encoded message block from the DIN7 - DIN0 input bus on the rising edge of CLK.The
device then computes polynomials for this data using a high performance Reed-Solomon coding algorithm, and then proceeds to use the
calculated polynomials to correct any errors,if possible.These polynomials are a series of complex equations that will indicate not only the
position of incorrect bytes but will also produce the necessary information to correct them.The timing of the decoding operation is defined
Decoder Message Output Timing
DOUT7 - DOUT0
K Data Bytes
R Parity Bytes
DATARDY
CORR
The action taken by the decoder with respect to a given message block is determined in all cases by the quantity of errors received. The
device reports its action via the CORR output pin.If P = R, a HIGH output on the CORR pin indicates that the message block being output
is correct.A LOW output indicates that a correction was not performed because there were too many errors or no errors.In situations where
P has been chosen to be not equal to R, the meaning of the UNCORR pin is that more than P/2 errors have occurred.
Decoder Optional Status Bytes
The optional status bytes, that may be output at the end of the message block, indicate the number of errors encountered and may be used
to determine the exact meaning of the CORR output when P ≠ R. The first status byte has all of its bits set LOW except bit 7, which is the
CA (correction attempted) flag.The CA flag goes LOW when E ≤ R/2 (the message block was successfully decoded). Therefore,anytime CA
is HIGH,the message block should be retransmitted since there were probably too many errors to reliably correct.Also,if P = R then CA will
always be LOW when the CORR output pin is HIGH and HIGH when CORR is LOW.
In the second status byte, bits 4 through O are a binary count of the number of errors encountered. Bit 4 is most significant. The remaining
bits are always LOW.
COic5130A Specifications
Pinout
9
~
Optic
Co~
Table 1: Device Pinout
Encoder /
Decoder
Pin# Signal Name
Description
Signal Type
TTL Output
1
2
3
4
5
6
NC
N/A
No Connection
Error Magnitude 0. This output indicates which bit of the current symbol
output on Q7-Q0 has been corrected when LOC is HIGH. This output is
indeterminate and should be ignored when LOC is low.
DEC_MAG0
NC
Decoder
N/A
No Connection
Error Magnitude 1. This output indicates which bit of the current symbol
output on Q7-Q0 has been corrected when LOC is HIGH. This output is
indeterminate and should be ignored when LOC is low.
DEC_MAG1
NC
Decoder
N/A
TTL Output
TTL Output
No Connection
Error Magnitude 2. This output indicates which bit of the current symbol
output on Q7-Q0 has been corrected when LOC is HIGH. This output is
indeterminate and should be ignored when LOC is low.
DEC_MAG2
DEC_DOUT6
Decoder
7
Decoder
N/A
Data output bit 6. Bit 7 is MSB.
+5 Volt Power
Output
Power
8
V
dd
9
DEC_DOUT5
NC
Decoder
N/A
Data output bit 5. Bit 7 is MSB.
No Connection
Output
10
11
12
13
14
15
16
17
18
19
20
21
GND
N/A
Ground
Power
NC
N/A
No Connection
DEC_DOUT4
NC
Decoder
N/A
Data output bit 4. Bit 7 is MSB.
No Connection
Output
Output
DEC_DOUT3
NC
Decoder
N/A
Data output bit 3. Bit 7 is MSB.
No Connection
V
N/A
+5 Volt Power
Power
Output
Output
Power
dd
DEC_DOUT2
DEC_DOUT1
GND
Decoder
Decoder
N/A
Data output bit 2. Bit 7 is MSB.
Data output bit 1. Bit 7 is MSB.
Ground
NC
N/A
No Connection
COic5130A Specifications
10
~
Optic
Co~
Table 1: Device Pinout, continued
Encoder /
Decoder
Pin# Signal Name
Description
Signal Type
22
23
DEC_DOUT0
GND
Decoder
N/A
Data output bit 0. Bit 7 is MSB.
Ground
Output
Power
Data Ready.Assertive HIGH. This output is held HIGH for data bytes and
low check bytes.
24
DEC_DATARDY Decoder
Output
Error Magnitude 3. This output indicates which bit of the current symbol output on
Q7-Q0 has been corrected when LOC is HIGH. This output is indeterminate and
should be ignored when LOC is low.
25
26
27
DEC_MAG3
NC
Decoder
N/A
TTL Output
No Connection
Error Magnitude 4. This output indicates which bit of the current symbol output on
Q7-Q0 has been corrected when LOC is HIGH. This output is indeterminate and
should be ignored when LOC is low.
DEC_MAG4
Decoder
TTL Output
TTL Output
28
29
NC
NC
N/A
N/A
No Connection
No Connection
Error Magnitude 5. This output indicates which bit of the current symbol output on
Q7-Q0 has been corrected when LOC is HIGH. This output is indeterminate and
should be ignored when LOC is low.
30
DEC_MAG5
Decoder
31
32
33
34
35
36
37
38
NC
NC
NC
NC
N/A
No Connection
No Connection
No Connection
No Connection
+5 Volt Power
Foundry Test Pin - Do not Use
Ground
N/A
N/A
N/A
V
N/A
Power
dd
ENC_TEST_SE
GND
Encoder
N/A
GND
N/A
Ground
Error Magnitude 6. This output indicates which bit of the current symbol output on
Q7-Q0 has been corrected when LOC is HIGH. This output is indeterminate and
should be ignored when LOC is low.
39
40
DEC_MAG6
Decoder
Decoder
TTL Output
Input
Status Enable.Asservie HIGH. If this signal is HIGH during reset then the decoder
will be programmed to output two status bytes with each message block.
DEC_STATEN
COic5130A Specifications
11
~
Optic
Co~
Table 1: Device Pinout, continued
Encoder /
Decoder
Pin# Signal Name
Description
Signal Type
41
42
NC
N/A
No Connection
Error Magnitude 7. This output indicates which bit of the current symbol output on
Q7-Q0 has been corrected when LOC is HIGH. This output is indeterminate and
should be ignored when LOC is low.
DEC_MAG7
Decoder
TTL Output
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
V
N/A
+5 Volt Power
Power
Input
dd
DEC_DIN7
ENC_TEST_SI
DEC_DIN6
GND
Decoder
Encoder
Decoder
N/A
Decoder symbol input bit 7. Bit 7 is MSB.
Foundry Test Pin - Do not Use
Decoder symbol input bit 6. Bit 7 is MSB.
Ground
Input
Power
Tristate
Power
Input
ENC_DOUT6
Encoder
N/A
Encoder data output bit 6
+5 Volt Power
V
dd
ENC_DIN6
Encoder
Decoder
N/A
Encoder data input bit 6
Foundry Test Pin - Do not Use
+5 Volt Power
DEC_TEST_SI
V
Power
Input
dd
DEC_DIN5
ENC_DIN7
GND
Decoder
Decoder
N/A
Decoder symbol input bit 5. Bit 7 is MSB.
Encoder data input bit 7
Ground
Input
Power
Tristate
Power
ENC_DOUT7
Encoder
N/A
Encoder data output bit 7
+5 Volt Power
V
dd
GND
N/A
Ground
DEC_DIN4
ENC_DOUT4
DEC_DIN3
NC
Decoder
Encoder
Decoder
N/A
Decoder symbol input bit 4. Bit 7 is MSB.
Encoder data output bit 4
Decoder symbol input bit 3. Bit 7 is MSB.
No Connection
Input
Tristate
Input
ENC_DIN4
Encoder
Encoder data input bit 4
Input
COic5130A Specifications
12
~
Optic
Co~
Table 1: Device Pinout, continued
Encoder /
Decoder
Pin# Signal Name
Description
No Connection
Signal Type
64
65
NC
N/A
Decoder uncorrectable block.Assertive HIGH. Indicates message block contains
uncorrectable errors.
DEC_UNCORR
Decoder
Output
66
67
68
69
70
71
72
73
74
75
76
77
78
79
V
N/A
+5 Volt Power
Power
Input
Tristate
Power
Input
Output
Input
Input
Power
Input
Input
Input
Power
Input
dd
ENC_DIN5
ENC_DOUT5
GND
Encoder
Encoder
N/A
Encoder data input bit 5
Encoder data output bit 5
Ground
DEC_DIN2
ENC_RDY
DEC_DIN1
ENC_ENOUT
Decoder
Encoder
Decoder
Encoder
N/A
Decoder symbol input bit 2. Bit 7 is MSB.
Indicates data symbols are on the encoder ENC_DOUT bus
Decoder symbol input bit 1. Bit 7 is MSB.
Enables encoder DIN bus onto the DOUT bus
+5 Volt
V
dd
ENC_ENIN
DEC_DIN0
ENC_RESET
GND
Encoder
Decoder
Encoder
N/A
Enable encoder DIN bus into the parity generator
Decoder symbol input bit 0. Bit 7 is MSB.
Initializes encoder into a know state (high)
Ground
ENC_TRIEN
Encoder
Tri-states the encoder ENC_DOUT bus drivers when HIGH
Decoder data enable.Assertive HIGH. This input is used to signal the difference
between data bytes and check bytes.
80
81
DEC_DATEN
DEC_ENABIN
Decoder
Decoder
Input
Input
"Decoder enable data correction.Assertive HIGH.When this input is asserted, the
device performs corrections on the message block.When CEN is low, the device does
not perform corrections but continues to report status is initialized to do so."
82
83
84
85
ENC_CLOCK
ENC_TA2
Encoder
Encoder
N/A
Encoder master and symbol clock.
Bit 2 of the encoder T select bus
+5 Volt Power
Input
Input
Power
Input
V
dd
ENC_TA1
Encoder
Bit 1 of the encoder T select bus
COic5130A Specifications
13
~
Optic
Co~
Table 1: Device Pinout, continued
Encoder /
Decoder
Pin# Signal Name
Description
Signal Type
Decoder parity input bit 3. This determines the value of (P) which is the maximum of
check bytes that the device will use in correction before flagging the block as
uncorrectable. Normally set to the # of check bytes (R). P4 is the most significant bits.
86
87
88
89
90
91
92
DEC_P3
ENC_TA0
DEC_P2
Vdd
Decoder
Encoder
Decoder
N/A
Input
Input
Input
Power
Input
Input
Input
Bit 0 of the encoder T select bus
Decoder parity input bit 2. This determines the value of (P) which is the maximum of
check bytes that the device will use in correction before flagging the block as
uncorrectable. Normally set to the # of check bytes (R). P4 is the most significant bits.
+5 Volt Power
Decoder parity input bit 1. This determines the value of (P) which is the maximum of
check bytes that the device will use in correction before flagging the block as
uncorrectable. Normally set to the # of check bytes (R). P4 is the most significant bits.
DEC_P1
ENC_DIN3
DEC_P4
Decoder
Encoder
Decoder
Encoder data input bit 3
Decoder parity input bit 4. This determines the value of (P) which is the maximum of
check bytes that the device will use in correction before flagging the block as
uncorrectable. Normally set to the # of check bytes (R). P4 is the most significant bits.
93
94
ENC_DOUT3
ENC_TA3
Encoder
Encoder
Encoder data output bit 3
Tristate
Input
Bit 3 of the encoder T select bus
Decoder latency select 2. Selects latency according to Table 2: Latency and Minimum
Block Size Selection.
95
DEC_SHORT2
Decoder
Input
96
97
98
99
NC
N/A
No Connection
ENC_DOUT2
NC
Encoder
N/A
Encoder data output bit 2
No Connection
Tristate
Input
ENC_DIN2
Encoder
N/A
Encoder data input bit 2
No Connection
100 NC
101 Vdd
N/A
+5 Volt Power
Power
Input
Decoder system reset.Assertive LOW. Reset timing is critical to the initialization
of the device
102 DEC_RESET
Decoder
103 ENC_DIN1
104 Vdd
Encoder
N/A
Encoder data input bit 1
+5 Volt Power
Input
Power
Tristate
105 ENC_DOUT1
Encoder
Encoder data output bit 1
COic5130A Specifications
14
~
Optic
Co~
Table 1: Device Pinout, continued
Encoder /
Decoder
Pin# Signal Name
Description
Ground
Signal Type
Power
106 GND
N/A
107 NC
N/A
No Connection
108 DEC_TEST_SO
109 GND
Decoder
N/A
Foundry Test Pin - Do not Use
Ground
Power
Input
Decoder latency select 1. Selects latency according to Table 2: Latency and Minimum
Block Size Selection.
110 DEC_SHORT1
Decoder
111 ENC_DOUT0
112 GND
Encoder
N/A
Encoder data output bit 0
Ground
Tristate
Power
Input
113 ENC_DIN0
Encoder
N/A
Encoder data input bit 0
+5 Volt Power
114
V
Power
dd
115 DEC_TEST_SE
116 ENC_TEST_SO
Decoder
Encoder
Foundry Test Pin - Do not Use
Foundry Test Pin - Do not Use
Decoder master clock.All inputs and outputs are synchronized by the rising edge
of DEC_CLOCK.
117 DEC_CLOCK
118 GND
Decoder
N/A
Input
Ground
Power
Output
Output
Decoder message block corrected.Assertive HIGH. Indicates that errors have been
found and corrected in message block.
119 DEC_CORR
Decoder
120 DEC_EOB
121 NC
Decoder
N/A
Decoder End of Block. 1/0 = End/Not end of block.
No Connection
122 DEC_DOUT7
Decoder
Data output bit 7. Bit 7 is MSB.
Output
Output
Power
Decoder Error Location.Assertive HIGH. This output goes HIGH if the current
symbol outout on Q7-Q0 has had a correction applied to it.
123 DEC_LOC
Decoder
124
V
N/A
N/A
N/A
N/A
N/A
+5 Volt Power
No Connection
Ground
dd
125 NC
126 GND
127 NC
Power
Power
No Connection
+5 Volt Power
128
V
dd
COic5130A Specifications
Pinout
15
~
Optic
Co~
Decoder Input Pins
Pin# Signal
Description
Signal Type
76
72
70
61
59
53
46
44
DEC_DIN0
DEC_DIN1
DEC_DIN2
DEC_DIN3
DEC_DIN4
DEC_DIN5
DEC_DIN6
DEC_DIN7
Decoder symbol input bit 0. Bit 7 is MSB.
Decoder symbol input bit 1. Bit 7 is MSB.
Decoder symbol input bit 2. Bit 7 is MSB.
Decoder symbol input bit 3. Bit 7 is MSB.
Decoder symbol input bit 4. Bit 7 is MSB.
Decoder symbol input bit 5. Bit 7 is MSB.
Decoder symbol input bit 6. Bit 7 is MSB.
Decoder symbol input bit 7. Bit 7 is MSB.
Input
Input
Input
Input
Input
Input
Input
Input
Decoder Output Pins
Pin# Signal
Description
Signal Type
22
19
18
15
13
9
DEC_DOUT0
Data output bit 0. Bit 7 is MSB.
Data output bit 1. Bit 7 is MSB.
Data output bit 2. Bit 7 is MSB.
Data output bit 3. Bit 7 is MSB.
Data output bit 4. Bit 7 is MSB.
Data output bit 5. Bit 7 is MSB.
Data output bit 6. Bit 7 is MSB.
Data output bit 7. Bit 7 is MSB.
Output
Output
Output
Output
Output
Output
Output
Output
DEC_DOUT1
DEC_DOUT2
DEC_DOUT3
DEC_DOUT4
DEC_DOUT5
DEC_DOUT6
7
122 DEC_DOUT7
Decoder Error Magnitude Pins
Pin# Signal
Description
Signal Type
Output
Error Magnitude 0. This output indicates which bit of the current symbol output on Q7-Q0 has been
corrected when LOC is HIGH. This output is indeterminate and should be ignored when LOC is low.
2
4
DEC_MAG0
DEC_MAG1
Error Magnitude 1. This output indicates which bit of the current symbol output on Q7-Q0 has been
corrected when LOC is HIGH. This output is indeterminate and should be ignored when LOC is low.
Output
COic5130A Specifications
16
~
Optic
Co~
Decoder Error Magnitude Pins, continued
Pin# Signal
Description
Signal Type
Output
Output
Output
Output
Output
Output
Error Magnitude 2. This output indicates which bit of the current symbol output on Q7-Q0 has been
corrected when LOC is HIGH. This output is indeterminate and should be ignored when LOC is low.
6
DEC_MAG2
DEC_MAG3
DEC_MAG4
DEC_MAG5
DEC_MAG6
DEC_MAG7
Error Magnitude 3. This output indicates which bit of the current symbol output on Q7-Q0 has been
corrected when LOC is HIGH. This output is indeterminate and should be ignored when LOC is low.
25
27
30
39
42
Error Magnitude 4. This output indicates which bit of the current symbol output on Q7-Q0 has been
corrected when LOC is HIGH. This output is indeterminate and should be ignored when LOC is low.
Error Magnitude 5. This output indicates which bit of the current symbol output on Q7-Q0 has been
corrected when LOC is HIGH. This output is indeterminate and should be ignored when LOC is low.
Error Magnitude 6. This output indicates which bit of the current symbol output on Q7-Q0 has been
corrected when LOC is HIGH. This output is indeterminate and should be ignored when LOC is low.
Error Magnitude 7. This output indicates which bit of the current symbol output on Q7-Q0 has been
corrected when LOC is HIGH. This output is indeterminate and should be ignored when LOC is low.
Decoder Parity Input Pins
Description
Pin# Signal
Signal Type
Input
Decoder parity input bit 1. This determines the value of (P) which is the maximum of check bytes
that the device will use in correction before flagging the block as uncorrectable. Normally set to the
# of check bytes (R). P4 is the most significant bits.
90
88
86
92
DEC_P1
Decoder parity input bit 2. This determines the value of (P) which is the maximum of check bytes
that the device will use in correction before flagging the block as uncorrectable. Normally set to the #
of check bytes (R). P4 is the most significant bits.
DEC_P2
DEC_P3
DEC_P4
Input
Input
Input
Decoder parity input bit 3. This determines the value of (P) which is the maximum of check bytes
that the device will use in correction before flagging the block as uncorrectable. Normally set to the
# of check bytes (R). P4 is the most significant bits.
Decoder parity input bit 4. This determines the value of (P) which is the maximum of check bytes
that the device will use in correction before flagging the block as uncorrectable. Normally set to the #
of check bytes (R). P4 is the most significant bits.
Decoder Latency Select Pins
Description
Pin# Signal
Signal Type
Input
Decoder latency select 1. Selects latency according to Table 2: Latency and Minimum Block
Size Selection.
110 DEC_SHORT1
Decoder latency select 2. Selects latency according to Table 2: Latency and Minimum Block
Size Selection.
95
DEC_SHORT2
Input
COic5130A Specifications
17
~
Optic
Co~
Decoder Control and Status Pins
Pin# Signal
Description
Signal Type
Input
117 DEC_CLOCK
119 DEC_CORR
Decoder master clock.All inputs and outputs are synchronized by the rising edge of DEC_CLOCK.
Decoder message block corrected.Assertive HIGH. Indicates that errors have been found and
corrected in message block.
Output
Output
Input
24
80
DEC_DATARDY Data Ready.Assertive HIGH. This output is held HIGH for data bytes and low check bytes.
Decoder data enable.Assertive HIGH. This input is used to signal the difference between data bytes
and check bytes.
DEC_DATEN
Decoder enable data correction.Assertive HIGH.When this input is asserted, the device performs
81
DEC_ENABIN
corrections on the message block.When CEN is low, the device does not perform corrections but
continues to report status is initialized to do so.
Input
120 DEC_EOB
123 DEC_LOC
Decoder End of Block. 1/0 = End/Not end of block.
Output
Output
Input
Decoder Error Location.Assertive HIGH. This output goes HIGH if the current symbol outout on
Q7-Q0 has had a correction applied to it.
102 DEC_RESET
Decoder system reset.Assertive LOW. Reset timing is critical to the initialization of the device.
Status Enable.Asservie HIGH. If this signal is HIGH during reset then the decoder will be
programmed to output two status bytes with each message block.
40
65
DEC_STATEN
DEC_UNCORR
Input
Decoder uncorrectable block.Assertive HIGH. Indicates message block contains uncorrectable errors.
Output
Encoder Data Input Pins
Pin# Signal
Description
Signal Type
113 ENC_DIN0
103 ENC_DIN1
Encoder data input bit 0.
Encoder data input bit 1.
Encoder data input bit 2.
Encoder data input bit 3.
Encoder data input bit 4.
Encoder data input bit 5.
Encoder data input bit 6.
Encoder data input bit 7.
Input
Input
Input
Input
Input
Input
Input
Input
99
91
63
67
50
54
ENC_DIN2
ENC_DIN3
ENC_DIN4
ENC_DIN5
ENC_DIN6
ENC_DIN7
COic5130A Specifications
18
~
Optic
Co~
Encoder Data Output Pins
Pin# Signal
Description
Signal Type
111 ENC_DOUT0
105 ENC_DOUT1
Encoder data output bit 0
Encoder data output bit 1
Encoder data output bit 2
Encoder data output bit 3
Encoder data output bit 4
Encoder data output bit 5
Encoder data output bit 6
Encoder data output bit 7
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
97
93
60
68
48
56
ENC_DOUT2
ENC_DOUT3
ENC_DOUT4
ENC_DOUT5
ENC_DOUT6
ENC_DOUT7
Encoder T Select Pins
Pin# Signal
Description
Signal Type
87
85
83
94
ENC_TA0
Bit 0 of the encoder T select bus
Bit 1 of the encoder T select bus
Bit 2 of the encoder T select bus
Bit 3 of the encoder T select bus
Input
Input
Input
Input
ENC_TA1
ENC_TA2
ENC_TA3
Encoder Control and Status Pins
Pin# Signal
Description
Signal Type
79
75
73
71
77
82
ENC_TRIEN
Tri-states the encoder ENC_DOUT bus drivers when HIGH
Enable encoder DIN bus into the parity generator
Enables encoder DIN bus onto the DOUT bus
Indicates data symbols are on the encoder ENC_DOUT bus
Initializes encoder into a know state (high)
Input
Input
Input
Output
Input
Input
ENC_ENIN
ENC_ENOUT
ENC_RDY
ENC_RESET
ENC_CLOCK
Encoder master and symbol clock.
COic5130A Specifications
19
~
Optic
Co~
Encoder and Decoder Foundry Test Pins
Pin# Signal
Description
Signal Type
115 DEC_TEST_SE
Foundry Test Pin - Do not Use
Foundry Test Pin - Do not Use
Foundry Test Pin - Do not Use
Foundry Test Pin - Do not Use
Foundry Test Pin - Do not Use
Foundry Test Pin - Do not Use
Input
Input
Output
Input
Input
Output
51
DEC_TEST_SI
108 DEC_TEST_SO
36
45
ENC_TEST_SE
ENC_TEST_SI
116 ENC_TEST_SO
Ground Pins
No Connect Pins
No Connect Pins, continued
Votlage Supply Pins
Pin# Signal Description
Pin# Signal Description
Pin# Signal Description
Pin# Signal Description
11
20
23
37
38
47
55
58
69
78
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
41
62
64
96
98
NC
NC
NC
NC
NC
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
8
V
+5 V Power
+5 V Power
+5 V Power
+5 V Power
+5 V Power
+5 V Power
+5 V Power
+5 V Power
+5 V Power
+5 V Power
+5 V Power
+5 V Power
+5 V Power
+5 V Power
+5 V Power
+5 V Power
dd
3
17
V
dd
5
35
V
dd
10
12
14
16
21
26
28
29
31
32
33
34
43
V
dd
49
V
dd
100 NC
107 NC
121 NC
125 NC
127 NC
52
V
dd
57
V
dd
66
V
dd
74
V
dd
84
V
dd
106 GND
109 GND
112 GND
118 GND
126 GND
89
V
dd
101
104
114
124
128
V
dd
V
dd
V
dd
V
dd
V
dd
COic5130A Specifications
Packaging
19
~
Optic
Co~
Table 6: PLCC Dimensions
D
D1
D3
C
θ = 0° – 7°
A
A2
A1
E3 E1
E
0.1
e
Index Corner
L
Pin 1
G
b
Notes:
Control Dimensions
Alternate Dimensions
in millimeters
in inches
Symbol
1. Pin 1 indicator may be a corner chamfer, dot or both.
2. Controlling dimensions are in millimeters.
Min
Nominal
Max
Min
Nominal
Max
A
A1
A2
D
3.45
0.25
4.10
0.50
0.136
0.010
0.126
1.219
1.094
0.161
0.020
0.142
1.238
1.110
3. The top package body size may be smaller than the bottom package
body size by a max. of 0.15 mm.
3.20
3.60
4. Dimension D1 and E1 do not include mold protrusion. Allowable pro-
trusion is 0.25mm per side. D1 and E1 are maximum plastic body size
dimensions including mold mismatch.
30.95
27.80
31.45
28.20
D1
D3
E
24.80 Ref.
0.976 Ref.
5. Dimension b does not include dambar protrusion. Allowable dambar
protrusion shall not cause the lead width to exceed the maximum b
dimension by more than 0.08 mm.
30.95
27.80
31.45
28.20
1.219
1.094
1.238
1.110
E1
E3
L
0.976 Ref.
0.031 BSC.
24.80 Ref.
0.80 BSC.
6. Coplanarity, measured at seating plane G, to be 0.10 mm max.
0.73
1.03
0.029
0.041
e
b
0.30
0.11
0.45
0.23
0.012
0.004
0.018
0.009
Part Numbers: Complete ordering code COic5130A
Parts are packaged in anti static tubes of 18 units each.
c
Pin Features
N
128
32
ND
NE
To order call 650-321-3390, fax 650-322-8569,
or email sales@co-optic.com
32
Note
Square
相关型号：
©2020 ICPDF网 联系我们和版权申明