CS18LV02565AAI-70 [ETC]
HIGH SPEED SUPER LOW POWER SRAM; 高速超低功率SRAM
| 型号： | CS18LV02565AAI-70 |
| 厂家： | 
ETC |
| 描述： | HIGH SPEED SUPER LOW POWER SRAM |
| 文件： | 总14页 (文件大小：294K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Speed Super Low Power SRAM
32K-Word By 8 Bit
CS18LV02565
Revision History
Rev. No.
History
Issue Date
Dec.29,2004
Remark
2.0
Initial issue with new naming rule
1
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
CS18LV02565
32K-Word By 8 Bit
ꢀGENERAL DESCRIPTION
The CS18LV02565 is a high performance, high speed and super low power CMOS Static Random
Access Memory organized as 32,768 words by 8bits and operates for a single 4.5 to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high speed, super low power features
and maximum access time of 55/70ns in 5.0V operation. Easy memory expansion is provided by an
active LOW chip enable (/CE) and active LOW output enable (/OE).
The CS18LV02565 has an automatic power down feature, reducing the power consumption
significantly when chip is deselected. The CS18LV02565 is available in JEDEC standard 28-pin TSOP I
(8x13.4 mm), SOP (330 mil) and PDIP (600 mil) packages.
ꢀFEATURES
ꢁ
ꢁ
Wide operation voltage : 4.5 ~ 5.5V
Ultra low power consumption : 2mA＠1MHz (Max.) , Vcc=5.0V.
1.0 uA (Typ.) CMOS standby current
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
High speed access time : 55/70ns.
Automatic power down when chip is deselected.
Three state outputs and TTL compatible.
Data retention supply voltage as low as 1.5V.
Easy expansion with /CE and /OE options.
ꢀPRODUCT FAMILY
Standby Current(Typ.)
Product Family
Operating Temp.
Vcc Range
Speed (ns)
Package Type
28 SOP
ICCSB1
1.0 uA
28 TSOP I
28 PDIP
Dice
0~70oC
55/70
(Vcc = 5.0V)
CS18LV02565
4.5~5.5V
28 SOP
28 TSOP I
28 PDIP
Dice
1.5 uA
-40~85oC
55/70
(Vcc= 5.0V)
2
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
32K-Word By 8 Bit
CS18LV02565
ꢀ PIN CONFIGURATIONS
OE
A11
A9
1
28
27
26
25
24
23
A10
CE
2
3
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A8
4
A13
WE
VCC
A14
A12
A7
5
6
7
28TSOP(I)-8x13.4mm
22
21
20
19
18
17
16
15
8
9
10
11
12
13
14
A6
A5
A4
A1
A3
A2
ꢀ FUNCTIONAL BLOCK DIAGRAM
A5
A6
A7
Address
Input
Buffer
A8
18
512
8
Row
Memory Array
512x512
A9
Decoder
A11
A12
A13
A14
512
8
DQ0
Data Input
Buffer
Column I/O
Data Output
Buffer
Write Driver
Sense Amp
DQ7
8
8
64
Column Decoder
/CE
12
/WE
/OE
Control
Address Input Buffer
VCC
GND
A0 A1 A2 A3 A4 A10
3
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
CS18LV02565
32K-Word By 8 Bit
ꢀPIN DESCRIPTIONS
Name
Type
Function
Input
Address inputs for selecting one of the 32,768 x 8 bit words in the RAM
/CE is active LOW. Chip enable must be active when data read from or write
to the device. If chip enable is not active, the device is deselected and in a
standby power mode. The DQ pins will be in high impedance state when the
device is deselected.
A0 – A14
Input
Input
/CE
The Write enable input is active LOW. It controls read and write operations.
With the chip selected, when /WE is HIGH and /OE is LOW, output data will
be present on the DQ pins, when /WE is LOW, the data present on the DQ
pins will be written into the selected memory location.
/WE
The output enable input is active LOW. If the output enable is active while the
chip is selected and the write enable is inactive, data will be present on the
DQ pins and they will be enabled. The DQ pins will be in the high impedance
state when /OE is inactive.
Input
I/O
/OE
These 8 bi-directional ports are used to read data from or write data into the
RAM.
DQ0~DQ7
Power Power Supply
Power Ground
Vcc
Gnd
ꢀTRUTH TABLE
Mode
Standby
/CE
/WE
/OE
X
DQ0~7
High Z
High Z
DOUT
Vcc Current
ICCSB, ICCSB1
H
L
L
L
X
H
H
L
Output Disabled
Read
H
ICC
ICC
ICC
L
Write
X
DIN
4
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
32K-Word By 8 Bit
CS18LV02565
ꢀABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
TBIAS
TSTG
Parameter
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
Rating
Unit
-0.5 to Vcc+0.5
-40 to +125
-60 to +150
1.0
V
OC
OC
W
Power Dissipation
PT
DC Output Current
20
mA
IOUT
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
ꢀ OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0~70oC
Vcc
4.5~5.5V
-40~85oC
4.5~5.5V
ꢀCAPACITANCE(1)(TA=25℃,f=1.0MHz)
Symbol
CIN
Parameter
Input Capacitance
Conduction
VIN=0V
MAX.
6
Unit
pF
Input/Output Capacitance
VI/O=0V
8
pF
CDQ
1. This parameter is guaranteed, and not 100% tested.
5
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
32K-Word By 8 Bit
CS18LV02565
ꢀ DC ELECTRICAL CHARACTERISTICS ( TA = 0o ~70oC, Vcc = 5.0V)
Name
Parameter
Guaranteed Input Low
Voltage (2)
Test Condition
MIN
TYP(1)
MAX Unit
Vcc=5.0V
-0.5
1.5
V
VIL
Guaranteed Input High
Voltage (2)
Vcc=5.0V
2.5
-1
Vcc+0.2
V
VIH
IIL
Input Leakage Current
VCC=MAX, VIN=0 to VCC
1
1
uA
uA
VCC=MAX, /CE=VIN, or
/OE=VIN , VIO=0V to VCC
Output Leakage Current
-1
IOL
Output Low Voltage
Output High Voltage
VCC=MAX, IOL = 1mA
VCC=MIN, IOH = -1mA
0.4
V
V
VOL
VOH
2.2
Operating Power Supply
Current
/CE=VIL, IDQ=0mA,
F=FMAX =1/ tRC
20
1
mA
mA
uA
ICC
TTL Standby Supply
/CE=VIH, IDQ=0mA,
ICCSB
/CE≧VCC-0.2V, VIN≧
VCC-0.2V or VIN≦0.2V,
CMOS Standby Current
1.0
4
ICCSB1
1. Typical characteristics are at TA = 25oC.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
ꢀ DATA RETENTION CHARACTERISTICS ( TA = 0o ~70oC, Vcc = 5.0V )
Name
Parameter
VCC for Data Retention
Test Condition
/CE ≧ VCC-0.2V, VIN
VCC-0.2V or VIN≦0.2V
/CE≧VCC-0.2V, VIN≧
VCC-0.2V or VIN≦0.2V
MIN TYP(1) MAX Unit
≧
VDR
1.5
V
Data Retention Current
ICCDR
0.5
3
uA
Chip Deselect to Data
Retention Time
TCDR
Refer to
0
ns
ns
Retention Waveform
tRC (2)
tR
Operation Recovery Time
1. TA = 25oC.
2. tRC= .Read Cycle Time.
6
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
CS18LV02565
32K-Word By 8 Bit
ꢀ
LOW Vcc DATA RETENTION WAVEFORM ( /CE Controlled )
Data Retention Mode
V
DR >= 1.5V
Vcc
CE
tCDR
VIH
tR
CE >= VCC - 0.2V
VIH
ꢀ AC TEST CONDITIONS
ꢀ KEY TO SWITCHING WAVEFORMS
WAVEFORMS
INPUTS
OUTPUTS
Input Pulse Levels
Vcc/0V
MUST BE STEADY MUST BE STEADY
Input Rise and Fall Times
5ns
Input and Output Timing
Reference Level
MAY CHANGE
FROM H TO L
WILL BE CHANGE FROM H
0.5Vcc
TO L
MAY CHANGE
FROM L TO H
WILL BE CHANGE FROM L
TO H
DON’T CARE ANY
CHANGE
CHANGE STATE
UNKNOWN
PERMITTED
CENTER LINE IS HIGH
IMPEDANCE OFF STATE
DOES NOT APPLY
ꢀ AC TEST LOADS AND WAVEFORMS
FIGURE 1A
FIGURE 1B
7
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
32K-Word By 8 Bit
CS18LV02565
ꢀ AC ELECTRICAL CHARACTERISTICS ( TA = 0o ~70oC, Vcc = 5.0V )
< READ CYCLE >
JEDEC
Name
-55
-70
Symbol
Description
Unit
MIN MAX MIN MAX
Read Cycle Time
55
70
ns
ns
ns
ns
tAVAX
tAVQV
tELQV
tGLQV
tRC
tAA
tACE
tOE
Address Access Time
Chip Select Access Time
Output Enable to Output
Valid
55
55
30
70
70
50
Chip Select to Output Low Z
Output Enable to Output in
Low Z
10
5
10
5
ns
ns
tELQX
tGLQX
tCLZ
tOLZ
Chip Deselect to Output in
High Z
0
0
35
30
0
0
35
30
ns
ns
ns
tEHQZ
tGHQZ
tAXOX
tCHZ
tOHZ
tOH
Output Disable to Output in
High Z
Address Change to Out
Disable
10
10
ꢀ SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
tRC
ADDRESS
tAA
tOH
tOH
DOUT
8
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
32K-Word By 8 Bit
CS18LV02565
READ CYCLE2 (1,3,4)
READ CYCLE3 (1,4)
ADDRESS
tRC
tAA
tOH
OE
CE
(1,5)
tOE
tOHZ
tOLZ
tCE
(5)
(5)
tCLZ
tCHZ
DOUT
NOTES:
1. /WE is high in read Cycle.
2. Device is continuously selected when /CE = VIL.
3. Address valid prior to or coincident with CE transition low.
4. /OE = VIL.
5. Test conditions assume signal transition times of 5ns or less, timing reference levels of 0.5VCC, input
pulse levels of 0V to VCC and output loading specified in Figure 1A.
6. Transition is measured ±500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is
guaranteed but not 100% tested.
9
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
CS18LV02565
32K-Word By 8 Bit
ꢀ AC ELECTRICAL CHARACTERISTICS ( TA = 0o ~70oC, Vcc = 5.0V )
< WRITE CYCLE >
JEDEC
Name
-55
-70
Symbol
Description
Unit
MIN MAX MIN MAX
Write Cycle Time
55
55
0
70
70
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAVAX
tE1LWH
tAVWL
tAVWH
tWLWH
tWHAX
tWLQZ
tDVWH
tWHDX
tGHQZ
tWC
tCW
tAS
tAW
tWP
tWR
tWHZ
tDW
tDH
Chip Select to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
55
40
0
70
50
0
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold for Write End
Output Disable to Output in
High Z
25
30
35
30
20
0
30
0
0
0
tOHZ
End of Write to Output Active
5
5
ns
tWHOX
tOW
10
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
32K-Word By 8 Bit
CS18LV02565
ꢀ SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (Write Enable Controlled)
WRITE CYCLE2 (Chip Enable Controlled)
11
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
CS18LV02565
32K-Word By 8 Bit
NOTES:
1.
/WE must be high during address transitions.
2.
The internal write time of the memory is defined by the overlap of /CE and /WE low. All signals must be active
to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold
timing should be referenced to the second transition edge of the signal that terminates the write.
3.
4.
TWR is measured from the earlier of /CE or /WE going high at the end of write cycle.
During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs
must not be applied.
5.
6.
If the /CE low transition occurs simultaneously with the /WE low transitions or after the /WE transition, output
remain in a high impedance state.
/OE is continuously low (/OE = VIL ).DOUT is the same phase of write data of this write cycle.
7. DOUT is the read data of next address.
8. If /CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase
to the outputs must not be applied to them.
9. Test conditions assume signal transition times of 5ns or less, timing reference levels of 0.5VCC, input pulse
levels of 0V to VCC and output loading specified in Figure 1A.
10. Transition is measured ±500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is
guaranteed but not 100% tested.
11. TCW is measured from the later of /CE going low to the end of write.
ꢀ
ORDER INFORMATION
12
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
CS18LV02565
32K-Word By 8 Bit
ꢀ PACKAGE DIMENSIONS
-
28 pin SOP (330 mil) :
SYMBOL
y
c
e
A
A1
A2
b
b1
c1
D
E
E1
L
L1
UNIT
_
_
Min. 2.540 0.102 2.362 0.35
0.35 0.20
0.20 17.983 8.280 11.506 1.118 0.700 1.520
0°
_
_
_
_
_
mm
Nom. 2.692 0.226 2.489
18.110 8.407 11.811 1.270 0.964 1.720
Max. 2.844 0.350 2.616 0.50
0.45 0.32
0.28 18.237 8.534 12.116 1.422 1.228 1.920
0.1
_
_
10°
0°
_
Min. 0.100 0.004 0.093 0.014 0.014 0.008 0.008 0.708 0.326 0.453 0.044 0.0276 0.0598
_
_
_
_
inch Nom. 0.106 0.009 0.098
0.713 0.331 0.465 0.050 0.0380 0.0677
Max. 0.112 0.014 0.103 0.020 0.018 0.012 0.011 0.718 0.336 0.477 0.056 0.0484 0.0756 0.004 10°
- 28 pin TSOP I (8x13.4 mm) :
12°(2x)
12°(2x)
HD
c
L
1
28
Seating Plane
y
14
15
"A"
12°(2X)
D
GAUGE PLANE
A
A
0
SEATING PLANE
15
14
12°(2X)
L
L1
"A" DATAIL VIEW
b
WITH PLATING
c
c1
1
28
BASE METAL
b1
SECTION A-A
SYMBOL
y
c
e
A
A1
A2
b
b1
c1
D
E
HD
L
L1
UNIT
_
_
Min. 1.00 0.050 0.95 0.17
0.17
0.20
0.23
0.10
_
0.10 11.70 7.90
0.45 13.20 0.40
0.55 13.40 0.50
0.65 13.60 0.70
0.70
0.80
0.90
0°
_
_
mm
Nom. 1.10 0.115 1.00
Max. 1.20 0.180 1.05
0.22
0.27
11.80 8.00
0.21 0.16 11.90 8.10
0.1
_
_
8°
0°
_
Min. 0.0393 0.0019 0.037 0.007 0.007 0.004 0.004 0.461 0.311 0.018 0.520 0.0157 0.0275
inch Nom. 0.0433 0.0045 0.039 0.009 0.008
_
_
0.465 0.315 0.022 0.528 0.0197 0.0315
Max. 0.0473 0.0071 0.041 0.011 0.009 0.008 0.006 0.469 0.319 0.026 0.536 0.0277 0.0355 0.004
8°
13
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
CS18LV02565
32K-Word By 8 Bit
28 pin PDIP (600mil):
-
SYMBOL
c
e
Q1
A1
A2
B
B1
D
E
E1
eB
L
S
UNIT
Min. 0.254 3.683 0.330 1.270 0.152 36.957 14.986 13.716
_
15.748 3.048 1.778 1.651
16.256 3.302 2.032 1.778
16.764 3.556 2.286 1.905
0.620 0.120 0.070 0.065
0.640 0.130 0.080 0.070
0.660 0.140 0.090 0.075
3°
6°
9°
3°
6°
9°
2.540
mm
Nom.
Max.
3.810 0.457 1.524 0.254 37.084 15.240 13.818
3.937 0.584 1.778 0.356 37.211 15.494 13.920
(TYP)
_
Min. 0.010 0.145 0.013 0.050 0.006 1.455 0.590 0.540
_
0.100
inch Nom.
Max.
0.150 0.018 0.060 0.010 1.460 0.600 0.544
0.155 0.023 0.070 0.014 1.465 0.610 0.548
(TYP)
_
14
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
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