CXP884P60 [ETC]
CMOS 8-bit Single Chip Microcomputer ; CMOS 8位单片机\n
| 型号： | CXP884P60 |
| 厂家： | 
ETC |
| 描述： | CMOS 8-bit Single Chip Microcomputer
|
| 文件： | 总34页 (文件大小：382K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXP884P60
CMOS 8-bit Single Chip Microcomputer
Description
The CXP884P60 is a CMOS 8-bit microcomputer which
consists of A/D converter, serial interface, timer/counter,
time-base timer, high precision timing pattern generation
circuit, PWM output, VISS/VASS circuit, 32kHz timer/counter,
remote control receiving circuit, VSYNC separator and the
measurement circuit which measure signals of capstan FG
and drum FG/PG and other servo systems, as well as
basic configurations like 8-bit CPU, ROM, RAM and I/O
port. They are integrated into a single chip.
100 pin QFP (Plastic)
Also, the CXP884P60 provides sleep/stop functions which
enable to lower power consumption.
This IC is the PROM-incorporated version of the CXP88460
with built-in mask ROM. This provides the additional feature
of being able to write directly into the program. Thus, it is most
suitable for evaluation use during system development and
for small-quantity production.
Structure
Silicon gate CMOS IC
Features
• A wide instruction set (213 instructions) which covers various types of data
— 16-bit arithmetic/multiplication and division/boolean bit operation instructions
• Minimum instruction cycle
250ns at 16MHz operation
122µs at 32kHz operation
60K bytes
• Incorporated PROM capacity
• Incorporated RAM capacity
• Peripheral functions
2048 bytes
— A/D converter
8 bits, 12 channels, successive approximation system
(Conversion time of 20µs/16MHz)
Incorporated 8-bit, 8-stage FIFO
— Serial interface
(Auto transfer for 1 to 8 bytes), 1 channel
Incorporated buffer RAM (Auto transfer for 1 to 32 bytes), 1 channel
Incorporated two-wire 8-bit and 8-stage FIFO (Auto transfer for
1 to 8 bytes), 1 channel
— Timer
8-bit timer/counter, 2 channels
19-bit time-base timer
32kHz timer/counter
— High precision timing pattern generation
circuit
PPG: Maximum of 19 pins 32 stages programmable
RTG: 5 pins, 1 channel
7-bit, 10-stage FIFO (RECCTL control/ATC control),
1 channel
— PWM/DA gate output
12 bits, 2 channels (Repetitive frequency 62.5kHz at 16MHz)
DA gate pulse output: 13 bits, 2 channels
PBCTL amplifier circuit
— Analog signal input circuit
Reel FG comparator
— CTL write/rewrite circuit
— Servo input control
— VSYNC separator
— FRC capture unit
— PWM output
Recording current control circuit
Capstan FG, Drum FG/PG, CTL, Reel FG input
Incorporated 26-bit and 8-stage FIFO
14 bits, 1 channel
— VISS/VASS circuit
— Remote control receiving circuit
— Tri-state output
Pulse duty auto detection circuit
8-bit pulse measurement counter, 6-stage FIFO
PPG output 2 pins
— High speed head switching circuit
• Interruption
• Standby mode
22 factors, 15 vectors, multi-interruption possible
Sleep/stop
• Package
100-pin plastic QFP
• Piggy/evaluation chip
CXP88400 100-pin ceramic PQFP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E01432A33
Block Diagram
NMI
2
AN0 to AN11
12
A/D CONVERTER
SERIAL
PA0 to PA7
8
8
8
SPC700
CPU CORE
CLOCK GENERATOR/
SYSTEM CONTROL
SCL0
SCL1
SDA0
SDA1
FIFO
RAM
FIFO
INTERFACE UNIT
PB0 to PB7
PC0 to PC7
PD0 to PD7
(CH2)
CS0
SI0
SO0
SERIAL
INTERFACE UNIT
(CH0)
PROM
60K
BYTES
RAM
2048
BYTES
SCK0
2
SI1
SERIAL
INTERFACE UNIT
(CH1)
SO1
8
SCK1
EC
PE0, 1, 6, 7
PE2 to PE5
2
6
8-BIT TIMER/COUNTER 0
8-BIT TIMER1
TO/DDO
SYNC
PF0 to PF3
PF4 to PF7
4
4
V SYNC SEPARATOR
PRESCALER/
TIME-BASE TIMER
2
2
EXI0
EXI1
CAPSTAIN
CFG
4
PG0 to PG3
DFG
DPG
DRUM
FRC
CAPTURE UNIT
SERVO INPUT
CONTROL
FIFO
32kHz
TIMER/COUNTER
CTLFAMPI
RFG0
5
PBCTL AMP
4
4
PH0 to PH3
PH4 to PH7
REEL
COMPARATOR
RFG1
FIFO
REMOCON INPUT
RMC
PWM
8
PI0 to PI7
2
VISS/VASS
REALTIME PULSE
GENERATOR
14-BIT PWM GENERATOR
PROGRAMABLE
PATTERN
GENERATOR
RAM
CH1
PWM0
DAA0
CH0
2
12-BIT PWM GENERATOR CH0
12-BIT PWM GENERATOR CH1
FIFO
PWM1
DAA1
19
5
4
5
ADJ
CTLHEAD
HEADL
CTL R/W CONTROL
CXP884P60
Pin Assignment (Top View)
100
99 98
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
97
PB5/PPO13
PB4/PPO12
PB3/PPO11
PB2/PPO10
PB1/PPO9
PB0/PPO8
PC7/RTO7
PC6/RTO6
PC5/RTO5
PC4/RTO4
PC3/RTO3
PC2/PPO18
PC1/PPO17
PC0/PPO16
PI7
1
2
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PE5/EXI1
PE6/PWM0/DAA0
PE7/PWM1/DAA1
RFG0
3
4
5
RFG1
6
ANOUT
7
AMPVDD
8
CTLFAMPO
CTLSAMPI
CTLAGND
CTLFAMPI (–)
CTLFAMPI (+)
HEADL (–)
HEADL (+)
CTLHEAD (+)
CTLHEAD (–)
AMPVSS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
PI6
PI5
VDD
PI4
PI3
AN0
PI2
AN1
PI1
AN2
PI0/INT0
AN3
PD7/SI0
PF0/AN4
PF1/AN5
PF2/AN6
PF3/AN7
AVDD
PD6/SO0
PD5/SCK0
PD4/CS0
PD3/SRVO/TO/DDO/ADJ
PD2/PWM
PD1/RMC
PD0/INT1/NMI
AVREF
AVSS
PF4/AN8
31
32 33
34
35
36 37 38
39
40 41 42
43 44 45 46
47
48 49 50
Note) 1. Vpp (Pin 90) is always connected to VDD.
2. VDD (Pins 63 and 89) are both connected to VDD
3. Vss (Pins 41 and 88) are both connected to GND.
4. MP (Pin 39) is always connected to GND.
– 3 –
CXP884P60
Pin Description
Symbol
I/O
Description
(Port A)
8-bit output port. Data is
gated with PPO contents
by OR-gate and they are
output.
PA0/PPO0
to
PA7/PPO7
Output/
Real-time output
Head switching output.
(8 pins)
(Port B)
Programmable pattern generator (PPG)
output. Functions as high precision real-
time pulse output port.
8-bit output port. Data is
gated with PPO contents
by OR-gate and they are
output.
PB0/PPO8
to
PB7/PPO15
Output/
Real-time output
(19 pins)
PB0 and PB2 can be tri-state controlled
with PPG.
(8 pins)
PC0/PPO16
to
PC2/PPO18
I/O/
(Port C)
Real-time output
8-bit I/O port. I/O can be
specified in 1-bit units.
Data is gated with PPO or
RTO contents by OR-gate
and they are output.
(8 pins)
Real-time pulse generator (RTG) output.
Functions as high precision real-time
pulse output port. PC3 can be tri-state
controlled with RTG.
PC3/RTO3
to
PC7/RTO7
I/O/
Real-time output
(5 pins)
PD0/INT1/
NMI
Input pin to request external interruption
and non-maskable interruption.
I/O/Input/Input
PD1/RMC
PD2/PWM
I/O/Input
Remote control receiving circuit input pin.
14-bit PWM output pin.
I/O/Output
PD3/TO
DDO/ADJ
SRVO
Timer/counter, CTL duty detector, 32kHz
oscillation adjustment and servo amplifier
output pin.
I/O/Output/Output/
Output/Output
(Port D)
8-bit I/O port. I/O can be
specified in 1-bit units.
(8 pins)
PD4/CS0
I/O/Input
I/O/I/O
Serial chip select (CH0) input pin.
Serial clock (CH0) I/O pin.
PD5/SCK0
PD6/SO0
PD7/SI0
I/O/Output
I/O/Input
Serial data (CH0) output pin.
Serial data (CH0) input pin.
PE0/SCK1
Output/I/O
Serial clock (CH1) I/O pin.
PE1/SO1
PE2/SI1
Output/Output
Input/Input
Serial data (CH1) output pin.
Serial data (CH1) input pin.
(Port E)
PE3/SYNC
Input/Input
Composite sync signal input pin.
8-bit port. Bits 2, 3, 4 and 5
are for inputs; bits 0, 1, 6
and 7 are for outputs.
(8 pins)
PE4/EXI0
PE5/EXI1
Input/Input
Input/Input
External input pin for FRC capture unit.
(2 pins)
PE6/PWM0/
DAA0
Output/Output
Output/Output
DA gate pulse
PWM output pin.
output pin.
(2 pins)
PE7/PWM1/
DAA1
(2 pins)
– 4 –
CXP884P60
Description
Description
AN0 to AN3
I/O
Input
PF0/AN4
to
PF3/AN7
(Port F)
Input/Input
Analog input pin to
A/D converter.
(12 pins)
Lower 4 bits are for inputs; upper 4 bits are for
outputs. Lower 4 bits also serve as standby
release input pins.
PF4/AN8
to
PF7/AN11
Output/Input
(8 pins)
Capstan FG input pin.
Drum FG input pin.
PG0/CFG
PG1/DFG
PG2/DPG
Input/Input
(Port G)
4-bit input port.
Drum PG input pin.
Input pin to request
external interruption.
Active when falling
edge.
(4 pins)
External event input
pin for
timer/counter.
PG3/EC/
INT2
Input/Input/Input
PH0/SCL0
PH1/SCL1
Serial clock (CH2) I/O pin.
Serial data (CH2) I/O pin.
(Port H)
8-bit I/O port. Upper four
bits are for outputs. I/O
can be specified in 1-bit
units for lower four bits.
I/O/I/O
Output
PH2/SDA0
PH3/SDA1
Lower four bits are N-ch open drain outputs and which can drive 12mA
sink current.
PH4 to PH7
Upper four bits are for outputs; N-ch open drain output of medium drive
voltage (12V) and large current (12mA).
(8 pins)
Input pin to request external interruption.
Active when falling edge.
I/O/Input
I/O
PI0/INT0
(Port I)
8-bit I/O port. I/O can be
specified in 1-bit units.
Function as standby release input can be specified in 1-bit units.
(8 pins)
PI1 to PI7
Input
Input ports. (2 pins)
Reel FG input pin.
RFG0, RFG1
ANOUT
Output
Output
Input
Output port. (1 pin)
Internal waveform output pin of analog circuit.
Output port. (1 pin)
CTLFAMPO
CTLSAMPI
CTLAGND
PBCTL signal 1st amplifier output pin.
Input port. (1 pin)
PBCTL signal 2nd amplifier input pin.
Output
Output port. (1 pin)
Smoothing capacitor connecting pin.
CTLFAMPI (–)
CTLFAMPI (+)
Input
Output
I/O
Input ports. (2 pins)
Output ports. (2 pins)
I/O ports. (2 pins)
Input PBCTL signal with capacitor coupled.
HEADL (–)
HEADL (+)
During playback, connect to CTLHEAD (–)
and CTLHEAD (+) with internal switch.
CTLHEAD (–)
CTLHEAD (+)
During playback, input pin of PBCTL signal;
during recording, output pin of PBCTL signal.
Analog signal input circuit GND pin.
AMPVSS
AMPVDD
Analog signal input circuit power supply pin.
– 5 –
CXP884P60
Symbol
EXTAL
I/O
Description
Input
Connecting pin of crystal oscillator for system clock. When supplying
the external clock, input it to EXTAL pin and input the opposite phase
clock to XTAL pin.
XTAL
TEX
Output
Input
Connecting pin of crystal oscillator for 32kHz timer clock. When used
as event counter, input to TEX pin and leave TX pin open.
(In this time, feedback resistor is not removed.)
Output
Input
TX
System reset pin; active at low level.
RST
Positive power supply pin for incorporated PROM write.
Connect this pin to VDD for normal operation.
Vpp
Input
Input
Test mode input pin. Always connect to GND.
Positive power supply pin of A/D converter.
Reference voltage input pin of A/D converter.
GND pin of A/D converter.
MP
AVDD
AVREF
AVSS
VDD
Positive power supply pin.
GND pin. Connect both Vss pins to GND.
VSS
– 6 –
CXP884P60
Input/Output Circuit Formats for Pins
Pin
After a reset
Circuit format
Port A
PPO data
Port B
PA0/PPO0
to
PA7/PPO7
Ports A and B data
Hi-Z
PB4/PPO12
to
Internal data bus
PB7/PPO15
RD (Port A or Port B)
Output becomes active from
high impedance by data writing
to port data register.
Port B
PPO8, PPO10 data
PB0, PB2 data
PB0/PPO8
PB2/PPO10
Hi-Z
Internal data bus
RD (Port B)
PPO9, PPO11 data
Output becomes active from high
impedance by data writing to port
data register.
PPG control/status
register bit 0
Tri-state control
selection
"0" after a reset
PPO9, PPO11 data
PB1/PPO9
PB3/PPO11
Hi-Z
PB1, PB3 data
Output becomes active from high
impedance by data writing to port
data register.
Internal data bus
RD (Port B)
– 7 –
CXP884P60
Circuit format
Pin
After a reset
Port C
PPO, RTO data
Port C data
PC0/PPO16
to
Input protection
circuit
PC2/PPO18
Port C direction
"0" after a reset
IP
Hi-Z
PC5/RTO5
to
PC7/RTO7
Internal data bus
Internal data bus
RD (Port C)
RD (Port C direction)
Port C
RTO3 data
PC3 data
PC3 direction
"0" after a reset
IP
Internal data bus
Internal data bus
PC3/RTO3
Hi-Z
RD (Port C)
RD (Port C direction)
RTO4 data
RTG interruption
control register bit 7
Tri-state control
selection
"0" after a reset
RTO4 data
PC4 data
PC4 direction
PC4/RTO4
Hi-Z
"0" after a reset
IP
Internal data bus
Internal data bus
RD (Port C)
RD (Port C direction)
– 8 –
CXP884P60
Pin
After a reset
Circuit format
Port D
Port D data
Port D direction
"0" after a reset
PD0/INT1/NMI
PD1/RMC
PD4/CS0
IP
Internal data bus
Hi-Z
RD (Port D)
PD7/SI0
Schmitt input
Internal data bus
RD (Port D direction)
PD1: Remote control circuit
PD0: Interruption circuit
PD4, PD7: Serial CH0
Port D
Port D function
select
"0" after a reset
PD2: 14-bit PWM
Timer/counter,
CTL duty detection circuit,
32kHz timer,
PD3:
amplifier circuit
MPX
PD2/PWM
PD3/SRVO/
TO/DDO/
ADJ
Port D data
Hi-Z
Port D direction
"0" after a reset
IP
Internal data bus
RD (Port D)
Internal data bus
RD (Port D direction)
Port D
Port D function
select
"0" after a reset
SIO CH0
MPX
Port D data
PD5/SCK0
PD6/SO0
Hi-Z
IP
Port D direction
"0" after a reset
MPX
Note)
PD5 is schmitt input
PD6 is inverter input
Internal data bus
RD (Port D)
SIO CH0
– 9 –
CXP884P60
Pin
After a reset
Circuit format
Port E
Port/SCK
output select
"1" after a reset
SIO CH1
MPX
PE0/SCK1
Hi-Z
Port E data
Hi-Z control
SIO CH1
IP
Internal data bus
RD (Port E)
Port E
Port E function
select
"1" after a reset
SIO CH1
MPX
PE1/SO1
Hi-Z
Port E data
Internal data bus
Hi-Z control
RD (Port E)
Port E
Schmitt input
IP
PE2: SIO CH1
PE3
PE4 : Servo input
PE5
PE2/SI1
PE3/SYNC
PE4/EXI0
PE5/EXI1
Hi-Z
Internal data bus
RD (Port E)
Note) For PE3/SYNC, CMOS schmitt input or TTL schmitt input can be selected
with the mask option.
Port E
Port/DA/PWM
select
"1" after a reset
DA gate output or
PWM output
PE6/PWM0/
DAA0
MPX
High level
PE7/PWM1/
DAA1
Port E data
Internal data bus
Hi-Z control
RD (Port E)
– 10 –
CXP884P60
After a reset
Hi-Z
Pin
Circuit format
Input multiplexer
AN0
to
AN3
A/D converter
A/D converter
IP
Port F
Input multiplexer
IP
PF0/AN4
to
Hi-Z
PF3/AN7
Internal data bus
RD (Port F)
Port F
Port F data
PF4/AN8
to
PF7/AN11
Hi-Z
Internal data bus
IP
RD (Port F)
Port/AD select
"1" after a reset
Input multiplexer
A/D converter
Port G
Power ON/OFF control
Schmitt input
PG0/CFG
PG1/DFG
PG2/DPG
Servo input
IP
Hi-Z
Internal data bus
RD (Port G)
Schmitt width selection
Port G
Schmitt input
IP
PG3/EC/INT2
Hi-Z
Internal data bus
RD (Port G)
– 11 –
CXP884P60
After a reset
Pin
Circuit format
Port H
SCL, SDA
I2C output enable
Port H data
Port H direction
"0" after a reset
PH0/SCL0
PH1/SCL1
PH2/SDA0
PH3/SDA1
IP
Hi-Z
Schmitt input
Internal data bus
Internal data bus
RD (Port H)
SCL, SDA
RD (Port H direction)
Other serial interface
(CH2) pin
(Serial interface
(CH2) circuit)
Port H
Port H data
Hi-Z
PH4 to PH7
Internal data bus
12V drive voltage,
large current 12mA
RD (Port H)
Port I
Pull-up resistor
"0" after a reset
PI0 data
PI0 direction
IP
"0" after a reset
Internal data bus
Internal data bus
RD (Port I)
Hi-Z
PI0/INT0
RD (Port I direction)
Internal data bus
RD (pull-up resistor)
Standby release
Edge detection
Interruption circuit
Pull-up transistor
approximately 100kΩ
– 12 –
CXP884P60
After a reset
Pin
Circuit format
Port I
Pull-up resistor
"0" after a reset
Port I data
Port I direction
"0" after a reset
IP
Internal data bus
Internal data bus
PI1 to PI7
RD (Port I)
Hi-Z
RD (Port I direction)
Internal data bus
RD (pull-up resistor)
Standby release
Edge detection
Pull-up transistor
approximately 100kΩ
CTLAGND
CTLFAMPI (+)
CTLFAMPI (+)
CTLFAMPI (–)
CTLFAMPO
IP
1/2AMPVDD
IP
CTLFAMPO
CTLFAMPI (–)
Input pin charge control
Input pin charge control
IP
CTLSAMPI
1/2AMPVDD
LPF circuit
CTLAGND
– 13 –
CXP884P60
Pin
Circuit format
After a reset
AMPVDD
CTLAGND
1/2AMPVDD
IP
CTL AMP
AMPVSS
AMPVDD
Write current select
RTO6
Recording current control circuit
Hi-Z
CTLHEAD (+)
IP
RTO7
RTO3
HEADL (+) pin
AMPVSS
AMPVDD
RTG control permission
Write current select
RTO7
Recording current control circuit
CTLHEAD (–)
IP
Hi-Z
RTO6
RTO3
HEADL (–) pin
AMPVSS
RTG control permission
CTLHEAD (+) pin
IP
HEADL (+)
Hi-Z
RTO3
RTG control permission
AMPVSS
CTLHEAD (–) pin
IP
HEADL (–)
RTO3
Hi-Z
RTG control permission
AMPVSS
– 14 –
CXP884P60
Pin
After a reset
Circuit format
Comparator
RFG0
RFG1
Hi-Z
Servo output
IP
• Shows the circuit composition
during oscillation.
EXTAL
XTAL
IP
EXTAL
XTAL
• Feedback resistor is removed
and XTAL outputs High level
during stop.
Oscillation
• Shows the circuit
composition during
oscillation.
32kHz
timer/counter
TEX
TX
IP
TEX
TX
• Feedback resistor is
removed during 32kHz
oscillation circuit stop by
software. At that time,
TEX outputs Low level
and TX outputs High level.
Oscillation
Mask option
Pull-up resistor
Schmitt input
Low level
(during a
reset)
RST
OP
IP
– 15 –
CXP884P60
Absolute Maximum Ratings
(Vss = 0V reference)
Remarks
Item
Symbol
VDD
Rating
–0.3 to +7.0
–0.3 to +13
AVss to +7.0
–0.3 to +0.3
Unit
V
V
PROM incorporated version
Vpp
1
V
AVDD
AVSS
AMPVDD
AMPVSS
VIN
Supply voltage
V
2
AMPVSS to +7.0
–0.3 to +0.3
V
V
3
–0.3 to +7.0
V
Input voltage
3
–0.3 to +7.0
V
Output voltage
VOUT
VOUTP
IOH
–0.3 to +15.0
V
Port H (PH7 to PH4) pin
Total of output pins
Medium drive output voltage
High level output current
High level total output current
–5
mA
mA
–50
∑IOH
Other than large current output
ports (value per pin)
15
20
mA
mA
IOL
Low level output current
4
Large current output port
IOLC
(value per pin)
130
–20 to +75
–55 to +150
600
mA
°C
Total of output pins
Low level total output current
Operating temperature
∑IOL
Topr
Tstg
PD
Storage temperature
°C
Allowable power dissipation
mW QFP package type
1
AVDD should not exceed VDD + 0.3V.
2
AMPVDD should not exceed VDD + 0.3V.
3
4
VIN and VOUT should not exceed VDD + 0.3V.
The large current output port is port H (PH7 to PH4).
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
better take place under the recommended operating conditions. Exceeding those conditions may
adversely affect the reliability of the LSI.
– 16 –
CXP884P60
Recommended Operating Conditions
(Vss = 0V reference)
Item
Symbol
Min.
4.5
Max.
5.5
Unit
V
Remarks
Guaranteed operation range for 1/2 and 1/4
frequency dividing clock
Guaranteed operation range for 1/16 frequency
dividing clock or during sleep mode
3.5
2.7
2.5
5.5
5.5
5.5
VDD
Supply voltage
Guaranteed operation range by TEX clock
Guaranteed data hold operation range
during stop
8
1
2
3
V
V
V
V
V
V
V
V
V
V
V
°C
Vpp
Vpp = VDD
4.5
AVDD
AMPVDD
VIH
5.5
5.5
Analog supply voltage
High level input voltage
4.5
0.7VDD
0.8VDD
2.2
VDD
VDD
VDD
4
CMOS schmitt input
VIHS
5
TTL schmitt input
VIHTS
VIHEX
VIL
6
7
EXTAL pin
TEX pin
VDD – 0.4 VDD + 0.3
3
0
0
0.3VDD
0.2VDD
0.8
4
CMOS schmitt input
VILS
Low level input voltage
5
TTL schmitt input
VILTS
VILEX
Topr
0
6
7
–0.3
–20
0.4
EXTAL pin
TEX pin
Operating temperature
+75
1
AVDD and VDD should be set to the same voltage.
AMPVDD and VDD should be set to the same voltage.
2
3
4
Normal input port (each pin of PC, PD2, PD3, PD6, PF0 to PF3, PI1 to PI7 and PH0 to PH3), MP pin
Each pin of RST, PD0/INT1/NMI, PD1/RMC, PD4/CS0, PD5/SCK0, PD7/SI0, PE0/SCK1, PE2/SI1,
PE3/SYNC, PE4/EXI0, PE5/EXI1, PI0/INT0, PG3/EC/INT2 (For PE3/SYNC, when CMOS schmitt input is
selected with mask option.)
5
6
7
8
PE3/SYNC (when TTL schmitt input is selected with mask option.)
Specifies only during external clock input.
Specifies only during external event input.
Vpp and VDD should be set to the same voltage.
– 17 –
CXP884P60
Electrical Characteristics
DC Characteristics (VDD = 4.5 to 5.5V)
(Ta = –10 to +75°C, Vss = 0V reference)
Item
Symbol
Pins
Conditions
Min.
4.0
Typ.
Max. Unit
VDD = 4.5V, IOH = –0.5mA
PA to PD,
PE0 to PE1,
PE6 to PE7,
PF4 to PF7,
PH (VOL only)
PI
V
V
High level
output voltage
VOH
3.5
VDD = 4.5V, IOH = –1.2mA
VDD = 4.5V, IOL = 1.8mA
VDD = 4.5V, IOL = 3.6mA
VDD = 4.5V, IOL = 12.0mA
VDD = 5.5V, VIH = 5.5V
VDD = 5.5V, VIL = 0.4V
VDD = 5.5V, VIH = 5.5V
V
0.4
Low level
output voltage
V
VOL
0.6
PH
V
1.5
40
0.5
–0.5
0.1
µA
µA
µA
µA
µA
IIHE
IILE
IIHT
IILT
IILR
EXTAL
–40
10
Input current
TEX
–0.1
–1.5
–10
–400
VDD = 5.5V,
VIL = 0.4V
1
RST
PA to PF,
PG3, PI, MP, VDD = 5.5V,
AN0 to AN3, VI = 0, 5.5V
RST
I/O leakage
current
µA
IIZ
±10
1
Open drain
PH4 to PH7 VDD = 5.5V, VOH = 12V
µA
µA
50
10
output leakage
current (N-CH
Tr off state)
ILOH
PH0 to PH3 VDD = 5.5V, VOH = 5.5V
16MHz crystal oscillation (C1 = C2 = 15pF)
IDD1
37
2.1
58
9
50
8
mA
3
VDD = 5.5V
Sleep mode
IDDS1
IDD2
mA
VDD = 5.5V
32kHz crystal oscillation (C1 = C2 = 47pF)
VDD = 3.3V
Supply
current
1000 µA
VDD, VSS
2
Sleep mode
IDDS2
35
30
µA
µA
VDD = 3V ± 0.3V
Stop mode
(EXTAL and TEX pins oscillation stop)
IDDS3
VDD = 5V ± 0.5V
– 18 –
CXP884P60
Item
Symbol
Pins
Conditions
Min.
Typ.
Max. Unit
PC, PD, PE0,
PE2 to PE5,
PF, PG, PI,
CTLHEAD (+),
CTLHEAD (–),
CTLFAMPI (+),
CTLFAMPI (–),
CTLSAMPI,
RFG,
Clock 1MHz
0V other than the measured pins
Input capacity
CIN
10
20
pF
XTAL, TEX
1
RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current
when no resistor is selected.
2
3
When entire output pins are left open.
When setting upper 2 bits (CPU clock selection) of clock control register (CLC: 00FEh) to "00" and
operating in high speed mode (1/2 frequency dividing clock).
– 19 –
CXP884P60
AC Characteristics
(1) Clock timing
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
Pins
Conditions
Min.
1
Typ.
Max. Unit
XTAL
EXTAL
Fig. 1, Fig. 2
MHz
ns
16
200
20
System clock frequency
fC
Fig. 1, Fig. 2
External clock drive
t
t
XL,
XH
XTAL
EXTAL
28
System clock input pulse width
Fig. 1, Fig. 2
External clock drive
System clock input rise and
fall times
XTAL
EXTAL
t
t
CR,
CF
ns
Event count clock input
pulse width
t
t
EH,
EL
1
Fig. 3
Fig. 3
ns
tsys
+
200
EC
EC
Event count clock input
rise and fall times
t
t
ER,
EF
ms
VDD = 2.7 to 5.5V
Fig. 2 (32kHz clock
applied condition)
TEX
TX
kHz
32.768
System clock frequency
fC
Event count clock input
pulse width
t
t
TL,
TH
Fig. 3
Fig. 3
µs
10
TEX
TEX
Event count clock input
rise and fall times
t
t
TR,
TF
ms
20
1
tsys indicates three values according to the contents of the clock control register (CLC: 00FEh) upper 2 bits
(CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
1/fc
VDD – 0.4V
0.4V
EXTAL
XTAL
tXH
tCF
tXL
tCR
Fig. 1. Clock timing
Crystal oscillation
Ceramic oscillation
32kHz clock applied condition
Crystal oscillation
External clock
EXTAL
XTAL
EXTAL
XTAL
TEX
TX
C1
C2
C1
C2
74HC04
Fig. 2. Clock applied condition
0.8VDD
0.2VDD
TEX
EC
tEH
tTH
tEF
tTF
tEL
tTL
tER
tTR
Fig. 3. Event count clock timing
– 20 –
CXP884P60
(2) Serial transfer (CH0)
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol Pins
Conditions
Min.
Max.
Unit
ns
CS0 ↓ → SCK0
Chip select transfer mode
(SCK0 = output mode)
t
t
t
t
t
DCSK
SCK0
tsys + 200
delay time
CS0 ↑ → SCK0
floating delay time
Chip select transfer mode
(SCK0 = output mode)
ns
ns
ns
ns
DCSKF SCK0
DCSO SO0
DCSOF SO0
WHCS CS0
tsys + 200
tsys + 200
tsys + 200
CS0 ↓ → SO0
Chip select transfer mode
Chip select transfer mode
Chip select transfer mode
delay time
CS0 ↑ → SO0
floating delay time
CS0
tsys + 200
high level width
Input mode
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2tsys + 200
16000/fc
tsys + 100
8000/fc – 100
–tsys + 100
200
SCK0
cycle time
t
KCY
SCK0
SCK0
SI0
Output mode
Input mode
t
t
KH
KL
SCK0
high and low level widths
Output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
SI0 input setup time
(against SCK0 ↑)
t
t
t
SIK
2tsys + 100
100
SI0 input hold time
(against SCK0 ↑)
KSI
SI0
2tsys + 100
100
KSO
SCK0 ↓ → SO0 delay time
SO0
Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 00FEh) upper
2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Note 2) The load of SCK0 output mode and SO0 output delay time is 50pF + 1TTL.
– 21 –
CXP884P60
tWHCS
0.8VDD
CS0
SCK0
SI0
0.2VDD
tKCY
tDCSK
tDCSKF
tKL
tKH
0.8VDD
0.8VDD
0.2VDD
tSIK tKSI
0.8VDD
0.2VDD
Input data
tDCSO
tKSO
tDCSOF
0.8VDD
SO0
Output data
0.2VDD
Fig. 4. Serial transfer timing (CH0)
– 22 –
CXP884P60
Serial transfer (CH1) (SIO mode)
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol Pins
Conditions
Input mode
Min.
2tsys + 200
16000/fc
tsys +100
8000/fc – 50
100
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK1 cycle time
t
KCY
SCK1
SCK1
SI1
Output mode
Input mode
SCK1 high and low
level widths
t
t
KH
KL
Output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode
SI1 input setup time
(for SCK1 ↑)
t
t
SIK
KSI
200
tsys + 200
100
SI1 input hold time
(for SCK1 ↑)
SI1
tsys + 200
100
SCK1 ↓ → SO1 delay time tKSO
SO1
Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 00FEh) upper
2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”)
Note 2) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL.
tKCY
tKL
tKH
SCK1
0.8VDD
0.2VDD
tSIK
tKSI
0.8VDD
0.2VDD
SI1
Input data
tKSO
0.8VDD
SO1
Output data
0.2VDD
Fig. 5. Serial transfer CH1 timing (SIO mode)
– 23 –
CXP884P60
Serial transfer (CH1) (Special mode) (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol Pins
SO1
Conditions
Min.
Typ.
104
Max. Unit
µs
1
SO1 cycle time
SI1 data setup time
t
LCY
SI1
SI1
SI1
t
t
LSU
LHD
2
2
µs
µs
SI1 data hold time
1
t
LCY is specified only when serial mode register (CH1) (SIOM1: 05F2h) lower 2 bits (SO1 clock selection)
are set at 104µs.
Note) The load of SO1 pin is 50pF + 1TTL.
tLCY
tLCY
0.5VDD
Start bit
Output data bit
SO1
tLCY/2
tLSU
tLHD
0.8VDD
0.2VDD
Input
data bit
SI1
Fig. 6. Serial transfer CH1 timing (Special mode)
– 24 –
CXP884P60
Serial transfer (CH2)
Item
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Symbol
fSLC
Pins
SCL
Conditions
Min.
Max.
400
Unit
kHz
µs
µs
µs
µs
µs
µs
ns
SCL clock frequency
Bus-free time before starting transfer
Hold time for starting transfer
Clock low level width
t
t
t
t
t
t
t
t
t
t
BUF
SDA, SCL
SDA, SCL
SCL
2.6
1.0
1.0
1.0
1.0
HD; STA
LOW
Clock high level width
Setup time for repetitive transfers
Data hold time
HIGH
SCL
SU; STA
HD; DAT
SU; DAT
R
SDA, SCL
SDA, SCL
SDA, SCL
SDA, SCL
SDA, SCL
SDA, SCL
1
0
Data setup time
100
SDA, SCL rise time
300
300
ns
SDA, SCL fall time
F
ns
Setup time for transfer completion
SU; STO
1.6
µs
1
The SCL fall time (300ns Max.) is not included in the data hold time.
SDA
tBUF
tR
tF
tHD; STA
SCL
tHD; STA
tSU; STO
tSU; STA
P
S
St
P
tLOW
tHD; DAT
tHIGH
tSU; DAT
Fig. 7. Serial transfer CH2 timing
Device
Device
RS
RS RS
RS RP
RP
SDA0
(or SDA1)
SCL0
(or SCL1)
Fig. 8. Device recommended circuit
• A pull-up resistor (RP) must be connected to SDA0 (or SDA1) and SCL0 (or SCL1).
• The SDA0 (or SDA1) and SCL0 (or SCL1) series resistance (Rs = 300Ω or less) can be used to reduce the
spike noise caused by CRT flashover.
– 25 –
CXP884P60
(4) A/D converter characteristics
(Ta = –10 to +75°C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V reference)
Item
Resolution
Symbol
Pins
Conditions
Min.
Typ.
Max. Unit
8
Bits
LSB
LSB
µs
Ta = 25°C
Linearity error
±1
±2
V
DD = AVDD = AVREF = 5.0V
Absolute error
VSS = AVSS = 0V
1
tCONV
SAMP
160/fADC
12/fADC
Conversion time
Sampling time
1
t
µs
VREF
VIAN
AVREF
AVDD – 0.5
0
AVDD
AVREF
1.0
V
Reference input voltage
Analog input voltage
AN0 to AN7
V
mA
0.6
Operating mode
Sleep mode
Stop mode
AVREF current
AVREF
IREF
10
µA
32kHz operating mode
FFh
FEh
1
fADC indicates the follwing values due to the peripheral
clock control register (PCC: 05F8h) bit 3 and clock control
register (CLC: 00FEh) upper 2 bits.
ADCCK
0 (φ/2 selection) 1 (φ selection)
PCK1, PCK0
Linearity error
Analog input
00 (φ = fEX/2)
01 (φ = fEX/4)
11 (φ = fEX/16)
fADC = fc/2
fADC = fc/4
fADC = fc/16
fADC = fc
01h
00h
fADC = fc/2
fADC = fc/8
VZT
VFT
Fig. 9. Definitions of A/D converter terms
– 26 –
CXP884P60
(4) Interruption, reset input
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
Pins
INT0
Conditions
Min.
Max.
Unit
INT1
INT2
NMI
External interruption high and
low level widths
t
t
IH
IL
1
µs
PI0 to PI7
Reset input low level width
32/fc
µs
t
RSL
RST
tIH
tIL
INT0
INT1
0.8VDD
INT2
NMI
0.2VDD
PI0 to PI7
(During standby release input)
(Falling edge)
Fig. 10. Interruption input timing
tRSL
RST
0.2VDD
Fig. 11. Reset input timing
(5) Others
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
Pins
CFG
Conditions
Min.
Max. Unit
ns
CFG input
t
t
CFH
CFL
24tFRC + 200
high and low level widths
DFG input
high and low level widths
t
t
DFH
DFL
ns
ns
ns
16tFRC + 200
8tFRC + 200
16tFRC + 200
DFG
DPG
DPG
DPG minimum pulse width
t
DPW
DPG minimum
removal time
trem
EXI input
high and low level widths
t
t
EIH
EIL
EXI0
EXI1
8tFRC + 200 + tsys
tsys = 2000/fc
ns
Note 1) tFRC = 1000/fc [ns]
Note 2) tsys indicates three values according to the contents of the clock control register (CLC: 00FEh)
upper 2 bits (CPU clock selection).
tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
– 27 –
CXP884P60
tCFH
tCFL
0.8VDD
CFG
0.2VDD
tDFH
tDFL
0.8VDD
DFG
0.2VDD
tDPW
trem
trem
0.8VDD
DPG
tEIH
tEIL
0.8VDD
EXI0
EXI1
0.2VDD
Fig. 12. Other timings
– 28 –
CXP884P60
Analog Circuit Characteristics
(AMPVDD = VDD = 5.0V, AMPVSS = Vss = 0V, Ta = –10 to +75°C)
(1) Amplifier circuit reference voltage characteristics
Symbol
VOR
Min. Typ. Max. Unit
Conditions
Item
Pins
Reference level
output voltage
CTLAGND
2.20
2.45 2.75
V
(2) CTL 1st amplifier characteristics
(AMPVDD = VDD = 5.0V, AMPVSS = Vss = 0V, Ta = –10 to +75°C)
Item
Symbol
Pins
Conditions
Min.
13.5
Typ.
15.5
Max. Unit
17.5
CTLFAMPI (–) = 0V,
Gain = 16dB
CTLFAMPI (–) = 0V,
Gain = 34dB
31.8
46.5
52.5
33.8
48.5
54.5
35.8
dB
CTLFAMPI (–)
CTLFAMPI (+)
1
Voltage gain
AVCTL1
CTLFAMPI (–) = 0V,
Gain = 49dB
50.5
CTLFAMPI (–) = 0V,
Gain = 55dB
56.5
CTLFAMPI (–),
CTLFAMPI (+) = open,
Gain = 16dB
Output offset
voltage
CTLFAMPI (–)
CTLFAMPI (+)
VOSCTL1
–25
0
+25
mV
1
The result after monitoring CTLFAMPO pin when the electrolytic capacitor (10µF) is connected to
CTLFAMP (–) and CTLFAMP (+).
(3) CTL 2nd amplifier characteristics
(AMPVDD = VDD = 5.0V, AMPVSS = Vss = 0V, Ta = –10 to +75°C)
Conditions
Gain = 5dB
Item
Symbol
Pins
Min.
3.5
Typ. Max. Unit
5.5
8.2
7.5
Gain = 8dB
Gain = 11dB
Gain = 14dB
Gain = 17dB
Gain = 20dB
6.2
10.2
13.0
16.0
19.0
22.0
9.0
11.0
14.0
17.0
20.0
1
dB
Voltage gain
AVCTL2
CTLSAMPI
12.0
15.0
18.0
Output offset
voltage
CTLSAMPI = open,
Gain = 5dB
VOSCTL2 CTLSAMPI
–30
0
+30
mV
12kHz, fDC – 3dB
20kHz, fDC – 3dB
8
12
20
24
42
LPF cut-off
frequency
FCCTL
CTLSAMPI
kHz
12
– 29 –
CXP884P60
Conditions
Item
Symbol
Pins
Min.
80
Typ. Max. Unit
Comparator level = +100mV0-p
Comparator level = +150mV0-p
Comparator level = +200mV0-p
Comparator level = +250mV0-p
Comparator level = +300mV0-p
Comparator level = +400mV0-p
Comparator level = +500mV0-p
Comparator level = +600mV0-p
Comparator level = +1000mV0-p
Comparator level = –100mV0-p
Comparator level = –150mV0-p
Comparator level = –200mV0-p
Comparator level = –250mV0-p
Comparator level = –300mV0-p
Comparator level = –400mV0-p
Comparator level = –500mV0-p
Comparator level = –600mV0-p
110
150
200
250
290
380
470
570
920
140
190
240
290
330
420
520
610
990
110
160
210
250
340
420
530
850
–90
Comparator
VCCTL
CTLSAMPI
mV
2
level
–120 –150
–110 –130 –190
–150 –190 –230
–200 –240 –280
–240 –280 –320
–340 –380 –420
–430 –480 –530
–540 –580 –620
Comparator level = –1000mV0-p –870 –970 –1070
1
The result after monitoring ANOUT pin when the electrolytic capacitor (10µF) is connected to CTLSAMPI.
The reference value of the comparator level is CTLAGND.
2
(4) CTL amplifier characteristics (CTL1stAMP + CTL2ndAMP)
(AMPVDD = VDD = 5.0V, AMPVSS = Vss = 0V, Ta = –10 to +75°C)
Item
Symbol
Pins
Conditions
Min.
17.0
Typ. Max. Unit
CTLHEAD (–) = 0V,
Gain = (16dB + 5dB)
20.5 23.5
dB
CTLHEAD (–)
CTLHEAD (+)
3
Voltage gain
AVCTL
CTLHEAD (–) = 0V,
Gain = (55dB + 20dB)
70.5
60
74.5 77.0
CTLHEAD (–) = 0V,
Gain = (55dB + 20dB)
Comparator = ±150mV0-p
CTLHEAD (–)
CTLHEAD (+)
Input sensitivity VSCTL
70
140
µVp-p
3
The result when waveform is input from CTLHEAD (+) pin and ANOUT pin is monitored after performing
coupling electrolytic capacitor (10µF) of CTLHEAD (–) and CTLHEAD (+), and coupling electrolytic capacitor
(10µF) of HEADL (–) and HEADL (+), CTLFAMPI (–) and CTLFAMPI (+) , and CTLFAMPO and CTLSAMPI.
Gain is maximum –1.5dB lowered when waveform is input from CTLHEAD (+) pin.
– 30 –
CXP884P60
(5) RECCTL write circuit characteristics (AMPVDD = VDD = 5.0V, AMPVSS = Vss = 0V, Ta = –10 to +75°C)
Item
Symbol
Pins
Conditions
Min.
0.8
1.4
2.0
2.4
3.0
3.5
4.5
5.0
5.5
Typ. Max. Unit
Write current 2.0mAp-p
Write current 3.0mAp-p
Write current 4.0mAp-p
Write current 5.0mAp-p
Write current 6.0mAp-p
Write current 7.0mAp-p
Write current 8.0mAp-p
Write current 9.0mAp-p
Write current 10.0mAp-p
1.8
2.8
3.8
4.8
6.0
6.8
7.8
8.8
7.7
3.6
5.0
7.0
8.5
CTLHEAD (–)
CTLHEAD (+)
1
10.0
11.5
13.0
15.0
17.0
mA
Write current
IOREC
1
The current which flows when CTLHEAD (–) and CTLHEAD (+) shorts.
(6) Auto threshold control circuit (ATC) characteristics
(AMPVDD = VDD = 5.0V, AMPVSS = Vss = 0V, Ta = –10 to +75°C)
Item
Symbol
VATCINIT
Pins
Conditions
Voltage = –150mV0-P
Voltage = –400mV0-P
Gain = 1/6 (16.7%)
Gain = 1/5 (20%)
Gain = 1/4 (25%)
Gain = 1/3 (33.3%)
Gain = 2/5 (40%)
Gain = 1/2 (50%)
Gain = 3/5 (60%)
Min.
–110
–350
Typ. Max. Unit
–150 –190
mV
ATC peak hold circuit
initialize voltage value
2
–400 –450
–70 –160
–90 –210
–90 –210
ATC comparator level
offset voltage
–70 –160
–90 –210
–70 –160
–90 –210
mV
VATCOFF
3
2
Reference is CTLAGND.
Reference is CTLAGND.
3
When comparator level is generated using ATC, actual comparator level is as follows by the offset voltage
inside the ATC.
Vin × gain + |offset voltage|
Example: Gain = 1/2
Vin × 1/2 + 160
(7) Schmitt characteristics
(AMPVDD = VDD = 5.0V, AMPVSS = Vss = 0V, Ta = –10 to +75°C)
Item
Symbol
Pins
Conditions
Min.
820
Typ. Max. Unit
RFG0,
RFG1
mV
RTG schmitt width
SRFG
Schmitt width 1Vp-p
920 1020
CFG,
DFG,
DPG
SCFG
SDFG
SDPG
Schmitt width 410mVp-p
Schmitt width 1Vp-p
– 31 –
180
700
300
420
CFG/DFG/DPG
mV
900 1100
CXP884P60
Appendix
(i)
(ii)
EXTAL
XTAL
Rd
TEX
TX
Rd
C2
C1
C2
C1
Fig. 13. Recommended oscillation circuit
Circuit
example
Manufacturer
Model
fc (MHz)
8.00
C1 (pF)
10
C2 (pF)
10
Rd (Ω)
RIVER
ELETEC
CO., LTD.
10.00
12.00
16.00
0
HC-49/U03
(i)
5
5
8.00
10.00
16 (12)
16 (12)
12
16 (12)
16 (12)
12
0
(i)
HC-49/U (-S)
P3
0
0
KINSEKI LTD.
12.00
16.00
12
12
470k
(ii)
32.768kHz
18
30
Mask option table
2
Item
Mask ROM
100-pin plastic QFP
CXP884P60Q-1-
Package
100-pin plastic QFP
40K/48K (CXP88340/88348)
52K/60K (CXP88452/88460)
ROM capacity
PROM 60K bytes
Reset pin pull-up resistor
Existent
Existent/Non-existent
1
Input circuit format
TTL schmitt
CMOS schmitt/TTL schmitt
1
The input circuit format can be selected for PE3/SYNC pin.
OEM No.
2
– 32 –
CXP884P60
Characteristics Curve
IDD vs. VDD
(fc = 16MHz, Ta = 25°C)
IDD vs. fC
(VDD = 5V, Ta = 25°C)
100
10
1
1/2 dividing mode
1/4 dividing mode
40
30
20
10
1/2 dividing mode
1/16 dividing mode
Sleep mode
1/4 dividing mode
32kHz mode
(instruction)
0.1
(100µA)
32kHz
Sleep mode
1/16 dividing mode
Sleep mode
0.01
(10µA)
0
1
2
3
4
5
6
7
0
5
10
15
VDD – Supply voltage [V]
fc – System clock [MHz]
– 33 –
CXP884P60
Package Outline
Unit: mm
100PIN QFP (PLASTIC)
23.9 ± 0.4
+ 0.1
0.15 – 0.05
+ 0.4
20.0 – 0.1
80
51
50
81
A
31
100
1
30
+ 0.15
0.65
+ 0.35
2.75 – 0.15
0.3 – 0.1
0.13
0.15
M
+ 0.2
0.1 – 0.05
0˚ to 10˚
DETAIL
A
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
EPOXY RESIN
SOLDER PLATING
QFP-100P-L01
QFP100-P-1420
SONY CODE
EIAJ CODE
LEAD MATERIAL
PACKAGE MASS
42/COPPER ALLOY
1.7g
JEDEC CODE
100PIN QFP (PLASTIC)
23.9 ± 0.4
+ 0.1
0.15 – 0.05
+ 0.4
20.0 – 0.1
80
51
50
81
A
31
100
1
30
+ 0.15
0.65
+ 0.35
2.75 – 0.15
0.3 – 0.1
0.13
0.15
M
+ 0.2
0.1 – 0.05
0˚ to 10˚
DETAIL
A
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
EPOXY RESIN
SOLDER PLATING
QFP-100P-L01
QFP100-P-1420
SONY CODE
EIAJ CODE
LEAD MATERIAL
PACKAGE MASS
42/COPPER ALLOY
1.7g
JEDEC CODE
LEAD PLATING SPECIFICATIONS
ITEM
SPEC.
42 ALLOY
LEAD MATERIAL
SOLDER COMPOSITION
PLATING THICKNESS
Sn-Bi Bi:1-4wt%
5-18µm
Sony Corporation
– 34 –
相关型号：
©2020 ICPDF网 联系我们和版权申明