CY7C1327C-200BGC [ETC]
x18 Fast Synchronous SRAM ; X18高速同步SRAM\n
| 型号： | CY7C1327C-200BGC |
| 厂家： | 
ETC |
| 描述： | x18 Fast Synchronous SRAM
|
| 文件： | 总24页 (文件大小：294K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1347C/GVT71128DA36
CY7C1327C/GVT71256DA18
256K x 18/128K x 36 Synchronous-Pipelined
Cache RAM
The CY7C1347C/GVT71128DA36 and CYC7C1327C/
GVT71256DA18 SRAMs integrate 131,072x36 and
262,144x18 SRAM cells with advanced synchronous periph-
Features
• Fast access times: 2.5 and 3.5 ns
eral circuitry and a 2-bit counter for internal burst operation. All
synchronous inputs are gated by registers controlled by a pos-
itive-edge-triggered clock input (CLK). The synchronous in-
puts include all addresses, all data inputs, address-pipelining
Chip Enable (CE), depth-expansion Chip Enables (CE2 and
CE2), Burst Control Inputs (ADSC, ADSP, and ADV), Write
Enables (BWa, BWb, BWc, BWd, and BWE), and Global Write
(GW).
• Fast clock speed: 250, 225, 200, and 166 MHz
• 1-ns set-up time and hold time
• Fast OE access times: 2.5 ns and 3.5 ns
• Optimal for depth expansion (one cycle chip deselect
to eliminate bus contention)
• 3.3V –5% and +10% power supply
• 3.3V or 2.5V I/O supply
• 5V tolerant inputs except I/Os
Asynchronous inputs include the Output Enable (OE) and
Burst Mode Control (MODE). The data outputs (Q), enabled
by OE, are also asynchronous.
• Clamp diodes to V at all inputs and outputs
SS
• Common data inputs and data outputs
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or Address Status Controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance pin (ADV).
• Byte Write Enable and Global Write control
• Three chip enables for depth expansion and address
pipeline
• Address, data, and control registers
• Internally self-timed Write Cycle
• Burst control pins (interleaved or linear burst se-
quence)
• Automatic power-down for portable applications
• JTAG boundary scan
• JEDEC standard pinout
• Low profile 119-lead, 14-mm x 22-mm BGA (Ball Grid
Array) and 100-pin TQFP packages
Address, data inputs, and write controls are registered on-chip
to initiate self-timed Write cycle. Write cycles can be one to
four bytes wide as controlled by the write control inputs. Indi-
vidual byte write allows individual byte to be written. BWa con-
trols DQa. BWb controls DQb. BWc controls DQc. BWd con-
trols DQd. BWa, BWb, BWc, and BWd can be active only with
BWE being LOW. GW being LOW causes all bytes to be writ-
ten. The x18 version only has 18 data inputs/outputs (DQa and
DQb) along with BWa and BWb (no BWc, BWd, DQc, and
DQd).
Functional Description
Four pins are used to implement JTAG test capabilities: Test
Mode Select (TMS), Test Data-in (TDI), Test Clock (TCK), and
Test Data-out (TDO). The JTAG circuitry is used to serially shift
data to and from the device. JTAG inputs use LVTTL/LVCMOS
levels to shift data during this testing mode of operation.
The Cypress Synchronous Burst SRAM family employs
high-speed, low-power CMOS designs using advanced tri-
ple-layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high-valued
resistors.
The
CY7C1347C/GVT71128DA36
and
CY7C1327C/
GVT71256DA18 operate from a +3.3V power supply. All inputs
and outputs are LVTTL compatible
Selection Guide
7C1347C-250
7C1347C-225
71128DA36-4.4
7C1327C-225
71256DA18-4.4
7C1347C-200
71128DA36-5
7C1327C-200
71256DA18-5
7C1347C-166
71128DA36-6
7C1327C-166
71256DA18-6
71128DA36-4
7C1327C-250
71256DA18-4
Maximum Access Time (ns)
2.5
450
10
2.5
400
10
2.5
360
10
3.5
300
10
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
July 21, 2000
CY7C1347C/GVT71128DA36
CY7C1327C/GVT71256DA18
Functional Block Diagram—128Kx36[1]
BYTE a WRITE
BWa#
BWE#
D
Q
CLK
BYTE b WRITE
BWb#
D
Q
GW#
BYTE c WRITE
BWc#
D
Q
BYTE d WRITE
BWd#
D
Q
Q
CE#
CE2
ENABLE
D
D
Q
CE2#
OE#
ZZ
Power Down Logic
Input
Register
ADSP#
15
A
Address
Register
OUTPUT
REGISTER
ADSC#
DQa,DQb
DQc,DQd
CLR
D
Q
ADV#
A1-A0
MODE
Binary
Counter
& Logic
Functional Block Diagram—256Kx18[1]
BYTE b
WRITE
BWb#
BWE#
D
Q
BYTE a
WRITE
BWa#
GW#
D
Q
ENABLE
CE#
CE2
D
Q
D
Q
CE2#
ZZ
Power Down Logic
OE#
ADSP#
Input
Register
16
A
Address
Register
OUTPUT
REGISTER
ADSC#
DQa,DQb
CLR
D
Q
ADV#
A1-A0
MODE
Binary
Counter
& Logic
Note:
1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information.
2
CY7C1347C/GVT71128DA36
CY7C1327C/GVT71256DA18
Pin Configurations
100-Pin TQFP
Top View
DQc
DQc
DQc
NC
NC
NC
CCQ
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
DQb
DQb
DQb
A
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
V
V
V
CCQ
V
CCQ
CCQ
V
V
SS
SS
V
V
SS
SS
DQc
DQc
DQc
DQc
NC
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQb
DQb
9
9
V
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SS
V
SS
V
SS
SS
V
V
CCQ
DQc
DQc
CCQ
DQb
DQb
V
V
CCQ
CCQ
DQb
DQb
DQa
DQa
NC
NC
V
V
SS
SS
V
V
CC
CC
NC
NC
CY7C1347C/
GVT71128DA36
CY7C1327C/
GVT71256DA18
NC
NC
V
V
CC
CC
V
V
SS
ZZ
DQa
DQa
SS
ZZ
DQa
DQa
DQd
DQd
DQb
DQb
V
V
CCQ
CCQ
V
SS
DQb
DQb
DQb
V
V
CCQ
CCQ
V
SS
V
V
SS
SS
DQd
DQd
DQd
DQa
DQa
DQa
DQa
DQa
DQa
NC
DQd
NC
NC
V
V
SS
V
SS
V
SS
SS
V
V
CCQ
V
CCQ
NC
NC
NC
V
CCQ
CCQ
DQd
DQd
DQd
DQa
DQa
DQa
NC
NC
NC
3
CY7C1347C/GVT71128DA36
CY7C1327C/GVT71256DA18
Pin Configurations (continued)
119-Ball BGA
Top View
CY7C1347C/GVT71128DA36
1
2
3
A
A
A
4
5
A
A
A
6
7
A
B
C
D
E
F
V
A
ADSP
ADSC
A
V
CCQ
CCQ
NC
NC
CE2
A
CE2
A
NC
NC
V
CC
DQc
DQc
DQc
DQc
DQc
DQc
DQc
V
NC
CE
V
DQb
DQb
DQb
DQb
DQb
DQb
DQb
SS
SS
SS
SS
SS
SS
V
V
V
V
V
OE
V
CCQ
CCQ
G
H
J
DQc
BWc
ADV
GW
BWb
DQb
DQc
V
V
DQb
SS
SS
V
V
NC
V
NC
V
V
CCQ
CCQ
CC
CC
CC
K
L
DQd
DQd
DQd
DQd
DQd
DQd
A
V
CLK
NC
V
DQa
DQa
DQa
DQa
DQa
A
DQa
SS
SS
DQd
BWd
BWa
DQa
M
N
P
R
T
V
V
V
V
BWE
A1
V
V
V
V
CCQ
CCQ
SS
SS
SS
SS
SS
SS
DQd
DQa
DQd
A0
DQa
NC
ZZ
MODE
A
V
NC
A
CC
NC
NC
A
NC
U
V
TCK
V
CCQ
CCQ
256Kx18
1
2
3
A
A
A
4
5
A
A
A
6
7
A
B
C
D
E
F
V
A
ADSP
ADSC
A
V
CCQ
CCQ
NC
CE2
A
CE2
A
NC
NC
DQb
NC
V
NC
NC
CC
NC
DQb
NC
DQb
NC
V
NC
CE
V
V
V
V
V
DQa
NC
DQa
NC
DQa
SS
SS
SS
SS
SS
SS
SS
SS
V
V
DQa
V
OE
V
CCQ
CCQ
G
H
J
NC
BWb
ADV
GW
DQa
DQb
V
NC
SS
V
V
NC
V
NC
V
V
CCQ
CCQ
CC
CC
CC
K
L
NC
DQb
NC
DQb
NC
DQb
A
V
V
V
V
V
CLK
NC
V
NC
DQa
NC
DQa
NC
A
DQa
SS
SS
SS
SS
SS
SS
DQb
BWa
NC
M
N
P
R
T
V
BWE
A1
V
V
V
V
CCQ
CCQ
SS
SS
SS
DQb
NC
NC
A0
DQa
NC
ZZ
MODE
A
V
NC
A
CC
NC
A
NC
A
U
V
TCK
V
CCQ
CCQ
4
CY7C1347C/GVT71128DA36
CY7C1327C/GVT71256DA18
128K X 36 Pin Descriptions
X36 BGA Pins
X36 QFP Pins Name
Type
Description
4P
4N
37
36
A0
A1
A
Input-
Addresses: These inputs are registered and must meet the
Synchronous set-up and hold times around the rising edge of CLK. The burst
counter generates internal addresses associated with A0 and
A1, during burst cycle and wait cycle.
2A, 3A, 5A, 6A,
3B, 5B, 2C, 3C, 100, 99, 82, 81,
35, 34, 33, 32,
5C, 6C, 2R, 6R,
3T, 4T, 5T
44, 45, 46, 47,
48, 49, 50
5L
5G
3G
3L
93
94
95
96
BWa
BWb
BWc
BWd
Input-
Byte Write: A byte write is LOW for a Write cycle and HIGH for
Synchronous a Read cycle. BWa controls DQa. BWb controls DQb. BWc
controls DQc. BWd controls DQd. Data I/O are high impedance
if either of these inputs are LOW, conditioned by BWE being
LOW.
4M
4H
4K
87
88
89
BWE
GW
Input-
Write Enable: This active LOW input gates byte write opera-
Synchronous tions and must meet the set-up and hold times around the
rising edge of CLK.
Input-
Global Write: This active LOW input allows a full 36-bit Write
Synchronous to occur independent of the BWE and BWn lines and must
meet the set-up and hold times around the rising edge of CLK.
CLK
Input-
Clock: This signal registers the addresses, data, chip enables,
Synchronous write control and burst control inputs on its rising edge. All
synchronous inputs must meet set-up and hold times around
the clock’s rising edge.
4E
6B
98
92
CE
Input-
Chip Enable: This active LOW input is used to enable the
Synchronous device and to gate ADSP.
CE2
Input-
Chip Enable: This active LOW input is used to enable the
Synchronous device.
2U
3U
4U
38
39
43
TMS
TDI
TCK
Input
IEEE 1149.1 test inputs. LVTTL-level inputs.
5U
42
TDO
NC
Output
-
IEEE 1149.1 test output. LVTTL-level output.
1B, 7B, 1C, 7C,
4D, 3J, 5J, 4L,
1R, 5R, 7R, 1T,
2T, 6T, 6U
14, 16, 66
No Connect: These signals are not internally connected.
256K X 18 Pin Descriptions
X18 BGA Pins
X18 QFP Pins Name
Type
Description
4P
4N
37
36
A0
A1
A
Input-
Addresses: These inputs are registered and must meet the
Synchronous set-up and hold times around the rising edge of CLK. The burst
counter generates internal addresses associated with A0 and
A1, during burst cycle and wait cycle.
2A, 3A, 5A, 6A,
3B, 5B, 2C, 3C, 100, 99, 82, 81,
35, 34, 33, 32,
5C, 6C, 2R, 6R,
2T, 3T, 5T, 6T
80, 48, 47, 46,
45, 44, 49, 50
5L
3G
93
94
BWa
BWb
Input-
Byte Write Enables: A byte write enable is LOW for a Write
Synchronous cycle and HIGH for a Read cycle. BWa controls DQa. BWb
controls DQb. Data I/O are high impedance if either of these
inputs are LOW, conditioned by BWE being LOW.
4M
87
BWE
Input-
Write Enable: This active LOW input gates byte write opera-
Synchronous tions and must meet the setup and hold times around the rising
edge of CLK.
5
CY7C1347C/GVT71128DA36
CY7C1327C/GVT71256DA18
256K X 18 Pin Descriptions
X18 BGA Pins
X18 QFP Pins Name
Type
Description
4H
88
GW
Input-
Global Write: This active LOW input allows a full 18-bit Write
Synchronous to occur independent of the BWE and WEn lines and must
meet the set-up and hold times around the rising edge of CLK.
4K
89
CLK
Input-
Clock: This signal registers the addresses, data, chip enables,
Synchronous write control and burst control inputs on its rising edge. All
synchronous inputs must meet set-up and hold times around
the clock’s rising edge.
4E
6B
2B
4F
4G
98
92
97
86
83
CE
CE2
CE2
OE
Input-
Chip Enable: This active LOW input is used to enable the
Synchronous device and to gate ADSP.
Input-
Chip Enable: This active LOW input is used to enable the
Synchronous device.
input-
Chip enable: This active HIGH input is used to enable the
Synchronous device.
Input
Output Enable: This active LOW asynchronous input enables
the data output drivers.
ADV
Input-
Address Advance: This active LOW input is used to control the
Synchronous internal burst counter. A HIGH on this pin generates wait cycle
(no address advance).
4A
4B
84
85
ADSP
ADSC
Input-
Address Status Processor: This active LOW input, along with
Synchronous CE being LOW, causes a new external address to be registered
and a READ cycle is initiated using the new address.
Input-
Address Status Controller: This active LOW input causes de-
Synchronous vice to be de-selected or selected along with new external ad-
dress to be registered. A Read or Write cycle is initiated de-
pending upon write control inputs.
3R
31
MODE
Input-
Static
Mode: This input selects the burst sequence. A LOW on this
pin selects Linear Burst. A NC or HIGH on this pin selects
Interleaved Burst.
Burst Address Table (MODE = GND)
Burst Address Table (MODE = NC/V
)
CC
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
A...A00
A...A01
A...A10
A...A11
A...A01
A...A10
A...A11
A...A00
A...A10
A...A11
A...A00
A...A01
A...A11
A...A00
A...A01
A...A10
A...A00
A...A01
A...A10
A...A11
A...A01
A...A00
A...A11
A...A10
A...A10
A...A11
A...A00
A...A01
A...A11
A...A10
A...A01
A...A00
6
CY7C1347C/GVT71128DA36
CY7C1327C/GVT71256DA18
Truth Table[2, 3, 4, 5, 6, 7, 8]
Address
Used
Operation
CE CE2 CE2 ADSP ADSC
ADV
X
X
X
X
X
X
X
X
X
X
L
WRITE OE
CLK
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
DQ
High-Z
High-Z
High-Z
High-Z
High-Z
Q
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
READ Cycle, Begin Burst
None
None
H
L
X
X
H
X
H
L
X
L
X
L
L
X
X
L
X
X
X
X
X
X
X
L
X
X
X
X
X
L
None
L
X
L
L
None
L
H
H
L
None
L
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
External
External
External
External
External
Next
L
X
X
L
READ Cycle, Begin Burst
L
L
L
H
X
L
High-Z
D
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
L
L
H
H
H
H
H
H
L
Q
READ Cycle, Begin Burst
L
L
L
H
L
High-Z
Q
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Next
L
H
L
High-Z
Q
Next
L
Next
L
H
X
X
L
High-Z
D
Next
L
Next
L
L
D
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
Q
H
L
High-Z
Q
H
X
X
High-Z
D
L
D
Partial Truth Table for READ/WRITE[9]
FUNCTION
GW
H
BWE
BWa
BWb
BWc
X
BWd
READ
READ
H
L
L
L
X
X
H
L
X
H
H
L
X
H
H
L
H
H
WRITE one byte
WRITE all bytes
H
H
H
L
L
WRITE all bytes
L
X
X
X
X
Note:
2. X means “don’t care.” H means logic HIGH. L means logic LOW.
For X36 product, WRITE = L means [BWE + BWa*BWb*BWc*BWd]*GW equals LOW. WRITE = H means [BWE + BWa*BWb*BWc*BWd]*GW equals HIGH.
For X18 product, WRITE = L means [BWE + BWa*BWb]*GW equals LOW. WRITE = H means [BWE + BWa*BWb]*GW equals HIGH.
3. BWa enables write to DQa. BWb enables write to DQb. BWc enables write to DQc. BWd enables write to DQd.
4. All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK.
5. Suspending burst generates wait cycle.
6. For a write operation following a read operation, OE must be HIGH before the input data required set-up time plus High-Z time for OE and staying HIGH
throughout the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP LOW along with chip being selected always initiates a READ cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE LOW
for the CLK L-H edge of the subsequent wait cycle. Refer to WRITE timing diagram for clarification.
9. For X18 product, there are only BWa and BWb.
7
CY7C1347C/GVT71128DA36
CY7C1327C/GVT71256DA18
Performing a TAP Reset
IEEE 1149.1 Serial Boundary Scan (JTAG)
The TAP circuitry does not have a reset pin (TRST, which is
optional in the IEEE 1149.1 specification). A RESET can be
Overview
This device incorporates a serial boundary scan access port
(TAP). This port is designed to operate in a manner consistent
with IEEE Standard 1149.1-1990 (commonly referred to as
JTAG), but does not implement all of the functions required for
IEEE 1149.1 compliance. Certain functions have been modi-
fied or eliminated because their implementation places extra
delays in the critical speed path of the device. Nevertheless,
the device supports the standard TAP controller architecture
(the TAP controller is the state machine that controls the TAPs
operation) and can be expected to function in a manner that
does not conflict with the operation of devices with IEEE Stan-
dard 1149.1 compliant TAPs. The TAP operates using
LVTTL/LVCMOS logic level signaling.
performed for the TAP controller by forcing TMS HIGH (V
)
CC
for five rising edges of TCK and pre-loads the instruction reg-
ister with the IDCODE command. This type of reset does not
affect the operation of the system logic. The reset affects test
logic only.
At power-up, the TAP is reset internally to ensure that TDO is
in a High-Z state.
Test Access Port (TAP) Registers
Overview
The various TAP registers are selected (one at a time) via the
sequences of ones and zeros input to the TMS pin as the TCK
is strobed. Each of the TAPs registers are serial shift registers
that capture serial input data on the rising edge of TCK and
push serial data out on subsequent falling edge of TCK. When
a register is selected, it is connected between the TDI and
TDO pins.
Disabling the JTAG Feature
It is possible to use this device without using the JTAG feature.
To disable the TAP controller without interfering with normal
operation of the device, TCK should be tied LOW (V ) to pre-
SS
vent clocking the device. TDI and TMS are internally pulled up
and may be unconnected. They may alternately be pulled up
to VCC through a resistor. TDO should be left unconnected.
Upon power-up the device will come up in a reset state which
will not interfere with the operation of the device.
Instruction Register
The instruction register holds the instructions that are execut-
ed by the TAP controller when it is moved into the run test/idle
or the various data register states. The instructions are three
bits long. The register can be loaded when it is placed between
the TDI and TDO pins. The parallel outputs of the instruction
register are automatically preloaded with the IDCODE instruc-
tion upon power-up or whenever the controller is placed in the
test-logic reset state. When the TAP controller is in the Cap-
ture-IR state, the two least significant bits of the serial instruc-
tion register are loaded with a binary “01” pattern to allow for
fault isolation of the board-level serial test data path.
Test Access Port (TAP)
TCK - Test Clock (INPUT)
Clocks all TAP events. All inputs are captured on the rising
edge of TCK and all outputs propagate from the falling edge of
TCK.
TMS - Test Mode Select (INPUT)
The TMS input is sampled on the rising edge of TCK. This is
the command input for the TAP controller state machine. It is
allowable to leave this pin unconnected if the TAP is not used.
The pin is pulled up internally, resulting in a logic HIGH level.
Bypass Register
The bypass register is a single-bit register that can be placed
between TDI and TDO. It allows serial test data to be passed
through the device TAP to another device in the scan chain
with minimum delay. The bypass register is set LOW (V
when the BYPASS instruction is executed.
)
SS
TDI - Test Data In (INPUT)
The TDI input is sampled on the rising edge of TCK. This is the
input side of the serial registers placed between TDI and TDO.
The register placed between TDI and TDO is determined by
the state of the TAP controller state machine and the instruc-
tion that is currently loaded in the TAP instruction register (refer
to Figure 1, TAP Controller State Diagram). It is allowable to
leave this pin unconnected if it is not used in an application.
The pin is pulled up internally, resulting in a logic HIGH level.
TDI is connected to the most significant bit (MSB) of any reg-
ister. (See Figure 2.)
Boundary Scan Register
The Boundary scan register is connected to all the input and
bidirectional I/O pins (not counting the TAP pins) on the device.
This also includes a number of NC pins that are reserved for
future needs. There are a total of 70 bits for x36 device and 51
bits for x18 device. The boundary scan register, under the con-
trol of the TAP controller, is loaded with the contents of the
device I/O ring when the controller is in Capture-DR state and
then is placed between the TDI and TDO pins when the con-
troller is moved to Shift-DR state. The EXTEST, SAMPLE/
PRELOAD and SAMPLE-Z instructions can be used to cap-
ture the contents of the I/O ring.
TDO - Test Data Out (OUTPUT)
The TDO output pin is used to serially clock data-out from the
registers. The output that is active depending on the state of
the TAP state machine (refer to Figure 1, TAP Controller State
Diagram). Output changes in response to the falling edge of
TCK. This is the output side of the serial registers placed be-
tween TDI and TDO. TDO is connected to the least significant
bit (LSB) of any register. (See Figure 2.)
The Boundary Scan Order table describes the order in which
the bits are connected. The first column defines the bit’s posi-
tion in the boundary scan register. The MSB of the register is
connected to TDI, and LSB is connected to TDO. The second
column is the signal name and the third column is the bump
number. The third column is the TQFP pin number and the
fourth column is the BGA bump number.
8
CY7C1347C/GVT71128DA36
CY7C1327C/GVT71256DA18
Identification (ID) Register
ture-DR mode and places the ID register between the TDI and
TDO pins in Shift-DR mode. The IDCODE instruction is the
default instruction loaded in the instruction upon power-up and
at any time the TAP controller is placed in the test-logic reset
state.
The ID Register is a 32-bit register that is loaded with a device
and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the
instruction register. The register is then placed between the
TDI and TDO pins when the controller is moved into Shift-DR
state. Bit 0 in the register is the LSB and the first to reach TDO
when shifting begins. The code is loaded from a 32-bit on-chip
ROM. It describes various attributes of the device as described
in the Identification Register Definitions table.
SAMPLE-Z
If the High-Z instruction is loaded in the instruction register, all
output pins are forced to a High-Z state and the boundary scan
register is connected between TDI and TDO pins when the
TAP controller is in a Shift-DR state.
TAP Controller Instruction Set
SAMPLE/PRELOAD
Overview
SAMPLE/PRELOAD is an IEEE 1149.1 mandatory instruction.
The PRELOAD portion of the command is not implemented in
this device, so the device TAP controller is not fully IEEE
1149.1-compliant.
There are two classes of instructions defined in the IEEE Stan-
dard 1149.1-1990; the standard (public) instructions and de-
vice specific (private) instructions. Some public instructions
are mandatory for IEEE 1149.1 compliance. Optional public
instructions must be implemented in prescribed ways.
When the SAMPLE/PRELOAD instruction is loaded in the in-
struction register and the TAP controller is in the Capture-DR
state, a snap shot of the data in the device’s input and I/O
buffers is loaded into the boundary scan register. Because the
device system clock(s) are independent from the TAP clock
(TCK), it is possible for the TAP to attempt to capture the input
and I/O ring contents while the buffers are in transition (i.e., in
a metastable state). Although allowing the TAP to sample
metastable inputs will not harm the device, repeatable results
can not be expected. To guarantee that the boundary scan
register will capture the correct value of a signal, the device
input signals must be stabilized long enough to meet the TAP
Although the TAP controller in this device follows the IEEE
1149.1 conventions, it is not IEEE 1149.1 compliant because
some of the mandatory instructions are not fully implemented.
The TAP on this device may be used to monitor all input and
I/O pads, but can not be used to load address, data, or control
signals into the device or to preload the I/O buffers. In other
words, the device will not perform IEEE 1149.1 EXTEST, IN-
TEST, or the preload portion of the SAMPLE/PRELOAD com-
mand.
When the TAP controller is placed in Capture-IR state, the two
least significant bits of the instruction register are loaded with
01. When the controller is moved to the Shift-IR state the in-
struction is serially loaded through the TDI input (while the
previous contents are shifted out at TDO). For all instructions,
the TAP executes newly loaded instructions only when the con-
troller is moved to Update-IR state. The TAP instruction sets
for this device are listed in the following tables.
controller’s capture setup plus hold time (t
plus t ). The
CS
CH
device clock input(s) need not be paused for any other TAP
operation except capturing the input and I/O ring contents into
the boundary scan register.
Moving the controller to Shift-DR state then places the bound-
ary scan register between the TDI and TDO pins. Because the
PRELOAD portion of the command is not implemented in this
device, moving the controller to the Update-DR state with the
SAMPLE/PRELOAD instruction loaded in the instruction reg-
ister has the same effect as the Pause-DR command.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is
to be executed whenever the instruction register is loaded with
all 0s. EXTEST is not implemented in this device.
BYPASS
When the BYPASS instruction is loaded in the instruction reg-
ister and the TAP controller is in the Shift-DR state, the bypass
register is placed between TDI and TDO. This allows the board
level scan path to be shortened to facilitate testing of other
devices in the scan path.
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the device responds as if a SAMPLE/PRELOAD instruction
has been loaded. There is one difference between two instruc-
tions. Unlike SAMPLE/PRELOAD instruction, EXTEST places
the device outputs in a High-Z state.
Reserved
Do not use these instructions. They are reserved for future
use.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the ID register when the controller is in Cap-
9
CY7C1347C/GVT71128DA36
CY7C1327C/GVT71256DA18
TEST-LOGIC
RESET
1
0
0
1
1
1
REUN-TEST/
IDLE
SELECT
SELECT
DR-SCAN
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
EXIT1-DR
0
1
EXIT1-IR
0
1
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
1
0
0
[10]
Figure 1. TAP Controller State Diagram
Note:
10. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
10
CY7C1347C/GVT71128DA36
CY7C1327C/GVT71256DA18
0
Bypass Register
Selection
Circuitry
Selection
Circuitry
2
1
0
TDO
TDI
Instruction Register
29
Identification Register
31 30
.
.
2
1
1
0
0
.
x
.
.
.
2
[11]
Boundary Scan Register
TDI
TDI
TAP Controller
Figure 2. TAP Controller Block Diagram
TAP DC Electrical Characteristics (20°C < T < 110°C; V = 3.3V –0.2V and +0.3V unless otherwise noted)
j
CC
Parameter
Description
Test Conditions
Min.
2.0
Max.
+ 0.3
CC
Unit
[12, 13]
V
V
Input High (Logic 1) Voltage
V
V
IH
Il
[12, 13]
Input Low (Logic 0) Voltage
Input Leakage Current
–0.3
–5.0
–30
0.8
5.0
30
V
IL
0V < V < V
µA
µA
µA
I
IN
CC
CC
IL
TMS and TDI Input Leakage Current 0V < V < V
IN
I
IL
Output Leakage Current
Output disabled,
0V < V < V
–5.0
5.0
O
IN
CCQ
[12, 14]
[12, 14]
V
LVCMOS Output Low Voltage
I
I
I
I
= 100 µA
0.2
0.4
V
V
V
V
OLC
OLC
OHC
OLT
V
LVCMOS Output High Voltage
= 100 µA
= 8.0 mA
= 8.0 mA
V
– 0.2
CC
OHC
[12]
V
LVTTL Output Low Voltage
OLT
[12]
V
LVTTL Output High Voltage
2.4
OHT
OHT
Notes:
11. X = 69 for the x36 configuration. X = 50 for the x18 configuration.
12. All Voltage referenced to VSS (GND).
13. Overshoot: VIH(AC)<VCC+1.5V for t<tKHKH/2, Undershoot: VIL(AC)<–0.5V for t<tKHKH/2, Power-up: VIH<3.6V and VCC<3.135V and VCCQ<1.4V for t<200 ms.
During normal operation, VCCQ must not exceed VCC. Control input signals (such as R/W, ADV/LD, etc.) may not have pulse widths less than tKHKL (min.).
14. This parameter is sampled.
11
CY7C1347C/GVT71128DA36
CY7C1327C/GVT71256DA18
[15, 16]
TAP AC Switching Characteristics Over the Operating Range
Parameter
Clock
Description
Min.
Max
Unit
t
f
t
t
Clock Cycle Time
Clock Frequency
Clock HIGH Time
Clock LOW Time
20
ns
MHz
ns
THTH
TF
50
8
8
THTL
TLTH
ns
Output Times
t
t
t
t
TCK LOW to TDO Unknown
TCK LOW to TDO Valid
TDI Valid to TCK HIGH
TCK HIGH to TDI Invalid
0
ns
ns
ns
ns
TLQX
TLQV
DVTH
THDX
10
5
5
Set-up Times
t
TMS Set-up
5
5
ns
ns
MVTH
t
Capture Set-up
CS
Hold Times
t
t
TMS Hold
5
5
ns
ns
THMX
Capture Hold
CH
Notes:
15. CS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
16. Test conditions are specified using the load in TAP AC Test Conditions.
t
12
CY7C1347C/GVT71128DA36
CY7C1327C/GVT71256DA18
TAP Timing and Test Conditions
ALL INPUT PULSES
TDO
3.0V
1.5V
Z0 = 50
Ω
50Ω
20 pF
VSS
1.5 ns
1.5 ns
Vt = 1.5V
(a)
13
CY7C1347C/GVT71128DA36
CY7C1327C/GVT71256DA18
Identification Register Definitions
Instruction Field
512K x 18
Description
REVISION NUMBER
(31:28)
XXXX
Reserved for revision number.
DEVICE DEPTH
(27:23)
00111
00011
Defines depth of words.
Defines width of bits.
Reserved for future use.
DEVICE WIDTH
(22:18)
RESERVED
(17:12)
XXXXXX
CYPRESS JEDEC ID CODE (11:1)
00011100100
1
Allows unique identification of DEVICE vendor.
Indicates the presence of an ID register.
ID Register Presence
Indicator (0)
Scan Register Sizes
Register Name
Instruction
Bit Size (x18)
3
1
Bypass
ID
32
51
Boundary Scan
Instruction Codes
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. Forces all device outputs to High-Z state. This instruction is not
IEEE 1149.1-compliant.
IDCODE
001
010
Preloads ID register with vendor ID code and places it between TDI and
TDO. This instruction does not affect device operations.
SAMPLE-Z
Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. Forces all device outputs to High-Z state.
RESERVED
011
100
Do not use these instructions; they are reserved for future use.
SAMPLE/PRELOAD
Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. This instruction does not affect device operations. This instruction
does not implement IEEE 1149.1 PRELOAD function and is therefore not
1149.1-compliant.
RESERVED
RESERVED
BYPASS
101
110
111
Do not use these instructions; they are reserved for future use.
Do not use these instructions; they are reserved for future use.
Places the bypass register between TDI and TDO. This instruction does not
affect device operations.
14
CY7C1347C/GVT71128DA36
CY7C1327C/GVT71256DA18
Boundary Scan Order (128K x 36)
Boundary Scan Order (128K x 36)
Bit#
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
Signal Name
CE
TQFP
92
93
94
95
96
97
98
99
100
1
Bump ID
6B
5L
Bit#
1
Signal Name
A
TQFP
44
45
46
47
48
49
50
51
52
53
56
57
58
59
62
63
64
68
69
72
73
74
75
78
79
80
81
82
83
84
85
86
87
88
89
Bump ID
2R
3T
2
BWa
BWb
BWc
BWd
2
A
5G
3G
3L
3
A
4T
4
A
5T
5
A
6R
3B
5B
6P
7N
6M
7L
CE
2B
4E
3A
2A
2D
1E
2F
6
A
2
CE
A
7
A
8
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
ZZ
A
9
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
2
3
6K
7P
6N
6L
6
1G
2H
1D
2E
2G
1H
5R
2K
1L
7
8
9
7K
7T
12
13
14
18
19
22
23
24
25
28
29
30
31
32
33
34
35
36
37
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
A
6H
7G
6F
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
MODE
A
7E
6D
7H
6G
6E
7D
6A
5A
4G
4A
4B
4F
2M
1N
2P
1K
2L
2N
1P
3R
2C
3C
5C
6C
4N
4P
A
ADV
ADSP
ADSC
OE
A
A
A
BWE
GW
CLK
4M
4H
4K
A1
A0
15
CY7C1347C/GVT71128DA36
CY7C1327C/GVT71256DA18
Boundary Scan Order (256K x 18)
Boundary Scan Order (256K x 18)
Signal
Name
Signal
Bit#
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
TQFP
99
100
8
Bump ID
3A
Bit#
1
Name
TQFP
44
45
46
47
48
49
50
58
59
62
63
64
68
69
72
73
74
80
81
82
83
84
85
86
87
88
89
92
93
94
97
98
Bump ID
2R
2T
A
A
A
2A
2
A
DQb
DQb
DQb
DQb
NC
1D
2E
3
A
3T
9
4
A
5T
12
13
14
18
19
22
23
24
31
32
33
34
35
36
37
2G
1H
5R
2K
5
A
6R
3B
5B
7P
6N
6L
6
A
7
A
DQb
DQb
DQb
DQb
DQb
MODE
A
8
DQa
DQa
DQa
DQa
ZZ
1L
9
2M
1N
2P
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
7K
7T
3R
2C
3C
5C
6C
4N
4P
DQa
DQa
DQa
DQa
DQa
A
6H
7G
6F
A
A
7E
6D
6T
A
A1
A0
A
6A
5A
4G
4A
4B
4F
A
Maximum Ratings
ADV
ADSP
ADSC
OE
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Voltage on V Supply Relative to V ..........–0.5V to +4.6V
CC
SS
V
.......................................................... –0.5V to V +0.5V
CC
IN
Storage Temperature (plastic) ...................... –55°C to +150°
Junction Temperature .................................................. +150°
Power Dissipation.......................................................... 1.0W
Short Circuit Output Current........................................ 50 mA
BWE
GW
CLK
CE2
BWa
BWb
CE2
CE
4M
4H
4K
6B
5L
Operating Range
3G
2B
4E
Ambient
Temperature
[17]
Range
Com’l
V
DD
0°C to +70°C
3.3V −5%/+10%
Note:
17.
TA is the case temperature.
16
CY7C1347C/GVT71128DA36
CY7C1327C/GVT71256DA18
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Data Inputs (DQx)
All Other Inputs
Min.
2.0
Max.
V +0.3
CC
Unit
V
[12, 18]
V
Input High (Logic 1) Voltage
IHD
IH
Il
V
V
2.0
4.6
V
[12, 18]
Input Low (Logic 0) Voltage
Input Leakage Current
–0.5
–5
0.8
5
V
IL
0V < V < V
µA
µA
I
IN
CC
IL
MODE and ZZ Input Leakage
0V < V < V
–30
30
I
IN
CC
[19]
Current
IL
Output Leakage Current
Output(s) disabled, 0V < V
< V
CC
–5
5
µA
V
O
OUT
[12]
V
Output High Voltage
I
I
= –5.0 mA
2.4
OH
OH
OL
[12]
V
Output Low Voltage
= 8.0 mA
0.4
3.6
V
OL
[12]
VCC
Supply Voltage
3.135
3.135
V
[12]
VCCQ
I/O Supply Voltage
V
V
CC
Parameter
Description
Conditions
Device selected; all inputs < V or > V ;
Typ.
-4
-4.4
-5
-6
Unit
I
I
I
I
Power Supply
Current:
150
450
400
360
300
mA
CC
IL
IH
cycle time > t min.; V = Max.;
KC
CC
[20, 21, 22]
Operating
outputs open
[21, 22]
CMOS Standby
Device deselected; V = Max.;
5
10
10
10
10
20
90
mA
mA
mA
SB2
SB3
SB4
CC
all inputs < V + 0.2 or >V – 0.2;
SS
CC
all inputs static; CLK frequency = 0
[21, 22]
TTL Standby
Device deselected; all inputs < V
10
40
20
20
20
IL
or > V ; all inputs static;
IH
V
= Max.; CLK frequency = 0
CC
[21, 22]
Clock Running
Device deselected;
all inputs < V or > V ; V = Max.;
140
125
110
IL
IH CC
CLK cycle time > t min.
KC
Capacitance[14]
Parameter
Description
Test Conditions
Typ.
Max.
Unit
C
C
Input Capacitance
T = 25°C, f = 1 MHz,
5
7
7
8
pF
pF
I
A
V
= 3.3V
CC
Input/Output Capacitance (DQ)
O
Thermal Resistance
Description
Test Conditions
Symbol
TQFP Typ.
Unit
Thermal Resistance (Junction to Ambient) Still Air, soldered on a 4.25 x 1.125 inch,
Θ
25
9
°C/W
°C/W
JA
JC
4-layer PCB
Thermal Resistance (Junction to Case)
Θ
Notes:
18. Overshoot: VIH ≤ +6.0V for t ≤ tKC /2.
Undershoot:VIL ≤ –2.0V for t ≤ tKC /2.
19. Output loading is specified with CL = 5 pF as in AC Test Loads.
20. ICC is given with no output current. ICC increases with greater output loading and faster cycle times.
21. “Device Deselected” means the device is in Power-Down mode as defined in the truth table. “Device Selected” means the device is active.
22. Typical values are measured at 3.3V, 25°C, and 20-ns cycle time.
17
CY7C1347C/GVT71128DA36
CY7C1327C/GVT71256DA18
AC Test Loads and Waveforms
317
Ω
3.3V
DQ
DQ
ALL INPUT PULSES
3.0V
0V
90%
10%
Z =50
Ω
90%
0
10%
1.5 ns
50
Ω
5 pF
351
Ω
1.5 ns
≤
≤
V = 1.5V
t
(c)
(a)
(b)
[23]
Switching Characteristics Over the Operating Range
-4
250 MHz
-4.4
225 MHz
-5
200 MHz
-6
166 MHz
Parameter
Clock
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
t
t
t
Clock Cycle Time
4.0
1.6
1.6
4.4
1.7
1.7
5.0
2.0
2.0
6.0
2.4
2.4
ns
ns
ns
KC
KH
KL
Clock HIGH Time
Clock LOW Time
Output Times
t
t
t
t
t
t
t
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
2.5
2.5
2.5
3.5
ns
ns
ns
ns
ns
ns
ns
KQ
1.25
0
1.25
0
1.25
0
1.25
0
KQX
[14, 19, 24]
[14, 19, 24]
KQLZ
KQHZ
OEQ
OELZ
OEHZ
Clock to Output in High-Z
1.25
3.0
2.5
1.25
3.0
2.5
1.25
3.0
2.5
1.25
4.0
3.5
[25]
OE to Output Valid
[14, 19, 24]
OE to Output in Low-Z
OE to Output in High-Z
0
0
0
0
[14, 19, 24]
2.5
2.5
2.5
3.5
Set-up Times
[26]
[26]
t
Address, Controls, and Data In
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
ns
ns
S
Hold Times
t
Address, Controls, and Data In
H
Typical Output Buffer Characteristics
Output High Voltage
(V)
Pull-Up Current
Output Low Voltage
(V)
Pull-Down Current
V
I
(mA) Min.
I
(mA) Max.
–105
–105
–105
–83
V
I
(mA) Min.
I (mA) Max.
OL
OH
OH
OH
OL
OL
–0.5
0
–38
–38
–38
–26
–20
0
–0.5
0
0
0
0
0
0.8
1.25
1.5
2.3
2.7
2.9
3.4
0.4
0.8
1.25
1.6
2.8
3.2
3.4
10
20
31
40
40
40
40
20
40
63
80
80
80
80
–70
–30
0
–10
0
0
0
0
Notes:
23. Test conditions as specified with the output loading as shown in part (a) of AC Test Loads unless otherwise noted.
24. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tOELZ
.
25. OE is a “don’t care” when a byte write enable is sampled LOW.
26. This is a synchronous device. All synchronous inputs must meet specified set-up and hold time, except for “don’t care” as defined in the truth table.
18
CY7C1347C/GVT71128DA36
CY7C1327C/GVT71256DA18
Switching Waveforms
[27, 28]
Read Timing
tKC
tKL
CLK
tKH
tS
ADSP#
tH
ADSC#
tS
ADDRESS
A1
A2
tH
BWa#, BWb#,
BWc#, BWd#,
BWE#, GW#
tS
CE#
ADV#
OE#
DQ
tS
tH
tKQ
tKQ
tOEQ
tOELZ
tKQLZ
Q(A1)
Q(A2)
Q(A2+1)
Q(A2+2)
Q(A2+3)
Q(A2)
Q(A2+1)
SINGLE READ
BURST READ
Notes:
27. CE active in this timing diagram means that all chip enables CE, CE2, and CE2 are active.
28. For X18 product, there are only BWa and BWb for byte write control.
19
CY7C1347C/GVT71128DA36
CY7C1327C/GVT71256DA18
Switching Waveforms (continued)
[27, 28]
Write Timing
CLK
tS
ADSP#
tH
ADSC#
tS
A1
A2
A3
ADDRESS
tH
BWa#, BWb#,
BWc#, BWd#,
BWE#, GW#
GW#
CE#
tS
ADV#
OE#
DQ
tH
tOEHZ
tKQX
Q
D(A1)
D(A2)
D(A2+1)
D(A2+1)
D(A2+2)
D(A2+3)
D(A3)
D(A3+1)
D(A3+2)
SINGLE WRITE
BURST WRITE
BURST WRITE
20
CY7C1347C/GVT71128DA36
CY7C1327C/GVT71256DA18
Switching Waveforms (continued)
[27, 28]
Read/Write Timing
CLK
tS
ADSP#
tH
ADSC#
tS
ADDRESS
A2
A3
A4
A5
A1
tH
BWa#, BWb#,
BWc#, BWd#,
BWE#, GW#
CE#
ADV#
OE#
DQ
Q(A1)
Q(A2)
D(A3)
Q(A4)
Q(A4+1)
Q(A4+2)
D(A5)
D(A5+1)
Single Reads
Single Write
Burst Read
Burst Write
21
CY7C1347C/GVT71128DA36
CY7C1327C/GVT71256DA18
Ordering Information
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
Package Type
250
CY7C1347C-250AC/
GVT71128DA36T-4
A101
BG119
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
Commercial
CY7C1347C-250BGC/
GVT71128DA36B-4
119-Lead FBGA (14 x 22 x 2.4 mm)
225
200
166
250
225
200
166
CY7C1347C-225AC/
GVT71128DA36T-4.4
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead FBGA (14 x 22 x 2.4 mm)
CY7C1347C-225BGC/
GVT71128DA36B-4.4
BG119
A101
CY7C1347C-200AC/
GVT71128DA36T-5
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead FBGA (14 x 22 x 2.4 mm)
CY7C1347C-200BGC/
GVT71128DA36B-5
BG119
A101
CY7C1347C-166AC/
GVT71128DA36T-6
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead FBGA (14 x 22 x 2.4 mm)
CY7C1347C-16BGC/
GVT71128DA36B-6
BG119
A101
CY7C1327C-250AC/
GVT71256DA18T-4
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead FBGA (14 x 22 x 2.4 mm)
Commercial
CY7C1327C-250BGC/
GVT71256DA18B-4
BG119
A101
CY7C1327C-225AC/
GVT71256DA18T-4.4
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead FBGA (14 x 22 x 2.4 mm)
CY7C1327C-225BGC/
GVT71256DA18B-4.4
BG119
A101
CY7C1327C-200AC/
GVT71256DA18T-5
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead FBGA (14 x 22 x 2.4 mm)
CY7C1327C-200BGC/
GVT71256DA18B-5
BG119
A101
CY7C1327C-166AC/
GVT71256DA18T-6
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead FBGA (14 x 22 x 2.4 mm)
CY7C1327C-16BGC/
GVT71256DA18B-6
BG119
Document #: 38-01000
22
CY7C1347C/GVT71128DA36
CY7C1327C/GVT71256DA18
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
23
CY7C1347C/GVT71128DA36
CY7C1327C/GVT71256DA18
Package Diagrams (continued)
119-Lead FBGA (14 x 22 x 2.4 mm) BG119
51-85115
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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