CY7C1334-100AC [ETC]
x32 Fast Synchronous SRAM ; X32高速同步SRAM\n
| 型号： | CY7C1334-100AC |
| 厂家： | 
ETC |
| 描述： | x32 Fast Synchronous SRAM
|
| 文件： | 总12页 (文件大小：194K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
334
CY7C1334
64Kx32 Pipelined SRAM with NoBL™ Architecture
• Low (16.5 mW) standby power
Features
Functional Description
• Pin compatible and functionally equivalent to ZBT™
device MT55L64L32P
The CY7C1334 is a 3.3V, 64K by 32 synchronous-pipelined
Burst SRAM designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
wait states. The CY7C1334 is equipped with the advanced No
Bus Latency™ (NoBL™) logic required to enable consecutive
Read/Write operations with data being transferred on every
clock cycle. This feature dramatically improves the throughput
of the SRAM, especially in systems that require frequent
Write-Read transitions.The CY7C1334 is pin/functionally com-
patible to ZBT SRAM MT55L64L32P
• Supports 133-MHz bus operations with zero wait states
— Data is transferred on every clock
• Internally self-timed output buffer control to eliminate
the need to use OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write Capability
• 64K x 32 common I/O architecture
• Single 3.3V power supply
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal, which
when deasserted suspends operation and extends the previ-
ous clock cycle. Maximum access delay from the clock rise is
4.2 ns (133-MHz device).
• Fast clock-to-output times
— 4.2 ns (for 133-MHz device)
— 5.0 ns (for 100-MHz device)
— 7.0 ns (for 80-MHz device)
Write operations are controlled by the four Byte Write Selects
(BWS[0-3]) and a Write Enable (WE) input. All writes are con-
ducted with on-chip synchronous self-timed write circuitry.
— 10.0 ns (for 50-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Asynchronous output enable
• JEDEC-standard 100-pin TQFP package
• Burst Capability—linear or interleaved burst order
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
Logic Block Diagram
32
D
CLK
Data-In REG.
CE
Q
32
ADV/LD
16
A[15:0]
CEN
CE
CE
CONTROL
and WRITE
LOGIC
32
32
64KX
MEMORY
ARRAY
1
2
DQ[31:0]
CE
16
3
32
WE
BWS
[3:0]
OE
.
Selection Guide
7C1334-133
7C1334-100
7C1334-80
7.0
7C1334-50
Maximum Access Time (ns)
4.2
400
5.0
5.0
360
5.0
10
260
5.0
Maximum Operating Current (mA)
Commercial
Commercial
310
Maximum CMOS Standby Current (mA)
5.0
No Bus Latency and NoBL are trademarks of Cypress Semiconductor.
ZBT is a trademark of Integrated Device Technology.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05065 Rev. **
Revised August 20, 2001
CY7C1334
Pin Configuration
100-Pin TQFP
NC
NC
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQ
16
2
DQ
15
DQ
V
17
3
DQ
V
14
DDQ
4
DDQ
SSQ
V
V
SSQ
5
DQ
18
19
20
21
6
DQ
DQ
DQ
DQ
V
13
12
11
10
DQ
DQ
DQ
V
7
8
9
SSQ
DDQ
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SSQ
DDQ
V
V
DQ
DQ
DQ
DQ
V
22
23
9
8
CY7C1334
V
DDQ
SS
DD
DD
V
V
V
DD
V
DD
V
NC
SS
DQ
DQ
V
24
25
DQ
DQ
V
7
6
DDQ
DDQ
SSQ
V
V
SSQ
DQ
DQ
DQ
DQ
DQ
V
26
27
28
29
5
4
3
2
DQ
DQ
DQ
V
SSQ
DDQ
SSQ
DDQ
V
V
DQ
DQ
DQ
DQ
NC
30
31
1
0
NC
Document #: 38-05065 Rev. **
Page 2 of 12
CY7C1334
Pin Definitions
Pin Number
Name
I/O
Description
Address Inputs used to select one of the 65,536 address locations. Sampled at the
49−44,
A[15:0]
Input-
81–82, 99,
100, 32–37
Synchronous rising edge of the CLK.
96–93
BWS[3:0]
Input-
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the
Synchronous SRAM. Sampled on the rising edge of CLK. BWS0 controls DQ[7:0], BWS1 controls
DQ[15:8], BWS2 controls DQ[23:16], BWS0 controls DQ[31:24]
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active
Synchronous LOW. This signal must be asserted LOW to initiate a write sequence.
Input- Advance/Load input used to advance the on-chip address counter or load a new
.
88
85
WE
Input-
ADV/LD
Synchronous address. When HIGH (and CEN is asserted LOW) the internal burst counter is
advanced. When LOW, a new address can be loaded into the device for an access.
After being deselected, ADV/LD should be driven LOW in order to load a new
address.
89
98
97
92
86
CLK
CE1
CE2
CE3
OE
Input-Clock
Clock input. Used to capture all synchronous inputs to the device. CLK is qualified
with CEN. CLK is only recognized if CEN is active LOW.
Input-
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE2 and CE3 to select/deselect the device.
Input- Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE1 and CE3 to select/deselect the device.
Input- Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE1 and CE2 to select/deselect the device.
Input- Output Enable, active LOW. Combined with the synchronous logic block inside the
Asynchronous device to control the direction of the I/O pins. When LOW, the I/O pins are allowed
to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act
as input data pins. OE is masked during the data portion of a write sequence,
during the first clock when emerging from a deselected state, and when the device
has been deselected.
87
CEN
Input-
Clock Enable Input, active LOW. When asserted LOW the clock signal is recog-
Synchronous nized by the SRAM. When deasserted HIGH the clock signal is masked. Since the
deasserting CEN does not deselect the device, CEN can be used to extend the
previous cycle when required.
29–28,
25–22,
19–18,
13–12, 9–6,
3–2, 79–78,
75–72,
69–68, 63–62
59–56, 53–52
DQ[31:0]
I/O-
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that
Synchronous is triggered by the rising edge of CLK. As outputs, they deliver the data contained
in the memory location specified by A[15:0] during the previous clock rise of the
read cycle. The direction of the pins is controlled by OE and the internal control
logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH,
DQ[31:0] are placed in a three-state condition. The outputs are automatically
three-stated during the data portion of a write sequence, during the first clock when
emerging from a deselected state, and when the device is deselected, regardless
of the state of OE.
31
Mode
Input
Strap Pin
ModeInput. Selectstheburstorder ofthedevice. TiedHIGHselectstheinterleaved
burst order. Pulled LOW selects the linear burst order. Mode should not change
statesduringoperation. WhenleftfloatingModewilldefaultHIGH, toaninterleaved
burst order.
15, 16, 41, 65, VDD
66, 91
Power Supply Power supply inputs to the core of the device. Should be connected to 3.3V power
supply.
17, 40, 67, 90 VSS
Ground
Ground for the core of the device. Should be connected to ground of the system.
Power supply for the I/O circuitry. Should be connected to a 3.3V power supply.
4, 11, 14, 20, VDDQ
27, 54, 61, 70,
77
I/O Power
Supply
5, 10, 21, 26, VSSQ
55, 60, 71, 76
I/O Ground
-
Ground for the I/O circuitry. Should be connected to ground of the system.
No Connect. Reserved for drive strength control input.
Page 3 of 12
64
NC
Document #: 38-05065 Rev. **
CY7C1334
Pin Definitions (continued)
Pin Number
Name
NC
I/O
Description
50, 83, 84
-
No connects. Reserved for address inputs for depth expansion. Pins 50, 83, and
84 will be used for 128K, 256K, and 512K depths respectively.
1, 30, 51, 80
NC
-
-
No connects. Reserved for parity I/O signals on x36 devices. These inputs are not
connected to the device.
38, 39, 42, 43 DNU
Do Not Use pins. These pins should be left floating or tied to VSS.
Burst Read Accesses
Introduction
The CY7C1334 has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new address into the
SRAM, as described in the Single Read Access section above.
The sequence of the burst counter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap-around when incremented sufficiently. A HIGH input on
ADV/LD will increment the internal burst counter regardless of
the state of chip enables inputs or WE. WE is latched at the
beginning of a burst cycle. Therefore, the type of access (Read
or Write) is maintained throughout the burst sequence.
Functional Overview
The CY7C1334 is a synchronous-pipelined Burst SRAM de-
signed specifically to eliminate wait states during Write-Read
transitions. All synchronous inputs pass through input regis-
ters controlled by the rising edge of the clock. The clock signal
is qualified with the Clock Enable input signal (CEN). If CEN is
HIGH, the clock signal is not recognized and all internal states
are maintained. All synchronous operations are qualified with
CEN. All data outputs pass through output registers controlled
by the rising edge of the clock. Maximum access delay from
the clock rise (tCO) is 4.2 ns (133-MHz device).
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If clock
enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device will be latched. The access
can either be a read or write operation, depending on the sta-
tus of the Write Enable (WE). BWS[3:0] can be used to conduct
byte write operations.
Single Write Accesses
A write access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the write signal WE
is asserted LOW. The address presented to A0−A15 is loaded
into the Address Register. The write signals are latched into
the Control Logic block.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
On the subsequent clock rise the data lines are automatically
three-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ0–DQ31. In
addition, the address for the subsequent access (Read/
Write/Deselect) is latched into the Address Register (provided
the appropriate control signals are asserted).
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been de-
selected in order to load a new address for the next operation.
Single Read Accesses
On the next clock rise the data presented to DQ0−DQ31 inputs
(or a subset for byte write operations, see Write Cycle Descrip-
tion table for details) is latched into the device and the write is
complete.
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the write enable input
signal WE is deasserted HIGH, and (4) ADV/LD is asserted
The data written during the Write operation is controlled by
BWS[3:0] signals. The CY7C1334 provides byte write capabil-
ity that is described in the Write Cycle Description table. As-
serting the Write Enable input (WE) with the selected Byte
Write Select (BWS[0:3]) input will selectively write to only the
desired bytes. Bytes not selected during a byte write operation
will remain unaltered. A Synchronous self-timed write mecha-
nism has been provided to simplify the write operations. Byte
write capability has been included in order to greatly simplify
Read/Modify/Write sequences, which can be reduced to sim-
ple byte write operations.
LOW. The address presented to the address inputs (A0−A15
)
is latched into the Address Register and presented to the
memory core and control logic. The control logic determines
that a read access is in progress and allows the requested
data to propagate to the input of the output register. At the
rising edge of the next clock the requested data is allowed to
propagate through the output register and onto the data bus
within 4.2 ns (133 MHz device) provided OE is active LOW.
After the first clock of the read access the output buffers are
controlled by OE and the internal control logic. OE must be
driven LOW in order for the device to drive out the requested
data. During the second clock, a subsequent operation
(Read/Write/Deselect) can be initiated. Deselecting the device
is also pipelined. Therefore, when the SRAM is deselected at
clock rise by one of the chip enable signals, its output will
three-state following the next clock rise.
Because the CY7C1334 is a common I/O device, data should
not be driven into the device while the outputs are active. The
Output Enable (OE) can be deasserted HIGH before present-
ing data to the DQ0−DQ31 inputs. Doing so will three-state the
output drivers. As a safety precaution, DQ0−DQ31 are auto-
matically three-stated during the data portion of a write cycle,
regardless of the state of OE.
Document #: 38-05065 Rev. **
Page 4 of 12
CY7C1334
Burst Write Accesses
dress, as described in the Single Write Access section above.
When ADV/LD is driven HIGH on the subsequent clock rise,
the chip enables (CE1, CE2, and CE3) and WE inputs are ig-
nored and the burst counter is incremented. The correct
BWS[3:0] inputs must be driven in each cycle of the burst write
in order to write the correct bytes of data.
The CY7C1334 has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Write operations without reasserting the address inputs.
ADV/LD must be driven LOW in order to load the initial ad-
Cycle Description Truth Table[1, 2, 3, 4, 6, 7]
Address
Used
ADV/
LD
Operation
CE
CEN
WE
BWSx
CLK
L-H
Comments
Deselected
External
1
0
L
X
X
I/Os three-state following next rec-
ognized clock.
Suspend
-
X
1
X
X
X
L-H
Clock ignored, all operations sus-
pended.
Begin Read
Begin Write
External
External
0
0
0
0
0
0
1
0
X
L-H
L-H
Address latched.
Valid
Address latched, data presented
two valid clocks later.
Burst Read
Operation
Internal
X
0
1
X
X
L-H
Burst Read operation. Previous
access was a Read operation. Ad-
dresses incremented internally in
conjunction with the state of Mode.
Burst Write
Operation
Internal
X
0
1
X
Valid
L-H
Burst Write operation. Previous
access was a Write operation. Ad-
dresses incremented internally in
conjunctionwiththestateofMode.
Bytes written are determined by
BWS[3:0]
.
Interleaved Burst Sequence
Linear Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
First
Address
Second
Address
Third
Address
Fourth
Address
Ax+1, Ax
Ax+1, Ax
Ax+1, Ax
Ax+1, Ax
Ax+1, Ax
Ax+1, Ax
Ax+1, Ax
Ax+1, Ax
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Notes:
1. X=”Don't Care”, 1=Logic HIGH, 0=Logic LOW, CE stands for ALL Chip Enables active.BWSx = 0 signifies at least one Byte Write Select is active, BWSx = Valid
signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BWS[3:0]. See Write Cycle Description table for details.
3. The DQ pins are controlled by the current cycle and the OE signal.
4. CEN=1 inserts wait states.
5. CEN=1 inserts wait states.
6. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
7. OE assumed LOW.
Document #: 38-05065 Rev. **
Page 5 of 12
CY7C1334
Write Cycle Description[8, 9]
Function
WE
1
BWS3
BWS2
BWS1
BWS0
Read
X
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
X
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
X
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
X
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Write - No bytes written
Write Byte 0 - DQ[7:0]
Write Byte 1 - DQ[15:8]
Write Bytes 1, 0
0
0
0
0
Write Byte 2 - DQ[23:16]
Write Bytes 2, 0
0
0
Write Bytes 2, 1
0
Write Bytes 2, 1, 0
Write Byte 3 - DQ[31:24]
Write Bytes 3, 0
0
0
0
Write Bytes 3, 1
0
Write Bytes 3, 1, 0
Write Bytes 3, 2
0
0
Write Bytes 3, 2, 0
Write Bytes 3, 2, 1
Write All Bytes
0
0
0
Current into Outputs (LOW) ........................................ 20 mA
Maximum Ratings
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current.................................................... >200 mA
Storage Temperature ..................................... −65°C to +150°C
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Operating Range
Ambient
Supply Voltage on VDD Relative to GND.........−0.5V to +4.6V
Range
Com’l
Temperature[11]
VDD/VDDQ
DC Voltage Applied to Outputs
in High Z State[10]....................................−0.5V to VDDQ + 0.5V
0°C to +70°C
3.3V ± 5%
DC Input Voltage[10]................................−0.5V to VDDQ + 0.5V
Notes:
8. X=”Don't Care”, 1=Logic HIGH, 0=Logic LOW.
9. Write is initiated by the combination of WE and BWSx.Bytes written are determined by BWS[3:0]. Bytes not selected during byte writes remain unaltered. All I/Os
are three-stated during byte writes.
10. Minimum voltage equals –2.0V for pulse durations less than 20 ns.
11. TA is the case temperature.
Document #: 38-05065 Rev. **
Page 6 of 12
CY7C1334
Electrical Characteristics Over the Operating Range
Parameter
VDD
Description
Test Conditions
Min.
3.135
3.135
2.4
Max.
3.465
3.465
Unit
V
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[10]
Input Load Current
Input Current of MODE
VDDQ
VOH
VOL
V
VDD = Min., IOH = −4.0 mA[12]
VDD = Min., IOL = 8.0 mA[12]
V
0.4
V
VIH
2.0
−0.3
−5
V
DD + 0.3V
V
VIL
0.8
5
V
IX
GND ≤ VI ≤ VDDQ
µA
µA
µA
−30
−5
30
5
IOZ
ICC
Output Leakage
Current
GND ≤ VI ≤ VDDQ, Output Disabled
VDD Operating Supply VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
12.5-ns cycle, 80 MHz
20.0-ns cycle, 50 MHz
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
12.5-ns cycle, 80 MHz
20.0-ns cycle, 50 MHz
All speed grades
400
360
310
260
60
mA
mA
mA
mA
mA
mA
mA
mA
mA
ISB1
Automatic CE
Power-Down
Current-TTL Inputs
Max. VDD, Device Deselected,
IN ≥ VIH or VIN ≤ VIL
V
50
f = fMAX = 1/tCYC
40
35
ISB2
Automatic CE
Power-Down
Max. VDD, Device Deselected,
IN ≤ 0.3V or VIN > VDDQ – 0.3V,
5.0
V
Current-CMOS Inputs f = 0
ISB3
Automatic CE
Power-Down
Current-CMOS Inputs f = fMAX = 1/tCYC
Max. VDD, Device Deselected, or 7.5-ns cycle, 133 MHz
50
40
30
25
mA
mA
mA
mA
VIN ≤ 0.3V or VIN > VDDQ – 0.3V
10-ns cycle, 100 MHz
12.5-ns cycle, 80 MHz
20-ns cycle, 50 MHz
Capacitance[13]
Parameter
Description
Input Capacitance
Test Conditions
Max.
Unit
CIN
TA = 25°C, f = 1 MHz,
VDD = 3.3V. VDDQ = 3.3V
4
4
4
pF
pF
pF
CCLK
CI/O
Clock Input Capacitance
Input/Output Capacitance
AC Test Loads and Waveforms
R=317Ω
3.3V
OUTPUT
[14]
OUTPUT
ALL INPUT PULSES
Z =50Ω
0
3.0V
R =50Ω
L
5 pF
R=351Ω
GND
V = 1.5V
L
INCLUDING
JIG AND
SCOPE
1334-2
(a)
(b)
Notes:
12. The load used for VOH and VOL testing is shown in figure (b) of the A/C test conditions.
13. Tested initially and after any design or process change that may affect these parameters.
14. A/C test conditions assume signal transition time of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading shown in (a)
of AC Test Loads.
Document #: 38-05065 Rev. **
Page 7 of 12
CY7C1334
Thermal Resistance
Description
Test Conditions
Symbol
TQFP Typ.
Units
Notes
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 4.25 x 1.125 inch,
4-layer printed circuit board
ΘJA
28
°C/W
13
Thermal Resistance
(Junction to Case)
ΘJC
4
°C/W
13
Switching Characteristics Over the Operating Range[14, 15, 16]
-133
-100
-80
-50
Parameter
tCYC
tCH
Description
Clock Cycle Time
Min. Max. Min. Max. Min. Max. Min. Max. Unit
7.5
2.2
2.2
10
3.5
3.5
12.5
4.0
20.0
6.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock HIGH
tCL
Clock LOW
4.0
6.0
tCO
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Address Set-Up Before CLK Rise
Address Hold After CLK Rise
CEN Set-Up Before CLK Rise
CEN Hold After CLK Rise
4.2
5.0
7.0
10.0
tDOH
tAS
1.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
1.7
0.5
2.0
0.5
1.5
1.5
1.5
2.2
0.5
2.2
0.5
2.2
0.5
2.2
0.5
2.0
0.5
2.2
0.5
1.5
1.5
1.5
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
1.5
1.5
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
1.5
1.5
1.5
tAH
tCENS
tCENH
tWES
tWEH
tALS
GW, BWS[3:0] Set-Up Before CLK Rise
GW, BWS[3:0] Hold After CLK Rise
ADV/LD Set-Up Before CLK Rise
ADV/LD Hold after CLK Rise
Data Input Set-Up Before CLK Rise
Data Input Hold After CLK Rise
Chip Enable Set-Up Before CLK Rise
Chip Enable Hold After CLK Rise
Clock to High-Z[13, 15, 16, 17]
tALH
tDS
tDH
tCES
tCEH
tCHZ
tCLZ
3.5
4.2
4.2
3.5
5.0
5.0
3.5
6.0
6.0
3.5
6.0
6.0
Clock to Low-Z[13, 15, 16, 17]
tEOHZ
tEOLZ
OE HIGH to Output High-Z[13, 15, 16, 17]
OE LOW to Output Low-Z[13, 15, 16, 17]
OE LOW to Output Valid[15]
1.0
1.0
1.0
1.0
tEOV
Notes:
15. tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with A/C test conditions shown in part (a) of AC Test Loads. Transition is measured ± 200 mV from steady-state
voltage.
16. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
17. This parameter is sampled and not 100% tested.
Document #: 38-05065 Rev. **
Page 8 of 12
CY7C1334
Switching Waveforms
Read/Write/Deselect Sequence
CLK
CEN
tCENH
tCENS
tCL
tCH
tCYC
tAH
tAS
WA2
WA5
RA1
RA3
RA4
RA6
ADDRESS
RA7
WE &
BWS[3:0]
tWS
tWH
CEN HIGH blocks
all synchronous inputs
tCEH
tCES
CE
tDH
tDS
tCHZ
tCHZ
tDOH
tCLZ
tDOH
D2
In
Data-
In/Out
Q4
Out
D5
In
Q1
Q3
Q6
Out
Q7
Out
Out
Out
Device
originally
tCO
deselected
The combination of WE & BWS[3:0] defines a write cycle (see Write Cycle Description table).
CE is the combination of CE1, CE2, and CE3. All chip enables need to be active in order to select
the device. Any chip enable can deselect the device. RAx stands for Read Address X, WAx stands for
Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. ADV/LD held LOW.
OE held LOW.
= UNDEFINED
= DON’T CARE
Document #: 38-05065 Rev. **
Page 9 of 12
CY7C1334
Switching Waveforms (continued)
Burst Sequences
CLK
tALH
tALS
ADV/LD
tCL
tCH
tCYC
tAH
tAS
RA1
WA2
ADDRESS
WE
RA3
tWS
tWH
tWS
tWH
BWS[3:0]
tCES
tCEH
CE
tCLZ
tCHZ
tDH
tDOH
Q1
tCLZ
Q3
Out
Data-
In/Out
Q1+2
Out
Q1+3
Out
D2
In
D2+2
In
D2+3
In
Q1+1
Out
D2+1
In
Out
Device
originally
deselected
tCO
tCO
tDS
The combination of WE & BWS[3:0] define a write cycle (see Write Cycle Description table).
CE is the combination of CE1, CE2, and CE3. All chip enables need to be active in order to select
the device. Any chip enable can deselect the device. RAx stands for Read Address X, WA stands for
Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. CEN held
LOW. During burst writes, byte writes can be conducted by asserting the appropriate BWS[3:0] input signals.
Burst order determined by the state of the Mode input. CEN held LOW. OE held LOW.
= UNDEFINED
= DON’T CARE
Document #: 38-05065 Rev. **
Page 10 of 12
CY7C1334
Switching Waveforms (continued)
OE Timing
OE
tEOV
tEOHZ
Three-State
tEOLZ
I/O’s
Ordering Information
Speed
Package
Name
Operating
Range
(MHz)
133
100
80
Ordering Code
Package Type
CY7C1334-133AC
CY7C1334-100AC
CY7C1334-80AC
CY7C1334-50AC
A101
A101
A101
A101
100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack
100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack
100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack
100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack
Commercial
Commercial
Commercial
Commercial
50
Package Diagram
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
Document #: 38-05065 Rev. **
Page 11 of 12
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1334
Document Title: CY7C1334 64K x 32 Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05065
Issue
ECN NO. Date
Orig. of
Change
REV.
Description of Change
**
107258
08/22/01
SZV
Change from Spec number: 38-00638 to 38-05065
Document #: 38-05065 Rev. **
Page 12 of 12
相关型号：
CY7C1334F-133AC
ZBT SRAM, 64KX32, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CYPRESS
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