DATA28_技术文档

NS7520 Overview

Figure 1 shows the NS7520 modules. Dashed lines indicate shared pins.

Debugger

PLL

JTAG Debug

Interface

NS7520

Reset

System

Clock

FIRQ

IRQ

ARM7TDMI

Watchdog

timer

2 timers

BBUS

D

M

A

D

M

A

D

M

A

D

M

A

3.3V

1.5V

Serial-A

Serial-B

4

Ethernet

controller

Power

level

interrupt

inputs

External

memory

controller

UART

SPI

UART

SPI

802.3

compliant

16 GPIO

Address bus

MII

Serial transceivers and other

devices

Memory

devices

Flash

SRAM

FP DRAM

SDRAM

Boot

config

Figure 1: NS7520 module overview

www.digi.com

ꢀ

1

Key Features

This table lists the key features of the NS7520.

CPU core

Integrated 10/100 Ethernet MAC

ꢀ

ARM7TDMI 32-bit RISC processor

32-bit internal bus

ꢀ

10/100 Mbps MII-based PHY interface

10 Mbps ENDEC interface

32-bit ARM and 16-bit Thumb mode

15 general purpose 32-bit registers

32-bit program counter (PC) and status register

Five supervisor modes, one user mode

TP-PMD and fiber-PMD device support

Full-duplex and half-duplex modes

Optional 4B/5B coding

Station, broadcast, and multicast address

detection

ꢀ

512-byte transmit FIFO, 2 Kbyte receive FIFO

Intelligent receive-side buffer selection

13-Channel DMA controller

Programmable Timers

ꢀ

Two channels dedicated to Ethernet transmit

and receive

ꢀ

Two independent timers (2μs–20.7 hours)

Watchdog timer (interrupt or reset on expiration)

Programmable bus monitor or timer

Four channels dedicated to two serial modules’

transmit and receive

Four channels for external peripherals. Only two

channels — either 3 and 5 or 4 and 6 — can be

configured at one time.

ꢀ

Three channels available for memory-to-memory

transfers

Flexible buffer management

General purpose I/O pins

Operating frequency

ꢀ

16 programmable GPIO interface pins

ꢀ

36, 46, or 55 MHz internal clock operation from

18.432 MHz crystal

4 pins programmable with level-sensitive

interrupt

ꢀ

f_MAX= 36, 46, or 55 (grade–dependent)

System clock source by external quartz crystal

or crystal oscillator, or clock signal

ꢀ

Programmable PLL, which allows a range of

operating frequencies from 10 to f_MAX

Maximum operating frequency from external

clock or using PLL multiplication f_MAX

2

ꢀ

NS7520 Datasheet 03/2006

Operating frequency

Serial ports

Bus interface

ꢀ

Two fully independent serial ports (UART, SPI)

ꢀ

Five independent programmable chip selects

with 256 Mb addressing per chip select

Digital phase lock loop (DPLL) for receive clock

extractions

ꢀ

Chip select support for SRAM, FP/EDO DRAM,

SDRAM, Flash, and EEPROM without external

glue

ꢀ

32-byte transmit/receive FIFOs

Internal programmable bit-rate generators

Bit rates 75–230400 in 16X mode

Bit rates 1200 bps–4 Mbps in 1X mode

ꢀ

8-, 16-, and 32-bit peripheral support

External address decoding and cycle termination

Dynamic bus sizing

Flexible baud rate generator, external clock for

synchronous operation

Internal DRAM/SDRAM controller with address

multiplexer and programmable refresh frequency

ꢀ

Receive-side character and buffer gap timers

Four receive-side data match detectors

ꢀ

Internal refresh controller (CAS before RAS)

Burst-mode support

0–63 wait states per chip select

Address pins that configurem chip operating

modes (see "NS7520 bootstrap initialization" on

page 22)

Power and Operating Voltages

ꢀ

500 mW maximum at 55 MHz (all outputs

switching)

418 mW maximum at 46 MHz (all outputs

switching)

291 mW maximum at 36 MHz (all outputs

switching)

ꢀ

3.3 V — I/O

1.5 V — Core

Operating frequency

The NS7520 is available in grades operating at three maximum operating frequencies: 36 MHz,

46 MHz, and 55 MHz. The operating frequency is set during bootstrap initialization, using pins

A[8:0]. These address pins load the PLL Settings register on powerup reset. A[8:7] determines IS

(charge pump current); A[6:5] determines FS (output divider), and A[4:0] defines ND (PLL

multiplier). Each bit in A[8:0] can be set individually. See the discussion of the PLL Settings register

in the NS7520 Hardware Reference for more information.

www.digi.com

ꢀ

3

Packaging and pinout

Table 1 provides the NS7520 packaging dimensions. Figure 2 shows the NS7520 pinout and

dimensions.

Symbol

Min

—

Nom

Max

1.4

A

—

A1

A2

b

0.35

—

0.40

0.45

0.95

0.55

—

0.45

0.50

D

13.0 BSC

11.2 BSC

13.0 BSC

11.2 BSC

0.8 BSC

0.1

D1

E

E1

e

aaa

Table 1: NS7520 packaging dimensions

4

ꢀ

NS7520 Datasheet 03/2006

Packaging and pinout

177 PFBGA

Figure 2: NS7520 pinout and dimensions

www.digi.com

ꢀ

5

Pinout detail tables

Each pinout table applies to a specific interface and contains the following information:

Signal

The pin name for each I/O signal. Some signals have multiple function modes and are identified

accordingly. The mode is configured through firmware using one or more configuration registers.

The pin number assignment for a specific I/O signal.

ꢀ

U next to the pin number indicates that the pin is a pullup resistor.

D next to the pin number indicates that the pin is a pulldown resistor.

No value next to the pin indicates that the pin has neither a pullup nor pulldown resistor.

See Figure 5, "Internal pullup characteristics," on page 24 and Figure 6, "Internal pulldown

characteristics," on page 25 for an illustration of the characteristics of these pins. Use the figures

to select the appropriate value of the complimentary resistor to drive the signal to the opposite

logic state. For those pins with no pullup or pulldown resistor, you must select the appropriate

value per your design requirements.

An underscore (bar) indicates that the pin is active low.

_

I/O

OD

The type of signal — input, output, or input/output.

The output drive strength of an output buffer. The NS7520 uses one of three drivers:

ꢀ

2 mA

4 mA

8 mA

Notes:

ꢀ

NO CONNECTas a pin description means do not connect to this pin.

The 177th pin (package ball) is for alignment of the package on the PCB.

System Bus interface

Symbol

I/O

OD

Description

BCLK

A6

0

8

Synchronous bus clock

External bus

ADDR27

ADDR26

External bus

ADDR25

ADDR24

ADDR23

ADDR22

ADDR21

Other

External bus

Addr bit 27

Addr bit 26

External bus

Other

CS0OE_

CS0WE_

N10 U

P10 U

I/O

4

Logical AND of CS0_ and OE_

Logical AND of CS_ and WE_

M10 U

R10 U

N9 U

I/O

4

Remainder of address bus (through ADDR0)

R9 U

M9 U

6

ꢀ

NS7520 Datasheet 03/2006

System Bus interface

Symbol

ADDR20

ADDR19

ADDR18

ADDR17

ADDR16

ADDR15

ADDR14

ADDR13

ADDR12

ADDR11

ADDR10

ADDR9

N8 U

P8 U

M7 U

R7 U

N7 U

R6 U

M6 U

P6 U

N6 U

M5 U

P5 U

N5 U

R4 U

R3 U

R2 U

M4 U

N4 U

R1 U

M3 U

N2 U

P1 U

N1

I/O

OD

4

Description

ADDR8

ADDR7

ADDR6

ADDR5

ADDR4

ADDR3

ADDR2

ADDR1

ADDR0

DATA31

DATA30

DATA29

DATA28

DATA27

DATA26

DATA25

DATA24

DATA23

DATA22

DATA21

DATA20

Data bus

M1

L3

L2

L4

L1

K3

K2

K1

J2

J3

J1

www.digi.com

ꢀ

7

System Bus interface

Symbol

DATA19

DATA18

DATA17

DATA16

DATA15

DATA14

DATA13

DATA12

DATA11

DATA10

DATA9

DATA8

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0

BE3_

H3

H4

H1

H2

G4

G1

G3

G2

F4

I/O

OD

4

2

4

Description

F2

F3

E1

E2

E3

D1

C1

B1

D4

D3

C2

D9

A9

C9

B9

A8

Byte enable D31:D24

Byte enable D23:D16

Byte enable D15:D08

Byte enable D07:D00

BE2_

BE1_

BE0_

TS_

DO NOT USE

Add an external 820 ohm pullup to 3.3 V.

TA_

D8 U

I/O

4

Data transfer acknowledge

Add an external 820 ohm pullup to 3.3 V.

TA_ is bidirectional. It is used in input mode to

terminate a memory cycle externally. It is used in

output mode for reference purposes only.

TEA_

C8 U

I/O

4

Data transfer error acknowledge

Add an external 820 ohm pullup to 3.3 V.

TEA_ is bidirectional. It is used in input mode to

terminate a memory cycle externally. It is used in

output mode for reference purposes only.

8

ꢀ

NS7520 Datasheet 03/2006

System Bus interface

Symbol

RW_

D6

D7

C7

B7

I/O

OD

Description

I/O

2

Transfer direction

BR_

NO CONNECT

BG_

BUSY_

System bus interface signal descriptions

Mnemonic

Signal

Description

BCLK

Bus clock

Provides the bus clock. All system bus interface signals are

referenced to the BCLK signal.

ADDR[27:0]

DATA[31:0]

Address bus

Data bus

Identifies the address of the peripheral being addressed by the

current bus master. The address bus is bi-directional.

Provides the data transfer path between the NS7520 and external

peripheral devices. The data bus is bi-directional.

Recommendation: Less than x32 (S)DRAM/SRAM memory

configurations. Unconnected data bus pins will float during memory

read cycles. Floating inputs can be a source of wasted power.

For other than x32 DRAM/SRAM configurations, the unused data

bus signals should be pulled up.

TS_

BE_

Transfer start

Byte enable

NO CONNECT

Identifies which 8-bit bytes of the 32-bit data bus are active during

any given system bus memory cycle. The BE_ signals are active low

and bi-directional.

TA_

Transfer acknowledge

Indicates the end of the current system bus memory cycle. This

signal is driven to 1 prior to

tri-stating its driver.

TA_ is bi-directional.

TEA_

Transfer error

acknowledge

Indicates an error termination or burst cycle termination:

ꢀ

In conjunction with TA_ to signal the end of a burst cycle.

ꢀ

Independently of TA_ to signal that an error occurred during the

current bus cycle. TEA_ terminates the current burst cycle.

This signal is driven to 1 prior to tri-stating its driver.

TEA_ is bi-directional. The NS7520 or the external peripheral can

drive this signal.

RW_

Read/write indicator

Indicates the direction of the system bus memory cycle. RW_ high

indicates a read operation; RW_ low indicates a write operation. The

RW_ signal is bi-directional.

BR_

Bus request

Bus grant

Bus busy

NO CONNECT

BG_

BUSY_

www.digi.com

ꢀ

9

Chip select controller

The NS7520 supports five unique chip select configurations.

Symbol

CS4_

B4

A4

C5

B5

D5

A1

C4

B3

A2

C6

B6

I/O

O

OD

4

Description

Chip select/DRAM RAS_

CS3_

O

4

Chip select/DRAM RAS_

CS2_

O

4

Chip select/DRAM RAS_

CS1_

O

4

Chip select/DRAM RAS_

CS0_

O

4

Chip select (boot select)

CAS3_

CAS2_

CAS1_

CAS0_

WE_

O

4

FP/EDO DRAM column strobe D31:D24/SDRAM RAS_

FP/EDO DRAM column strobe D23:D16/SDRAM CAS_

FP/EDO DRAM column strobe D15:D08/SDRAM WE_

FP/EDO DRAM column strobe D07:D00/SDRAM A10(AP)

Write enable for NCC Ctrl’d cycles

Output enable for NCC Ctrl’d cycles

O

4

O

4

O

4

O

4

OE_

O

4

Chip select controller signal descriptions

Mnemonic

Signal

Description

CS0_

CS1_

CS2_

CS3_

CS4_

Chip select 0

Chip select 1

Chip select 2

Chip select 3

Chip select 4

Unique chip select outputs supported by the NS7520. Each chip select

can be configured to decode a portion of the available address space

and can address a maximum of 256 Mbytes of address space. The

chip selects are configured using registers in the memory module.

A chip select signal is driven low to indicate the end of the current

memory cycle. For FP/EDO DRAM, these signals provide the RAS

signal.

CAS0_

CAS1_

CAS2_

CAS3_

Column address

strobe signals

Activated when an address is decoded by a chip select module

configured for DRAM mode. The CAS_ signals are active low and

provide the column address strobe function for DRAM devices.

The CAS_ signals also identify which 8-bit bytes of the 32-bit data bus

are active during any given system bus memory cycle.

For SDRAM, CAS[3:1]_ provides the SDRAM command field. CAS0_

provides the auto-precharge signal.

For non-DRAM settings, these signals are 1.

WE_

OE_

Write enable

Active low signal that indicates that a memory write cycle is in

progress. This signal is activated only during write cycles to

peripherals controlled by one of the chip selects in the memory

module.

Output enable

Active low signal that indicates that a memory read cycle is in

progress. This signal is activated only during read cycles from

peripherals controlled by one of the chip selects in the memory

module.

1 0

ꢀ

NS7520 Datasheet 03/2006

Ethernet interface MAC

Note:

ENDEC values for general-purpose output and TXD refer to bits in the Ethernet General

Control register. ENDEC values for general-purpose input and RXD refer to bits in the

Ethernet General Status register.

In this table, GP designates general-purpose.

Symbol

I/O

OD

Description

MII

ENDEC

MDC

GP output

D10

O

2

MII

State of (LPBK bit XOR

(Mode=SEEQ))

management

clock

MDIO

TXCLK

TXD3

TXD2

TXD1

GP output

B10 U

C10

A12

B11

I/O

I

2

MII data

State of UTP_STP bit

TX clock

TX data 3

TX data 2

TX data 1

GP output

O

2

State of AUI_TP[0] bit

State of AUI_TP[1] bit

D11

Inverted state of PDN bit, open

collector

TXD0

TXER

TXD

A11

A13

B12

A14

D12

C12

D14

B15

A15

B13

C15

D15

O

I

2

TX data 0

TX code error

TX enable

Collision

Transmit data

GP output

State of LNK_DIS_ bit

TXEN

TXCOL

RXCRS

RXCLK

RXD3

RXD2

RXD1

RXD0

RXER

I

Carrier sense

RX clock

I

GP input

RXD

I

RX data 3

RX data 2

RX data 1

RX data 0

RX error

Read state in bit 12

Read state in bit 15

Read state in bit 13

Receive data

I

GP input

I

Read state in bit 11

Read state in bit 10

RXDV

I

RX data valid

Ethernet interface MAC signal descriptions

The Ethernet MII (media independent interface) provides the connection between the Ethernet PHY

and the MAC (media access controller).

www.digi.com

ꢀ

11

Ethernet interface MAC

Mnemonic Signal

Description

MDC

MII management clock

Provides the clock for the MDIO serial data channel. The MDC signal

is an NS7520 output. The frequency is derived from the system

operating frequency per the CLKS field setting (see the CLKS field in

Table 69: "MII Management Configuration register bit definition" on

page 191).

MDIO

Management data IO

Transmit clock

A bi-directional signal that provides a serial data channel between the

NS7520 and the external Ethernet PHY module.

TXCLK

An input to the NS7520 from the external PHY module. TXCLK

provides the synchronous data clock for transmit data.

TXD3

TXD2

TXD1

TXD0

Transmit data signals

Nibble bus used by the NS7520 to drive data to the external Ethernet

PHY. All transmit data signals are synchronized to TXCLK.

In ENDEC mode, only TXD0 is used for transmit data.

TXER

TXEN

COL

Transmit coding error

Transmit enable

Output asserted by the NS7520 when an error has occurred in the

transmit data stream.

Asserted when the NS7520 drives valid data on the TXD outputs.

This signal is synchronized to TXCLK.

Transmit collision

Receive carrier sense

Receive clock

Input signal asserted by the external Ethernet PHY when a collision

is detected.

CRS

Asserted by the external Ethernet PHY whenever the receive medium

is non-idle.

RXCLK

An input to the NS7520 from the external PHY module. The receive

clock provides the synchronous data clock for receive data.

RXD3

RXD2

RXD1

RXD0

Receive data signals

Nibble bus used by the NS7520 to input receive data from the

external Ethernet PHY. All receive data signals are synchronized to

RXCLK.

In ENDEC mode, only RXD0 is used for receive data.

RXER

Receive error

Input asserted by the external Ethernet PHY when the Ethernet PHY

encounters invalid symbols from the network.

RXDV

Receive data valid

Input asserted by the external Ethernet PHY when the PHY drives

valid data on the RXD inputs.

1 2

ꢀ

NS7520 Datasheet 03/2006

“No connect” pins

R13

P12

N12

R15

M11

P11

N11

R12

R14

P13

Description

Tie to V_CC

XTALB1: Tie to V_CC

XTALB2: NO CONNECT

NO CONNECT

General Purpose I/O

GPIO signal Serial

signal

Other

signal

Serial channel

description

Other

description

I/O

OD

2

PORTA7

PORTA6

TXDA

J14 U I/O

J13 U I/O

Channel 1 TXD

Channel 1 DTR_

DTRA_

DREQ1_

2

DMA channel 3/5

Req

PORTA5

PORTA4

RTSA_

J15 U I/O

J12 U I/O

2

Channel 1 RTS_

RXCA/RIA_/

OUT1A_

Pgm’able Out/

Channel 1

RXCLK/ Channel

1 ring signal/

Channel 1 SPI

clock (CLK)

PORTA3

RXDA

DACK1_

H15 U I/O

2

Channel 1 RXD

DMA channel 3/5

ACK

PORTA2

PORTA1

DSRA_

CTSA_

AMUX

H12 U I/O

H13 U I/O

2

Channel 1 DSR_

Channel 1 CTS_

DRAM addr mux

DONE1_ (O)

DMA channel 3/5

DONE_Out

PORTA0

TXCA/

OUT2A_/

DCDA_

DONE1_ (I)

DREQ2_

G12 U I/O

2

Pgm’able Out/

Channel 1 DCD/

Channel 1 SPI

enable (SEL_)/

Channel 1 TXCLK

DMA channel 3/5

DONE_In

PORTC7

PORTC6

TXDB

G13 U I/O

G14 U I/O

2

Channel 2 TXD

Channel 2 DTR_

GEN interrupt out

DTRB_

DMA Channel 4/6

Req

www.digi.com

ꢀ

13

General Purpose I/O

GPIO signal Serial

signal

Other

signal

Serial channel

description

Other

description

I/O

OD

2

PORTC5

RTSB_

REJECT_

RESET_

F15 U I/O

F12 U I/O

Channel 2 RTS_

CAM reject

PORTC4¹

RXCB/RIB_/

OUT1B_

2

Pgm’able Out/

Channel 2

RESET output

RXCLK/Channel 2

ring signal/

Channel 2 SPI

clock (CLK)

PORTC3²

RXDB

LIRQ3/

DACK2_

F13 U I/O

2

Channel 2 RXD

LevelsensitiveIRQ/

DMA channel 4/6

ACK

PORTC2²

PORTC1²

DSRB_

CTSB_

LIRQ2/RPSF_ E15 U I/O

2

Channel 2 DSR_

Channel 2 CTS_

Level sensitive IRQ/

CAM request

LIRQ1/

DONE2_(O)

E12 U I/O

E14 U I/O

LevelsensitiveIRQ/

DMA channel 4/6

DONE_Out

PORTC0²

TXCB/

OUT2B_/

DCDB_

LIRQ0/

2

Pgm’able Out/

Channel 2 DCD/

Channel 2 SPI

enable (SEL_)/

Channel 2 TXCLK

LevelsensitiveIRQ/

DMA channel 4/6

DONE_In

DONE2_(I)

Notes:

1

RESET output indicates the reset state of the NS7520. PORTC4 persists beyond the negation of

RESET_ for approximately 512 clock cycles if the PLL is disabled. When the PLL is enabled,

PORTC4 persists beyond the negation of RESET_ to allow for PLL lock for 100 microseconds

times the ratio of the VCO to XTALA.

This GPIO is left in output mode active following a hardware RESET.

2

PORTC[3:0] pins provide level-sensitive interrupts. The inputs do not need to be synchronous

to any clock. The interrupt remains active until cleared by a change in the input signal level.

1 4

ꢀ

NS7520 Datasheet 03/2006

System clock and reset

Symbol

XTALA1

K14

K12

L15

L12

A10

I/O

OD

Description

I

ARM/system oscillator circuit

XTALA2

O

P

I

PLLVDD (1.5V)

PLLVSS

PLL clean power

PLL return

RESET_

System reset

Signal descriptions

The NS7520 has three clock domains:

ꢀ

System clock (SYSCLK)

Bit rate generation and programmable timer reference clock (XTALA1/2)

System bus clock (BCLK)

The SYS module provides the NS7520 with these clocks, as well as system reset and backup

resources.

Mnemonic

Signal

Description

XTALA1

XTALA2

Oscillator input

Oscillator output

A standard parallel quartz crystal or crystal oscillator can be

attached to these pins to provide the main input clock to the

NS7520.

PLLVDD

PLLVSS

Clean PLL power

Connect directly to the

GND plane

Power and ground for PLL circuit.

RESET_

System reset

Resets the NS7520 hardware.

Table 2: Clock generation and reset signal description

This figure shows the timing and specification for RESET_ rise/fall times:

tF

tR

tF max= 18ns

Vin = 2.0Vto 0.8V

tR max= 18ns

Vin = 0.8Vto 2.0V

www.digi.com

ꢀ

15

System mode (test support)

PLLTST_, BISTEN_, and SCANEN_ primary inputs control different test modes for both functional

and manufacturing test operations (see Table 3: "NS7520 test modes" on page 22).

Symbol

I/O

OD

Description

PLLTST_

N15

I

Encoded with BISTEN_ and SCANEN_

Add an external pullup to 3.3V or pulldown to GND.

BISTEN_

M15

L13

I

Encoded with PLLTST_ and SCANEN_

Add an external pullup to 3.3V or pulldown to GND.

SCANEN_

Encoded with BISTEN_ and PLLTST_

Add an external pullup to 3.3V or pulldown to GND.

JTAG test

JTAG boundary scan allows a tester to check the soldering of all signal pins and tri-state all

outputs.

Symbol

TDI

I/O

OD

Description

Test data in.

N14 U

M13

I

TDO

O

I

2

Test data out.

Test mode select.

Test mode reset.

TMS

M12 U

M14

TRST_

I

Requires external termination when not being used (see

Figure 3, "TRST_ termination," on page 17 for an

illustration of the termination circuit on the development

PCB).

TCK

P15

I

Test mode clock.

Add an external pullup to 3.3V.

ARM debugger signal descriptions

Mnemonic

Signal

Description

TDI

Test data in

TDI operates the JTAG standard. Consult the JTAG specifications

for use in boundary-scan testing. These signals meet the

requirements of the Raven and Jeeni debuggers.

TDO

TMS

Test data out

TDO operates the JTAG standard. Consult the JTAG specifications

for use in boundary-scan testing. These signals meet the

requirements of the Raven and Jeeni debuggers.

Test mode select

TMS operates the JTAG standard. Consult the JTAG specifications

for use in boundary-scan testing. These signals meet the

requirements of the Raven and Jeeni debuggers.

1 6

ꢀ

NS7520 Datasheet 03/2006

Power supply

Mnemonic

Signal

Description

TRST_

Test mode reset

TRST_ operates the JTAG standard. Consult the JTAG

specifications for use in boundary-scan testing. These signals meet

the requirements of the Raven and Jeeni debuggers.

TCK

Test mode clock

TCK operates the JTAG standard. Consult the JTAG specifications

for use in boundary-scan testing. These signals meet the

requirements of the Raven and Jeeni debuggers.

Figure 3: TRST_ termination

Power supply

Signal

Description

Oscillator VCC (3.3V)

Core VCC (1.5V)

I/O VCC (3.3V)

GND

N13, C3

Oscillator power supply

R8, L14, C14, C13

Core power supply

I/O power supply

E4, K4, M2, N3, P3, R5, H14, F14, B8, A3

D2, F1, J4, P4, P7, M8, P9, R11, K15, G15, E13, Ground

D13, B14, C11, A7, A5, B2, P2, P14, K13

www.digi.com

ꢀ

17

NS7520 modules

CPU module

The CPU uses an ARM7TDMI core processor. The ARM architecture is based on Reduced Instruction

Set Computer (RISC) principles, which result in high instruction throughput and impressive real-

time interrupt response for a small, cost-effective circuit. For more information about ARM7TDMI,

see the ARM7TDMI Data Sheet from ARM Ltd. (www.arm.com).

GEN module

The GEN module provides the NS7520 with its main system control functions, as well as these

features:

ꢀ

Two programmable timers with interrupt

One programmable bus-error timer

One programmable watchdog timer

Two 8-bit programmable general-purpose I/O ports

System (SYS) module

The system module provides the system clock (SYS_CLK)and system reset (SYS_RESET)resources.

The system control signals determine the basic operation of the chip:

Signal mnemonic

Signal name

Description

{XTALA1, XTALA2}

Clock source

Operate in one of two ways:

ꢀ

The signals are affixed with a 10-20 MHz parallel mode

quartz crystal or crystal oscillator and the appropriate

components per the component manufacturer.

ꢀ

XTALA1 is driven with a clock signal and XTALA2 is

left open.

{PLLVDD, PLLVSS}

RESET_

PLL power

Chip reset

Provide an isolated power supply for the PLL.

Active low signal asserted to initiate a hardware reset of the

chip.

{TDI, TDO, TNS,

TRST_, TCK}

JTAG interface

Chip mode

Provide a JTAG interface for the chip. This interface is used

for both boundary scan and ICE control of the internal

processor.

{PLLTEST_, BISTEN_,

SCANEN_}

Encoded to determine the chip mode.

1 8

ꢀ

NS7520 Datasheet 03/2006

BBus module

The NS7520 clock module creates the BCLK and FXTAL signals. Both signals are used internally, but

BCLK can also be accessed at ball A6 by setting the BCLKD field in the System Control register to 0.

ꢀ

BCLK functions as the system clock and provides the majority of the NS7520’s timing.

FXTAL provides the timing for the DRAM refresh counter, can be selected instead of BCLK

to provide timing for the watchdog timer, the two internal timers, and the Serial module.

BBus module

The BBus module provides the data path among NS7520 internal modules. This module provides the

address and data multiplexing logic that supports the data flow through the NS7520. The BBus

module is the central arbiter for all the NS7520 bus masters and, once mastership is granted,

handles the decoding of each address to one (or none) of the NS7520 modules.

Memory module (MEM)

The MEM module provides a glueless interface to external memory devices such as Flash, DRAM,

and EEPROM. The memory controller contains an integrated DRAM controller and supports five

unique chip select configurations.

The MEM module monitors the BBus interface for access to the bus module; that is, any access not

addressing internal resources. If the address to be used corresponds to a Base Address register in

the MEM module, the MEM module provides the memory access signals and responds to the BBus

with the necessary completion signal.

The MEM module can be configured to interface with FP, EDO, or SDRAM (synchronous DRAM),

although the NS7520 cannot interface with more than one device type at a time.

DMA controller

The NS7520 contains one DMA controller, with 13 DMA channels. Each DMA channel moves blocks of

data between memory and a memory peripheral.

The DMA controller supports both fly-by operations and memory-to-memory operations:

ꢀ

When configured for fly-by operation, the DMA controller transfers data between one of the

NS7520 peripherals and a memory location.

When configured for memory-to-memory operations, the DMA controller uses a temporary

holding register between read and write operations. Two memory cycles are executed.

Ethernet controller

The Ethernet controller provides the NS7520 with one IEEE 802.3u compatible Ethernet interface.

The Ethernet interface includes the Ethernet front-end (EFE) and media access controller (MAC).

The Ethernet module supports both media independent interface (MII) and ENDEC modes.

www.digi.com

ꢀ

19

Ethernet controller

The MAC module interfaces to an external physical layer (PHY) device using the MII standard

defined by IEEE 802.3u. The MAC interface includes the MII clock and data signals.

Figure 4 shows a high-level block diagram of the EFE module, which provides the FIFO handling

interface between the NS7520 BBus and the MAC modules.

MAC RX interface

RX

filtering &

statistics

MAC TX interface

2K

byte

512

byte

Local

Receive

FIFO

local

Transmit

FIFO

BBus

Figure 4: EFE module block diagram

2 0

ꢀ

NS7520 Datasheet 03/2006

Serial controller

The NS7520 supports two independent universal asynchronous/synchronous receiver/transmitter

channels. Each channel supports these features:

ꢀ

Independent programmable bit-rate generator

UART and SPI (master) modes

High-speed data transfer:

–

x1 mode: 4Mbits/sec

x16 mode: 230 Kbits/sec

ꢀ

32–byte TX FIFO

32–byte RX FIFO

Programmable data format: 5–8 data bits; odd, even, or no parity; 1, 2 stop bits

Programmable channel modes: normal, local loopback, remote loopback

Control signal support

Maskable interrupt conditions:

–

Receive break detection

Receive framing error

Receive parity error

Receive overrun error

Receive FIFO ready

Receive FIFO half-full

Transmit FIFO ready

Transmit FIFO half-empty

CTS, DSR, DCD, RI state change detection

ꢀ

Clock/data encoding: NRZ, NRZB, NRZI, FM, Manchester

Multi-drop capable

www.digi.com

ꢀ

21

NS7520 bootstrap initialization

Many internal NS7520 features are configured when the RESET pin is asserted. The address bus

configures the appropriate control register bits at powerup. This table shows which bits control

which functions:

Address bit

Name

Description

ADDR[27]

Endian configuration

0

1

Little Endian configuration

Big Endian configuration

ADDR[26]

CPU bootstrap

0

1

CPU disabled; GEN_BUSER=1

CPU enabled; GEN_BUSER=0

ADDR[24:23]

CS0/MMCR[19:18] setting

00 8-bit SRAM, 63 wait-states/b00

01 32-bit SRAM, 63 wait-states/b01

10 32-bit SRAM

11 16-bit SRAM, 63 wait-states/b11

ADDR[19:9]

ADDR[8:7]

ADDR[6:5]

ADDR[4:0]

GEN_ID setting

PLL IS setting

PLL FS setting

PLL ND setting

GEN_ID=A[19:09],default=’h3ff

IS=A[8:7], default=’b10

FS=A[6:5], default=’b00

ND=A[4:0], default=’b01011

Table 3: NS7520 test modes

JTAG

The NS7520 provides full support for 1149.1 JTAG boundary scan testing. All NS7520 pins can be

controlled using the JTAG interface port. The JTAG interface provides access to the ARM7TDMI

debug module when the appropriate combination of PLLTST_, BISTEN_, and SCANEN_is selected (as

shown in Table 3: "NS7520 test modes").

ARM Debug

The ARM7TDMI core uses a JTAG TAP controller that shares the pins with the TAP controller used for

1149.1 JTAG boundary scan testing. To enable the ARM7TDMI TAP controller,

{PLLTST_,BISTEN_,SCANEN_}must be set as shown in Table 3: "NS7520 test modes".

2 2

ꢀ

NS7520 Datasheet 03/2006

DC characteristics and other operating specifications

The NS7520 operates using an internal core V_DDsupply voltage of 1.5V. A 3.3VC supply is required

for the I/O cells, which drive/accept 3.3V levels.

Table 4 provides the DC characteristics for inputs; Table 5 provides the DC characteristics for

outputs.

Sym

V_IH

Parameter

Conditions

Min

Typ

Max

3.6

Unit

V

Input high voltage

Input low voltage

2.0

V_IL

V_SS– 0.3

0.8

V

Table 4: DC characteristics — Inputs

Sym

Parameter

Conditions

Min

Max

Unit

P

Power consumption

F_SYSCLK= 55 MHz

F_SYSCLK= 46 MHz

F_SYSCLK= 36 MHz

508

mW

Core

I/O

192

316

425

333

Core

I/O

161

264

Core

I/O

126

207

V_OL

V_OH

Output low voltage

Output high voltage

Outputs & bi-directional

0

0.4

V

2.4

V_DD

Table 5: DC characteristics — Outputs

Table 6 defines the DC operating (thermal) conditions for the NS7520. Operating the NS7520 outside

these conditions results in unpredictable behavior.

Sym

V_DD

V_CC

T_OP

T_J

Parameter

Conditions

Min

1.4

3.0

-40

Typ

1.5

Max

1.6

3.6

85

Unit

V

Core supply voltage

I/O supply voltage

Ambient temperature

Junction temperature

Storage temperature

Pkg thermal resistance

Input threshold

3.3

V

^oC

110

50

^oC

T_STG

θ_J

-40

-10

125

10

^oC

^oC/W

I_IH

No pullup

μΑ

Table 6: Recommended operating temperatures

www.digi.com

ꢀ

23

Absolute maximum ratings

Sym

I_IL

Parameter

Conditions

No pullup

Any input

V_O=0

Min

10

Typ

Max

10

Unit

μA

Input current as “0”

HighZ leakage current

Pin capacitance

I_OZ

-10

10

μA

C_IO

7

pF

Table 6: Recommended operating temperatures

Absolute maximum ratings

This table defines the maximum values for the voltages that the NS7520 can withstand without

being damaged.

Sym

Parameter

Min

Max

V_DD

V_CC

V_IN

Core supply voltage

I/O supply voltage

Input voltage

-0.3

3.15

3.9

V_OUT

Output voltage

Pad pullup and pulldown characteristics

Figure 5 illustrates characteristics for a pad with internal pullup; Figure 6 illustrates characteristics

for a pad with internal pulldown. See "Pinout detail tables," beginning on page 6, for information

about which pins use pullup and pulldown resistors.

Figure 5: Internal pullup characteristics

2 4

ꢀ

NS7520 Datasheet 03/2006

AC characteristics

Figure 6: Internal pulldown characteristics

AC characteristics

AC electrical specifications define the timing relationship between signals for interfaces and modes

within a given interface.

AC electrical specifications

The AC electrical specifications are based on the system configuration shown in Figure 7, with a

5pF allowance for PCB capacitance and a 0.25 ns allowance for PCB delay. The timing of the

buffers, SDRAM, and the like must be added to complete timing analysis. In systems where SDRAM is

not used, two devices are expected to replace the SDRAMs shown in Figure 7; that is, they are tied

directly to the chip. System loading information is shown in Table 7: "System loading details" on

page 26.

www.digi.com

ꢀ

25

AC electrical specifications

SDRAM

NS7520

Buffer

other

memory

devices

Figure 7: System configuration for specified timing

Signal

Estimated load (pF)

Device loads

BCLK

23

Two SDRAMs, 1 clock buffer/clock

input to PLD

A[27:0], CAS[3:0]_

CS[4:0]_

23

13

18

19

Two SDRAM An, 1 buffer/PLD

Two SDRAM CSn, 1 buffer PLD

One SDRAM DQ, 1 buffer/PLD

1 buffer/PLD

DATA[31:0]

BE*_

TS_, TA_, TEA_, BR_, BG_, BUSY_, WE_, 15

OE_

PORTA3, PORTA1, PORTC3, PORTC1

(operating external DMA)

15

1 buffer/PLD

Other PORTA[*] and PORTC[*], TDO

MDC, MDIO, TXEN, TXER, TXD[3:0]

85

20

Tester load

One PHY

Table 7: System loading details

Exceeding the loading shown in Table 7 can result in additional signal delay. The delay can be

approximated by derating the output buffer based on the expected load capacitance per the values

shown in Table 8.

Signal

Derating (ns/pF)

BCLK

0.069

A[27:0], TS_, TA_, TEA_, BR_, BG_, BUSY_, DATA[31:0] 0.150

BE[3:0]

0.300

Table 8: Output buffer derating by load capacitance

2 6

ꢀ

NS7520 Datasheet 03/2006

Oscillator Characteristics

Signal

Derating (ns/pF)

CS[4:0]_, CAS[3:0], RW_, WE_, OE_

MDC, TXD[3:0], TXER, TXEN, TDO

0.137

0.274

Table 8: Output buffer derating by load capacitance

Oscillator Characteristics

Figure 8 illustrates the recommended oscillator circuit details.

ꢀ

Rise/fall time. The max rise/fall time on the system clock input pin is 1.5ns when used

with an external oscillator.

Duty cycle. The duty cycle is system-dependent with an external oscillator. It affects the

setup and hold times of signals that change in the falling clock edges, such as WE_/OE_.

Recommendation: Use a 3.3V, 50±10% duty cycle oscillator with a 100 ohm series resistor

at the output. The PLLs can handle a 25% duty cycle clock (minimum high/low time

4.5nS).

3R3V

U1

R1

5

4

3

10K

1

2

R2

L13

A10

NC

SCANEN_

RESET_

Rise time = 18ns;

0.8V to 2.0V

0 OHM

LVC04

RESET_

Optional 36.864-55.296MHz Oscillator

PLL bypassed - U1 & R2 OUT, R1 IN

3R3V

TB1

Y2

4

VCC

2

NS7520

R11

GND

1

3

C3

100nF

TEST

OUT

SM_Oscillator

100 OHM

A 18.432MHz crystal or 55.296MHz

oscillator allows full speed operation.

C1

K14

K12

XTAL1

XTAL2

10pF

X2

R3

1M

C2

R4

XTAL2

10pF

10-20MHz

0 OHM

PLL enabled - U1 & R2 IN, R1 OUT

Figure 8: Oscillator circuit details

www.digi.com

ꢀ

27

Timing Diagrams

Timing_Specifications

All timing specifications consist of the relationship between a reference clock and a signal:

ꢀ

There are bussed and non–bussed signals. Non–bussed signals separately illustrate 0–to–1

and 1–to–0 transitions.

ꢀ

Inputs have setup/hold times versus clock rising.

Outputs have switching time relative to either clock rising or clock falling.

Note:

Timing relationships in this diagram are drawn without proportion to actual delay.

Clock

0-to-1 from rising edge

1-to-0 from rising edge

Signal

0-to-1 from falling edge

1-to-0 from falling edge

Setup time

Hold time

Valid from falling edge

Valid from rising edge

Hold

Bus

Setup time

2 8

ꢀ

NS7520 Datasheet 03/2006

Reset_timing

From a cold start, RESET_ must be asserted until all power supplies are above their specified

thresholds. An additional 8 microseconds is required for oscillator settling time (allow 40ms for

crystal startup).

Due to an internal three flip-flop delay on the external RESET_ signal, after the oscillator is

settled, RESET_ must be asserted for three periods of the XTALA1 clock in these situations:

ꢀ

Before release of reset after application of power

While valid power is maintained to initiate hot reset (reset while power is at or above

specified thresholds)

ꢀ

Before loss of valid power during power outage/power down

The PORTC4 output indicates the reset state of the chip. PORTC4 persists beyond the negation of

RESET_ for approximately 512 system clock cycles if the PLL is disabled. When the PLL is enabled,

PORTC4 persists beyond the negation of RESET_ to allow for PLL lock for 100 microseconds times

the ratio of the VCO to XTALA.

VDD, VCC

1

XTALA1

2

3

4

RESET_

Reset timing parameters

Num

Description

Min

Typ

Max

Units

1

Power valid before reset negated

40

ms

Note: RESET_ should remain low

for at least 40ms after power

reaches 3.0V.

2

3

4

Reset asserted after power valid

Reset asserted while power valid

Reset asserted before power invalid

3

T_XTALA1

www.digi.com

ꢀ

29

SRAM timing

BCLK max frequency: 55.296 MHz

Operating conditions:

Temperature:

Voltage:

-15.00 (min)

1.60 (min)

25.0pf

110.00 (max)

1.40 (max)

Output load:

Input drive:

CMOS buffer

SRAM timing parameters

Num

36

6

Description

Min

Max

15.5

13.5

14

Unit

ns

BCLK high to BE* valid

BCLK high to address valid

BCLK high to data out valid

BCLK high to data out high impedance

Data in valid to BCLK high (setup)

BCLK high to data in invalid (hold)

TA* valid to BCLK high (setup)

BCLK high to TA* invalid (hold)

BCLK high to CS* valid

5

9

13

10

11

14

15

27

28

29

30

31

18

19

12

13

5

3

5

3

12.5

13

BCLK low to OE* valid

BCLK low to WE* valid

BCLK high to TA* valid

13.5

16

BCLK high to TEA* valid

BCLK low to A27 (CS0OE*) valid

BCLK low A26 (CS0WE*) valid

BCLK high to RW* valid

13.5

3 0

ꢀ

NS7520 Datasheet 03/2006

SRAM timing

SRAM read

CS* controlled read (wait = 2)

T1

TW

T2

Note-1

T1

BCLK

30

31

30

TA* (Note-4)

31

TEA* (Note-4)

15

14

TA* (input)

6

A[27:0]

36

27

Note-2

BE[3:0]*

CS[4:0]*

27

18

11

10

read D[31:0]

Sync OE*

CS0OE*

RW*

28

18

12

Notes:

1

If the next transfer is DMA, null periods between memory transfers can occur. Thirteen clock

pulses are required for DMA context switching.

2

Port size determines which byte enable signals are active:

–

8-bit port = BE3*

16-bit port = BE[3:0]

32-bit port = BE[3:0]

3

4

The TW cycles are present when the WAIT field is set to 2 or more.

The TA* and TEA*/LAST signals are for reference only.

www.digi.com

ꢀ

31

SRAM timing

SRAM burst read

CS* controlled, four word (4-2-2-2), burst read (wait = 2, BCYC = 01)

T1

TW

T2

30

TW

30

T2

TW

T2

TW

T2 Note-1 T1

BCLK

TA* (Note-4)

31

TEA*/LAST (Note-4)

A[27:0]

6

36

27

BE[3:0]* (Note-2)

CS[4:0]*

27

18

11

10

read D[31:0]s

Sync OE*

CS0OE*

RW*

28

18

12

Notes:

1

If the next transfer is DMA, null periods between memory transfers can occur. Thirteen clock

pulses are required for DMA context switching.

2

Port size determines which byte enable signals are active:

–

8-bit port = BE3*

16-bit port = BE[3:0]

32-bit port = BE[3:0]

3

4

The TW cycles are present when the WAIT field is set to 2 or more.

The TA* and TEA*/LAST signals are for reference only.

3 2

ꢀ

NS7520 Datasheet 03/2006

SRAM timing

SRAM burst read (2111)

CS* controlled read (wait = 0, BCYC = 00)

T1

T2

Note-1

T1

BCLK

TA* (Note-3)

TEA* (Note-3)

A[27:0]

30

31

6

36

27

Note-2

BE[3:0]*

27

CS[4:0]*

11

10

read D[31:0]

Sync OE*

CS0OE*

RW*

28

18

12

Notes:

1

If the next transfer is DMA, null periods between memory transfers can occur. Thirteen clock

pulses are required for DMA context switching.

2

Port size determines which byte enable signals are active:

–

8-bit port = BE3*

16-bit port = BE[3:0]

32-bit port = BE[3:0]

3

The TA* and TEA*/LAST signals are for reference only.

www.digi.com

ꢀ

33

SRAM timing

SRAM write

CS controlled write (internal and external), (wait = 2)

T1

TW

T2

Note-1

T1

BCLK

TA* (Note-4)

TEA* (Note-4)

30

31

30

31

15

14

TA* (input)

A[27:0]

6

36

27

13

Note-2

BE[3:0]*

CS[4:0]*

write D[31:0]

Sync WE*

CS0WE*

RW*

27

9

29

19

12

Notes:

1

If the next transfer is DMA, null periods between memory transfers can occur. Thirteen clock

pulses are required for DMA context switching.

2

Port size determines which byte enable signals are active:

–

8-bit port = BE3*

16-bit port = BE[3:0]

32-bit port = BE[3:0]

3

4

The TW cycles are present when the WAIT field is set to 2 or more.

The TA* and TEA*/LAST signals are for reference only.

3 4

ꢀ

NS7520 Datasheet 03/2006

SRAM timing

SRAM burst write

CS controlled, four word (4-2-2-2), burst write (wait = 2, BCYC = 01)

T1

TW

T2

30

TW

30

T2

TW

T2

TW

T2

Note-1 T1

BCLK

TA* (Note-4)

TEA*/LAST (Note-4)

A[27:0]

31

6

36

27

13

29

19

BE[3:0]* (Note-2)

CS[4:0]*

27

9

write D[31:0]

Sync WE*

29

19

CS0WE*

12

RW*

Notes:

1

If the next transfer is DMA, null periods between memory transfers can occur. Thirteen clock

pulses are required for DMA context switching.

2

Port size determines which byte enable signals are active:

–

8-bit port = BE3*

16-bit port = BE[3:0]

32-bit port = BE[3:0]

3

4

The TW cycles are present when the WAIT field is set to 2 or more.

The TA* and TEA*/LAST signals are for reference only.

www.digi.com

ꢀ

35

SRAM timing

SRAM OE read

OE* controlled read (wait = 2)

T1

TW

T2

Note-1

T1

BCLK

30

31

30

31

TA* (Note-4)

TEA*/LAST (Note-4)

15

14

TA* (input)

6

A[27:0]

36

27

Note-2

BE[3:0]*

CS[4:0]*

27

11

10

read D[31:0]

Async OE*

CS0OE*

RW*

28

18

28

18

12

Notes:

1

At least one null period occurs between memory transfers. More null periods can occur if the

next transfer is DMA. Thirteen clock pulses are required for DMA context switching.

2

Port size determines which byte enable signals are active:

–

8-bit port = BE3*

16-bit port = BE[3:0]

32-bit port = BE[3:0]

3

4

The TW cycles are present when the WAIT field is set to 2 or more.

The TA* and TEA*/LAST signals are for reference only.

3 6

ꢀ

NS7520 Datasheet 03/2006

SRAM timing

SRAM OE burst read

OE* controlled, four word (3-2-2-2), burst read (wait = 2, BCYC = 01)

T1

TW

T2

TW

30

T2

TW

T2

TW

T2

Note-1

T1

BCLK

TA* (Note-4)

TEA*/LAST (Note-4)

A[27:0]

30

31

6

36

27

BE[3:0]* (Note-2)

CS[4:0]*

27

11

10

read D[31:0]

Async OE*

CS0OE*

RW*

28

18

28

18

12

Notes:

1

At least one null period occurs between memory transfers. More null periods can occur if the

next transfer is DMA. Thirteen clock pulses are required for DMA context switching.

2

Port size determines which byte enable signals are active:

–

8-bit port = BE3*

16-bit port = BE[3:0]

32-bit port = BE[3:0]

3

4

The TW cycles are present when the WAIT field is set to 2 or more.

The TA* and TEA*/LAST signals are for reference only.

www.digi.com

ꢀ

37

SRAM timing

SRAM WE write

WE* controlled write (wait = 2)

T1

TW

T2

Note-1

T1

BCLK

30

31

30

31

TA* (Note-4)

TEA*/LAST (note-4)

TA* (input)

15

14

6

A[27:0]

36

27

13

Note-2

BE[3:0]*

CS[4:0]*

27

9

write D[31:0]

Async WE*

CS0WE*

RW*

29

19

29

19

12

Notes:

1

At least one null period occurs between memory transfers. More null periods can occur if the

next transfer is DMA. Thirteen clock pulses are required for DMA context switching.

2

Port size determines which byte enable signals are active:

–

8-bit port = BE3*

16-bit port = BE[3:0]

32-bit port = BE[3:0]

3

4

The TW cycles are present when the WAIT field is set to 2 or more.

The TA* and TEA*/LAST signals are for reference only.

3 8

ꢀ

NS7520 Datasheet 03/2006

SRAM timing

SRAM WE burst write

WE* controlled, four word (3-2-2-2), burst write (wait = 2, BCYC = 01)

T1

TW

T2

30

TW

30

T2

TW

T2

TW

T2

Note-1

T1

BCLK

TA* (Note-4)

TEA*/LAST (Note-4)

A[27:0]

31

6

36

Note-2

36

27

13

BE[3:0]*

27

9

CS[4:0]*

write D[31:0]

Async WE*

CS0WE*

29

19

12

RW*

Notes:

1

At least one null period occurs between memory transfers. More null periods can occur if the

next transfer is DMA. Thirteen clock pulses are required for DMA context switching.

2

Port size determines which byte enable signals are active:

–

8-bit port = BE3*

16-bit port = BE[3:0]

32-bit port = BE[3:0]

3

4

The TW cycles are present when the WAIT field is set to 2 or more.

The TA* and TEA*/LAST signals are for reference only.

www.digi.com

ꢀ

39

SDRAM timing

BCLK max frequency: 55.296 MHz

Operating conditions:

Temperature:

Voltage:

-15.00 (min)

1.60 (min)

25.0pf

110.00 (max)

1.40 (max)

Output load:

Input drive:

CMOS buffer

SDRAM timing parameters

Num

36

6

Description

Min

Max

15.5

13.5

14

Unit

ns

BCLK high to BE*/DQM* valid

BCLK high to non-muxed address valid

BCLK high to data out valid

5

9

13

10

11

27

30

31

37

35

34

12

BCLK high to data out high impedance

Data in valid to BCLK high (setup)

BCLK high to data in invalid (hold)

BCLK high to CS* valid

13

5

3

15.5

13.5

16

BCLK high to TA* valid

BCLK high to TEA* valid

BCLK high to PORTA2/AMUX valid

BCLK high to muxed address valid

BCLK high to CAS* valid

14

6

14.5

12

BCLK high to RW* valid

13.5

4 0

ꢀ

NS7520 Datasheet 03/2006

SDRAM timing

SDRAM read

SDRAM read, CAS latency = 2

T1

T2

bterm

T1

prechg

active

read

nop

inhibit

30

inhibit

BCLK

TA* (Note-5)

30

31

TEA*/LAST* (Note-5)

PortA2/AMUX

37

6

Non-muxed address

Muxed address

35

36

35

36

BE[3:0]* (DQM)

10

11

read D[31:0]

CS[4:0]*

27

34

27

34

CAS3* (RAS)

CAS2* (CAS)

CAS1* (WE)

CAS0* (A10/AP)

RW*

34

12

34

A10

Notes:

1

Port size determines which byte enable signals are active:

–

8-bit port = BE3*

16-bit port = BE[3:2]

32-bit port = BE[3:0]

2

The precharge and/or active commands are not always present. These commands depend on

the address of the previous SDRAM access.

3

4

5

If CAS latency = 3, 2 NOPs occur between the read and burst terminate commands.

If CAS latency = 3, 3 inhibits occur after burst terminate.

The TA* and TEA*/LAST signals are for reference only.

www.digi.com

ꢀ

41

SDRAM timing

SDRAM read

SDRAM read, CAS latency = 1

T1

prechg

T2

bterm

T1

active

read

inhibit

BCLK

TA* (Note-3)

30

31

37

TEA*/LAST* (Note-3)

PortA2/AMUX

37

35

6

Non-muxed address

35

Muxed address

36

BE[3:0]* (DQM)

10

11

read D[31:0]

27

CS[4:0]*

34

CAS3* (RAS#)

34

CAS2* (CAS#)

34

CAS1* (WE#)

34

A10

CAS0* (A10/AP)

12

RW*

Notes:

1

Port size determines which byte enable signals are active:

–

8-bit port = BE3*

16-bit port = BE[3:2]

32-bit port = BE[3:0]

2

3

The precharge and/or active commands are not always present. These commands depend on

the address of the previous SDRAM access.

The TA* and TEA*/LAST signals are for reference only.

4 2

ꢀ

NS9360 Datasheet 03/2006

SDRAM timing

SDRAM burst read

SDRAM read, CAS latency = 2

T1

T2

nop

T2

nop

T2

T1

prechg active

read

nop

bterm inhibit inhibit

BCLK

TA* (Note-5)

30

31

TEA*/LAST* (Note-5)

PortA2/AMUX

37

35

37

6

Non-muxed address

Muxed address

35

36

27

BE*[3:0]* (DQM)

11

10

read D[31:0]

CS[4:0]*

27

34

CAS3* (RAS)

CAS2* (CAS)

CAS1* (WE)

CAS0* (A10/AP)

RW*

34

12

34

A10

Notes:

1

Port size determines which byte enable signals are active:

–

8-bit port = BE3*

16-bit port = BE[3:2]

32-bit port = BE[3:0]

2

The precharge and/or active commands are not always present. These commands depend on

the address of the previous SDRAM access.

3

4

5

If CAS latency = 3, 5 NOPs occur between the read and burst terminate commands.

If CAS latency = 3, 3 inhibits occur after burst terminate.

The TA* and TEA*/LAST signals are for reference only.

www.digi.com

ꢀ

43

SDRAM timing

SDRAM burst read

SDRAM read, CAS latency = 1

T1

T2

nop

T2

nop

T2

T1

prechg

active

read

nop

bterm

inhibit

BCLK

TA* (Note-5)

30

31

TEA*/LAST* (Note-5)

PortA2/AMUX

37

6

Non-muxed address

Muxed address

35

36

35

36

27

BE[3:0]* (DQM)

11

10

read D[31:0]

CS[4:0]*

27

34

CAS3* (RAS)

CAS2* (CAS)

CAS1* (WE)

CAS0* (A10/AP)

RW*

34

12

34

A10

Notes:

1

Port size determines which byte enable signals are active:

–

8-bit port = BE3*

16-bit port = BE[3:2]

32-bit port = BE[3:0]

2

The precharge and/or active commands are not always present. These commands depend on

the address of the previous SDRAM access.

3

4

5

If CAS latency = 3, 5 NOPs occur between the read and burst terminate commands.

If CAS latency = 3, 3 inhibits occur after burst terminate.

The TA* and TEA*/LAST signals are for reference only.

4 4

ꢀ

NS9360 Datasheet 03/2006

SDRAM timing

SDRAM write

T1

prechg

T2

write

T1

active

inhibit

BCLK

TA* (Note-3)

30

31

37

30

31

37

TEA*/LAST* (Note-3)

PortA2/AMUX

Non-muxed address

Muxed address

BE[3:0]* (DQM)

write D[31:0]

6

35

36

35

36

13

27

Note-1

9

27

34

CS[4:0]*

34

CAS3* (RAS)

CAS2* (CAS)

CAS1* (WE)

34

12

34

A10

CAS0* (A10/AP)

RW*

Notes:

1

Port size determines which byte enable signals are active:

–

8-bit port = BE3*

16-bit port = BE[3:2]

32-bit port = BE[3:0]

2

3

The precharge and/or active commands are not always present. These commands depend on

the address of the previous SDRAM access.

The TA* and TEA*/LAST signals are for reference only.

www.digi.com

ꢀ

45

SDRAM timing

SDRAM burst write

T1

prechg

T2

write

T2

write

T2

write

T2

write

T1

active

inhibit

30

BCLK

TA* (Note-3)

30

31

37

TEA*/LAST* (Note-3)

PortA2/AMUX

Non-muxed address

Muxed address

write D[31:0]1

BE[3:0]* (DQM)

CS[4:0]*

37

35

6

35

9

13

36

27

36

27

34

CAS3* (RAS)

CAS2* (CAS)

CAS1* (WE)

34

12

34

A10

CAS0* (A10/AP)

RW*

Notes:

1

Port size determines which byte enable signals are active:

–

8-bit port = BE3*

16-bit port = BE[3:2]

32-bit port = BE[3:0]

2

3

The precharge and/or active commands are not always present. These commands depend on

the address of the previous SDRAM access. When the active command is not present,

parameter #35 is valid during the write (T2) cycle.

The TA* and TEA*/LAST signals are for reference only.

4 6

ꢀ

NS9360 Datasheet 03/2006

SDRAM timing

SDRAM load mode

prechg

nop

load

BCLK

CS[4:0]*

27

34

CAS3* (RAS)

CAS2* (CAS)

CAS1* (WE)

CAS0* (A10/AP)

A[13:0]

34

35

34

35

op code

SDRAM refresh

prechg

inhibit

refresh

BCLK

CS[4:0]*

27

34

CAS3* (RAS)

CAS2* (CAS)

CAS1* (WE)

CAS0* (A10/AP)

34

www.digi.com

ꢀ

47

FP DRAM timing

BCLK max frequency: 55.296 MHz

Operating conditions:

Temperature:

Voltage:

-15.00 (min)

1.60 (min)

25.0pf

110.00 (max)

1.40 (max)

Output load:

Input drive:

CMOS buffer

FP DRAM timing parameters

Num

36

6

Description

Min

Max

15.5

13.5

14

Unit

ns

BCLK high to BE* valid

BCLK high to address valid

BCLK high to data out valid

BCLK high to data out high impedance

Data in valid to BCLK high (setup)

BCLK high to data in invalid (hold)

TA* valid to BCLK high (setup)

BCLK high to TA* invalid (hold)

BCLK low to OE* valid

5

9

13

10

11

14

15

28

29

30

31

37

35

43

27

12

13

5

3

5

3

12.5

13

BCLK low to WE* valid

BCLK high to TA* valid

13.5

16

BCLK high to TEA* valid

BCLK high to PORTA2/AMUX valid

BCLK high to muxed address valid

BCLK low to CAS* valid

14

6

14.5

13

BCLK low to RAS* valid

12

BCLK high to RW* valid

13.5

4 8

ꢀ

NS9360 Datasheet 03/2006

FP DRAM timing

FP DRAM read

Fast Page read

T1

TW

T2

Note-1

T1

BCLK

TA* (Note-4)

30

31

30

31

TEA*/LAST (Note-4)

15

14

TA* (input)

BE[3:0]*

36

6

36

Note-2

Non-muxed address

Muxed address

35

11

10

read D[31:0]1

OE*

28

27

28

27

RAS[4:0]*1

CAS[3:0]*1

PortA2/AMUX

RW*

43

37

Note-3

37

12

Notes:

1

If the next transfer is DMA, null periods between memory transfers can occur. Thirteen clock

pulses are required for DMA context switching.

2

Port size determines which byte enable signals are active:

–

8-bit port = BE3*

16-bit port = BE[3:2]

32-bit port = BE[3:0]

3

4

Port size determines which CAS signals are active:

–

8-bit port = CAS3*

16-bit port = CAS[3:2]

32-bit port = CAS[3:0]

The TA* and TEA*/LAST signals are for reference only.

www.digi.com

ꢀ

49

FP DRAM timing

FP DRAM burst read

Fast Page burst read

T1

TW

T2

TW

T2

TW

T2

TW

T2

Note-1

T1

BCLK

30

TA* (Note-4)

31

36

TEA*/LAST (Note-4)

36

Note-2

BE[3:0]*

Non-muxed address

Muxed address

6

35

11

10

read D[31:0]

OE*

28

27

28

37

27

RAS[4:0]*

CAS[3:0]*

PortA2/AMUX

RW*

43

Note-3

37

12

Notes:

1

If the next transfer is DMA, null periods between memory transfers can occur. Thirteen clock

pulses are required for DMA context switching.

2

Port size determines which byte enable signals are active:

–

8-bit port = BE3*

16-bit port = BE[3:2]

32-bit port = BE[3:0]

3

4

Port size determines which CAS signals are active:

–

8-bit port = CAS3*

16-bit port = CAS[3:2]

32-bit port = CAS[3:0]

The TA* and TEA*/LAST signals are for reference only.

5 0

ꢀ

NS9360 Datasheet 03/2006

FP DRAM timing

FP DRAM write

Fast Page write

T1

TW

T2

Note-1

T1

BCLK

TA* (Note-4)

30

31

30

31

TEA*/LAST (Note-4)

15

14

TA* (input)

BE[3:0]*

36

6

36

13

Note-2

Non-muxed address

Muxed address

write D[31:0]

WE*

35

9

29

27

29

27

(FP)RAS[4:0]*

(FP)CAS[3:0]*

PortA2/AMUX

RW*

43

37

Note-3

37

12

Notes:

1

If the next transfer is DMA, null periods between memory transfers can occur. Thirteen clock

pulses are required for DMA context switching.

2

Port size determines which byte enable signals are active:

–

8-bit port = BE3*

16-bit port = BE[3:2]

32-bit port = BE[3:0]

3

4

Port size determines which CAS signals are active:

–

8-bit port = CAS3*

16-bit port = CAS[3:2]

32-bit port = CAS[3:0]

The TA* and TEA*/LAST signals are for reference only.

www.digi.com

ꢀ

51

FP DRAM timing

FP DRAM burst write

Fast Page burst write

T1

TW

T2

TW

T2

TW

T2

TW

T2

Note-1

T1

BCLK

30

TA* (Note-4)

31

36

TEA*/LAST (Note-4)

36

Note-2

BE[3:0]*

Non-muxed address

Muxed address

writeD[31:0]

WE*

6

35

9

13

29

27

RAS[4:0]*

43

Note-3

CAS[3:0]*

37

PortC3/AMUX

RW*

12

Notes:

1

If the next transfer is DMA, null periods between memory transfers can occur. Thirteen clock

pulses are required for DMA context switching.

2

Port size determines which byte enable signals are active:

–

8-bit port = BE3*

16-bit port = BE[3:2]

32-bit port = BE[3:0]

3

Port size determines which CAS signals are active:

–

8-bit port = CAS3*

16-bit port = CAS[3:2]

32-bit port = CAS[3:0]

4

5

The TA* and TEA*/LAST signals are for reference only.

The BCYC field should never be set to 00.

5 2

ꢀ

NS9360 Datasheet 03/2006

FP DRAM timing

fp_refresh_cycles

Fast page refresh (RCYC = 00)

RF1

RF2

RF3

RF4

27

RF5

RF6

RF7

RF8

T1

BCLK

RAS[4:0]*

CAS3*

CAS2*

CAS1*

CAS0*

WE*

27

43

12

43

12

Fast page refresh (RCYC = 01)

RF1

RF2

RF3

RF4

RF5

RF6

RF8

T1

BCLK

RAS[4:0]*

CAS3*

CAS2*

CAS1*

CAS0*

WE*

27

43

12

27

43

12

www.digi.com

ꢀ

53

FP DRAM timing

Fast page refresh (RCYC = 10)

RF1

RF2

RF3

RF4

RF5

RF8

T1

BCLK

RAS[4:0]*

CAS3*

CAS2*

CAS1*

CAS0*

WE*

27

43

12

43

12

Fast page refresh (RCYC = 11)

RF1

RF2

RF3

RF4

RF8

T1

BCLK

RAS[4:0]*

CAS3*

CAS2*

CAS1*

CAS0*

WE*

27

43

12

43

12

5 4

ꢀ

NS9360 Datasheet 03/2006

Ethernet timing

Operating conditions:

Temperature:

Voltage:

-15.00 (min)

110.00 (max)

1.40 (max)

1.60 (min)

25.0pf

Output load:

Input drive:

CMOS buffer

Ethernet timing parameters

Num

44

45

46

49

47

48

50

52

53

Description

Min

Max

Unit

ns

TXCLK high to TXD*, TXEN, TXER valid

RXD*, RXER, RXDV, TXCOL, RXCRS valid to RXCLK high (setup)

RXCLK high to RXD*, RXER, RXDV, TXCOL, RXCRS hold time

MDC high to MDIO valid

11.5

3

2

50

MDIO valid to MDC high (setup)

3

MDC high to MDIO hold time

RXCLK high to RSPF* valid

15.5

REJECT* valid to RXCLK high (setup)

REJECT* valid from RXCLK high (hold)

3

1.5

Ethernet PHY timing

TXCLK

44

46

TXD[3:0],TXEN,TXER

RXCLK

45

RXD[3:0],RXER,RXDV,CRS,COL

47

48

49

MDIO (input)

MDC

MDIO (output)

www.digi.com

ꢀ

55

Ethernet timing

Ethernet cam timing

RXCLK

50

RPSF_

53

51

52

REJECT_

5 6

ꢀ

NS9360 Datasheet 03/2006

JTAG timing

Operating conditions:

Temperature:

Voltage:

-15.00 (min)

110.00 (max)

1.40 (max)

1.60 (min)

25.0pf

Output load:

Input drive:

CMOS buffer

jtag arm ice timing parameters

Num

54

Description

Min

Max

21

Units

ns

TCK to TDO valid

55

TCK to TDO HighZ

TDI setup to TCK rising

TDI hold from TCK rising

TRST* width

21

ns

56

1

3

1

3

ns

57

ns

58

T_TCK

ns

60

TMS setup to TCK rising

TMS hold from TCK rising

61

ns

jtag arm ice timing diagram

TCK

54

55

TDO

57

61

56

60

TDI

58

TRST_

TMS

www.digi.com

ꢀ

57

JTAG timing

jtag bscan timing parameters

Num

62

Description

Min

Max

21

Units

ns

TCK to TDO valid

63

TCK to TDO HighZ

TDI setup to TCK rising

TDI hold from TCK rising

TRST* width

21

ns

64

1

3

1

3

ns

65

ns

66

T_TCK

ns

68

TMS setup to TCK rising

TMS hold to TCK rising

69

ns

jtag bscan timing diagram

TCK

62

63

TDO

65

69

64

68

TDI

66

TRST_

TMS

5 8

ꢀ

NS9360 Datasheet 03/2006

External DMA timing

BCLK max frequency: 55.296 MHz

Operating conditions:

Temperature:

Voltage:

-15.00 (min)

1.60 (min)

25.0pf

110.00 (max)

1.40 (max)

Output load:

Input drive:

CMOS buffer

External DMA timing parameters

Num

72

Description

Min

Max

14

Unit

ns

BCLK high to DACK* valid

75

BCLK high to DONE* (output) valid

DREQ* low to BCLK high (setup)

BCLK high to DREQ* valid (hold)

DONE* (input) valid BCLK high (setup)

BLCK high to DONE* (input) valid (hold)

15

ns

70

5

0

5

0

ns

71

ns

73

ns

74

ns

Fly-by external DMA

T1

TW

T2

BCLK

Mem signals (Note-1)

71

70

DREQ*

DACK*

72

75

72

75

DONE* (output)

74

73

Note2

DONE* (input)

Notes:

1

The memory signals are data[31:0], addr[27:0], BE[3:0], CS/RAS[4:0], CAS[3:0], RW, OE*. WE*,

and PORTC3/AMUX. The timing of these signals depends on how the memory is configured

(Sync SRAM, Async SRAM, FP DRAM, or SDRAM).

2

The DONE* signal works as an input only when the DMA channel is configured as fly-by write.

www.digi.com

ꢀ

59

External DMA timing

Memory-to-memory external DMA

T1

TW

T2

Note-1

T1

TW

T2

BCLK

Mem signals (Note-2)

R/W

71

70

DREQ*

DACK*

72

75

72

75

DONE* (output)

Notes:

1

A null period sometimes occurs between memory cycles.

2

The memory signals are data[31:0], addr[27:0], BE[3:0], CS/RAS[4:0], CAS[3:0], RW, OE*. WE*,

and PORTA2/AMUX. The timing of these signals depends on how the memory is configured

(Sync SRAM, Async SRAM, FP DRAM, or SDRAM).

6 0

ꢀ

NS9360 Datasheet 03/2006

Serial internal/external timing

Operating conditions:

Temperature:

Voltage:

-15.00 (min)

1.60 (min)

25.0pf

110.00 (max)

1.40 (max)

Output load:

Input drive:

CMOS buffer

Note:

SPI timing diagrams are in Chapter 10, "Serial Controller Module." See Figure 25, "SPI

master mode 0 and 1 two-byte transfer," on page 219 and Figure 26, "SPI slave mode 0

and 1 two-byte transfer," on page 222. Only SPI modes 0 and 1 are supported.

Serial internal timing characteristics

Num

76

Description

Min

Max

Unit

T_SCLK

ns

SCLK to ENABLE high

SCLK to TXD (PORTA7/C7)

RXD (PORTA3/C3) setup to SCLK

RXD hold to SCLK

1

77

1 T_SYS*

78

1

ns

79

ns

* The T_SYSparameter represents one period of the internal system clock.

Serial external timing characteristics

Num

Description

Min

Max

10

Unit

MHz

%

80

SCLK frequency

SCLK duty cycle

45

1

55

81

82

83

84

SCLK to ENABLE

T_SCLK

ns

SCLK to TXD (PORTA7/C7)

RXD (PORTA3/C3) setup to SCLK

RXD hold to SCLK

2T_SYS*

2

ns

1.5

ns

* The T_SYSparameter represents one period of the internal system clock.

www.digi.com

ꢀ

61

Serial internal/external timing

synchronous serial internal clock

SCLK

Enable

TXD

76

77

79

76

77

78

RXD

synchronous serial external clock

80

SCLK

Enable

TXD

81

82

84

81

82

83

RXD

6 2

ꢀ

NS9360 Datasheet 03/2006

GPIO timing

Operating conditions:

Temperature:

Voltage:

-15.00 (min)

110.00 (max)

1.40 (max)

1.60 (min)

25.0pf

Output load:

Input drive:

CMOS buffer

GPIO timing parameters

Num

85

Description

Min

3

Max

Unit

ns

GPIO (setup) to BCLK rising

GPIO (hold) from BCLK rising

BCLK to GPIO (output)

86

0

ns

87

17

ns

GPIO timing diagram

BCLK

86

87

85

GPIO (input)

GPIO (output)

www.digi.com

ꢀ

63

P/N: 90000303_D

Release date: March 2006

Digi, Digi International, the Digi logo, the Making Device Networking Easy logo, NetSilicon, a Digi

International Company, NET+, NET+OS and NET+Works are trademarks or registered trademarks of

Digi International, Inc. in the United States and other countries worldwide. All other trademarks

are the property of their respective owners.

Information in this document is subject to change without notice and does not represent a

committment on the part of Digi International.

Digi provides this document “as is,” without warranty of any kind, either expressed or implied,

including, but not limited to, the implied warranties of, fitness or merchantability for a particular

purpose. Digi may make improvements and/or changes in this manual or in the product(s) and/or

the program(s) described in this manual at any time.

This product could include technical inaccuracies or typographical errors. Changes are made

periodically to the information herein; these changes may be incorporated in new editions of the

publication.

Digi International

11001 Bren Road East

Minnetonka, MN 55343 U.S.A.

United States: +1 877 912-3444

Other locations: +1 952 912-3444

Fax: +1 952 912-4960

www.digi.com/support

www.digi.com


型号：	DATA28
厂家：	ETC
描述：	Figure 1 shows the NS7520 modules. Dashed lines indicate shared pins
文件：	总68页 (文件大小：1557K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DATA28 [ETC]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E