DDR223 [ETC]

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8408

Quad 8-Bit Multiplying CMOS

D/A Converter with Memory

Logic Diagram

own reference input, feedback resistor, and onboard data

latches that feature read/write capability. The readback func-

tion serves as memory for those systems requiring self-diag-

nostics.

FEATURES:

•

RAD-PAK® patented shielding against natural

space radiation

Total dose hardness:

A common 8-bit TTL/CMOS compatible input port is used to

load data into any of the four DAC data-latches. Control lines

DS1, DS2 and A/B determine which DAC will accept data.

Data loading is similar to that of a RAMs write cycle. Data can

be read back onto the same bus with control line R/W. The

8408 is a bus compatible with most 8-bit microprocessors,

including the 6800, 8080, 8085, and Z80. The 8408 operates

on a single +5 volt supply and dissipates less than 20 mW.

The 8408 is manufactured using highly stable, thin-film resis-

tors on an advanced oxide-isolated, silicon-gate, CMOS pro-

cess. The improved latch-up resistant design eliminates the

need for external protective Schottky diodes.

- equal to 100 krad (Si), depending upon orbit

and space mission

Package:

- 28 pin R^AD-PAK® Flat Pack

Single Supply Ooperation (+5V)

Four 8 Bit DACs in one 28 Pin Package

D/As Matched to within 1%

TTL/CMOS Compatable

•

Four-Quadrant Multiplication

Maxwell Technologies' patented R^AD-PAK® packaging technol-

ogy incorporates radiation shielding in the microcircuit pack-

age. It eliminates the need for box shielding while providing

the required radiation shielding for a lifetime in orbit or space

mission. In a GEO orbit, R^AD-PAK provides greater than 100

krad (Si) radiation dose tolerance. This product is available

with screening up to Class S.

DESCRIPTION:

Maxwell Technologies’ 8408 is a monolithic quad 8-bit multi-

plying digital-to-analog CMOS converter. Each DAC has its

08.20.02 REV 1

All data sheets are subject to change without notice

(858) 503-3300- Fax: (858) 503-3301- www.maxwell.com

Quad 8-Bit Multiplying CMOS

D/A Converter with Memory

8408

TABLE 1. 8408 PINOUT DESCRIPTION

SYMBOL

DESCRIPTION

V_DD

Supply Voltage

_REFA

REF Voltage (A)

R_FBA

I_{OUT 1A}

REF Feedback (A)

Current Output (1A)

Current Output (2A/2B)

Current Output (1B)

REF Feedback (B)

REF Voltage (B)

_{OUT 2A}/I_{OUT 2B}

I_{OUT 1B}

R_FBB

V_REFB

DB0 (LSB)

DB 1 - 6

DB 7 (MSB)

A/B

Data Bit 0, least significant bit

Data bits 1-6

10 - 15

19 - 20

Data Bit 7, most significant bit

A/B

R/W

Read/Write

DS1 - 2

Data Strobes

_REFD

REF Voltage (D)

R_FBD

REF Feedback (D)

Current Output (1D)

Current Output (2C/2D)

Current Output (1C)

REF Feedback (C)

REF Voltage (C)

I_{OUT 1D}

_{OUT 2C}/I_{OUT 2D}

I_{OUT 1C}

R_FBC

_REFC

DGND

Digital Ground

TABLE 2. 8408 ABSOLUTE MAXIMUM RATINGS

PARAMETER

SYMBOL

MIN

MAX

UNIT

V_DDto I_{OUT 2A, OUT 2B,}

V_DDto DGND

_{OUT 1A,}I_{OUT 1B,}I_{OUT 1C, OUT 1D}

R_RFA, R_RFB, V_RFC, R_RFD to I_OUT

I_{OUT 2A, OUT 2B,}I_{OUT 2C, OUT 2D}to DGND

DB0 through DB7 to DGND

Control Logic Input Voltage to DGND

V_REFA, V_REFB, V_REFC, V_REFD to I_{OUT 2A,}I_{OUT 2B,}I_{OUT 2C, OUT 2D}

I_{OUT 2C, OUT 2D}

to DGND

-0.3

V_DD+ 0.3

±25

-0.3

V_DD+ 0.3

_DD+ 0.3

±25

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Quad 8-Bit Multiplying CMOS

D/A Converter with Memory

8408

TABLE 2. 8408 ABSOLUTE MAXIMUM RATINGS

PARAMETER

SYMBOL

MIN

MAX

UNIT

Power Dissipation

P_D

T_A

T_S

^°C

Operating Temperature

Storage Temperature Range

-55

-65

125

150

TABLE 3. DELTA LIMITS

PARAMETER

VARIATION

I_DD

±10% of value specified in Table 4

TABLE 4. 8408 SPECIFICATIONS

(V_DD= +5 V; V_REF= ±10V; V_OUTA, B, C, D = 0V, T_A= -55 TO 125 ^°C UNLESS OTHERWISE NOTED)

P^ARAMETER

SYMBOL

TEST CONDITION

SUBGROUPS

MIN

TYP

MAX

UNIT

STATIC ACCURACY

Resolution

1, 2, 3

Bits

LSB

Non-linearity^{1, 2}

INL

±1/2

±1

Differential Nonlinearity

Gain Error

DNL

G_FSE

TC_GFS

LSB

(Using Internal R_FB)

±1

LSB

Gain Tempco^{3, 4}

Power Supply Rejection

±2

±40

ppm/^°C

PSR ∆V_DD= ±10%

0.001 %FSR/

_{OUT 1A, B,C, D}Leakage Current⁵

I_LKG

+25°C

±30

-55 to 125°C

2, 3

±200

REFERENCE INPUT

Input Voltage Range

Input Resistance

1, 2, 3

±20

R_IN

KΩ

DIGITAL INPUTS

Digital Input High Voltage

Digital Input Low Voltage

Digital Input Current⁶

V_IH

V_IL

I_IN

1, 2, 3

2.4

0.8

+25°C

±0.01

±1.0

±10.0

µA

-55 to 125°C

2, 3

Digital Input Capacitance⁴

DATA BUS OUTPUTS

Digital Output Low

C_IN

1, 2, 3

V_OL

V_OH

16 mA Sink

1, 2, 3

0.4

Digital Output High

400 µA Source

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Quad 8-Bit Multiplying CMOS

D/A Converter with Memory

8408

TABLE 4. 8408 SPECIFICATIONS

(V_DD= +5 V; V_REF= ±10V; V_OUTA, B, C, D = 0V, T_A= -55 TO 125 ^°C UNLESS OTHERWISE NOTED)

P^ARAMETER

SYMBOL

TEST CONDITION

SUBGROUPS

MIN

TYP

MAX

UNIT

Output Leakage Current

I_LKG

+25°C

±0.005

±1.0

µA

-55 to 125°C

2, 3

±0.075 ±10.0

DAC OUTPUTS⁴

Propogation Delay⁷

Settling Time^{8, 9}

t_PD

t_s

9, 10, 11

150

190

180

250

Output Capacitance

C_OUT

DAC latches All “0s”

DAC latches All “1s”

AC Feedthrough

20 V_P-P@ F = 100 kHz 9, 10, 11

SWITCHING CHARACTERISTICS^{4, 10}

Write to Data Strobe Time

t_DS1

t_DS2

t_DSU

+25°C

145

150

175

-55 to 125°C

+25°C

10, 11

Data Valid to Strobe Set-up Time

-55 to 125°C

10, 11

9, 10, 11

Data Valid to Strobe Hold Time

DAC Select to Strobe Set-Up Time

DAC Select to Strobe Hold Time

t_DH

t_AS

t_AH

Write Select to Strobe Set-Up

Time

t_WSU

Write Select to Strobe Hold Time

Read to Data Strobe Width

t_WH

9, 10, 11

t_RDS

+25°C

220

350

320

430

200

270

-55 to 125°C

+25°C

10, 11

Data Strobe to Output Valid Time

Output Data Deselect Time

t_CO

-55 to 125°C

+25°C

10, 11

t_OTD

-55 to 125°C

10, 11

9, 10, 11

Read Select to Strobe Set-Up

Time

t_RSU

t_RH

Read Select to Strobe Hold Time

POWER SUPPLY

9, 10, 11

Voltage Range

V_DD

I_DD

1, 2, 31

1, 2, 3

4.5

5.5

Supply Current¹¹

µA

Supply Current¹²

I_DD

+25°C

1.0

1.5

-55 to 125°C

2, 3

08.20.02 REV 1

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Quad 8-Bit Multiplying CMOS

D/A Converter with Memory

8408

1. This is an end-point linearity specification.

2. Guaranteed to be monotonic over the full operating temperature range.

3. ppm/°C of FSR (FSR = Full Scale Range = V_REF-1 LSB).

4. Guaranteed by design.

5. All Digital Inputs = 0V; VREF = +10V.

6. Logic Inputs are MOS gates. Typical input current at +25°C is less than 10 nA.

7. From Digital Input to 90% of final analog output current.

8. Digital Inputs = 0V to V_DDor V_DDto 0V.

9. Extrapolated: ts (1/2 LSB) = tPD + 6.2τ where τ = the measured first constant of the final RC decay.

10.See Timing Diagram

11. All Digital Inputs “0” or V_DD

12.All Digital Inputs V_IHor V_IL

08.20.02 REV 1

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Quad 8-Bit Multiplying CMOS

D/A Converter with Memory

8408

FIGURE 1. TIMING DIAGRAM

FIGURE 2. SUPPLY CURRENT VS. LOGIC LEVEL

08.20.02 REV 1

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Quad 8-Bit Multiplying CMOS

D/A Converter with Memory

8408

CIRCUIT INFORMATION

The 8408 combines four identical 8-bit CMOS DACs onto a single monolithic chip. Each DAC has its own reference

input, feedback resistor, and on-board data latches. It also features a read/write function that serves as an accessible

memory location for digital-input data words. The DAC’s three-state readback drivers place the data word back onto

the data bus.

D/A CONVERTER SECTION

Each DAC contains a highly stable, silicon-chromium, thin-film, R-2R resistor ladder network and eight pairs of current

steering switches. These switches are in series with each ladder resistor and are single-pole, double-throw NMOS

transistors; the gates of these transistors are controlled by CMOS inverters. Figure 3 shows a simplified circuit of the

R-2R resistor ladder section, and Figure 4 shows an approximate equivalent switch circuit. The current through each

resistor leg is switched between IOUT 1 and IOUT 2. This maintains a constant current in each leg, regardless of the

digital input logic states.

Each transistor switch has a finite “ON” resistance that can introduce errors to the DAC’s specified performance.

These resistances must be accounted for by making the voltage drop across each transistor equal to each other. This

is done by binarily scaling the transistor’s “ON” resistance from the most significant bit (MSB) to the least significant bit

(LSB). With 10 volts applied at the reference input, the current through the MSB switch is 0.5 mA, the next bit is 0.25

mA, etc.; this maintains a constant 10 mV drop across each switch and the converter’s accuracy is maintained. It also

results in a constant resistance appearing at the DAC’s reference input terminal; this allows the DAC to be driven by a

voltage or current source, ac or dc, of positive or negative polarity.

Shown in Figure 5 is an equivalent output circuit for DAC A. The circuit is shown with all digital inputs high. The leak-

age current source is the combination of surface and junction leakages to the substrate. The 1/256 current source rep-

resents the constant 1-bit current drain through the ladder terminating resistor. The situation is reversed with all digital

inputs low, as shown in Figure 6. The output capacitance is code dependent, and therefore, is modulated between the

low and high values.

08.20.02 REV 1

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Quad 8-Bit Multiplying CMOS

D/A Converter with Memory

8408

FIGURE 3. SIMPLIFIED D/A CIRCUIT OF 8408

F^IGURE4. N-CHANNEL CURRENT STEERING SWITCH

FIGURE 5. EQUIVALENT DAC CIRCUIT (AII DIGITAL INPUTS HIGH)

08.20.02 REV 1

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Quad 8-Bit Multiplying CMOS

D/A Converter with Memory

8408

FIGURE 6. EQUIVALENT DAC CIRCUIT (AII DIGITAL INPUTS LOW)

DIGITAL SECTION

Figure 7 shows the digital input/output structure for one bit. The digital WR, WR, and RD controls shown in the figure

are internally generated from the external A/B, R/W, DS1, and DS2 signals. The combination of these signals decide

which DAC is selected. The digital inputs are CMOS inverters, designed such that TTL input levels (2.4 V and 0.8 V)

are converted into CMOS logic levels. When the digital input is in the region of 1.2 V to 1.8 V, the input stages operate

in their linear region and draw current from the +5 V supply (see Typical Supply Current vs. Logic Level curve on page

6). It is recommended that the digital input voltages be as close to VDD and DGND as is practical in order to minimize

supply currents. This allows maximum savings in power dissipation inherent with CMOS devices. The three-state

readback digital output drivers (in the active mode) provide TTL-compatible digital outputs with a fan-out of one TTL

load. The three state digital readback leakage-current is typically 5 nA.

FIGURE 7. DIGITAL INPUT/OUTPUT STRUCTURE

08.20.02 REV 1

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Quad 8-Bit Multiplying CMOS

D/A Converter with Memory

8408

NTERFACE LOGIC SECTION

DAC Operating Modes

• All DACs in HOLD MODE.

• DAC A, B, C, or D individually selected (WRITE MODE).

• DAC A, B, C, or D individually selected (READ MODE).

• DACs A and C simultaneously selected (WRITE MODE).

• DACs B and D simultaneously selected (WRITE MODE).

DAC Selection: Control inputs, DS1, DS2, and A/B select which DAC can accept data from the input port (see Mode

Selection Table).

Mode Selection: Control inputs DS and R/W control the operating mode of the selected DAC.

Write Mode: When the control inputs DS and R/W are both low, the selected DAC is in the write mode. The input data

latches of the selected DAC are transparent, and its analog output responds to activity on the data inputs DB0–DB7.

Hold Mode: The selected DAC latch retains the data that was present on the bus line just prior to DS or R/W going to

a high state. All analog outputs remain at the values corresponding to the data in their respective latches.

Read Mode: When DS is low and R/W is high, the selected DAC is in the read mode, and the data held in the appro-

priate latch is put back onto the data bus.

08.20.02 REV 1

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Quad 8-Bit Multiplying CMOS

D/A Converter with Memory

8408

TABLE 4. MODE SELECTION TABLE

BASIC APPLICATIONS

Some basic circuit configurations are shown in Figures 8 and 9. Figure 8 shows the 8408 connected in a unipolar con-

figuration (2-Quadrant Multiplication), and Table 5 shows the Code Table. Resistors R1, R2, R3, and R4 are used to

trim full scale output. Full-scale output voltage = VREF –1 LSB = VREF (1–2–8) or VREF x (255/256) with all digital

inputs high. Low temperature coefficient (approximately 50 ppm/°C) resistors or trimmers should be selected if used.

Full scale can also be adjusted using VREF voltage. This will eliminate resistors R1, R2, R3, and R4. In many applica-

tions, R1 through R4 are not required, and the maximum gain error will then be that of the DAC.

Each DAC exhibits a variable output resistance that is code dependent.This produces a code-dependent, differential

nonlinearity term at the amplifier’s output which can have a maximum value of 0.67 times the amplifier’s offset voltage.

This differential nonlinearity term adds to the R-2R resistor ladder differential-nonlinearity; the output may no longer be

monotonic. To maintain monotonicity and minimize gain and linearity errors, it is recommended that the op amp offset

voltage be adjusted to less than 10% of 1 LSB (1 LSB = 2–8 x VREF or 1/256 x VREF), or less than 3.9 mV over the

operating temperature range. Zeroscale output voltage (with all digital inputs low) may be adjusted using the op amp

offset adjustment. Capacitors C1, C2, C3, and C4 provide phase compensation and help prevent overshoot and ring-

ing when using high speed op amps.

Figure 9 shows the recommended circuit configuration for the bipolar operation (4-quadrant multiplication), and Table

6 shows the Code Table. Trimmer resistors R17, R18, R19, and R20 are used only if gain error adjustments are

required and range between 50 Ω and 1000 Ω. Resistors R21, R22, R23, and R24 will range between 50 Ω and 500

Ω. If these resistors are used, it is essential that resistor pairs R9–R13, R10–R14, R11–R15, R12–R16 are matched

both in value and tempco. They should be within 0.01%; wire wound or metal foil types are preferred for best temper-

ature coefficient matching. The circuits of Figure 8 and 9 can either be used as a fixed reference D/A converter, or as

an attenuator with an ac input voltage.

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Quad 8-Bit Multiplying CMOS

D/A Converter with Memory

8408

TABLE 5. UNIPOLAR BINARY CODE TABLE (REFER TO FIGURE 8)

F^IGURE8. QUAD DAC UNIPOLAR OPERATION (2-QUADRANT MULTIPLICATION)

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Quad 8-Bit Multiplying CMOS

D/A Converter with Memory

8408

FIGURE 9. QUAD DAC BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION)

T^ABLE6. BIPOLAR (OFFSET BINARY) CODE TABLE (REFER TO FIGURE 9)

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Quad 8-Bit Multiplying CMOS

D/A Converter with Memory

8408

APPLICATION HINTS

General Ground Management: AC or transient voltages between AGND and DGND can appear as noise at the 8408’s

analog output. Note that in Figures 5 and 6, IOUT2A/IOUT2B and IOUT 2C/IOUT 2D are connected to AGND. There-

fore, it is recommended that AGND and DGND be tied together at the 8408 socket. In systems where AGND and

DGND are tied together on the backplane, two diodes (1N914 or equivalent) should be connected in inverse parallel

between AGND and DGND.

Write Enable Timing: During the period when both DS and R/W are held low, the DAC latches are transparent and the

analog output responds directly to the digital data input. To prevent unwanted variations of the analog output, the R/W

should not go low until the data bus is fully settled (DATA VALID).

SINGLE SUPPLY, VOLTAGE OUTPUT OPERATION

The 8408 can be connected with a single +5 V supply to produce DAC output voltages from 0 V to +1.5 V. In Figure

10, the 8408 R-2R ladder is inverted from its normal connection. A +1.500 V reference is connected to the current out-

put pin 4 (IOUT 1A), and the normal VREF input pin becomes the DAC output. Instead of a normal current output, the

R-2R ladder outputs a voltage. The OP-490, consisting of four precision low power op amps that can operate its inputs

and outputs to zero volts, buffers the DAC to produce a low impedance output voltage from 0 V to +1.5 V full-scale.

Table 7 shows the code table.

With the supply and reference voltages as shown, better than 1/2 LSB differential and integral nonlinearity can be

expected. To maintain this performance level, the +5 V supply must not drop below 4.75 V. Similarly, the reference

voltage must be no higher than 1.5 V. This is because the CMOS switches require a minimum level of bias in order to

maintain the linearity performance.

TABLE 7. SINGLE SUPPLY BINARY CODE TABLE (REFER TO FIGURE 10)

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Quad 8-Bit Multiplying CMOS

D/A Converter with Memory

8408

FIGURE 10. UNIPOLAR SUPPLY, VOLTAGE OUTPUT DAC OPERATION

FIGURE 11. A DIGITALLY PROGRAMMABLE UNIVERSAL ACTIVE FILTER

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Quad 8-Bit Multiplying CMOS

D/A Converter with Memory

8408

A DIGITALLY PROGRAMMABLE ACTIVE FILTER

A powerful D/A converter application is a programmable active filter design as shown in Figure 11. The design is

based on the state-variable filter topology which offers stable and repeatable filter characteristics. DAC B and DAC D

can be programmed in tandem with a single digital byte load which sets the center frequency of the filter. DAC A sets

the Q of the filter. DAC C sets the gain of the filter transfer function. The unique feature of this design is that varying

the gain of filter does not affect the Q of the filter. Similarly, the reverse is also true. This makes the programmability of

the filter extremely reliable and predictable. Note that low-pass, high-pass, and bandpass outputs are available. This

sophisticated function is achieved in only two IC packages.

The network analyzer photo shown in Figure 12 superimposes five actual bandpass responses ranging from the low-

est frequency of 75 Hz (1 LSB ON) to a full-scale frequency of 19.132 kHz (all bits ON), which is equivalent to a 256 to

1 dynamic range. The frequency is determined by fC = 1/2πRC where R is the ladder resistance (RIN) of the 8408,

and C is 1000 pF. Note that from device to device, the resistance RIN varies. Thus some tuning may be necessary.

FIGURE 12. PROGRAMMABLE ACTIVE FILTER BAND-PASS FREQUENCY RESPONSE

All components used are available off-the-shelf. Using low drift thin-film resistors, the 8408 exhibits very stable perfor-

mance over temperature. The wide bandwidth of the OP-470 produces excellent high frequency and high Q response.

In addition, the OP470’s low input offset voltage assures an unusually low dc offset at the filter output.

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Quad 8-Bit Multiplying CMOS

D/A Converter with Memory

8408

FIGURE 13. A DIGITALLY PROGRAMMABLE, LOW-DISTORTION SINEWAVE OSCILLATOR

A LOW-DISTORTION, PROGRAMMABLE SINEWAVE OSCILLATOR

By varying the previous state-variable filter topology slightly, one can obtain a very low distortion sinewave oscillator

with programmable frequency feature as shown in Figure 13. Again, DAC B and DAC D in tandem control the oscillat-

ing frequency based on the relationship fC = 1/2πRC. Positive feedback is accomplished via the 82.5 kΩ and the 20

kΩ potentiometer. The Q of the oscillator is determined by the ratio of 10 kΩ and 475Ω in series with the FET transis-

tor, which acts as an automatic gain control variable resistor. The AGC action maintains a very stable sinewave ampli-

tude at any frequency. Again, only two ICs accomplish a very useful function.

At the highest frequency setting, the harmonic distortion level measures 0.016%. As the frequencies drop, distortion

also drops to a low of 0.006%. At the lowest frequency setting, distortion came back up to a worst case of 0.035%

08.20.02 REV 1

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Quad 8-Bit Multiplying CMOS

D/A Converter with Memory

8408

28 PIN RAD-PAK® FLAT PACKAGE

DIMENSION

SYMBOL

MIN

NOM

MAX

0.190

0.015

0.004

0.207

0.017

0.005

0.720

0.410

0.224

0.022

0.009

0.740

0.420

0.440

0.380

0.180

0.030

0.250

0.080

0.050 BSC

0.370

0.073

0.027

0.360

0.062

0.000

0.380

0.081

F28-02

Note: All dimensions in inches

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Quad 8-Bit Multiplying CMOS

D/A Converter with Memory

8408

Important Notice:

These data sheets are created using the chip manufacturers published specifications. Maxwell Technologies verifies

functionality by testing key parameters either by 100% testing, sample testing or characterization.

The specifications presented within these data sheets represent the latest and most accurate information available to

date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no

responsibility for the use of this information.

Maxwell Technologies’ products are not authorized for use as critical components in life support devices or systems

without express written approval from Maxwell Technologies.

Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Tech-

nologies. Maxwell Technologies’ liability shall be limited to replacement of defective parts.

08.20.02 REV 1

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Quad 8-Bit Multiplying CMOS

D/A Converter with Memory

8408

Product Ordering Options

Model Number

8408

Option Details

Feature

S = Maxwell Class S

B = Maxwell Class B

Screening Flow

I = Industrial (testing @ -55°C,

+25°C, +125°C)

E = Engineering (testing @ +25°C)

F = Flat Pack

Package

RP = R^AD-PAK® package

Radiation Feature

Quad 8-Bit Multiplying CMOS D/A

Converter with Memory

Base Product

Nomenclature

08.20.02 REV 1

All data sheets are subject to change without notice 20

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DDR223 [ETC]

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SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E