DHM0950AQS1B [ETC]
MICROPROCESSOR|32-BIT|PGA|462PIN|CERAMIC ;
| 型号： | DHM0950AQS1B |
| 厂家： | 
ETC |
| 描述： | MICROPROCESSOR|32-BIT|PGA|462PIN|CERAMIC 外围集成电路 时钟 |
| 文件： | 总104页 (文件大小：869K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary Release
TM
Mobile AMD Duron
Processor
Model 7 Data Sheet
Featuring:
Publication # 24068
Rev: F
Issue Date: December 2001
Preliminary Release
© 2001 Advanced Micro Devices, Inc. All rights reserved.
The contents of this document are provided in connection with Advanced
Micro Devices, Inc. (“AMD”) products. AMD makes no representations or
warranties with respect to the accuracy or completeness of the contents of
this publication and reserves the right to make changes to specifications and
product descriptions at any time without notice. No license, whether express,
implied, arising by estoppel or otherwise, to any intellectual property rights
is granted by this publication. Except as set forth in AMD’s Standard Terms
and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims
any express or implied warranty, relating to its products including, but not
limited to, the implied warranty of merchantability, fitness for a particular
purpose, or infringement of any intellectual property right.
AMD’s products are not designed, intended, authorized or warranted for use
as components in systems intended for surgical implant into the body, or in
other applications intended to support or sustain life, or in any other applica-
tion in which the failure of AMD’s product could create a situation where per-
sonal injury, death, or severe property or environmental damage may occur.
AMD reserves the right to discontinue or make changes to its products at any
time without notice.
Trademarks
AMD, the AMD Arrow logo, AMD Athlon, AMD Duron, and combinations thereof, AMD PowerNow!, and 3DNow!
are trademarks of Advanced Micro Devices, Inc.
HyperTransport is a trademark of the HyperTransport Technology Corporation.
MMX is a trademark of Intel Corporation.
Other product names used in this publication are for identification purposes only and may be trademarks of
their respective companies.
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Contents
List of Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1
2
1.1
Mobile AMD Duron™ Processor Model 7 Upgrades Versus
the Mobile AMD Duron Processor Model 3 . . . . . . . . . . . . . . . 2
Mobile AMD Duron Processor Model 7 Microarchitecture
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2
Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
2.2
2.3
2.4
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Signaling Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Push-Pull (PP) Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
AMD Duron System Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . 6
3
4
Logic Symbol Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1
Power Management States . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Working State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Stop Grant States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Probe State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
FID_Change State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Processor Performance States and the FID_Change
Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Connect and Disconnect Protocol . . . . . . . . . . . . . . . . . . . . . . 18
Connect Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Connect State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SYSCLK Multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Special Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.2
4.3
4.4
4.5
5
6
7
CPUID Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Thermal Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.1
7.2
7.3
7.4
7.5
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Interface Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Soft Voltage Identification (SOFTVID[4:0]) . . . . . . . . . . . . . 35
Frequency Identification (FID[3:0]) . . . . . . . . . . . . . . . . . . . . 35
VCCA AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . . 35
Table of Contents
iii
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
7.6
7.7
7.8
7.9
Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Valid Voltage and Frequency Combinations . . . . . . . . . . . . . 36
VCC_CORE AC and DC Characteristics . . . . . . . . . . . . . . . . 37
Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.10 VCC_CORE Voltage and Current . . . . . . . . . . . . . . . . . . . . . . 40
7.11 SYSCLK and SYSCLK# AC and DC Characteristics . . . . . . 41
7.12 AMD Duron System Bus AC and DC Characteristics . . . . . . 43
7.13 General AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . 45
7.14 Open Drain Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.15 Thermal Diode Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 48
7.16 Reserved Pins DC Characteristics . . . . . . . . . . . . . . . . . . . . . 51
7.17 FID_Change Induced PLL Lock Time . . . . . . . . . . . . . . . . . . 52
8
Signal and Power-Up Requirements . . . . . . . . . . . . . . . . . . . . 53
8.1
8.2
Power-Up Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Signal Sequence and Timing Description . . . . . . . . . . . . . . . . 53
Clock Multiplier Selection (FID[3:0]) . . . . . . . . . . . . . . . . . . . 56
Processor Warm Reset Requirements . . . . . . . . . . . . . . . . . . 56
Mobile AMD Duron Processor Model 7 and Northbridge
Reset Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
9
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
9.1
9.2
9.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Die Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
10
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
10.1 Pin Diagram and Pin Name Abbreviations . . . . . . . . . . . . . . 61
10.2 Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.3 Detailed Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
A20M# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
AMD Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
AMD Duron System Bus Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Analog Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
CLKFWDRST Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
CLKIN and RSTCLK (SYSCLK) Pins . . . . . . . . . . . . . . . . . . . 78
CONNECT Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
COREFB and COREFB# Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 78
CPU_PRESENCE# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
DBRDY and DBREQ# Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
FERR Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
FID[3:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
FLUSH# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
IGNNE# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
INIT# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
INTR Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
J TAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
K7CLKOUT and K7CLKOUT# Pins. . . . . . . . . . . . . . . . . . . . . 80
iv
Table of Contents
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Key Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
NC Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
NMI Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
PGA Orientation Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
PLL Bypass and Test Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
PWROK Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
RSVD Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
SADDIN[1:0]# and SADDOUT[1:0]# Pins . . . . . . . . . . . . . . . . 81
Scan Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
SMI# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
SOFTVID[4:0] and VID[4:0] Pins. . . . . . . . . . . . . . . . . . . . . . . 81
STPCLK# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
SYSCLK and SYSCLK#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
THERMDA and THERMDC Pins . . . . . . . . . . . . . . . . . . . . . . . 83
VCCA Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
VREF_SYS Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
ZN and ZP Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
11
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
11.1 Standard Mobile AMD Duron Processor Model 7
Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Appendix A Conventions, Abbreviations, and References . . . . . . . . . . . . . . . . . . . . 87
Signals and Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Data Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Abbreviations and Acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Related Publications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
AMD Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Websites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table of Contents
v
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
vi
Table of Contents
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
List of Figures
Figure 1. Typical Mobile AMD Duron™ Processor Model 7 System
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Symbol Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Mobile AMD Duron Processor Model 7 Power Management
States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. SOFTVID Transition During the AMD Duron System Bus
Disconnect for FID_Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 5. AMD Duron System Bus Disconnect Sequence in the Stop
Grant State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 6. Exiting the Stop Grant State and Bus Connect Sequence . . . . 21
Figure 7. Northbridge Connect State Diagram . . . . . . . . . . . . . . . . . . . . . 22
Figure 8. Processor Connect State Diagram . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 9. VCC_CORE Voltage Waveform . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 10. SYSCLK and SYSCLK# Differential Clock Signals . . . . . . . . . 41
Figure 11. SYSCLK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 12. General ATE Open Drain Test Circuit . . . . . . . . . . . . . . . . . . . . 47
Figure 13. Signal Relationship Requirements During Power-Up
Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 14. Mobile AMD Duron Processor Model 7 CPGA Package . . . . . . 59
Figure 15. Mobile AMD Duron Processor Model 7 Pin Diagram —
Topside View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 16. Mobile AMD Duron Processor Model 7 Pin Diagram —
Bottomside View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 17. OPN Example for the Mobile AMD Duron Processor
Model 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
List of Figures
vii
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
viii
List of Figures
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
List of Tables
Table 1.
FID[4:0] SYSCLK Multiplier Combinations . . . . . . . . . . . . . . . 25
Processor Special Cycle Definition . . . . . . . . . . . . . . . . . . . . . . 27
Thermal Design Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Interface Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
SOFTVID[4:0] DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 35
FID[3:0] DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
VCCA AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 35
Valid Voltage and Frequency Combinations . . . . . . . . . . . . . . 36
VCC_CORE AC and DC Characteristics . . . . . . . . . . . . . . . . . . 37
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 11. VCC_CORE Voltage and Current . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 12. SYSCLK and SYSCLK# DC Characteristics . . . . . . . . . . . . . . . 41
Table 13. SYSCLK and SYSCLK# AC Characteristics . . . . . . . . . . . . . . . 42
Table 14. AMD Duron™ System Bus DC Characteristics . . . . . . . . . . . . . 43
Table 15. AMD Duron System Bus AC Characteristics . . . . . . . . . . . . . . . 44
Table 16. General AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . . . 45
Table 17. Thermal Diode Electrical Characteristics . . . . . . . . . . . . . . . . . 48
Table 18. Guidelines for Platform Thermal Protection of the
Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 19. Reserved Pins (N1, N3, and N5) DC Characteristics . . . . . . . . 51
Table 20. FID_Change Induced PLL Lock Time . . . . . . . . . . . . . . . . . . . . 52
Table 21. CPGA Mechanical Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 22. Dimensions for the CPGA Package . . . . . . . . . . . . . . . . . . . . . . 58
Table 23. Pin Name Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 24. Cross-Reference by Pin Location . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 25. SOFTVID[4:0] and VID[4:0] Code to Voltage Definition . . . . . 82
Table 26. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 27. Acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
List of Tables
ix
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
x
List of Tables
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Revision History
Date
Rev
Description
Updated data sheet for the 1.0 GHz AMD Duron Processor Model 7 release.
Revised the following sections:
■
■
■
■
Table 3, “Thermal Design Power,” on page 31
December 2001
November 2001
F
Table 8, “Valid Voltage and Frequency Combinations,” on page 36
Table 11, “VCC_CORE Voltage and Current,” on page 40
“Ordering Information” on page 85
E
Revised “Thermal Protection Characterization” on page 49.
Updated data sheet for the 950 MHz AMD Duron Processor Model 7 release.
Revised the following sections:
■
■
■
■
■
■
“Processor Performance States and the FID_Change Protocol” on page 12
“SYSCLK Multipliers” on page 24
“Thermal Diode Characteristics” on page 48
Figure 13, “Signal Relationship Requirements During Power-Up Sequence” on page 53
“Power-Up Timing Requirements” on page 54
November 2001
D
“Clock Multiplier Selection (FID[3:0])” on page 56
Added the following sections and figures:
■
■
“Open Drain Test Circuit” and Figure 12, “General ATE Open Drain Test Circuit” on page 47.
“Thermal Protection Characterization” on page 49 and Table 18, “Guidelines for Platform Thermal
Protection of the Processor,” on page 51
September 2001
August 2001
C
B
Updated Figure 9 on page 38.
Initial public release.
Revision History
xi
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
xii
Revision History
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
1
Overview
The Mobile AMD Duron™ Processor Model 7 enables an optimized
PC solution for value-conscious business and home users by
providing the capability and flexibility to meet their computing
needs for both today and tomorrow.
Th e m ob ile AMD Du ron ™ p roce ssor m od e l 7 is t h e la t e st
offe r in g from AMD d e sign e d for t h e va lu e se gm e n t of t h e
notebook PC market. The innovative design was developed to
accommodate new and more advanced applications, meeting
the requirements of today's most demanding value-conscious
buyers without compromising their budget. Model 7 is the CPU
m od e l nu m b e r re t u r n e d by t h e CP U ID in st r u ct ion for t h is
processor. See Chapter 5, “CPUID Support” on page 29 for
more information.
De live r e d in a CP GA p a ck a ge , t h e m ob ile AMD Du r on
processor model 7 is the new AMD workhorse processor for
value notebook systems, delivering high performance integer,
floating-point and 3D multimedia capabilities for applications
running on notebook PC platforms. The mobile AMD Duron
processor model 7 provides value-conscious cust omers with
a cce ss t o a d va n ce d t e ch n ology t h a t a llows t h e ir syst e m
investment to last for years to come.
Whether at work or at play, the mobile AMD Duron processor
m od e l 7 p rovid es a n op t imum b ala n ce of p e rform a n ce an d
value for today’s advanced operating system software, business
p rod u ct ivit y a p p lica t ion s, In t e r n e t com p u t in g a n d d igit a l
entertainment.
Th e m ob ile AMD Du r on p r oce ssor m od e l 7 fe a t u r e s a
se ve n t h -ge n e r a t ion m icr oa r ch it e ct u r e wit h a fu ll-sp e e d
integrated L2 cache, which supports the growing processor and
syst e m b a n d wid t h r e q u ir e m e n t s of e m e r gin g soft wa r e ,
gra p h ics, I/O, a n d m e m ory t e ch n ologie s. Th e h igh -sp e e d
e xe cu t ion cor e of t h e p r oce ssor in clu d e s m u lt ip le x86
instruction decoders, a dual-ported 128-Kbyte split level-one
(L1) cache, a 64-Kbyte on-chip L2 cache, three independent
integer pipelines, three address calculation pipelines, and a
s u p e r s c a l a r, f u l ly p i p e l i n e d , o u t -o f -o r d e r, t h r e e -wa y
floating-point engine. The floating-point engine is capable of
delivering 4.0 gigaflops (Gflops) of single-precision and more
than 2.0 Gflops of double-precision floating-point resu lts at
Chapter 1
Overview
1
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
1.0 GHz, for superior performa nce on nume rica lly com plex
applications.
This processor incorpora tes AMD PowerNow!™ te chnology,
enabling performance and power saving modes specifically for
notebook designs and is available in a low-profile, lidless CPGA
package.
The mobile AMD Duron processor model 7 microarchitecture
in corp ora t e s AMD’s 3DNow!™ P rofe ssion a l t e ch n ology, a
h igh -p e r for m a n ce ca ch e a r ch it e ct u r e , a n d t h e 200-MH z
1 .6 -G i g a b y t e p e r s e c o n d A M D D u r o n s y s t e m b u s . Th e
AMD Du ron syst e m b u s com b in e s t h e la t e st t e ch n ologica l
advances, such as point-to-point topology, source-synchronous
packet-based transfers, and low-voltage signaling, to provide a
powerful, scalable bus architecture.
The mobile AMD Duron processor model 7 is binary-compatible
with existing x86 software and substantially compatible with
applications optimized for 3DNow! Professional, MMX™, and
SSE in st r u ct ion s. AMD’s 3DNow! P rofe ssion a l t e ch n ology
im p le m en t ed in t h e m ob ile AMD Du ron p roce ssor m od e l 7
i n c l u d e s n e w i n t e g e r m u l t i m e d i a i n s t r u c t i o n s a n d
soft wa re -d ire ct e d d a t a m ove m e n t in st r u ct ion s t o d e live r
exceptional performance in multimedia applications.
1.1
Mobile AMD Duron™ Processor Model 7 Upgrades Versus the
Mobile AMD Duron™ Processor Model 3
Th e followin g fe a t u re s su m m a r ize t h e m ob ile AMD Du ron
processor model 7 feature upgrades and differences from the
mobile AMD Duron processor model 3:
■ AMD PowerNow! technology for improved battery life
•
Model Specific Registers (MSRs) and SOFTVID and FID
control pins which are compatible with the mobile
AMD Athlon™ processor model 6
•
Automatic load sense
■ Redesigned core, optimized for lower power and improved
frequency scalability
■ On-die temperature sensing diode
2
Overview
Chapter 1
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
1.2
Mobile AMD Duron™ Processor Model 7 Microarchitecture
Summary
Th e followin g fe a t u re s su m m a r ize t h e m ob ile AMD Du ron
processor model 7 microarchitecture:
■ Performance on demand and extended battery life
specifically for notebook designs with AMD PowerNow!
technology
■ The industry's first nine-issue, superpipelined, superscalar
x86 processor microarchitecture designed for high clock
frequencies
■ Multiple x86 instruction decoders
■ Three
out-of-order,
superscalar,
fully
pipelined
floating-point execution units, which execute all x87
(floating-point), SSE, MMX, and 3DNow! Professional
instructions
■ Three out-of-order, superscalar, pipelined integer units
■ Three
out-of-order,
superscalar,
pipelined
address
calculation units
■ 72-entry instruction control unit
■ Advanced dynamic branch prediction
■ 3DNow! Professional technology with added instructions to
enable improved integer math calculations for speech or
video encoding and improved data movement for internet
plug-ins and other streaming applications
■ 200-MHz AMD Duron system bus for high-performance main
memory access, multimedia, graphics, and I/O
■ High-performance
cache
architecture
featuring an
integrated 128-Kbyte L1 cache and a 16-way, on-chip
64-Kbyte L2 cache
Chapter 1
Overview
3
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
The mobile AMD Duron processor model 7 delivers superior
n o t e b o o k P C s y s t e m p e r fo r m a n c e i n a c o s t -e f f e c t ive ,
industry-standard Socket A compatible 462-pin CPGA package.
Figure 1 shows a typical mobile AMD Duron processor model 7
system block diagram.
Mobile AMD Duron™
Processor Model 7
Programmable
Voltage Regulator
Thermal Monitor
AGP Bus
AMD Duron
System Bus
AGP
Memory Bus
System Controller
SDRAM or DDR
(Northbridge)
PCI Bus
Peripheral Bus
Controller
(Southbridge)
Docking
Controller
LAN
PC Card
Modem / Audio
ISA or LPC
USB
Dual EIDE
Super I/O
Embedded Controller
Battery
Figure 1. Typical Mobile AMD Duron™ Processor Model 7 System Block Diagram
4
Overview
Chapter 1
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
2
Interface Signals
2.1
Overview
Th e AMD Du ron ™ syst e m b u s a rch it e ct u re is d e sign e d t o
d e l ive r e x ce l l e n t d a t a m ove m e n t b a n d w id t h fo r n e x t -
ge n e ra t ion x86 p la t for m s a s we ll a s t h e h igh -p e r for m a n ce
required by enterprise-class application software. The system
b u s a rch it e ct u re con sist s of t h re e h igh -sp e e d ch a n n e ls (a
u n id ire ct ion a l p roce ssor re q u e st ch a n n e l, a u n id ire ct ion a l
p r ob e ch a n n e l, a n d a 72-b it b id ire ct ion a l d a t a ch a n n e l),
source-synchronous clocking, and a packet-based protocol. In
addition, the system bus supports several control, clock, and
le ga cy sign a ls. Th e in t e r fa ce sign a ls u se a n im p e d a n ce
controlled push-pull, low-voltage, swing-signaling technology
contained within the Socket A socket.
For more information, see “AMD Duron™ System Bus Signals”
on page 6, Chapter 10, “Pin Descriptions” on page 61, and the
AMD At h lon ™ a n d AMD Du ron ™ Syst em Bu s Specificat ion,
order# 21902.
2.2
Signaling Technology
The AMD Duron system bus uses a low-voltage, swing-signaling
technology, that ha s been enhanced to provide large r noise
ma rgin s, re d u ce d r in gin g, a n d va r iab le volt a ge leve ls. Th e
signals are push-pull and impedance compensated. The signal
in p u t s u se d iffe re n t ia l re ce ive rs t h a t re q u ire a re fe re n ce
voltage (VREF). The reference signal is used by the receivers to
determine if a signal is asserted or deasserted by the source.
Te rm in a t ion resist ors are n ot n ee d ed b e ca u se t h e d river is
impedance-matched to the motherboard and a high impedance
reflection is used at the receiver to bring the signal past the
input threshold.
For more information about pins and signals, see Chapter 10,
“Pin Descriptions” on page 61.
Chapter 2
Interface Signals
5
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
2.3
Push-Pull (PP) Drivers
The mobile AMD Duron processor model 7 supports Push-Pull
(PP) drivers. The system logic configures the processor with the
con figu ra t ion p a ra m e t e r ca lle d SysP u sh P u ll (1=P P ). Th e
impedance of the PP drivers is set to match the impedance of
the motherboard by two external resistors connected to the ZN
and ZP pins.
See “ZN and ZP Pins” on page 83 for more information.
2.4
AMD Duron™ System Bus Signals
The AMD Duron system bus is a clock-forwarded, point-to-point
interface with the following three point-to-point channels:
■ A 13-bit unidirectional output address/command channel
■ A 13-bit unidirectional input address/command channel
■ A 72-bit bidirectional data channel
For more information, see Chapter 7, “Electrical Data” on page
33 a n d t h e AMD At h lon ™ a n d AMD Du r on ™ Syst em Bu s
Specification, order# 21902.
6
Interface Signals
Chapter 2
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
3
Logic Symbol Diagram
Figure 2 is the logic symbol diagram of the processor. This
diagram shows the logical grouping of the input and out put
signals.
Clock
SYSCLK SYSCLK#
SOFTVID[4:0]
SDATA[63:0]#
VID[4:0]
COREFB
COREFB#
PWROK
Voltage
Control
SDATAINCLK[3:0]#
SDATAOUTCLK[3:0]#
SDATAINVALID#
SDATAOUTVALID#
SFILLVALID#
Data
Frequency
Control
FID[3:0]
Mobile AMD Duron™
Processor Model 7
FERR
IGNNE#
INIT#
SADDIN[14:2]#
SADDINCLK#
Probe/SysCMD
Request
Legacy
INTR
NMI
A20M#
SMI#
SADDOUT[14:2]#
SADDOUTCLK#
PROCRDY
CLKFWDRST
CONNECT
STPCLK#
FLUSH#
Power
Management
and Initialization
Thermal
Diode
THERMDA
THERMDC
RESET#
Figure 2. Logic Symbol Diagram
Chapter 3
Logic Symbol Diagram
7
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
8
Logic Symbol Diagram
Chapter 3
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
4
Power Management
This chapter describes the power management features of the
m o b i l e A M D D u r o n ™ p r o c e s s o r m o d e l 7 . Th e p owe r
management features of the processor are compliant with the
AC P I 1 . 0 b a n d AC P I 2 . 0 s p e c i f i c a t i o n s a n d s u p p o r t
AMD PowerNow!™ technology.
4.1
Power Management States
The mobile AMD Duron™ processor model 7 has a variety of
operating states that are designed to support different power
management goals. In addition to the standard operating state,
the processor supports low-power Halt and Stop Grant states
and the FID_Change state. These states are used by Advanced
Configuration and Power Interface (ACPI) enabled operating
systems, for processor power management. AMD PowerNow!
software is used to control processor performance states with
op e r a t in g syst e m s t h a t d o n ot su p p or t ACP I 2.0-d e fin e d
processor performance state control.
Figure 3 on page 10 shows the power management states of the
p r oce ssor. Th e figu r e in c lu d e s t h e AC P I “ Cx” n a m in g
convention for these states.
Chapter 4
Power Management
9
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Write to FidVidCtl MSR
Execute HLT
C1
Halt
C0
Working4
FID_Change
SIP Stream and
SMI#, INTR, NMI, INIT#, RESET#
System Bus Connect
P
S
T
P
C
L
K
#
r
S
T
P
C
L
K
#
o
b
e
S
S
d
S
d
T
T
e
e
e
P
P
a
a
r
C
L
K
C
s
s
s
v
L
s
e
K
e
r
i
r
t
#
c
#
t
e
e
d
e
a
d
3
a
s
d
s
s
s
e
e
r
t
r
t
e
e
d
2
d
C3/S1
Stop Grant
Cache Not Snoopable
Sleep
Incoming Probe
Probe Serviced
C2
Probe
State1
Stop Grant
Cache Snoopable
Legend
Hardware transitions
Software transitions
Note:
The AMD DuronTM System Bus is connected during the following states:
1) The Probe state
2) During transitions between the Halt state and the C2 Stop Grant state
3) During transitions between the C2 Stop Grant state and the Halt state
4) C0 Working state
Figure 3. Mobile AMD Duron™ Processor Model 7 Power Management States
Th e followin g se ct ion s p r ovid e a n ove r vie w of t h e p owe r
management states. For more details, refer to the AMD Athlon™
and AMD Duron™ System Bus Specification, order# 21902.
Note: In all power management states that the processor is
powered, the system must not stop the system clock
(SYSCLK/SYSCLK#) to the processor.
Working State
Halt State
The Working state is the state in which the processor is executing
instructions.
When the processor executes the HLT instruction, the processor
e n t e rs t h e H a lt st a t e a n d issu e s a H a lt sp e cia l cycle t o t h e
AMD Duron system bus. The processor only enters the low power
st at e d ict a t e d by t h e CLK_Ct l MSR if t h e syst em con t roller
(Nor t h b r id ge ) d iscon n e ct s t h e AMD Du ron syst e m b u s in
response to the Halt special cycle.
10
Power Management
Chapter 4
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
If STPCLK# is asserted, the processor will exit the Halt state
and enter the Stop Grant state. The processor will initiate a
syste m bus conne ct, if it is disconne ct ed, t hen issue a Stop
Gr a n t sp e cia l cycle . Wh e n STP CLK# is d e a sse r t e d , t h e
processor will exit the Stop Grant state and re-enter the Halt
st a t e . Th e p roce ssor will issu e a H a lt sp e cia l cycle wh e n
re-entering the Halt state.
Th e H a lt st a t e is e xit e d wh e n t h e p r oce ssor d e t e ct s t h e
assertion of INIT#, INTR, NMI, RESET#, or SMI#. When the
Halt state is exited the processor will initiate an AMD Duron
system bus connect if it is disconnected.
Stop Grant States
When the processor executes the HLT instruction, the processor
e n t e rs t h e H alt st a t e an d issu e s a H alt sp ecial cycle t o t h e
AMD Du ron syst em b u s. Th e p roce ssor on ly e n t e rs t h e low
p owe r st a t e d ict a t e d b y t h e CLK_Ct l MSR if t h e syst e m
controller (Northbridge) disconnects the AMD Duron system
bus in response to the Halt special cycle.
If STPCLK# is asserted, the processor will exit the Halt state
and enter the Stop Grant state. The processor will initiate a
syste m bus conne ct, if it is disconne ct ed, t hen issue a Stop
Gr a n t sp e cia l cycle . Wh e n STP CLK# is d e a sse r t e d , t h e
processor will exit the Stop Grant state and re-enter the Halt
st a t e . Th e p roce ssor will issu e a H a lt sp e cia l cycle wh e n
re-entering the Halt state.
Th e H a lt st a t e is e xit e d wh e n t h e p r oce ssor d e t e ct s t h e
assertion of INIT#, INTR, NMI, RESET#, or SMI#. When the
Halt state is exited the processor will initiate an AMD Duron
system bus connect if it is disconnected.
In C2, probes are allowed, as shown in Figure 3 on page 10.
The operating syst em places th e processor into t he C3 Stop
Grant state by reading the P_LVL3 register in the Southbridge.
In C3, the operating system and Northbridge hardware enforce
a policy that prevents the processor from being probed. The
Southbridge will deassert STPCLK# and bring the processor
out of the C3 Stop Grant state if a bus master request, interrupt,
or any other enabled resume event occurs.
The Stop Grant state is also entered for the S1, Powered On
Suspend, system sleep state based on a write to the SLP_TYP
Chapter 4
Power Management
11
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
and SLP_EN fields in the ACPI-defined Power Management 1
control register in the Southbridge. During the S1 sleep state,
system software ensures no bus master or probe activity occurs.
The Southbridge deasserts STPCLK# and brings the processor
out of the S1 Stop Grant state when any enabled resume event
occurs.
Probe State
The Probe state is entered when the Northbridge connects the
AMD Duron system bus to probe the processor (for example, to
snoop the processor caches) when the processor is in the Halt or
St op Gra n t st a t e . Wh e n in t h e P rob e st a t e , t h e p roce ssor
responds to a probe cycle in the same manner as when it is in
t h e Work in g st a t e . Wh e n t h e p rob e h a s b e e n se rvice d , t h e
p roce ssor re t u r n s t o t h e sa m e st a t e a s wh e n it e n t e red t h e
Probe state (Halt or Stop Grant state). When probe activity is
completed the processor only returns to a low-power state after
the Northbridge disconnects the AMD Duron system bus again.
FID_Change State
The FID_Change State is part of the AMD Duron system bus
F ID_Ch a n ge P rot ocol. Du r in g t h e F ID_Ch a n ge st a t e t h e
Frequency Identification (FID[4:0]) code that determines the
core fre q u en cy of th e p roce ssor a n d Volt age Id e n t ificat ion
(VID[4:0]) driven on the SOFTVID[4:0] pins are transitioned to
change the core frequency and core voltage of the processor.
Note: The FID[3:0] pins of the processor do not transition as part
of the FID_Change protocol.
Processor
The FID_Change protocol is used by AMD PowerNow! software
t o t ra n sit ion t h e p roce ssor from on e p e r for m a n ce st a t e t o
a n ot h e r. Th e F ID_Ch a n ge p r ot ocol is a lso u se d for ACP I
2.0-compliant processor performance state control.
Performance States
and the FID_Change
Protocol
Processor performance states are combinations of processor
core voltage and core frequency. Processor performance states
are used in mobile systems to optimize the power consumption
of t h e p roce ssor (a n d t h e re fore b a t t e ry p owe re d r u n -t im e )
based upon processor utilization.
See “Valid Voltage and Frequency Combinations” on page 36
for more information.
The core frequency is determined by a 5-bit Frequency ID (FID)
code. The core voltage is determined by a 5-bit Voltage ID (VID)
code.
12
Power Management
Chapter 4
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
■ Before PWROK is asserted to the processor, the VID[4:0]
outputs of the processor dictate the core voltage level of the
processor.
■ After PWROK is asserted, the core voltage of the processor
is dictated by the SOFTVID[4:0] outputs. The SOFTVID[4:0]
outputs of the processor are not driven to a deterministic
value until after PWROK is asserted to the processor. The
motherboard therefore must provide a ‘VID Multiplexer’ to
drive the VID[4:0] outputs to the DC/DC converter for the
core voltage of the processor before PWROK is asserted and
drive the SOFTVID[4:0] outputs to the DC to DC converter
after PWROK is asserted.
■ The FID[3:0] signals are valid after PWROK is asserted. The
chipset must not sample the FID[3:0] signals until they
become valid.
■ After RESET# is deasserted, the FID[3:0] outputs are not
used to transmit FID information for subsequent software
controlled changes in the operating frequency of the
processor.
■ Processor performance state transitions are required to
occur as two separate transitions. The order of these
transitions depends on whether the transition is to a higher
or lower performance state. When transitioning from a lower
performance state to a higher performance state the order
of the transitions is:
1. The FID_Change protocol is used to transition to the
higher voltage, while keeping the frequency fixed at
the current setting.
2. The FID_Change protocol is then used to transition to
the higher frequency, while keeping the voltage fixed
at the higher setting.
When transitioning from a high performance state to a
lower performance state the order of the transitions is:
1. The FID_Change protocol is used to transition to the
lower frequency, while keeping the voltage fixed at its
current setting.
2. The FID_Change protocol is then used to transition to
the lower voltage, while keeping the frequency fixed at
the lower setting.
■ The processor provides two MSRs to support the
FID_Change protocol: the FidVidCtl MSR and the
Chapter 4
Power Management
13
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
FidVidStatus MSR. For a definition of these MSRs and their
use, refer to the Mobile AMD Athlon™ and Mobile
AMD Duron™ Processors BIOS Developers Application Note,
order# 24141.
FID_Change Protocol Description By Example:
Note: In any FID_Change transition only the core voltage or core
frequency of the processor is transitioned. Two FID_Change
transitions are required to transition the voltage and
frequency to a valid performance state. When the voltage is
being transitioned, the frequency is held constant by
transitioning to the same FID[3:0] as the current FID
reported in the FidVidStatus MSR.
For d e t a ile d in for m a t ion on t h e op t im ize d volt a ge a n d
frequency combinations, see “Valid Voltage and Frequency
Combinations” on page 36.
■ System software determines that a change in processor
performance state is required.
■ System software executes a WRMSR instruction to write to
the FidVidCtl MSR to dictate:
•
The new VID[4:0] code that will be driven to the DC/DC
converter from the SOFTVID[4:0] outputs of the
processor that selects the new core voltage level.
•
•
The new FID[4:0] code that will be used by the processor
to dictate its new operating frequency.
A Stop Grant Timout Count (SGTC)[19:0] value that
determines how many SYSCLK/SYSCLK# 100-MHz clock
periods the processor will remain in the FID_Change
state. This time accounts for the time that it takes for the
PLL of the processor to lock to the new core frequency
and the time that it takes for the core voltage of the
processor to ramp to the new value.
•
•
The FIDCHGRATIO bit must be set to 1.
The VIDC bit must be set to a 1 if the voltage is going to
be changed.
•
The FIDC bit must be set to a 1 if the frequency is going
to be changed.
Writing the SGTC field to a non-zero value initiates the
FID_Change protocol.
14
Power Management
Chapter 4
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
■ On the instruction boundary that the SGTC field of the
FidVidCtl MSR is written to a non-zero value, the processor
stops code execution and issues a FID_Change special cycle
on the AMD Duron system bus.
■ The FID_Change special cycle has a data encoding of
0007_0002h that is passed on SDATA[31:0].
■ SDATA[36:32] contain the new FID[4:0] code during the
FID_Change special cycle. The Northbridge is required to
capture this FID[4:0] code when the FID_Change special
cycle is run.
■ In response to receiving the FID_Change special cycle, the
Northbridge is required to disconnect. The Northbridge will
complete any in-progress bus cycles and then disable its
arbiter before disconnecting the AMD Duron system bus so
that it will not initiate a AMD Duron system bus connect
based on bus master or other activity. The Northbridge must
disconnect the AMD Duron system bus or the system will
hang because the processor is not executing any operating
system or application code and is waiting for the
AMD Duron system bus to disconnect so that it can continue
with the FID_Change protocol. The Northbridge initiates an
AMD Duron system bus disconnect in the usual manner: it
deasserts CONNECT.
■ The processor allows the disconnect to complete by
deasserting PROCRDY. The Northbridge completes the
disconnect by asserting CLKFWDRST.
■ Once the AMD Duron system bus has been disconnected in
response to a FID_Change special cycle, the Northbridge is
not allowed to initiate a re-connect, the processor is
responsible for the eventual re-connect.
■ After the AMD Duron system bus is disconnected, the
processor enters a low-power state where the clock grid is
ramped down by a value specified in the CLK_Ctl MSR.
■ After entering the low-power state, the processor will:
•
•
•
begin counting down the value that was programmed into
the SGTC field
drive the new VID[4:0] value on SOFTVID[4:0], causing
its core voltage to transition
drive the new FID[4:0] value to its PLL, causing the PLL
to lock to the new core frequency.
Chapter 4
Power Management
15
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
■ When the SGTC count reaches zero, the processor will ramp
its entire clock grid to full frequency (the PLL is already
locked to) and signal that it is ready for the Northbridge to
transmit the new SIP (Serial Initialization Protocol) stream
associated with the new processor core operating frequency.
The processor signals this by pulsing PROCRDY high and
then low.
■ The Northbridge responds to this high pulse on PROCRDY
by pulsing CLKFWDRST low and then transferring a SIP
stream as it does after PROCRDY is deasserted after the
deassertion of RESET#. The difference is that the SIP
stream that the Northbridge transmits to the processor now
corresponds to the FID[4:0] that was transmitted on
SDATA[36:32] during the FID_Change special cycle.
■ After the SIP stream is transmitted, the processor initiates
the AMD Duron system bus connect sequence by asserting
PROCRDY. The Northbridge responds by deasserting
CLKFWDRST. The forward clocks are started and the
processor issues a Connect special cycle.
■ The AMD Duron system bus connection causes the processor
to resume execution of operating system and application
code at the instruction that follows the WRMSR to the
FidVidCtl MSR that started the FID_Change protocol and
processor performance state transition.
16
Power Management
Chapter 4
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Figure 4 below illustrates the processor SOFTVID transition during the
AMD Du ron syst e m b u s d iscon n e ct in re sp on se t o a F ID_Ch a n ge
special cycle.
< 100 µs
1.4 V
1.2 V
CPUCOREVCC
SOFTVID[4:0] from the
processor
VID combination that
VID combination that selects 1.2 V
selects 1.4 V
ProcRdy
Connect
ClkFwdRst
The processor core frequency changes and new
SOFTVID[4:0] values are driven after the system
bus interface disconnect occurs and the
processor has entered a low power state. The
duration of the disconnect is dictated by
software programming the FidVidControl MSR in
the processor.
Figure 4. SOFTVID Transition During the AMD Duron™ System Bus Disconnect for FID_Change
Chapter 4
Power Management
17
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
4.2
Connect and Disconnect Protocol
Sign ifica n t p owe r savin gs of t h e p roce ssor on ly occu r if t h e
processor is disconnected from the system bus by the Northbridge
wh ile in t h e H a lt or St op Gra n t st a t e . Th e Nor t h b r id ge ca n
optionally initiate a bus disconnect upon the receipt of a Halt or
Stop Grant special cycle. The option of disconnecting is controlled
by an enable bit in the Northbridge. If the Northbridge requires
the processor to service a probe after the system bus has been
disconnected, it must first initiate a system bus connect.
Connect Protocol
In addition to the legacy STPCLK# signal and the Halt and Stop
Grant special cycles, the AMD Duron system bus connect protocol
includes the CONNECT, PROCRDY, and CLKFWDRST signals and
a Connect special cycle.
A MD Du r o n sy st e m b u s d isc o n n e ct s a r e i n i t i a t e d b y t h e
Northbridge in response to the receipt of a Halt, Stop Grant, or
FID_Change special cycle. Reconnect is initiated by the processor
in response to a n interrupt for Halt, STP CLK# deassertion, or
completion of a FID_Change transition. Reconnect is initiated by
the Northbridge to probe the processor. The Northbridge contains
BIOS programmable registers to enable the system bus disconnect
in re sp on se t o H a lt a n d St op Gra n t sp e cia l cycle s. Wh e n t h e
Northbridge receives the Halt or Stop Grant special cycle from the
p r oce ssor a n d , if t h e r e a r e n o ou t st a n d in g p r ob e s or d a t a
movements, the Northbridge deasserts CONNECT a minimum of
e igh t SYSCLK p e r iod s a ft e r t h e la st com m a n d se n t t o t h e
processor. The processor detects the deassertion of CONNECT on a
r i s i n g e d g e o f S YS C L K a n d d e a s s e r t s P R O C R DY t o t h e
Northbridge. In return, the Northbridge asserts CLKFWDRST in
anticipation of reestablishing a connection at some later point.
Note: The Northbridge must disconnect the processor from the
AMD Duron system bus before issuing the Stop Grant special
cycle to the PCI bus or passing the Stop Grant special cycle to
the Southbridge for systems that connect to the Southbridge
with HyperTransport™ technology.
This note applies to current chipset implementation—
alternate chipset implementations that do not require this are
possible.
Note: In response to Halt special cycles, the Northbridge passes the
Halt special cycle to the PCI bus or Southbridge immediately.
18
Power Management
Chapter 4
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
The processor can receive an interrupt after it sends a Halt
special cycle, or STPCLK# deassertion after it sends a Stop
Gr a n t s p e cia l cycle t o t h e Nor t h b r id ge b u t b e for e t h e
disconnect actually occurs. In this case, the processor sends the
Con n e ct sp e cia l cycle t o t h e Nor t h b r id ge , r a t h e r t h a n
continuing with the disconnect sequence. In response to the
Connect special cycle, the Northbridge cancels the disconnect
request.
The system is required to assert the CONNECT signal before
returning the C-bit for the connect special cycle (assum ing
CONNECT has been deasserted).
For more information, see the AMD Athlon™ and AMD Duron™
System Bus Specification, order# 21902 for the definition of the
C-bit and the Connect special cycle.
Chapter 4
Power Management
19
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Figure 5 shows STPCLK# assertion resulting in the processor in the
Stop Grant state and the AMD Duron system bus disconnected.
STPCLK#
AMD Duron™
System Bus
Stop Grant
CONNECT
PROCRDY
CLKFWDRST
PCI Bus
Stop Grant
Figure 5. AMD Duron™ System Bus Disconnect Sequence in the Stop Grant State
An example of the AMD Duron system bus disconnect sequence is as
follows:
1. The peripheral controller (Southbridge) asserts STPCLK# to
place the processor in the Stop Grant state.
2. When the processor recognizes STPCLK# asserted, it enters the
Stop Grant state and then issues a Stop Grant special cycle.
3. When the special cycle is received by the Northbridge, it
deasserts CONNECT, assuming no probes are pending, initiating
a bus disconnect to the processor.
4. The processor responds to the Northbridge by deasserting
PROCRDY.
5. The Northbridge asserts CLKFWDRST to complete the bus
disconnect sequence.
6. After the processor is disconnected from the bus, the processor
enters a low-power state. The Northbridge passes the Stop Grant
special cycle along to the Southbridge.
20
Power Management
Chapter 4
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Figu re 6 sh ows t h e sign a l se q u e n ce of e ve n t s t h a t t a k e s t h e
processor out of the Stop Grant state, connects the processor to the
AMD Duron system bus, and puts the processor into the Working
state.
STPCLK#
PROCRDY
CONNECT
CLKFWDRST
Figure 6. Exiting the Stop Grant State and Bus Connect Sequence
The following sequence of events removes the processor from the
Stop Grant state and connects it to the system bus:
1. The Southbridge deasserts STPCLK#, informing the processor of
a wake event.
2. When the processor recognizes STPCLK# deassertion, it exits
the low-power state and asserts PROCRDY, notifying the
Northbridge to connect to the bus.
3. The Northbridge asserts CONNECT.
4. The Northbridge deasserts CLKFWDRST, synchronizing the
forwarded clocks between the processor and the Northbridge.
5. The processor issues a Connect special cycle on the system bus
and resumes operating system and application code execution.
Chapter 4
Power Management
21
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Connect State
Diagram
Figure 7 and Figure 8 on page 23 describe the Northbridge and
processor connect state diagrams, respectively.
4/A
1
2/A
Disconnect
Pending
Disconnect
Requested
Connect
3/C
3
5/B
8
8
Reconnect
Pending
Probe
Pending 2
Disconnect
7/D,C
6/C
7/D
Probe
Pending 1
Condition
Action
1 A disconnect is requested and probes are still pending.
2 A disconnect is requested and no probes are pending.
3 A Connect special cycle from the processor.
4 No probes are pending.
Deassert CONNECT eight SYSCLK periods
after last SysDC sent.
A
B Assert CLKFWDRST.
C Assert CONNECT.
D Deassert CLKFWDRST.
5 PROCRDY is deasserted.
6 A probe needs service.
7 PROCRDY is asserted.
Three SYSCLK periods after CLKFWDRST is deasserted.
Although reconnected to the system interface, the
8
Northbridge must not issue any non-NOP SysDC
commands for a minimum of four SYSCLK periods after
deasserting CLKFWDRST.
Figure 7. Northbridge Connect State Diagram
22 Power Management
Chapter 4
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Connect
6/B
1
2/B
Connect
Pending 2
Disconnect
Pending
5
Connect
Pending 1
3/A
Disconnect
4/C
Condition
Action
CONNECT is deasserted by the Northbridge (for a
previously sent Halt or Stop Grant special cycle).
A CLKFWDRST is asserted by the Northbridge.
B Issue a Connect special cycle.*
1
2
Processor receives a wake-up event and must cancel
the disconnect request.
Return internal clocks to full speed and assert
C
PROCRDY.
3 Deassert PROCRDY and slow down internal clocks.
Note:
*
The Connect special cycle is only issued after a
processor wake-up event (interrupt or STPCLK#
deassertion) occurs. If the AMD Duron™ system
bus is connected so the Northbridge can probe the
processor, a Connect special cycle is not issued at
that time (it is only issued after a subsequent
processor wake-up event).
Processor wake-up event or CONNECT asserted by
Northbridge.
4
5 CLKFWDRST is deasserted by the Northbridge.
Forward clocks start three SYSCLK periods after
CLKFWDRST is deasserted.
6
Figure 8. Processor Connect State Diagram
Chapter 4
Power Management
23
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
4.3
Clock Control
The processor implem ents a Clock Control (CLK_Ct l) MSR
(a d d re ss C001_001Bh ) t h a t d e t e r m in e s t h e in t e r n a l clock
divisor when the AMD Duron system bus is disconnected.
Refer to the AMD Athlon™ and AMD Duron™ Processors BIOS,
Software, and Debug Developers Guide, order# 21656, for more
details on the CLK_Ctl register.
4.4
SYSCLK Multipliers
The processor provides two mechanisms for communicating
p r oce ssor cor e op e r a t in g fr e q u e n cy in for m a t ion t o t h e
Northbridge. These are the processor FID[3:0] outputs and the
FID_Change special cycle. The FID[3:0] outputs specify the
core frequency of the processor as a multiple of the 100-MHz
input clock (SYSCLK/SYSCLK#) of the processor.
The FID[3:0] signals are valid after PWROK is asserted. The
chipset must not sample the FID[3:0] signals until they become
valid.The FID[3:0] outputs of the processor provide processor
operating frequency information that the Northbridge uses
when creating the SIP stream that the Northbridge sends to the
processor after RESET# is deasserted. The FID[3:0] outputs
always select a 5x SYSCLK multiplier:
FID[3:0] = 0 1 0 0
Software will use the FID_Change protocol to transition the
processor to the desired performance state.
The FID[3:0] outputs are not used as part of the FID_Change
protocol and do not change from their RESET# value during
software-controlled processor core frequency transitions.
Th e F ID_Ch a n ge sp e cia l cycle is u se d t o com m u n ica t e
processor operating frequency information to the Northbridge
d u r in g soft wa r e -con t r olle d p r oce ssor cor e volt a ge a n d
frequency (performance state) transitions. The FidVidCtl MSR
a l l o w s s o f t wa r e t o s p e c i f y a 5 -b i t F I D v a l u e d u r i n g
software-controlled processor performance state transitions.
Th e a d d it ion a l b it a llows t r a n sit ion s t o lowe r SYSCLK
multipliers of 3x to 4x as well as all other SYSCLK multipliers
supported by the processor.
24
Power Management
Chapter 4
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
For a d e scr ip t ion of t h e F ID_Ch a n ge p rot ocol re fe r t o t h e
earlier section in this chapter.
Table 1 lists the FID[4:0] SYSCLK multiplier codes for the
processor used by software to dictate the core frequency of the
processor and the 5-bit value driven on SDATA[36:32]# by the
processor during the FID_Change special bus cycle.
Note: Only clock multipliers associated with operating frequencies
specified in the “Electrical Data” chapter are valid for this
processor.
Note: Software distinguishes the speed grade of the processor by
reading the MFID field of the FidVidStatus MSR.
Table 1. FID[4:0] SYSCLK Multiplier Combinations1
2,3,5
4
Clock Mode
11x
FID[4:0]
SDATA[36:32]#
11111
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
11.5x
12x
11110
11101
12.5x
5x
11100
11011
5.5x
6x
11010
11001
6.5x
7x
11000
10111
7.5x
10110
8x
10101
8.5x
10100
Notes:
1. On power up, the FID[3:0] balls are set to a clock multiplier value of 5x. After reset, software
is responsible for transitioning the processor to the desired frequency.
2. Value programmed into the FidVidCtl MSR.
3. The maximum FID that may be selected by software is reported in the FidVidStatus MSR.
4. Value driven on SDATA[36:32]# balls during the FID_Change special bus cycle. The SDATA
bus is active Low, so the SDATA[36:32]# values listed are what would be observed on the
motherboard with a digital storage scope.
5. BIOS initializes the CLK_Ctl MSR to 6007_9263h during the POST routine. This CLK_Ctl setting
is used with all FID combinations and selects a halt disconnect divisor of 128 and a Stop–Grant
disconnect divisor of 512.
Chapter 4
Power Management
25
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Table 1. FID[4:0] SYSCLK Multiplier Combinations1
2,3,5
4
Clock Mode
9x
FID[4:0]
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
SDATA[36:32]#
10011
10010
9.5x
10x
10001
10.5x
3x
10000
01111
Reserved
4x
Reserved
01101
Reserved
13x
Reserved
11100
13.5x
14x
11100
11100
Reserved
15x
Reserved
11100
Reserved
16x
Reserved
11100
16.5x
17x
11100
11100
18x
11100
Reserved
Reserved
Reserved
Reserved
Notes:
1. On power up, the FID[3:0] balls are set to a clock multiplier value of 5x. After reset, software
is responsible for transitioning the processor to the desired frequency.
2. Value programmed into the FidVidCtl MSR.
3. The maximum FID that may be selected by software is reported in the FidVidStatus MSR.
4. Value driven on SDATA[36:32]# balls during the FID_Change special bus cycle. The SDATA
bus is active Low, so the SDATA[36:32]# values listed are what would be observed on the
motherboard with a digital storage scope.
5. BIOS initializes the CLK_Ctl MSR to 6007_9263h during the POST routine. This CLK_Ctl setting
is used with all FID combinations and selects a halt disconnect divisor of 128 and a Stop–Grant
disconnect divisor of 512.
26
Power Management
Chapter 4
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
4.5
Special Cycles
I n a d d i t i o n t o t h e s p e c i a l cy c l e s d o c u m e n t e d i n t h e
AMD At h lon ™ a n d AMD Du ron ™ Syst em Bu s Specificat ion ,
order# 21902, t he processor support s the SMM Ent er, SMM
Exit, and FID_Change special cycles.
Table 2 defines the contents of SDATA[31:0] during the special
cycles.
Table 2. Processor Special Cycle Definition
Special Cycle
SMM Enter
SMM Exit
Contents of SDATA[31:0]
0005_0002h
0006_0002h
*
0007_0002h
FID_Change
Note:
*
The new FID[4:0] taken from the FID[4:0] field of the FidVidCtl MSR is driven on
SDATA[36:32] during the FID_Change special cycle.
Chapter 4
Power Management
27
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
28
Power Management
Chapter 4
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
5
CPUID Support
Th e m ob ile AMD Du ron ™ p roce ssor m od e l 7 ve rsion a n d
feature set recognition can be performed through the use of the
CPUID instruction, that provides complete information about
the processor—vendor, type, name, etc., and its capabilities.
Software can make use of this information to accurately tune
the system for maximum performance and benefit to users.
For information about the CPUID features supported by the
mobile AMD Duron processor model 7, refer to the following
documents:
■ AMD Processor Recognition Application Note, order# 20734
Chapter 5
CPUID Support
29
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
30
CPUID Support
Chapter 5
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
6
Thermal Design
The mobile AMD Duron™ processor model 7 provides a diode
that can be used in conjunction with an external temperature
sensor to determine the die temperature of the processor.
The diode anode (THERMDA) and cathode (THERMDC) are
available as pins on the processor.
R e fe r t o “ Th e r m a l Diod e Ch a ra ct e r ist ics” on p a ge 48 a n d
“THERMDA and THERMDC Pins” on page 83 for more details.
For in form at ion ab ou t t h e u sa ge of t h is d iod e a n d t h e rm a l
design, including layout and airflow considerations, see the
Mobile System Thermal Design Guidelines, order# 24383.
Table 3 shows the thermal design power.
Table 3. Thermal Design Power
Thermal Design
Frequency
(MHz)
Voltage
1
Power
1.50 V
1.50 V
1.45 V
1.45 V
1.40 V
25 W
25 W
25 W
25 W
25 W
800
850
900
950
1000
Notes:
1. Thermal design power represents the maximum sustained power dissipated while executing
publicly-available software or instruction sequences under normal system operation at
nominal VCC_CORE. Thermal solutions must monitor the temperature of the processor to
prevent the processor from exceeding its maximum die temperature. Specified through
characterization for a die temperature of 95°C.
Chapter 6
Thermal Design
31
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
32
Thermal Design
Chapter 6
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
7
Electrical Data
7.1
Conventions
The conventions used in this chapter are as follows:
■ Current specified as being sourced by the processor is
negative.
■ Current specified as being sunk by the processor is positive.
7.2
Interface Signal Groupings
The electrical data in this chapter is presented separately for
each signal group.
Table 4 defines each group and the signals contained in each
group.
Table 4. Interface Signal Groupings
Signal Group
Signals
Notes
See “” on page 38, “Soft Voltage
Identification (SOFTVID[4:0])” on
page 35, “VCCA AC and DC
Characteristics” on page 35,
“VCC_CORE AC and DC
Characteristics” on page 37,
“COREFB and COREFB# Pins” on
page 78, “SOFTVID[4:0] and
VID[4:0] Pins” on page 81, and
“VCCA Pin” on page 83.
Power
VID[4:0], SOFTVID[4:0], VCCA, VCC_CORE, COREFB, COREFB#
See “Frequency Identification
(FID[3:0])” on page 35 and
“FID[3:0] Pins” on page 79.
Frequency
FID[3:0]
See “SYSCLK and SYSCLK# AC and
DC Characteristics” on page 41,
“SYSCLK and SYSCLK#” on
page 83, and “PLL Bypass and Test
Pins” on page 80.
SYSCLK, SYSCLK# (Tied to CLKIN/CLKIN# and
RSTCLK/RSTCLK#), PLLBYPASSCLK, PLLBYPASSCLK#,
System Clocks
Chapter 7
Electrical Data
33
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Table 4. Interface Signal Groupings (continued)
Signal Group
Signals
Notes
SADDIN[14:2]#, SADDOUT[14:2]#, SADDINCLK#,
SADDOUTCLK#, SFILLVALID#, SDATAINVALID#,
SDATAOUTVALID#, SDATA[63:0]#, SDATAINCLK[3:0]#,
SDATAOUTCLK[3:0]#, CLKFWDRST, PROCRDY, CONNECT
See “AMD Duron™ System Bus AC
and DC Characteristics” on page
43 and “CLKFWDRST Pin” on
page 78.
System Bus
See “General AC and DC
Characteristics” on page 45, “INTR
Pin” on page 79, “NMI Pin” on
page 80, “SMI# Pin” on page 81,
“INIT# Pin” on page 79, “A20M#
Pin” on page 78, “FERR Pin” on
page 79, “IGNNE# Pin” on
page 79, “STPCLK# Pin” on
page 82, and “FLUSH# Pin” on
page 79.
RESET#, INTR, NMI, SMI#, INIT#, A20M#, FERR, IGNNE#,
STPCLK#, FLUSH#
Southbridge
See “General AC and DC
Characteristics” on page 45.
JTAG
Test
TMS, TCK, TRST#, TDI, TDO
See “General AC and DC
Characteristics” on page 45, “PLL
Bypass and Test Pins” on page 80,
“Scan Pins” on page 81, and
“Analog Pin” on page 78,
PLLTEST#, PLLBYPASS#, PLLMON1, PLLMON2, SCANCLK1,
SCANCLK2, SCANSHIFTEN, SCANINTEVAL, ANALOG
See “General AC and DC
Characteristics” on page 45,
“DBRDY and DBREQ# Pins” on
page 79, and “PWROK Pin” on
page 80.
Miscellaneous DBREQ#, DBRDY, PWROK
See “Reserved Pins DC
Characteristics” on page 51, and
“RSVD Pins” on page 80.
Reserved
Pins N1, N3, and N5
(RSVD)
See “Thermal Diode
Characteristics” on page 48 and
“THERMDA and THERMDC Pins”
on page 83
Thermal
THERMDA, THERMDC
34
Electrical Data
Chapter 7
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
7.3
Soft Voltage Identification (SOFTVID[4:0])
Table 5 shows the SOFTVID[4:0] DC Characteristics. For more
information, see “SOFTVID[4:0] and VID[4:0] Pins” on
page 81.
Table 5. SOFTVID[4:0] DC Characteristics
Parameter
Description
Output Current Low
SOFTVID[4:0] Output High Voltage
Min
16 mA
–
Max
I
OL
SOFTVID_V
2.625V *
OH
Note:
*
The SOFTVID pins must not be pulled above this voltage by an external pullup resistor.
7.4
Frequency Identification (FID[3:0])
Table 6 shows the FID[3:0] DC characteristics. For more
information, see “FID[3:0] Pins” on page 79.
Table 6. FID[3:0] DC Characteristics
Parameter
Description
Output Current Low
Output High Voltage
Min
16 mA
–
Max
I
OL
V
2.625 V *
OH
Note:
*
The FID pins must not be pulled above this voltage by an external pullup resistor.
7.5
VCCA AC and DC Characteristics
Table 7 shows the AC and DC characteristics for VCCA. For
more information, see “VCCA Pin” on page 83.
Table 7. VCCA AC and DC Characteristics
Symbol
Parameter
Min
2.25
0
Nom
Max
2.75
50
Units
V
Notes
V
VCCA Pin Voltage (AC and DC)
VCCA Pin Current
2.5
1
2
VCCA
I
mA/GHz
VCCA
Notes:
1. Minimum and maximum voltages are absolute. No transients below minimum nor above maxiumum voltages are permitted.
2. Measured at 2.5 V.
Chapter 7
Electrical Data
35
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
7.6
Decoupling
Se e t h e AMD At h lon ™ Processor-Ba sed Mot h erboa rd Design
Gu ide, ord e r # 24363, or con t a ct you r loca l AMD office for
information about the decoupling required on the motherboard
for use with the mobile AMD Duron™ processor model 7.
7.7
Valid Voltage and Frequency Combinations
Table 8 specifies the valid voltage and frequency combinations
that this processor is characterized to operate. The Maximum
Frequency column corresponds to the rated frequency of the
processor. The Maximum FID (MFID) field in the FidVidStatus
MSR is used by software to determine the maximum frequency
of t he processor. Each row in the table shows the m aximum
frequency allowable at the voltage specified in each column.
“ P o w e r M a n a g e m e n t ” o n p a g e 9 d e s c r i b e s h o w
A M D P owe r N ow !™ s o f t wa r e u s e s t h i s i n fo r m a t i o n t o
implement processor performance states.
Table 8. Valid Voltage and Frequency Combinations
VCC_CORE_NOM Voltage
Maximum
Frequency
1.50 V
800 MHz
850 MHz
N/A
1.45 V
700 MHz
750 MHz
900 MHz
950 MHz
N/A
1.40 V
650 MHz
700 MHz
800 MHz
850 MHz
1000 MHz
1.35 V
600 MHz
650 MHz
750 MHz
800 MHz
900 MHz
1.30 V
550 MHz
600 MHz
700 MHz
750 MHz
850 MHz
1.25 V
500 MHz
550 MHz
650 MHz
700 MHz
800 MHz
1.20 V
≤ 500 MHz
≤ 500 MHz
≤ 550 MHz
≤ 600 MHz
≤ 700 MHz
800 MHz
850 MHz
900 MHz
950 MHz
1000 MHz
Notes:
N/A
N/A
1. All voltages listed are nominal.
2. The “≤” symbol indicates that any BIOS vendor can use any performance state equal to or less than the specified frquency at that
given voltage. For example, “≤ 700 MHz” means that the BIOS may use 700 MHz, 600 MHz, 550 MHz, 500 MHz, 400 Mhz, or
300 Mhz provided that the chipset and system support the chosen processor operating frequencies.
3. The maximum processor die temperature is 95º C for all voltage and frequency combinations.
36
Electrical Data
Chapter 7
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
7.8
VCC_CORE AC and DC Characteristics
Table 9 shows the AC and DC characteristics for VCC_CORE.
For more information, see Table 24, “Cross-Reference by Pin
Location,” on page 70 and Figure 9 on page 38.
Table 9. VCC_CORE AC and DC Characteristics
2
Symbol
Parameter
Maximum static voltage above V
Maximum static voltage below V
Maximum excursion above V
Units
mV
mV
mV
Limit in Working State
1
V
100
CC_CORE_DC_MAX
CC_CORE_NOM
1
V
–50
150
CC_CORE_DC_MIN
CC_CORE_NOM
1
V
CC_CORE_AC_MAX
CC_CORE_NOM
1, 3
V
Maximum excursion below V
–100
10
mV
µs
CC_CORE_AC_MIN
CC_CORE_NOM
t
Positive excursion time for AC transients
Negative excursion time for AC transients
MAX_AC
t
5
µs
MIN_AC
Notes:
1. VCC_CORE nominal values are shown in Table 8, “Valid Voltage and Frequency Combinations,” on page 36.
2. All voltage measurements are taken differentially at the COREFB/COREFB# pins.
3. Absolute minimum allowable VCC_CORE voltage, including all transients, is 1.10 V.
Chapter 7
Electrical Data
37
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Figu re 9 sh ows t h e p roce ssor core volt a ge (VCC_COR E )
waveform response to perturbation. The tMIN_AC (negative AC
transient excursion time) and tMAX_AC (positive AC transient
excursion time) represent the maximum allowable time below
or above the DC tolerance thresholds.
tmax_AC
V
CC_CORE_MAX_AC
V
CC_CORE_MAX_DC
V
CC_CORE_NOM
V
CC_CORE_MIN_DC
V
CC_CORE_MIN_AC
tmin_AC
ICORE_MAX
dI /dt
ICORE_MIN
Figure 9. VCC_CORE Voltage Waveform
38
Electrical Data
Chapter 7
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
7.9
Absolute Ratings
Do n ot su b j ect t h e p rocessor t o con d it ion s t h a t exce ed t h e
ab solu t e ra t in gs list ed in Tab le 10, a s su ch con d it ion s m ay
adversely affect long-term reliability or result in functional
damage.
Table 10. Absolute Ratings
Parameter
Description
Min
Max
VCC_CORE
VCCA
Mobile AMD Duron™ Processor Model 7 core supply
AMD Duron Processor Model 7 PLL supply
–0.5 V
–0.5 V
VCC_CORE Max + 0.5 V
VCCA Max + 0.5 V
V
Voltage on any signal pin
–0.5 V
–40ºC
VCC_CORE Max + 0.5 V
100ºC
PIN
T
Storage temperature of processor
STORAGE
Chapter 7
Electrical Data
39
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
7.10
VCC_CORE Voltage and Current
Table 11 shows the voltage and current of the processor during
normal and reduced power states.
Table 11. VCC_CORE Voltage and Current
Maximum I (Power
Frequency
(MHz)
Nominal
Voltage
CC
Die Temperature
Notes
Supply Current)
800
850
1.50 V
16.70 A
900
1.45 V
1.40 V
17.20 A
95°C
950
17.90
1000
2.00 A
1.07 A
0.80 A
1, 2, 3
Halt/Stop Grant C2
Stop Grant C2
Stop Grant C3/S1
1.20 V
1, 2, 3, 4
1, 2, 3, 4
50°C
Notes:
1. See also Figure 3, “Mobile AMD Duron™ Processor Model 7 Power Management States” on page 10.
2. The maximum Stop Grant currents are absolute worst case currents for parts that may yield from the worst case corner of the
process, and are not representative of the typical Stop Grant current that is currently about one-third of the maximum specified
current.
3. These currents occur when the AMD Duron system bus is disconnected and a low power ratio of 1/512 is applied to the core clock
grid of the processor as dictated by a value of 6007_9263h programmed into the Clock Control (CLK_Ctl) MSR.
4. The Stop Grant current consumption is characterized and not tested.
40
Electrical Data
Chapter 7
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
7.11
SYSCLK and SYSCLK# AC and DC Characteristics
Tab le 12 sh ows t h e DC ch ara ct e r ist ics of t h e SYSCLK a n d
SYSCLK# differential clocks. The SYSCLK signal represents
CLKIN and RSTCLK tied together while the SYSCLK# signal
represents CLKIN# and RSTCLK# tied together.
Table 12. SYSCLK and SYSCLK# DC Characteristics
Symbol
Description
Min
400
Max
Units
mV
mV
µA
V
Crossing before transition is detected (DC)
Threshold-DC
V
Crossing before transition is detected (AC)
450
Threshold-AC
I
Leakage current through P-channel pullup to VCC_CORE
Leakage current through N-channel pulldown to VSS (Ground)
–250
LEAK_P
I
250
µA
LEAK_N
VCC_CORE/2
+/– 100
V
Differential signal crossover
Capacitance
mV
pF
CROSS
C
4
12
PIN
Figure 10 shows the DC cha racteristics of the SYSCLK and
SYSCLK# signals.
V
VThreshold-DC = 400 mV
VThreshold-AC = 450 mV
CROSS
Figure 10. SYSCLK and SYSCLK# Differential Clock Signals
Chapter 7
Electrical Data
41
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Tab le 13 sh ows t h e m ob ile AMD Du ron p roce ssor m od e l 7
SYSCLK/SYSCLK# differential clock AC characteristics.
Table 13. SYSCLK and SYSCLK# AC Characteristics
Symbol
Description
Clock Frequency
Min
50
Max
100
Units
MHz
–
Notes
Duty Cycle
Period
30%
10
70%
t
ns
1, 2
1
t
High Time
Low Time
Fall Time
1.8
1.8
ns
ns
ns
ns
ps
2
t
3
t
2
2
4
t
Rise Time
Period Stability
5
± 300
Notes:
1. Circuitry driving the SYSCLK and SYSCLK# inputs must exhibit a suitably low closed-loop jitter bandwidth to allow the PLL to track
the jitter. The –20 dB attenuation point, as measured into a 10-pF or 20-pF load must be less than 500 kHz.
2. Circuitry driving the SYSCLK and SYSCLK# inputs may purposely alter the SYSCLK and SYSCLK# period (spread spectrum clock
generators). In no cases can the period violate the minimum specification above. SYSCLK and SYSCLK# inputs may vary from
100% of the specified period to 99% of the specified period at a maximum rate of 100 kHz.
Figure 11 shows a sample waveform.
t2
V
V
Threshold-AC
CROSS
t3
t4
t5
t1
Figure 11. SYSCLK Waveform
42
Electrical Data
Chapter 7
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
7.12
AMD Duron™ System Bus AC and DC Characteristics
Tab le 14 sh ows t h e DC ch a ra ct e r ist ics of t h e AMD Du ron
system bus.
Table 14. AMD Duron™ System Bus DC Characteristics
Symbol
Parameter
Condition
Min
Max
Units Notes
(0.5 x VCC_CORE) (0.5 x VCC_CORE)
V
DC Input Reference Voltage
mV
µA
µA
1
REF
–50
+50
I
V
Tristate Leakage Pullup V =V
–100
VREF_LEAK_P
REF IN REFNominal
V
Tristate Leakage
REF
I
V =V
+100
VREF_LEAK_N
IN REFNominal
Pulldown
V
V
+ 200
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
VCC_CORE + 500 mV
IH
REF
V
V
– 200
–500
mV
mV
mV
IL
REF
V
I
= –200 µA
0.85*VCC_CORE VCC_CORE+500
2
2
OH
OUT
V
I
= 1 mA
–500
–250
400
OL
OUT
V = VSS
IN
I
Tristate Leakage Pullup
µA
LEAK_P
(Ground)
V = VCC_CORE
IN
I
Tristate Leakage Pulldown
Input Pin Capacitance
+250
12
µA
pF
LEAK_N
Nominal
C
4
IN
Notes:
1. V
–RVERFEF is nominally set by a (1%) resistor divider from VCC_CORE.
– The suggested divider resistor values are 100 ohms over 100 ohms to produce a divisor of 0.50.
– Example: VCC_CORE = 1.4 V, VREF = 750 mV (1.4 x 0.50).
– Peak-to-Peak AC noise on VREF (AC) should not exceed 2% of VREF (DC).
2. Specified at T = 95°C and VCC_CORE.
Chapter 7
Electrical Data
43
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
The AC characteristics of the AMD Duron system bus are shown
in Table 15. The parameters are grouped based on the source or
destination of the signals involved.
Table 15. AMD Duron™ System Bus AC Characteristics
Group
Symbol
Parameter
Output Rise Slew Rate
Output Fall Slew Rate
Min
1
Max
3
Units
V/ns
V/ns
Notes
T
1
RISE
All Signals
T
1
3
1
2
FALL
Output skew with respect to
the same clock edge
T
–
–
385
770
ps
ps
SKEW-SAMEEDGE
Output skew with respect to a
different clock edge
T
2
SKEW-DIFFEDGE
T
Input Data Setup Time
Input Data Hold Time
Capacitance on input Clocks
Capacitance on output Clocks
RSTCLK to Output Valid
Setup to RSTCLK
300
300
4
–
–
ps
ps
pF
pF
ps
ps
ps
3
3
SU
T
HD
C
12
12
2000
–
IN
C
4
OUT
T
250
500
1000
4, 5
4, 6
4, 6
VAL
T
SU
T
Hold from RSTCLK
–
HD
Notes:
1. Rise and fall time ranges are guidelines over which the I/O has been characterized.
2. TSKEW-SAMEEDGE is the maximum skew within a clock forwarded group between any two signals or between any signal and its
forward clock, as measured at the package, with respect to the same clock edge.
TSKEW-DIFFEDGE is the maximum skew within a clock forwarded group between any two signals or between any signal and its
forward clock, as measured at the package, with respect to different clock edges.
3. Input SU and HD times are with respect to the appropriate Clock Forward Group input clock.
4. The synchronous signals include PROCRDY, CONNECT, and CLKFWDRST.
5. TVAL is RSTCLK rising edge to output valid for PROCRDY. Test Load is 25 pF.
6. T is setup of CONNECT/CLKFWDRST to rising edge of RSTCLK. THD is hold of CONNECT/CLKFWDRST from rising edge of
SU
RSTCLK.
44
Electrical Data
Chapter 7
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
7.13
General AC and DC Characteristics
Table 16 shows the mobile AMD Duron processor model 7 AC
and DC charact erist ics of t he Sout hbridge, J TAG, te st , and
miscellaneous pins.
Table 16. General AC and DC Characteristics
Symbol
Parameter Description
Input High Voltage
Condition
Min
Max
VCC_CORE Max
350
Units Notes
(VCC_CORE/2) +
200mV
V
V
1, 2
1, 2
IH
V
Input Low Voltage
–300
mV
mV
IL
VCC_CORE +
300
V
Output High Voltage
VCC_CORE – 400
OH
V
Output Low Voltage
–300
–250
400
mV
µA
OL
I
V = VSS (Ground)
Tristate Leakage Pullup
LEAK_P
IN
V = VCC_CORE
IN
I
Tristate Leakage Pulldown
250
–16
µA
LEAK_N
Nominal
I
Output High Current
Output Low Current
Sync Input Setup Time
Sync Input Hold Time
mA
mA
ns
3
OH
I
16
2.0
0.0
3
OL
T
4, 5
4, 5
SU
T
ps
HD
Output Delay with respect to
RSTCLK
T
0.0
6.1
ns
ns
5
DELAY
T
Input Time to Acquire
20.0
7, 8
BIT
Notes:
1. Characterized across DC supply voltage range.
2. Values specified at nominal VCC_CORE. Scale parameters between VCC_CORE Min and VCC_CORE Max.
3. IOL and IOH are measured at V maximum and V minimum, respectively.
OL
OH
4. Synchronous inputs/outputs are specified with respect to RSTCLK and RSTCK# at the pins.
5. These are aggregate numbers.
6. Edge rates indicate the range over which inputs were characterized.
7. In asynchronous operation, the signal must persist for this time to enable capture.
8. This value assumes RSTCLK frequency is 10 ns ==> TBIT = 2*fRST.
9. The approximate value for standard case in normal mode operation.
10. This value is dependent on RSTCLK frequency, divisors, Low Power mode, and core frequency.
11. Reassertions of the signal within this time are not guaranteed to be seen by the core.
12. This value assumes that the skew between RSTCLK and K7CLKOUT is much less than one phase.
13. This value assumes RSTCLK and K7CLKOUT are running at the same frequency, though the processor is capable of other
configurations.
14. Time to valid is for any open drain pins. See requirements 7 and 8 in Chapter 8, “Power–Up Timing Requirements,“ for more
information.
Chapter 7
Electrical Data
45
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Table 16. General AC and DC Characteristics
Symbol
Parameter Description
Input Time to Reacquire
Signal Rise Time
Condition
Min
40.0
1.0
1.0
4
Max
Units Notes
T
ns
V/ns
V/ns
pF
9–13
RPT
T
3.0
3.0
12
6
6
RISE
T
Signal Fall Time
FALL
C
Pin Capacitance
PIN
T
Time to data valid
100
ns
14
VALID
Notes:
1. Characterized across DC supply voltage range.
2. Values specified at nominal VCC_CORE. Scale parameters between VCC_CORE Min and VCC_CORE Max.
3. IOL and IOH are measured at V maximum and V minimum, respectively.
OL
OH
4. Synchronous inputs/outputs are specified with respect to RSTCLK and RSTCK# at the pins.
5. These are aggregate numbers.
6. Edge rates indicate the range over which inputs were characterized.
7. In asynchronous operation, the signal must persist for this time to enable capture.
8. This value assumes RSTCLK frequency is 10 ns ==> TBIT = 2*fRST.
9. The approximate value for standard case in normal mode operation.
10. This value is dependent on RSTCLK frequency, divisors, Low Power mode, and core frequency.
11. Reassertions of the signal within this time are not guaranteed to be seen by the core.
12. This value assumes that the skew between RSTCLK and K7CLKOUT is much less than one phase.
13. This value assumes RSTCLK and K7CLKOUT are running at the same frequency, though the processor is capable of other
configurations.
14. Time to valid is for any open drain pins. See requirements 7 and 8 in Chapter 8, “Power–Up Timing Requirements,“ for more
information.
46
Electrical Data
Chapter 7
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
7.14
Open Drain Test Circuit
Figure 12 is a test circuit that may be used on Automated Test
Equipment (ATE) to test for validity on open drain pins.
Refer to Table 16, “General AC and DC Characteristics,” on
page 45 for timing requirements.
1
V
Termination
50 Ω ±3%
IOL = Output Current2
Open Drain Pin
Notes:
1. VTermination = 1.2 V for VID and FID pins
2. IOL = –16 mA for VID and FID pins
Figure 12. General ATE Open Drain Test Circuit
Chapter 7
Electrical Data
47
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
7.15
Thermal Diode Characteristics
Thermal Diode Electrical Characteristics. Table 17 shows the mobile
AMD Duron processor model 7 electrical characteristics of the
on-die thermal diode.
Table 17. Thermal Diode Electrical Characteristics
Symbol Parameter Description Min
Nom
Max
300
Units
Notes
1
I
Forward bias current
Diode ideality factor
5
µA
fw
n
1.002
1.008
1.016
2, 3, 4, 5
Notes:
1. The sourcing current should always be used in forward bias only.
2. Characterized at 95°C with a forward bias current pair of 10 µA and 100 µA.
3. Not 100% tested. Specified by design and limited characterization.
4. The diode ideality factor, n, is a correction factor to the ideal diode equation.
For the following equations, use the following variables and constants:
n
k
q
T
Diode ideality factor
Boltzmann constant
Electron charge constant
Diode temperature (Kelvin)
VBE Voltage from base to emitter
IC
IS
N
Collector current
Saturation current
Ratio of collector currents
The equation for V is:
BE
IC
----
IS
nkT
q
ꢀ
.
---------
VBE
=
ln
0
By sourcing two currents and using the above equation, a difference in base emitter voltage
can be found that leads to the following equation for temperature:
∆VBE
T = -----------------------------
k
--
n ln(N)
q
5. If a different sourcing current pair is used other than 10 µA and 100 µA, the following equation
should be used to correct the temperature. Subtract this offset from the temperature measured
by the temperature sensor.
For the following equations, use the following variables and constants:
I
High sourcing current
Low sourcing current
high
I
low
Toffset (in °C) can be found using the following equation:
(Ihigh – Ilow
)
Toffset = (6.0 104)
– 2.34
-------------------------------
Ihigh
ꢀ
.
----------
ln
0
Ilow
48
Electrical Data
Chapter 7
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Thermal Protection Characterization. The following section describes
parameters relating to thermal protection. The implementation
of thermal control circuitry to control processor temperature is
left to the manufacturer to determine how to implement.
Thermal limits in motherboard design are necessary to protect
t h e p r oce ssor fr om t h e r m a l d a m a ge . TS H U T D OW N is t h e
t e m p e ra t u re for t h e r m a l p r ot e ct ion circu it r y t o in it ia t e
shutdown of the processor. TSD_DELAY is the maximum time
allowed from the detection of the over-temperature condition to
p r oce ssor sh u t d own t o p r e ve n t t h e r m a l d a m a ge t o t h e
processor.
Systems that do not implement thermal protection circuitry or
that do not react within the time specified by TSD_DELAY can
cause t he rmal damage to the processor during t he unlikely
events of fan failure or powering up the processor without a
h e a t -sin k . Th e p roce ssor re lie s on t h e r ma l circu it ry on t h e
m ot h e r b oa rd t o t u r n off t h e re gu la t e d core volt a ge t o t h e
processor in response to a thermal shutdown event.
Thermal protection circuitry reference designs and thermal
solution guidelines are found in the following documents:
■ AMD Athlon™ Processor-Based Motherboard Design Guide,
order# 24363
■ Thermal Diode Monitoring Circuits, order# 25658
■ AMD Thermal, Mechanical, and Chassis Cooling Design Guide,
order# 23794
■ http://www1.amd.com/products/athlon/thermals
Mobile specific thermal documentation:
■ Measuring Processor and system Power in a Mobile System,
order# 24353
■ Mobile System Thermal Design Guide, order# 24383
■ Measuring Temperature on AMD Athlon™ and AMD Duron™
Pin Grid Array Processors with and without an On-Die Thermal
Diode, order#24228
Chapter 7
Electrical Data
49
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Table 18 shows the TSHUTDOWN and TSD_DELAY specifications
for circu it ry in m ot h e r b oa rd d e sign n e ce ssa ry for t h e r m a l
protection of the processor.
Table 18. Guidelines for Platform Thermal Protection of the Processor
Symbol
Parameter Description
Max
Units
Notes
T
Thermal diode shutdown temperature for processor protection
125
°C
1, 2, 3
SHUTDOWN
Maximum allowed time from T
shutdown
detection to processor
SHUTDOWN
T
500
ms
1, 3
SD_DELAY
Notes:
1. The thermal diode is not 100% tested, it is specified by design and limited characterization.
2. The thermal diode is capable of responding to thermal events of 40°C/s or faster.
3. The mobile AMD Duron™ processor model 7 provides a thermal diode for measuring die temperature of the processor. The
processor relies on thermal circuitry on the motherboard to turn off the regulated core voltage to the processor in response to a
thermal shutdown event. Refer to Thermal Diode Monitoring Circuits, order# 25658, for thermal protection circuitry designs.
50
Electrical Data
Chapter 7
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
7.16
Reserved Pins DC Characteristics
Table 19 shows the DC characteristics of the Reserved (RSVD)
pins.
Table 19. Reserved Pins (N1, N3, and N5) DC Characteristics
Symbol Parameter Description
Min
Max
Units
µA
Note
I
Tristate Leakage Pullup
–250
*
*
LEAK_P
I
Tristate Leakage Pulldown
250
µA
LEAK_N
Note:
*
Measured at 2.5 V
Chapter 7
Electrical Data
51
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
7.17
FID_Change Induced PLL Lock Time
Table 20 shows the time required for the PLL of the processor to
lock at the new frequency specified in a FID_Change transition.
Software must program the SGTC field of the FidVidCtl MSR to
produce a FID_Change duration equal to or greater than the
FID_Change induced PLL lock time.
For m ore in for m a t ion ab ou t t h e F ID_Ch a n ge p rot ocol, se e
“Power Management” on page 9.
Table 20. FID_Change Induced PLL Lock Time
Parameter Description
Max
Units
FID_Change Induced PLL Lock Time
50
µs
52
Electrical Data
Chapter 7
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
8
Signal and Power-Up Requirements
This chapte r de scr ibe s the mobile AMD Duron™ proce ssor
model 7 power-up requirements during system power-up and
warm resets.
8.1
Power-Up Requirements
Signal Sequence and
Timing Description
Figure 13 shows the relationship between key signals in the
syste m during a powe r-up se que nce. This figure details the
requirements of the processor.
3.3 V Supply
VCCA (2.5 V)
(for PLL)
VCC_CORE
2
(Processor Core)
Warm reset
condition
1
RESET#
6
4
NB_RESET#
5
PWROK
FID[3:0]
8
7
3
System Clock
Figure 13. Signal Relationship Requirements During Power-Up Sequence
Notes:
1. Figure 13 represents several signals generically by using names not necessarily consistent
with any pin lists or schematics.
2. Requirements 1–8 in Figure 13 are described in “Power-Up Tim ing Requirements” on
page 54.
Chapter 8
Signal and Power-Up Requirements
53
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Power-Up Timing Requirements. The signal timing requirements are
as follows:
1. RESET# must be asserted before PWROK is asserted.
The mobile AMD Duron™ processor model 7 does not set
the correct clock multiplier if PWROK is asserted prior to a
RESET# assertion. It is recommended that RESET# be
asserted at least 10 nanoseconds prior to the assertion of
PWROK.
In practice, Southbridges will assert RESET# milliseconds
before PWROK is deasserted.
2. All motherboard voltage planes must be within
specification before PWROK is asserted.
PWROK is an output of the voltage regulation circuit on the
motherboard. PWROK indicates that VCC_CORE and all
other voltage planes in the system are within specification.
The motherboard is required to delay PWROK assertion for
a minimum of 3 milliseconds from the 3.3 V supply being
within specification. This ensures that the system clock
(SYSCLK/SYSCLK#) is operating within specification when
PWROK is asserted.
The processor core voltage, VCC_CORE, must be within
specification before PWROK is asserted as dictated by the
VID[4:0] pins strapped on the processor package. Before
PWROK assertion, the processor is clocked by a ring
oscillator. Before PWROK is asserted, the SOFTVID[4:0]
outputs of the processor are not driven to a deterministic
value. The processor drives the SOFTVID[4:0] outputs to
the same value as dictated by the VID[4:0] pins within 20
nanoseconds of PWROK assertion.
The processor PLL is powered by VCCA. The processor PLL
does not lock if VCCA is not high enough for the processor
logic to switch for some period before PWROK is asserted.
VCCA must be within specification at least 5 microseconds
before PWROK is asserted.
In practice VCCA, VCC_CORE, and all other voltage planes
must be within specification for several milliseconds before
PWROK is asserted.
After PWROK is asserted, the processor PLL locks to its
operational frequency.
3. The system clock (SYSCLK/SYSCLK#) must be running
before PWROK is asserted.
54
Signal and Power-Up Requirements
Chapter 8
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
When PWROK is asserted, the processor switches from
driving the internal processor clock grid from the ring
oscillator to driving from the PLL. The reference system
clock must be valid at this time. The system clocks are
guaranteed to be running after 3.3 V has been within
specification for 3 milliseconds.
4. PWROK assertion to deassertion of RESET#
The duration of RESET# assertion during cold boots is
intended to satisfy the time it takes for the PLL to lock with
a less than 1 ns phase error. The processor PLL begins to
run after PWROK is asserted and the internal clock grid is
switched from the ring oscillator to the PLL. The PLL lock
time may take from hundreds of nanoseconds to tens of
microseconds. It is recommended that the minimum time
between PWROK assertion to the deassertion of RESET# be
at least 1.0 milliseconds. Southbridges enforce a delay of
1.5 to 2.0 milliseconds between PWRGD (Southbridge
version of PWROK) assertion and NB_RESET# deassertion.
5. PWROK must be monotonic and meet the timing
requirements as defined in Table 16, “General AC and DC
Characteristics,” on page 45. The processor should not
switch between the ring oscillator and the PLL after the
initial assertion of PWROK.
6. NB_RESET# must be asserted (causing CONNECT to also
assert) before RESET# is deasserted. In practice all
Southbridges enforce this requirement.
If NB_RESET# does not assert until after RESET# has
deasserted, the processor misinterprets the CONNECT
assertion (due to NB_RESET# being asserted) as the
beginning of the SIP transfer. There must be sufficient
overlap in the resets to ensure that CONNECT is sampled
asserted by the processor before RESET# is deasserted.
7. The FID[3:0] signals are valid within 100 ns after PWROK is
asserted. The chipset must not sample the FID[3:0] signals
until they become valid. Refer to the AMD Athlon™
Processor-Based Motherboard Design Guide, order# 24363, for
the specific implementation and additional circuitry
required.
Chapter 8
Signal and Power-Up Requirements
55
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
8. The FID[3:0] signals become valid within 100 ns after
RESET# is asserted. Refer to the AMD Athlon™ Processor-
Based Motherboard Design Guide, order# 24363, for the
specific implementation and additional circuitry required.
Clock Multiplier
Selection (FID[3:0])
The chipset samples the FID[3:0] signals in a chipset-specific
m a n n e r fr om t h e p roce ssor a n d u se s t h is in for m a t ion t o
determine the correct Serial Initialization Packet (SIP). The
chipset then sends the SIP information to t he processor for
con figu ra t ion of t h e AMD Du ron syst e m b u s for t h e clock
multiplier that determines the processor frequency indicated
by the FID[3:0] code. The SIP is sent to the processor using the
SIP protocol. This protocol uses the PROCRDY, CONNECT, and
CLKFWDRST signals, that are synchronous to SYSCLK.
For more information, seeSee “FID[3:0] Pins” on page 79.
Serial Initialization Packet (SIP) Protocol. Refer to AMD Athlon™ and
AMD Duron™ System Bus Specification, order# 21902 for details
of the SIP protocol.
8.2
Processor Warm Reset Requirements
Mobile AMD Duron™ RESET# cannot be asserted to the processor without also being
Processor Model 7
and Northbridge
Reset Pins
asserted to the Northbridge. RESET# to the Northbridge is the
same as PCI RESET#. The minimum assertion for PCI RESET#
is one millisecond. Southbridges enforce a minimum assertion
of RESET# for the processor, Northbridge, and PCI of 1.5 to 2.0
milliseconds.
56
Signal and Power-Up Requirements
Chapter 8
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
9
Mechanical Data
9.1
Introduction
Th e m ob ile AMD Du ron p roce ssor m od e l 7 con n ect s t o t h e
motherboard through a CPGA socket named Socket A. For more
information, see the AMD Athlon™ Processor-Based Motherboard
Design Guide, order# 24363.
9.2
Die Loading
The processor die on the CPGA package is exposed at the top of
the package. This is done to facilitate heat transfer from the die
t o an ap p rove d h ea t sin k . It is cr it ica l t h a t t h e m e ch an ica l
loading of the heat sink does not exceed the limits shown in
Table 21. Any heat sink design should avoid loads on corners
and edges of die. The CPGA package has compliant pads that
serve to bring surfaces in planar contact.
Table 21. CPGA Mechanical Loading1
Location
Die Surface
Die Edge
Notes:
Dynamic (MAX)
Static (MAX)
Units
lbf
Note
100
10
30
10
2
3
lbf
1. Tool-assisted zero insertion force sockets should be designed such that no load is placed on
the ceramic substrate of the package.
2. Load specified for coplanar contact to die surface.
3. Load defined for a surface at no more than a two degree angle of inclination to die surface.
Chapter 9
Mechanical Data
57
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
9.3
Package Description
Figu re 14 on p age 59 sh ows t he m e ch a n ica l d rawin g of t h e
C P G A p a ck a g e . Ta b l e 2 2 p r ov i d e s t h e d i m e n s i o n s i n
millimeters assigned to the letters and symbols shown in the
Figure 14 diagram.
Table 22. Dimensions for the CPGA Package
Minimum
Maximum
Minimum
Maximum
Letter or
Symbol
Letter or
Symbol
1
1
1
1
Dimension Dimension
49.27 49.78
45.72 BSC
11.698 REF
3.30
Dimension Dimension
D/E
D1/E1
D2
D3
D4
D5
D6
D7
D8
E2
E9
G/H
A
1.66
—
1.96
4.50
2.24 REF
3.60
12.39
12.39
6.46
A1
A2
A3
A4
φP
φb
φb1
S
1.27
0.80
0.116
—
1.53
0.88
—
11.84
11.84
5.91
1.90
6.60
0.50
10.65
3.05
11.20
3.35
—
0.43
9.034 REF
1.40 REF
37
E3
2.35
7.25
2.65
7.80
1.435
3.05
2.375
3.31
E4
L
E5
7.25
7.80
M
N
E6
8.86
8.86
15.59
9.41
9.41
16.38
453 (pins)
1.27 BSC
2.54 BSC
E7
e
E8
e1
Note:
1. Dimensions are given in millimeters.
58
Mechanical Data
Chapter 9
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Figure 14. Mobile AMD Duron™ Processor Model 7 CPGA Package
Chapter 9
Mechanical Data
59
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
60
Mechanical Data
Chapter 9
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
10
Pin Descriptions
10.1
Pin Diagram and Pin Name Abbreviations
Figure 15 on page 62 shows the staggered pin grid array (SPGA)
for the mobile AMD Duron processor model 7. Because some of
t h e p in n a m e s a r e t oo lon g t o fit in t h e g r id , t h e y a r e
a b b r e v i a t e d . Ta b l e 2 3 o n p a g e 6 4 l i s t s a l l t h e p i n s i n
alphabetical order by pin name, along with the abbreviation
where necessary.
Chapter 10
Pin Descriptions
61
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
62
Pin Descriptions
Chapter 10
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Chapter 10
Pin Descriptions
63
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Table 23. Pin Name Abbreviations
Abbreviation
Full Name
A20M#
Pin
AE1
Abbreviation
Full Name
Pin
A19
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
AMD
AH6
AJ13
AJ21
AN17
AL17
AL23
AG11
AG13
AK6
AA1
AA3
AG1
W1
A31
C13
E25
E33
F30
G11
G13
G19
G21
G27
G29
G31
H28
H30
H32
J5
ANLOG
ANALOG
CLKFWDRST
CLKIN
CLKIN#
CONNECT
COREFB
COREFB#
CPU_PRESENCE#
DBRDY
DBREQ#
FERR
CLKFR
CNNCT
CPR#
FID[0]
FID[1]
FID[2]
FID[3]
FLUSH#
IGNNE#
INIT#
W3
Y1
Y3
AL3
AJ1
J31
K30
L31
AJ3
INTR
AL1
AL21
AN21
G7
L35
N31
Q31
S31
K7CO
K7CLKOUT
K7CLKOUT#
KEY
K7CO#
KEY
G9
U31
U37
W7
KEY
G15
G17
G23
G25
N7
KEY
KEY
W31
Y5
KEY
KEY
Y31
KEY
Q7
Y33
AA5
AA31
AC7
AC31
AD8
AD30
AE7
AE31
KEY
Y7
KEY
AA7
AG7
AG9
AG15
AG17
AG27
AG29
KEY
KEY
KEY
KEY
KEY
KEY
64
Pin Descriptions
Chapter 10
Preliminary Information
24068F—December 2001
Mobile AMD Duron™ Processor Model 7 Data Sheet
Table 23. Pin Name Abbreviations (continued)
Abbreviation
Full Name
Pin
AF6
Abbreviation
PLTST#
Full Name
PLLTEST#
Pin
AC3
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NMI
AF8
PRCRDY
PROCREADY
PWROK
AN23
AE3
N1
AF10
AF28
AF30
AF32
AG5
RSVD
RSVD
N3
RSVD
N5
RESET#
AG3
AN19
AL19
AJ29
AL29
AG33
AJ37
AL35
AE33
AJ35
AG37
AL33
AN37
AL37
AG35
AN29
AN35
AN31
AJ33
J1
AG19
AG21
AG23
AG25
AG31
AH8
RCLK
RSTCLK
RCLK#
SAI#0
RSTCLK#
SADDIN[0]#
SADDIN[1]#
SADDIN[2]#
SADDIN[3]#
SADDIN[4]#
SADDIN[5]#
SADDIN[6]#
SADDIN[7]#
SADDIN[8]#
SADDIN[9]#
SADDIN[10]#
SADDIN[11]#
SADDIN[12]#
SADDIN[13]#
SADDIN[14]#
SADDINCLK#
SADDOUT[0]#
SADDOUT[1]#
SADDOUT[2]#
SADDOUT[3]#
SADDOUT[4]#
SADDOUT[5]#
SADDOUT[6]#
SADDOUT[7]#
SADDOUT[8]#
SADDOUT[9]#
SADDOUT[10]#
SADDOUT[11]#
SADDOUT[12]#
SADDOUT[13]#
SAI#1
SAI#2
SAI#3
AH30
AJ7
SAI#4
SAI#5
AJ9
SAI#6
AJ11
AJ15
AJ17
AJ19
AJ27
AK8
SAI#7
SAI#8
SAI#9
SAI#10
SAI#11
SAI#12
SAI#13
SAI#14
SAIC#
AL7
AL9
AL11
AL25
AL27
AM8
AN7
AN9
AN11
AN25
AN27
AN3
AJ25
AN15
AL15
AN13
AL13
SAO#0
SAO#1
SAO#2
SAO#3
SAO#4
SAO#5
SAO#6
SAO#7
SAO#8
SAO#9
SAO#10
SAO#11
SAO#12
SAO#13
J3
C7
A7
E5
A5
E7
C1
C5
PLBYP#
PLLBYPASS#
PLLBYPASSCLK
PLLBYPASSCLK#
PLLMON1
C3
PLBYC
PLBYC#
PLMN1
PLMN2
G1
E1
A3
PLLMON2
G5
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Pin Descriptions
65
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Table 23. Pin Name Abbreviations (continued)
Abbreviation
SAO#14
Full Name
SADDOUT[14]#
SADDOUTCLK#
SCANCLK1
SCANCLK2
SCANINTEVAL
SCANSHIFTEN
SDATA[0]#
Pin
Abbreviation
SD#33
Full Name
SDATA[33]#
Pin
E29
G3
E3
S1
S5
S3
Q5
SAOC#
SCNCK1
SCNCK2
SCNINV
SCNSN
SD#0
SD#34
SD#35
SD#36
SD#37
SD#38
SD#39
SD#40
SD#41
SD#42
SD#43
SD#44
SD#45
SD#46
SD#47
SD#48
SD#49
SD#50
SD#51
SD#52
SD#53
SD#54
SD#55
SD#56
SD#57
SD#58
SD#59
SD#60
SD#61
SD#62
SD#63
SDIC#0
SDIC#1
SDIC#2
SDIC#3
SDINV#
SDOC#0
SDOC#1
SDOC#2
SDATA[34]#
A27
A25
E21
C23
C27
A23
A35
C35
C33
C31
A29
C29
E23
C25
E17
SDATA[35]#
SDATA[36]#
SDATA[37]#
SDATA[38]#
AA35
W37
W35
Y35
SDATA[39]#
SD#1
SDATA[1]#
SDATA[40]#
SD#2
SDATA[2]#
SDATA[41]#
SD#3
SDATA[3]#
SDATA[42]#
SD#4
SDATA[4]#
U35
U33
S37
SDATA[43]#
SD#5
SDATA[5]#
SDATA[44]#
SD#6
SDATA[6]#
SDATA[45]#
SD#7
SDATA[7]#
S33
SDATA[46]#
SD#8
SDATA[8]#
AA33
AE37
AC33
AC37
Y37
SDATA[47]#
SD#9
SDATA[9]#
SDATA[48]#
SD#10
SD#11
SD#12
SD#13
SD#14
SD#15
SD#16
SD#17
SD#18
SD#19
SD#20
SD#21
SD#22
SD#23
SD#24
SD#25
SD#26
SD#27
SD#28
SD#29
SD#30
SD#31
SD#32
SDATA[10]#
SDATA[11]#
SDATA[12]#
SDATA[13]#
SDATA[14]#
SDATA[15]#
SDATA[16]#
SDATA[17]#
SDATA[18]#
SDATA[19]#
SDATA[20]#
SDATA[21]#
SDATA[22]#
SDATA[23]#
SDATA[24]#
SDATA[25]#
SDATA[26]#
SDATA[27]#
SDATA[28]#
SDATA[29]#
SDATA[30]#
SDATA[31]#
SDATA[32]#
SDATA[49]#
E13
E11
C15
E9
SDATA[50]#
SDATA[51]#
AA37
AC35
S35
SDATA[52]#
SDATA[53]#
A13
C9
SDATA[54]#
Q37
Q35
N37
J33
SDATA[55]#
A9
SDATA[56]#
C21
A21
E19
C19
C17
A11
A17
A15
W33
J35
SDATA[57]#
SDATA[58]#
G33
G37
E37
SDATA[59]#
SDATA[60]#
SDATA[61]#
G35
Q33
N33
L33
SDATA[62]#
SDATA[63]#
SDATAINCLK[0]#
SDATAINCLK[1]#
SDATAINCLK[2]#
SDATAINCLK[3]#
SDATAINVALID#
SDATAOUTCLK[0]#
SDATAOUTCLK[1]#
SDATAOUTCLK[2]#
N35
L37
E27
E15
AN33
AE35
C37
A33
J37
A37
E35
E31
66
Pin Descriptions
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Preliminary Information
24068F—December 2001
Mobile AMD Duron™ Processor Model 7 Data Sheet
Table 23. Pin Name Abbreviations (continued)
Abbreviation
SDOC#3
Full Name
SDATAOUTCLK[3]#
SDATAOUTVALID#
SFILLVALID#
SMI#
Pin
C11
Abbreviation
Full Name
VCC_CORE
Pin
F28
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
SDOV#
SFILLV#
AL31
AJ31
AN5
F8
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
F32
F34
F36
H2
SVID[0]
SVID[1]
SVID[2]
SVID[3]
SVID[4]
STPC#
SOFTVID[0]
SOFTVID[1]
SOFTVID[2]
SOFTVID[3]
SOFTVID[4]
STPCLK#
K8
H4
H6
H12
H16
H20
H24
K32
K34
K36
M2
M4
M6
M8
P30
P32
P34
P36
R2
H8
H10
AC1
Q1
TCK
TDI
U1
TDO
U5
THDA
THDC
THERMDA
THERMDC
TMS
S7
U7
Q3
TRST#
U3
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
B4
B8
B12
B16
B20
B24
B28
B32
B36
D2
R4
R6
R8
T30
T32
T34
T36
V2
D4
D8
D12
D16
D20
D24
D28
D32
F12
F16
F20
F24
V4
V6
V8
X30
X32
X34
X36
Z2
Z4
Chapter 10
Pin Descriptions
67
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Table 23. Pin Name Abbreviations (continued)
Abbreviation
Full Name
VCC_CORE
Pin
Abbreviation
Full Name
VCC_CORE
Pin
AM34
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Z6
Z8
VCC
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCCA
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VREF_SYS
VSS
AJ23
L1
AB30
AB32
AB34
AB36
AD2
L3
L5
L7
J7
AD4
VREF_S
W5
B2
AD6
AF14
AF18
AF22
AF26
AF34
AF36
AH2
VSS
B6
VSS
B10
B14
B18
B22
B26
B30
B34
D6
VSS
VSS
VSS
VSS
VSS
AH4
VSS
AH10
AH14
AH18
AH22
AH26
AJ5
VSS
VSS
D10
D14
D18
D22
D26
D30
D34
D36
F2
VSS
VSS
VSS
VSS
AK10
AK14
AK18
AK22
AK26
AK30
AK34
AK36
AL5
VSS
VSS
VSS
VSS
VSS
F4
VSS
F6
VSS
F10
F14
F18
F22
F26
H14
H18
H22
H26
H34
VSS
VSS
AM2
AM10
AM14
AM18
AM22
AM26
AM30
VSS
VSS
VSS
VSS
VSS
VSS
VSS
68
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Preliminary Information
24068F—December 2001
Mobile AMD Duron™ Processor Model 7 Data Sheet
Table 23. Pin Name Abbreviations (continued)
Abbreviation
Full Name
Pin
H36
Abbreviation
Full Name
Pin
AF12
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
ZN
K2
AF16
AF2
K4
K6
AF20
AF24
AH16
AH34
AF4
M30
M32
M34
M36
P2
AH12
AH20
AH24
AH28
AH32
AH36
AK2
P4
P6
P8
R30
R32
R34
R36
T2
AK4
AK12
AK16
AK20
AK24
AK28
AK32
AM4
AM6
AM12
AM16
AM20
AM24
AM28
AM32
AM36
AC5
T4
T6
T8
V30
V32
V34
V36
X2
X4
X6
X8
Z30
Z32
Z34
Z36
AB2
AB8
AB4
AB6
AD32
AD34
AD36
ZP
AE5
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Pin Descriptions
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Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
10.2
Pin List
Table 24 cross-references Socket A pin location to signal name.
The “L” (Level) column shows the electrical specification for
t h is p in . “ P” in d ica t e s a p u sh -p u ll mod e d r ive n by a sin gle
source. “O” indicates open-drain mode that allows devices to
share the pin.
Note: Socket A AMD Duron processors support push-pull drivers.
For more information, see “Push-Pull (PP) Drivers” on
page 6.
The “P” (Port) column indicates if this signal is an input (I),
output (O), or bidirectional (B) signal. The “R” (Reference)
column indicates if this signal should be referenced to VSS (G)
or VCC_CORE (P) planes for the purpose of signal routing with
respect to the current return paths. The “–” is used to indicate
that this description is not applicable for this pin.
Table 24. Cross-Reference by Pin Location
Pin
A1
Name
Description
L
–
P
P
P
P
P
P
P
P
-
P
–
R
–
Pin
A35
Name
SDATA[40]#
SDATA[30]#
VSS
Description
L
P
P
–
-
P
B
B
-
R
G
P
-
No Pin
page 80
A3
SADDOUT[12]#
SADDOUT[5]#
SADDOUT[3]#
SDATA[55]#
SDATA[61]#
SDATA[53]#
SDATA[63]#
SDATA[62]#
NC Pin
O
O
O
B
B
B
B
B
-
G
G
G
P
A37
B2
A5
A7
B4
VCC_CORE
VSS
-
-
A9
B6
-
-
-
A11
A13
A15
A17
A19
A21
A23
A25
A27
A29
A31
A33
P
B8
VCC_CORE
VSS
-
-
-
G
G
G
-
B10
B12
B14
B16
B18
B20
B22
B24
B26
B28
B30
-
-
-
VCC_CORE
VSS
-
-
-
-
-
-
page 80
page 80
VCC_CORE
VSS
-
-
-
SDATA[57]#
SDATA[39]#
SDATA[35]#
SDATA[34]#
SDATA[44]#
NC Pin
P
P
P
P
P
-
B
B
B
B
B
-
G
G
P
-
-
-
VCC_CORE
VSS
-
-
-
-
-
-
P
VCC_CORE
VSS
-
-
-
G
-
-
-
-
VCC_CORE
VSS
-
-
-
SDATAOUTCLK[2]#
P
O
P
-
-
-
Chapter 10
Pin Descriptions
70
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Table 24. Cross-Reference by Pin Location (continued)
Pin
B32
Name
VCC_CORE
VSS
Description
L
-
P
-
R
-
Pin
D26
Name
Description
L
-
P
-
R
-
VSS
B34
B36
C1
-
-
-
D28
D30
D32
D34
D36
E1
VCC_CORE
VSS
-
-
-
VCC_CORE
SADDOUT[7]#
SADDOUT[9]#
SADDOUT[8]#
SADDOUT[2]#
SDATA[54]#
SDATAOUTCLK[3]#
NC Pin
-
-
-
-
-
-
P
P
P
P
P
P
-
O
O
O
O
B
O
-
G
G
G
G
P
G
-
VCC_CORE
VSS
-
-
-
C3
-
-
-
C5
VSS
-
-
-
C7
SADDOUT[11]#
SADDOUTCLK#
SADDOUT[4]#
SADDOUT[6]#
SDATA[52]#
SDATA[50]#
SDATA[49]#
SDATAINCLK[3]#
SDATA[48]#
SDATA[58]#
SDATA[36]#
SDATA[46]#
NC Pin
P
P
P
P
P
P
P
P
P
P
P
P
-
O
O
O
O
B
B
B
I
P
G
P
G
P
P
G
G
P
G
P
P
-
C9
E3
C11
C13
C15
C17
C19
C21
C23
C25
C27
C29
C31
C33
C35
C37
D2
E5
page 80
E7
SDATA[51]#
SDATA[60]#
SDATA[59]#
SDATA[56]#
SDATA[37]#
SDATA[47]#
SDATA[38]#
SDATA[45]#
SDATA[43]#
SDATA[42]#
SDATA[41]#
SDATAOUTCLK[1]#
VCC_CORE
VCC_CORE
VSS
P
P
P
P
P
P
P
P
P
P
P
P
-
B
B
B
B
B
B
B
B
B
B
B
O
-
P
G
G
G
P
G
G
G
G
G
G
G
-
E9
E11
E13
E15
E17
E19
E21
E23
E25
E27
E29
E31
E33
E35
E37
F2
B
B
B
B
-
page 80
page 80
SDATAINCLK[2]#
SDATA[33]#
SDATA[32]#
NC Pin
P
P
P
-
I
G
P
P
-
B
B
-
D4
-
-
-
SDATA[31]#
SDATA[22]#
VSS
P
P
-
B
B
-
P
G
-
D6
-
-
-
D8
VCC_CORE
VSS
-
-
-
D10
D12
D14
D16
D18
D20
D22
D24
-
-
-
F4
VSS
-
-
-
VCC_CORE
VSS
-
-
-
F6
VSS
-
-
-
-
-
-
F8
SOFTVID[0]
VSS
page 81
O
-
O
-
-
VCC_CORE
VSS
-
-
-
F10
F12
F14
F16
F18
-
-
-
-
VCC_CORE
VSS
-
-
-
VCC_CORE
VSS
-
-
-
-
-
-
-
-
-
VCC_CORE
VSS
-
-
-
VCC_CORE
-
-
-
-
-
-
Chapter 10
Pin Descriptions
71
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Table 24. Cross-Reference by Pin Location (continued)
Pin
F20
Name
VCC_CORE
VSS
Description
L
-
P
-
R
-
Pin
H14
Name
Description
L
-
P
-
R
-
VSS
F22
F24
F26
F28
F30
F32
F34
F36
G1
-
-
-
H16
H18
H20
H22
H24
H26
H28
H30
H32
H34
H36
J1
VCC_CORE
VSS
-
-
-
VCC_CORE
VSS
-
-
-
-
-
-
-
-
-
VCC_CORE
VSS
-
-
-
VCC_CORE
NC Pin
-
-
-
-
-
-
page 80
-
-
-
VCC_CORE
VSS
-
-
-
VCC_CORE
VCC_CORE
VCC_CORE
SADDOUT[10]#
SADDOUT[14]#
SADDOUT[13]#
Key Pin
-
-
-
-
-
-
-
-
-
NC Pin
page 80
page 80
page 80
-
-
-
-
-
-
NC Pin
-
-
-
P
P
P
-
O
O
O
-
P
G
G
-
NC Pin
-
-
-
G3
VSS
-
-
-
G5
VSS
-
-
-
G7
page 80
page 80
page 80
page 80
page 80
page 80
page 80
page 80
page 80
page 80
page 80
page 80
page 80
SADDOUT[0]#
SADDOUT[1]#
NC Pin
page 81
page 81
page 80
page 81
page 80
P
P
-
O
O
-
-
G9
Key Pin
-
-
-
J3
-
G11
G13
G15
G17
G19
G21
G23
G25
G27
G29
G31
G33
G35
G37
H2
NC Pin
-
-
-
J5
-
NC Pin
-
-
-
J7
VID[4]
O
-
O
-
-
Key Pin
-
-
-
J31
J33
J35
J37
K2
NC Pin
-
Key Pin
-
-
-
SDATA[19]#
SDATAINCLK[1]#
SDATA[29]#
VSS
P
P
P
-
B
I
G
P
P
-
NC Pin
-
-
-
NC Pin
-
-
-
B
-
Key Pin
-
-
-
Key Pin
-
-
-
K4
VSS
-
-
-
NC Pin
-
-
-
K6
VSS
-
-
-
NC Pin
-
-
-
K8
SOFTVID[1]
NC Pin
page 81
page 80
O
-
O
-
-
NC Pin
-
-
-
K30
K32
K34
K36
L1
-
SDATA[20]#
SDATA[23]#
SDATA[21]#
VCC_CORE
VCC_CORE
SOFTVID[2]
SOFTVID[3]
SOFTVID[4]
VCC_CORE
P
P
P
-
B
B
B
-
G
G
G
-
VCC_CORE
VCC_CORE
VCC_CORE
VID[0]
-
-
-
-
-
-
-
-
-
page 81
page 81
page 81
page 81
page 80
O
O
O
O
-
O
O
O
O
-
-
H4
-
-
-
L3
VID[1]
-
H6
page 81
page 81
page 81
O
O
O
-
O
O
O
-
-
L5
VID[2]
-
H8
-
L7
VID[3]
-
H10
H12
-
L31
L33
NC Pin
-
-
SDATA[26]#
P
B
P
72
Pin Descriptions
Chapter 10
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Table 24. Cross-Reference by Pin Location (continued)
Pin
L35
Name
NC Pin
Description
L
-
P
-
R
-
Pin
R2
Name
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VSS
Description
L
-
P
-
R
-
page 80
L37
M2
M4
M6
M8
M30
M32
M34
M36
N1
SDATA[28]#
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VSS
P
-
B
-
P
-
R4
-
-
-
R6
-
-
-
-
-
-
R8
-
-
-
-
-
-
R30
R32
R34
R36
S1
-
-
-
-
-
-
VSS
-
-
-
-
-
-
VSS
-
-
-
VSS
-
-
-
VSS
-
-
-
VSS
-
-
-
SCANCLK1
SCANINTEVAL
SCANCLK2
THERMDA
NC Pin
page 81
page 81
page 81
page 83
page 80
P
P
P
-
I
-
VSS
-
-
-
S3
I
-
RSVD
page 80
page 80
page 80
page 80
page 80
-
-
-
S5
I
-
N3
RSVD
-
-
-
S7
-
-
N5
RSVD
-
-
-
S31
S33
S35
S37
T2
-
-
-
N7
Key Pin
-
-
-
SDATA[7]#
SDATA[15]#
SDATA[6]#
VSS
P
P
P
-
B
B
B
-
G
P
G
-
N31
N33
N35
N37
P2
NC Pin
-
-
-
SDATA[25]#
SDATA[27]#
SDATA[18]#
VSS
P
P
P
-
B
B
B
-
P
P
G
-
T4
VSS
-
-
-
T6
VSS
-
-
-
P4
VSS
-
-
-
T8
VSS
-
-
-
P6
VSS
-
-
-
T30
T32
T34
T36
U1
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
TDI
-
-
-
P8
VSS
-
-
-
-
-
-
P30
P32
P34
P36
Q1
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
TCK
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
page 79
page 79
page 79
page 83
page 80
P
P
P
-
I
-
-
-
-
U3
TRST#
I
-
page 79
page 79
page 81
page 80
page 80
P
P
P
-
I
-
U5
TDO
O
-
-
Q3
TMS
I
-
U7
THERMDC
NC Pin
-
Q5
SCANSHIFTEN
Key Pin
I
-
U31
U33
U35
U37
V2
-
-
-
Q7
-
-
SDATA[5]#
SDATA[4]#
NC Pin
P
P
-
B
B
-
G
G
-
Q31
Q33
Q35
Q37
NC Pin
-
-
-
SDATA[24]#
SDATA[17]#
SDATA[16]#
P
P
P
B
B
B
P
G
G
page 80
VCC_CORE
VCC_CORE
-
-
-
V4
-
-
-
Chapter 10
Pin Descriptions
73
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Table 24. Cross-Reference by Pin Location (continued)
Pin
V6
Name
VCC_CORE
VCC_CORE
VSS
Description
L
-
P
-
R
-
Pin
Z30
Name
Description
L
-
P
-
R
-
VSS
VSS
VSS
VSS
V8
-
-
-
Z32
Z34
Z36
AA1
AA3
AA5
AA7
-
-
-
V30
V32
V34
V36
W1
W3
W5
W7
W31
W33
W35
W37
X2
-
-
-
-
-
-
VSS
-
-
-
-
-
-
VSS
-
-
-
DBRDY
DBREQ#
NC Pin
page 79
page 79
page 80
page 80
page 80
P
P
-
O
I
-
VSS
-
-
-
-
FID[0]
page 79
page 79
page 83
page 80
page 80
O
O
P
-
O
O
-
-
-
-
FID[1]
-
Key Pin
-
-
-
VREF_SYS
NC Pin
-
AA31 NC Pin
-
-
-
-
-
AA33 SDATA[8]#
AA35 SDATA[0]#
AA37 SDATA[13]#
P
P
P
-
B
B
B
-
P
G
G
-
NC Pin
-
-
-
SDATAINCLK[0]#
SDATA[2]#
SDATA[1]#
VSS
P
P
P
-
I
G
G
P
-
B
B
-
AB2
AB4
AB6
AB8
VSS
VSS
VSS
VSS
-
-
-
-
-
-
X4
VSS
-
-
-
-
-
-
X6
VSS
-
-
-
AB30 VCC_CORE
AB32 VCC_CORE
AB34 VCC_CORE
AB36 VCC_CORE
-
-
-
X8
VSS
-
-
-
-
-
-
X30
X32
X34
X36
Y1
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
FID[2]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AC1
AC3
AC5
AC7
STPCLK#
PLLTEST#
ZN
page 81
page 80
page 83
page 80
page 80
P
P
P
-
I
-
-
-
-
I
-
page 79
page 79
page 80
page 80
page 80
page 80
O
O
-
O
O
-
-
-
-
Y3
FID[3]
-
NC Pin
-
-
Y5
NC Pin
-
AC31 NC Pin
-
-
-
Y7
Key Pin
-
-
-
AC33 SDATA[10]#
AC35 SDATA[14]#
AC37 SDATA[11]#
P
P
P
-
B
B
B
-
P
G
G
-
Y31
Y33
Y35
Y37
Z2
NC Pin
-
-
-
NC Pin
-
-
-
SDATA[3]#
SDATA[12]#
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
P
P
-
B
B
-
G
P
-
AD2
AD4
AD6
AD8
VCC_CORE
VCC_CORE
VCC_CORE
NC Pin
-
-
-
-
-
-
Z4
-
-
-
page 80
page 80
-
-
-
Z6
-
-
-
AD30 NC Pin
AD32 VSS
-
-
-
Z8
-
-
-
-
-
-
74
Pin Descriptions
Chapter 10
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Table 24. Cross-Reference by Pin Location (continued)
Pin
Name
Description
L
-
P
-
R
-
Pin
Name
Description
page 78
page 80
page 80
page 80
page 80
page 80
page 80
page 80
page 80
page 80
L
-
P
-
-
-
-
-
-
-
-
-
-
I
I
I
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I
I
-
R
-
AD34 VSS
AD36 VSS
AG13 COREFB#
AG15 Key Pin
AG17 Key Pin
AG19 NC Pin
-
-
-
-
-
AE1
AE3
AE5
AE7
A20M#
PWROK
P
P
P
-
I
-
-
-
I
-
-
-
ZP
page 83
page 80
page 80
-
-
AG21 NC Pin
-
-
NC Pin
-
-
AG23 NC Pin
-
-
AE31 NC Pin
-
-
-
AG25 NC Pin
-
-
AE33 SADDIN[5]#
AE35 SDATAOUTCLK[0]#
AE37 SDATA[9]#
P
P
P
-
I
G
P
G
-
AG27 Key Pin
AG29 Key Pin
AG31 NC Pin
-
-
O
B
-
-
-
-
-
AF2
AF4
AF6
AF8
VSS
AG33 SADDIN[2]#
AG35 SADDIN[11]#
AG37 SADDIN[7]#
P
P
P
-
G
G
P
-
VSS
-
-
-
NC Pin
NC Pin
page 80
page 80
page 80
-
-
-
-
-
-
AH2
AH4
AH6
AH8
VCC_CORE
VCC_CORE
AMD Pin
NC Pin
AF10 NC Pin
AF12 VSS
-
-
-
-
-
-
-
-
page 78
page 80
-
-
AF14 VCC_CORE
AF16 VSS
-
-
-
-
-
-
-
-
AH10 VCC_CORE
AH12 VSS
-
-
AF18 VCC_CORE
AF20 VSS
-
-
-
-
-
-
-
-
AH14 VCC_CORE
AH16 VSS
-
-
AF22 VCC_CORE
AF24 VSS
-
-
-
-
-
-
-
-
AH18 VCC_CORE
AH20 VSS
-
-
AF26 VCC_CORE
AF28 NC Pin
AF30 NC Pin
AF32 NC Pin
AF34 VCC_CORE
AF36 VCC_CORE
-
-
-
-
-
page 80
page 80
page 80
-
-
-
AH22 VCC_CORE
AH24 VSS
-
-
-
-
-
-
-
-
-
-
AH26 VCC_CORE
AH28 VSS
-
-
-
-
-
-
-
-
-
-
AH30 NC Pin
AH32 VSS
page 80
-
-
AG1
AG3
AG5
AG7
AG9
FERR
page 79
P
-
O
I
-
-
-
RESET#
NC Pin
Key Pin
Key Pin
-
AH34 VSS
-
-
page 80
page 80
page 80
page 78
-
-
-
AH36 VSS
-
-
-
-
-
AJ1
AJ3
AJ5
IGNNE#
INIT#
page 79
page 79
P
P
-
-
-
-
-
-
AG11 COREFB
-
-
-
VCC_CORE
-
Chapter 10
Pin Descriptions
75
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Table 24. Cross-Reference by Pin Location (continued)
Pin
AJ7
Name
Description
page 80
page 80
page 80
page 78
page 80
page 80
page 80
page 78
page 83
page 80
page 80
page 81
L
-
P
-
-
-
-
-
-
-
I
-
I
-
I
I
I
I
I
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R
-
Pin
AL1
Name
Description
page 79
L
P
P
-
P
I
R
-
NC Pin
NC Pin
NC Pin
INTR
AJ9
-
-
AL3
AL5
AL7
AL9
FLUSH#
VCC_CORE
NC Pin
page 79
I
-
AJ11
AJ13
AJ15
AJ17
AJ19
AJ21
-
-
-
-
Analog
-
-
page 80
page 80
page 80
page 80
page 80
page 78
page 78
page 80
page 78
page 80
page 80
page 81
-
-
-
NC Pin
-
-
NC Pin
-
-
-
NC Pin
-
-
AL11 NC Pin
-
-
-
NC Pin
-
-
AL13 PLLMON2
AL15 PLLBYPASSCLK#
O
P
P
P
P
P
-
O
I
-
CLKFWDRST
P
-
P
-
-
AJ23 VCCA
AL17
CLKIN#
I
P
P
-
AJ25 PLLBYPASS#
AJ27 NC Pin
P
-
-
AL19 RSTCLK#
I
-
AL21 K7CLKOUT
AL23 CONNECT
AL25 NC Pin
O
I
AJ29 SADDIN[0]#
P
P
P
P
P
-
-
P
-
AJ31
SFILLVALID#
G
G
P
G
-
-
AJ33 SADDINCLK#
AJ35 SADDIN[6]#
AL27 NC Pin
-
-
-
AL29 SADDIN[1]#
AL31 SDATAOUTVALID#
AL33 SADDIN[8]#
AL35 SADDIN[4]#
AL37 SADDIN[10]#
P
P
P
P
P
-
I
-
AJ37
AK2
AK4
AK6
AK8
SADDIN[3]#
VSS
O
I
P
P
G
G
-
VSS
-
-
I
CPU_PRESENCE#
NC Pin
page 78
page 80
-
-
I
-
-
AM2
AM4
AM6
AM8
VCC_CORE
VSS
-
AK10 VCC_CORE
AK12 VSS
-
-
-
-
-
-
-
VSS
-
-
-
AK14 VCC_CORE
AK16 VSS
-
-
NC Pin
page 80
-
-
-
-
-
AM10 VCC_CORE
AM12 VSS
-
-
-
AK18 VCC_CORE
AK20 VSS
-
-
-
-
-
-
-
AM14 VCC_CORE
AM16 VSS
-
-
-
AK22 VCC_CORE
AK24 VSS
-
-
-
-
-
-
-
AM18 VCC_CORE
AM20 VSS
-
-
-
AK26 VCC_CORE
AK28 VSS
-
-
-
-
-
-
-
AM22 VCC_CORE
AM24 VSS
-
-
-
AK30 VCC_CORE
AK32 VSS
-
-
-
-
-
-
-
AM26 VCC_CORE
AM28 VSS
-
-
-
AK34 VCC_CORE
AK36 VCC_CORE
-
-
-
-
-
-
-
AM30 VCC_CORE
-
-
-
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Chapter 10
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Table 24. Cross-Reference by Pin Location (continued)
Pin
Name
Description
L
-
P
-
R
-
AM32 VSS
AM34 VCC_CORE
AM36 VSS
-
-
-
-
-
-
AN1
AN3
AN5
AN7
AN9
No Pin
NMI
page 80
-
-
-
P
P
-
I
-
SMI#
I
-
NC Pin
NC Pin
page 80
page 80
page 80
page 80
page 80
page 78
page 78
page 80
-
-
-
-
-
AN11 NC Pin
-
-
-
AN13 PLLMON1
AN15 PLLBYPASSCLK
AN17 CLKIN
O
P
P
P
P
P
-
B
I
-
-
I
P
P
-
AN19 RSTCLK
I
AN21 K7CLKOUT#
AN23 PROCRDY
AN25 NC Pin
O
O
-
P
-
page 80
page 80
AN27 NC Pin
-
-
-
AN29 SADDIN[12]#
AN31 SADDIN[14]#
AN33 SDATAINVALID#
AN35 SADDIN[13]#
AN37 SADDIN[9]#
P
P
P
P
P
I
G
G
P
G
G
I
I
I
I
Chapter 10
Pin Descriptions
77
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
10.3
Detailed Pin Descriptions
The information in this section pertains to Table 23 on page 64
and Table 24 on page 70.
A20M# Pin
AMD Pin
A20M# is an input from the system used to simulate address
wrap-around in the 20-bit 8086.
AMD Socket A processors do not implement a pin at location
AH6. All Socket A designs must have a top plate or cover that
b lock s t h is p in loca t ion . Wh e n t h e cove r p la t e b lock s t h is
location, a non-AMD part (e.g., PGA370) does not fit into the
socket. However, socket manufacturers are allowed to have a
contact loaded in the AH6 position. Therefore, motherboard
socket design should account for the possibility that a contact
could be loaded in this position.
AMD Duron™ System
Bus Pins
S e e t h e AM D At h l on ™ a n d AM D Du r on ™ Sy st em Bu s
Specification, order# 21902 for information about the system
b u s p in s —P ROCR DY, P WROK, R E SE T#, SADDIN[14:2]#,
S A D D I N C L K # , S A D D O U T [ 1 4 :2 ] # , S A D D O U T C L K # ,
SDATA[63:0]#, SDATAINCLK[3:0]#, SDATAINVALID#,
SDATAOUTCLK[3:0]#, SDATAOUTVALID#, SFILLVALID#.
Analog Pin
Treat this pin as a NC.
CLKFWDRST Pin
CLKFWDRST resets clock-forward circuitry for both the system
and processor.
CLKIN and RSTCLK
(SYSCLK) Pins
Con n e ct CLKIN (AN17) wit h R STCLK (AN19) a n d n a m e it
SYSCLK. Connect CLKIN# (AL17) with RSTCLK# (AL19) and
n a me it SYSCLK#. Le n gt h ma t ch t h e clock s from t h e clock
generator to the Northbridge and processor.
See “SYSCLK and SYSCLK#” on page 83 for more information.
CONNECT Pin
CONNE CT is a n in p u t fr om t h e syst e m u se d for p owe r
management and clock-forward initialization at reset.
COREFB and
COREFB# Pins
COREFB and COREFB# are outputs to the system that provide
processor core voltage feedback to the system.
CPU_PRESENCE# Pin
CP U _P R E SE NCE # is con n e ct e d t o VSS on t h e p r oce ssor
package. If pulled-up on the motherboard, CPU_PRESENCE#
may be used to detect the presence or absence of a processor.
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Pin Descriptions
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Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
DBRDY and DBREQ#
Pins
DBRDY (AA1) and DBREQ# (AA3) are rout ed t o the debug
con n e ct or. DBR E Q# is t ie d t o VCC_COR E wit h a p u llu p
resistor.
FERR Pin
F E R R is a n ou t p u t t o t h e syst e m t h a t is a sse r t e d for a ny
unmasked numerical exception independent of the NE bit in
CR 0. F E R R is a p u sh -p u ll a ct ive H igh sign a l t h a t mu st b e
inverted and level shifted to an active Low signal. For more
in for m a t ion a b ou t F E R R a n d F E R R #, se e t h e “ R e q u ire d
Cir cu it s” ch a p t e r of t h e AMD At h lon ™ Pr ocessor-Ba sed
Motherboard Design Guide, order# 24363.
FID[3:0] Pins
The FID[3:0] pins drive a value of:
FID[3:0] = 0 1 0 0
that corresponds to a 5x SYSCLK multiplier after PWROK is
asserted to the processor. This information is used by the
Northbridge to create the SIP stream that the Northbridge
sends to the processor after RESET# is deasserted.
For more information, see “SYSCLK Multipliers” on page 24
and “Frequency Identification (FID[3:0])” on page 35 for the
AC and DC characteristics for FID[3:0].
FLUSH# Pin
FLUSH# must be tied to VCC_CORE with a pullup resistor. If a
d eb u g con n e ct or is im p le me n t ed , F LU SH # is rou t e d t o t h e
debug connector.
IGNNE# Pin
INIT# Pin
IGNNE# is an input from the system that tells the processor to
ignore numeric errors.
INIT# is a n in p u t from t h e syst e m t h a t re se t s t h e in t e ge r
registers without affecting the floating-point registers or the
internal caches. Execution starts at 0FFFF FFF0h.
INTR Pin
JTAG Pins
INTR is an input from the system that causes the processor to
start an interrupt acknowledge transaction that fetches the
8-bit interrupt vector and starts execution at that location.
TCK (Q1), TMS (Q3), TDI (U1), TRST# (U3), and TDO (U5) are
t h e J TAG in t e r fa ce . Con n e ct t h e se p in s d ir e ct ly t o t h e
mot h e r b oa rd d eb u g con n e ct or. Pu llu p TDI, TCK, TMS, a n d
TRST# to VCC_CORE with pullup resistors.
Chapter 10
Pin Descriptions
79
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
K7CLKOUT and
K7CLKOUT# Pins
K7CLKOUT (AL21) and K7CLKOUT# (AN21) are each run for 2
to 3 inches and then terminated with a resistor pair, 100 ohms to
VCC_CORE and 100 ohms to VSS. The effective termination
resistance and voltage are 50 ohms and VCC_CORE/2.
Key Pins
These 16 locations are for processor type keying for forwards
and backwards compatibility (G7, G9, G15, G17, G23, G25, N7,
Q7, Y7, AA7, AG7, AG9, AG15, AG17, AG27, a n d AG29).
Mot h e r b oa rd d e sign e rs sh ou ld t re a t key p in s like NC (No
Connect) pins. A socket designer has the option of creating a
top mold piece that allows PGA key pins only where designated.
However, sockets that populate all 16 key pins must be allowed,
so the motherboard must always provide for pins at all key pin
locations.
NC Pins
The motherboard should provide a plated hole for an NC pin.
The pin hole should not be electrically connected to anything.
NMI Pin
NMI is an input from the system that causes a non-maskable
interrupt.
PGA Orientation Pins
No pin is present at pin locations A1 and AN1. Motherboard
d e sign e rs sh ou ld n ot a llow for a P GA socke t p in a t t h e se
locations.
For more information, see the AMD Athlon™ Processor-Based
Motherboard Design Guide, order# 24363.
PLL Bypass and Test
Pins
PLLTEST# (AC3), PLLBYPASS# (AJ 25), PLLMON1 (AN13),
P L L M O N 2 ( A L 1 3 ) , P L L BY PA S S C L K ( A N 1 5 ) , a n d
P LLBYPASSCLK# (AL15) a r e t h e P LL b yp a ss a n d t e st
interface. This interface is tied disabled on the motherboard.
All six pin signals are routed to the debug connector. All four
processor inputs (PLLTEST#, PLLBYPASS#, PLLMON1, and
PLLMON2) are tied to VCC_CORE with pullup resistors.
PWROK Pin
The PWROK input to the processor must not be asserted until
all voltage planes in the system are within specification and all
system clocks are running within specification.
F o r m o r e i n f o r m a t i o n , s e e “ S i g n a l a n d P o w e r -U p
Requirements” on page 53.
RSVD Pins
Reserved pins (N1, N3, and N5) must have pulldown resistors to
ground on the motherboards.
80
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Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
SADDIN[1:0]# and
SADDOUT[1:0]# Pins
The mobile AMD Duron processor model 7 does not support
SADDIN[1:0]# or SADDOUT[1:0]#. SADDIN[1]# is tied to VCC
wit h p u llu p r e sist or s, if t h is b it is n ot su p p or t e d b y t h e
Nor t h b r id ge (fu t u r e m od e ls of t h e m ob ile AMD Du r on
processors may support SADDIN[1]#). SADDOUT[1:0]# are tied
to VCC with pullup resistors if these pins are supported by the
Northbridge. For more information, see the AMD Athlon™ and
AMD Duron™ System Bus Specification, order# 21902.
Scan Pins
SMI# Pin
SCANSHIFTEN (Q5), SCANCLK1 (S1), SCANINTEVAL (S3),
and SCANCLK2 (S5) are the scan interface. This interface is
AMD internal and is tied disabled with pulldown resistors to
ground on the motherboard.
SMI# is an input that causes the processor to enter the system
management mode.
SOFTVID[4:0] and
VID[4:0] Pins
The VID[4:0] (Voltage ID) and SOFTVID[4:0] (Software driven
Voltage ID) outputs are used by the DC to DC power converter
t o se le ct t h e p rocessor core volt a ge. Th e VID[4:0] p in s a re
st rapped to ground or left unconnected on the package and
must be pulled up on the motherboard. The SOFTVID[4:0] pins
are open drain and 2.5-V tolerant. The SOFTVID[4:0] pins of
the processor must not be pulled to voltages higher than 2.5 V.
The motherboard is required to implement a VID multiplexer to
select a deterministic voltage for the processor at power–up
b e fore t h e P WROK in p u t is a sse r t e d . Be fore P WROK is
a sse r t e d , t h e VID m u lt ip le xe r d r ive s t h e VID va lu e from
VID[4:0] pins to the DC to DC converter for VCC_CORE. After
PWROK is asserted, the VID multiplexer drives the VID value
from t h e SOFTVID[4:0] p in s t o t h e DC t o DC conver te r for
VCC_COR E of t h e p roce ssor. R e fe r t o t h e AMD At h lon ™
Processor-Based Motherboard Design Guide, order# 24363 for the
recommended VID multiplexer circuit.
The SOFTVID[4:0] pins are driven by the processor to select the
m a ximu m VCC_COR E of t h e p roce ssor a s re p or t e d by t h e
Maximum VID field of the FidVidStatus MSR within 20 ns of
P W R O K a s s e r t i o n . Be f o r e P W R O K i s a s s e r t e d , t h e
SOFTVID[4:0] outputs are not driven to a deterministic value.
The SOFTVID[4:0] outputs must be used to select VCC_CORE
a ft e r P WROK is a sse r t e d . An y t im e t h e R E SE T# in p u t is
asserted, the SOFTVID[4:0] pins will be driven to select the
maximum voltage.
Chapter 10
Pin Descriptions
81
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Note: The Start–up VID and Maximum VID fields of the
FidVidStatus MSR report the same value that corresponds
to the nominal voltage that the processor requires to operate
at maximum frequency.
AMD Powe r Now!™ t e ch n ology ca n u se t h e F ID_Ch a n ge
p rot ocol d e scr ib e d in Se ct ion on p a ge 9 t o t ra n sit ion t h e
SOFTVID[4:0] out put s and therefore VCC_COR E as part of
processor performance state transitions.
The VID codes used by the mobile AMD Duron processor model
7 are defined in Table 25.
Note: VID codes for the mobile AMD Duron processors are
different from the VID codes for the desktop AMD Duron
processors.
Table 25. SOFTVID[4:0] and VID[4:0] Code to Voltage Definition
VID[4:0]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
VCC_CORE (V)
2.000
VID[4:0]
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
VCC_CORE (V)
1.275
1.950
1.250
1.900
1.225
1.850
1.200
1.800
1.175
1.750
1.150
1.700
1.125
1.650
1.100
1.600
1.075
1.550
1.050
1.500
1.025
1.450
1.000
1.400
0.975
1.350
0.950
1.300
0.925
Shutdown
Shutdown
STPCLK# Pin
STPCLK# is an input that causes the processor to enter a lower
power mode and issue a Stop Grant special cycle.
82
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Mobile AMD Duron™ Processor Model 7 Data Sheet
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SYSCLK and SYSCLK#
SYSCLK a n d SYSCLK# a re d iffe re n tial in p u t clock sign a ls
provided to the processor’s PLL from a system-clock generator.
See “CLKIN and RSTCLK (SYSCLK) Pins” on page 78 for more
information.
THERMDA and
THERMDC Pins
Thermal Diode anode (THERMDA) and cathode (THERMDC)
p in s a r e u se d t o m on it or t h e a ct u a l t e m p e r a t u r e of t h e
processor die, providing more accurate temperature control to
the system. See Table 17 on page 48 for more details.
VCCA Pin
VCCA is the processor PLL supply. For information about the
VCCA pin, see Table 7, “VCCA AC and DC Characteristics,” on
page 35 and the AMD At hlon™ Processor-Ba sed Mot herboard
Design Guide, order# 24363.
VREF_SYS Pin
VREF_SYS (W5) drives the threshold voltage for the system
bus input receivers. The value of VREF_SYS is system specific.
In a d d it ion , t o m in im ize VCC_COR E n oise re j e ct ion from
V R E F _S YS , i n c l u d e d e c o u p l i n g c a p a c i t o r s . Fo r m o r e
information, see the AMD Athlon™ Processor-Based Motherboard
Design Guide, order# 24363.
ZN and ZP Pins
ZN (AC5) and ZP (AE5) are the push-pull compensation circuit
p in s. In P u sh -P u ll m od e (se le ct e d b y t h e SIP p a r a m e t e r
SysPushPull asserted), ZN is tied to VCC_CORE with a resistor
t h a t h a s a re sist a n ce m a t ch in g t h e im p e d a n ce Z0 of t h e
transmission line. ZP is tied to VSS with a resistor that has a
resistance matching the impedance Z0 of the transmission line.
Chapter 10
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83
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
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84
Pin Descriptions
Chapter 10
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
11
Ordering Information
11.1
Standard Mobile AMD Duron™ Processor Model 7 Products
AMD st a n d a rd p rod u ct s a re ava ilab le in seve ra l op e ra t in g
ra n ge s. Th e or d e r in g p a r t n u m b e r (OP N) is for m e d b y a
combination of the elements shown in Figure 17. This OPN is
given as an example only.
CPGA OPN
D HM 1000 A V S 1 B
Max FSB: B= 200 MHz
Size of L2 Cache: 1=64Kbytes
Die Temperature: S=95ºC
Operating Voltage: L=1.50 V, Q=1.45 V, V=1.40 V
Package Type: A = CPGA
Speed: 0800=800 MHz, 0850=850, 0900=900 MHz,
0950=950 MHz, 1000=1000 MHz
Generation: HM = High-Performance Processor for Mobile Systems
Family/Architecture: D = AMD Duron™ Processor Architecture
Note: Spaces are added to the number shown
above for viewing clarity only.
Figure 17. OPN Example for the Mobile AMD Duron™ Processor Model 7
Chapter 11
Ordering Information
85
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
86
Ordering Information
Chapter 11
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Signals and Bits
Appendix A
Appendix A
Conventions, Abbreviations,
and References
This section contains information about the conventions and
abbreviations used in this document.
■ Active-Low Signals—Signal names containing a pound sign,
such as SFILL#, indicate active-Low signals. They are
asserted in their Low-voltage state and negated in their
High-voltage state. When used in this context, High and
Low are written with an initial upper case letter.
■ Signal Ranges—In a range of signals, the highest and lowest
signal numbers are contained in brackets and separated by
a colon (for example, D[63:0]).
■ Reserved Bits and Signals—Signals or bus bits marked
reserved must be driven inactive or left unconnected, as
indicated in the signal descriptions. These bits and signals
are reserved by AMD for future implementations. When
software reads registers with reserved bits, the reserved bits
must be masked. When software writes such registers, it
must first read the register and change only the
non-reserved bits before writing back to the register.
■ Three-State —In timing diagrams, signal ranges that are
high impedance are shown as a straight horizontal line
half-way between the high and low levels.
87
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
■ Invalid and Don’t-Care —In timing diagrams, signal ranges
that are invalid or don't-care are filled with a screen
pattern.
Data Terminology
The following list defines data terminology:
■ Quantities
•
•
•
•
A word is two bytes (16 bits)
A doubleword is four bytes (32 bits)
A quadword is eight bytes (64 bits)
A mobile AMD Duron processor model 7 cache line is
eight quadwords (64 bytes)
■ Addressing—Memory is addressed as a series of bytes on
eight-byte (64-bit) boundaries in which each byte can be
separately enabled.
■ Abbreviations—The following notation is used for bits and
bytes:
•
•
•
Kilo (K, as in 4-Kbyte page)
Mega (M, as in 4 Mbits/sec)
Giga (G, as in 4 Gbytes of memory space)
See Table 26 for more abbreviations.
■ Little-Endian Convention —The byte with the address
xx...xx00 is in the least-significant byte position (little end).
In byte diagrams, bit positions are numbered from right to
left —the little end is on the right and the big end is on the
left. Data structure diagrams in memory show low addresses
at the bottom and high addresses at the top. When data
items are aligned, bit notation on a 64-bit data bus maps
directly to bit notation in 64-bit-wide memory. Because byte
addresses increase from right to left, strings appear in
reverse order when illustrated.
■ Bit Ranges—In text, bit ranges are shown with a dash (for
example, bits 9–1). When accompanied by a signal or bus
name, the highest and lowest bit numbers are contained in
brackets and separated by a colon (for example, AD[31:0]).
■ Bit Values—Bits can either be set to 1 or cleared to 0.
■ Hexadecimal and Binary Numbers—Unless the context
makes interpretation clear, hexadecimal numbers are
followed by an h and binary numbers are followed by a b.
88
Appendix A
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Abbreviations and Acronyms
Table 26 contains the definitions of abbreviations used in this
document.
Table 26.
Abbreviations
Abbreviation
A
Meaning
Ampere
F
Farad
G
Giga–
Gbit
Gbyte
H
Gigabit
Gigabyte
Henry
h
Hexadecimal
Kilo–
K
Kbyte
M
Kilobyte
Mega–
Mbit
Mbyte
MHz
m
Megabit
Megabyte
Megahertz
Milli–
ms
Millisecond
Milliwatt
Micro–
mW
µ
µA
µF
Microampere
Microfarad
Microhenry
Microsecond
Microvolt
nano–
µH
µs
µV
n
nA
nF
nanoampere
nanofarad
nanohenry
nanosecond
Ohm
nH
ns
ohm
pF
picofarad
picohenry
picosecond
pH
ps
Appendix A
89
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Table 26.
Abbreviations (continued)
Abbreviation
Meaning
Second
Volt
s
V
W
Watt
Table 27 cont a ins t he defin it ions of acronym s u sed in t his
document.
Table 27.
Acronyms
Abbreviation
ACPI
Meaning
Advanced Configuration and Power Interface
Accelerated Graphics Port
AGP
APCI
AGP Peripheral Component Interconnect
Application Programming Interface
Basic Input/Output System
API
BIOS
BIST
Built-In Self-Test
BIU
Bus Interface Unit
CPGA
DDR
Ceramic Pin Grid Array
Double-Data Rate
DIMM
DMA
DRAM
EIDE
EISA
Dual Inline Memory Module
Direct Memory Access
Direct Random Access Memory
Enhanced Integrated Device Electronics
Extended Industry Standard Architecture
Enhanced Programmable Read Only Memory
First In, First Out
EPROM
FIFO
GART
HSTL
IDE
Graphics Address Remapping Table
High-Speed Transistor Logic
Integrated Device Electronics
Industry Standard Architecture
Joint Electron Device Engineering Council
Joint Test Action Group
ISA
JEDEC
JTAG
LAN
Large Area Network
LRU
Least-Recently Used
LVTTL
MSB
Low Voltage Transistor to Transistor Logic
Most Significant Bit
MTRR
Memory Type and Range Registers
90
Appendix A
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Table 27.
Acronyms (continued)
Abbreviation
MUX
NMI
Meaning
Multiplexer
Non-Maskable Interrupt
Organic Ball Grid Array
Open Drain
OBGA
OD
PBGA
PA
Plastic Ball Grid Array
Physical Address
PCI
Peripheral Component Interconnect
Page Directory Entry
PDE
PDT
Page Directory Table
PLL
Phase Locked Loop
PMSM
POS
Power Management State Machine
Power-On Suspend
POST
RAM
ROM
RXA
Power-On Self-Test
Random Access Memory
Read Only Memory
Read Acknowledge Queue
System DRAM Interface
Synchronous Direct Random Access Memory
Serial Initialization Packet
System Management Bus
Serial Presence Detect
Synchronous Random Access Memory
Serial Read Only Memory
Translation Lookaside Buffer
Top of Memory
SDI
SDRAM
SIP
SMbus
SPD
SRAM
SROM
TLB
TOM
TTL
Transistor to Transistor Logic
Virtual Address Space
VAS
VPA
Virtual Page Address
VGA
USB
Video Graphics Adapter
Universal Serial Bus
ZDB
Zero Delay Buffer
Appendix A
91
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Related Publications
Th e followin g b ook s d iscu ss va r iou s a sp e ct s of com p u t e r
architecture that may enhance your understanding of AMD
products:
AMD Publications
Mobile AMD At h lon ™ a n d Mobile AMD Du r on ™ Pr ocessor
System Requirements, order# 24106
Mobile AMD Athlon™ and Mobile AMD Duron™ Processor Power
Module Supply Design Guide, order# 24125
Mobile System Thermal Design Guide, order# 24383
Measuring Temperature on AMD Athlon™ and AMD Duron™ Pin
Grid Array Processors with and without an On-die Thermal Diode,
order# 24228
Thermal Characterization of Notebook PCs, order# 24382
Methodologies for Measuring Power, order# 24353
Methodologies for Measuring Temperature on AMD Athlon™ and
AMD Duron™ Processors, order# 24228
Instruction Sheet for Mobile Thermal Kits, order# 24400
AMD Mobile Thermal Kit Documentation and Software CD–ROM,
order# 24406
Websites
Visit the AMD website for documentation of AMD products.
www.amd.com
Other websites of interest include the following:
■ J EDEC home page —www.jedec.org
■ IEEE home page —www.computer.org
■ AGP Forum —www.agpforum.org
92
Appendix A
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