EDI88130LP70ZM [ETC]

x8 SRAM ; X8 SRAM\n


型号：	EDI88130LP70ZM
厂家：	ETC
描述：	x8 SRAM X8 SRAM\n 内存集成电路静态存储器
文件：	总8页 (文件大小：156K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

EDI88128C

HI-RELIABILITY PRODUCT

128Kx8 Monolithic SRAM, SMD 5962-89598

FEATURES

The EDI88128C is a high speed, high performance, Monolithic

CMOS Static RAM organized as 128Kx8.

■ Access Times of 70, 85, 100ns

■ Available with Single Chip Selects (EDI88128) or Dual Chip

The device is also available as EDI88130C with an additional chip

select line (CS2) which will automatically power down the device

when proper logic levels are applied.

Selects (EDI88130)

■ 2V Data Retention (LP Versions)

■ CS and OE Functions for Bus Control

■ TTL Compatible Inputs and Outputs

■ Fully Static, No Clocks

The second chip select line (CS2) can be used to provide system

memory security during power down in non-battery backed up

systems and simplifiy decoding schemes in memory banking

where large multiple pages of memory are required.

■ Organized as 128Kx8

The EDI88128C and the EDI88130C have eight bi-directional in-

put-output lines to provide simultaneous access to all bits in a

word. An automatic power down feature permits the on-chip

circuitry to enter a very low standby mode and be brought back

into operation at a speed equal to the address access time.

■ Industrial, Military and Commercial Temperature Ranges

■ Thru-hole and Surface Mount Packages JEDEC Pinout

• 32 pin Ceramic DIP, 0.6 mils wide (Package 9)

• 32 lead Ceramic ZIP (Package 100)

• 32 lead Ceramic SOJ (Package 140)

Low power versions, EDI88128LP and EDI88130LP, offer a 2V data

retention function for battery back-up opperation. Military prod-

uct is available compliant to Appendix A of MIL-PRF-38535.

■ Single +5V (±10%) Supply Operation

FIG. 1 PIN CONFIGURATION

PIN DESCRIPTION

32 DIP

I/O0-7

A0-16

Data Inputs/Outputs

Address Inputs

Write Enable

32 SOJ

32 ZIP

TOP VIEW

A16

A14

A12

A6 11

A5 13

A4 15

A3 17

A2 19

A1 21

AØ 23

I/OØ 25

I/O1 27

I/O2 29

A16

A14

A12

A2 10

A1 11

AØ 12

I/OØ 13

I/O1 14

I/O2 15

32 VCC

VCC

A15

NC/CS2*

CS1, CS2

Chip Selects

31 A15

30 NC/CS2*

29 WE

28 A13

27 A8

26 A9

25 A11

24 OE

23 A10

22 CS1

21 I/O7

20 I/O6

19 I/O5

18 I/O4

17 I/O3

Output Enable

Power (+5V ±10%)

Ground

VCC

10 A13

12 A8

14 A9

VSS

Not Connected

16 A11

18 OE

20 A10

22 CS1

24 I/O7

26 I/O6

28 I/O5

30 I/O4

32 I/O3

BLOCK DIAGRAM

Memory Array

VSS 31

SS 16

Address

Buffer

Address

Decoder

I/O

Circuits

Ø-16

I/OØ-7

CS1

* Pin 30 is NC for 88128 or CS2 for 88130.

July 1999 Rev. 13

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

EDI88128C

TRUTH TABLE

ABSOLUTE MAXIMUM RATINGS

Parameter

Unit

CS1

CS2

Mode

Standby

Output

Power

Icc2, Icc3

Icc1

High Z

Data Out

Data In

Voltage on any pin relative to Vss

Operating Temperature TA (Ambient)

Commercial

-0.5 to 7.0

Standby

Output Deselect

Read

0 to +70

-40 to +85

-55 to +125

-65 to +150

°C

Icc1

Industrial

Icc1

Military

Write

Icc1

Storage Temperature, Plastic

Power Dissipation

RECOMMENDED OPERATING CONDITIONS

Output Current

°C

Junction Temperature, TJ

175

Parameter

Symbol

VCC

Min

4.5

Typ

5.0

Max

5.5

Unit

NOTE:

Supply Voltage

Input High Voltage

Input Low Voltage

Stress greater than those listed under "Absolute Maximum Ratings" may cause

permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions greater than those indi-

cated in the operational sections of this specification is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect reliability.

VSS

VIH

2.2

-0.3

—

Vcc +0.5

+0.8

V^IL

CAPACITANCE

(TA = +25°C)

Parameter

Symbol

Condition

IN = Vcc or Vss, f = 1.0MHz

VOUT = Vcc or Vss, f = 1.0MHz

Max Unit

Address Lines

Input/Output Lines

C^O

These parameters are sampled, not 100% tested.

DC CHARACTERISTICS

(VCC = 5V, TA = +25°C)

Parameter

Symbol

Conditions

Units

Min

Typ

—

Max

Input Leakage Current

Output Leakage Current

ILI

VIN = 0V to VCC

-5

-10

—

2.4

µA

ILO

VI/O = 0V to VCC, CS1 ≥ VIH and/or CS2 ≤ VIL

—

+10

120

110

(70-85ns)

(100ns)

WE, CS1 = VIL, II/O = 0mA, Min Cycle

CS2 = VIH

Operating Power Supply Current

ICC1

Standby (TTL) Power Supply Current

Full Standby Power Supply Current

ICC2

ICC3

CS1 ≥ VIH and/or CS2 ≤ VIL, VIN ≥ VIH or ≤ VIL

CS1 ≥ VCC -0.2V and/or CS2 ≤ Vcc +0.2V

VIN ≥ Vcc -0.2V or VIN ≤ 0.2V

—

Output Low Voltage

Output High Voltage

VOL

V^OH

IOL = 2.1mA

IOH = -1.0mA

0.4

—

NOTE: DC test conditions: V^IL= 0.3V, VIH = Vcc -0.3V

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

EDI88128C

AC CHARACTERISTICS – READ CYCLE

(VCC = 5.0V, VSS = 0V, TA = 0°C to +70°C)

Symbol

JEDEC

70ns

85ns

100ns

Parameter

Alt.

tRC

tAA

Min

Max

Min

Max

Min

Max

Units

Read Cycle Time

tAVAV

tAVQV

100

Address Access Time

Chip Select Access Time

100

tELQV

tSHQV

tACS

100

Chip Select to Output in Low Z (1)

Chip Disable to Output in High Z (1)

tELQX

tSHQX

tCLZ

tEHQZ

tSLQZ

tCHZ

Output Hold from Address Change

Output Enable to Output Valid

tAVQX

tGLQV

tGLQX

tGHQZ

tOH

tOE

Output Enable to Output in Low Z (1)

Output Disable to Output in High Z (1)

tOLZ

tOHZ

1. This parameter is guaranteed by design but not tested.

AC TEST CONDITIONS

Figure 1

Figure 2

Input Pulse Levels

VSS to 3.0V

Vcc

Input Rise and Fall Times

Input and Output Timing Levels

Output Load

5ns

1.5V

480Ω

Figure 1

NOTE: For t^EHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2)

30pF

5pF

255Ω

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

EDI88128C

AC CHARACTERISTICS – WRITE CYCLE

(VCC = 5.0V, VSS = 0V, TA = 0°C to +70°C)

Symbol

JEDEC

70ns

85ns

100ns

Parameter

Alt.

Min

Max

Min

Max

Min

Max

Units

Write Cycle Time

Chip Select to End of Write

tAVAV

tWC

100

tELWH

tELEH

tSHWH

tSHSL

tCW

Address Setup Time

tAVWL

tAVEL

tAVSH

tAS

Address Valid to End of Write

Write Pulse Width

tAVWH

tAW

tWLWH

tWLEH

tWLSL

tWP

Write Recovery Time

Data Hold Time

tWHAX

tEHAX

tSLAX

tWR

tWHDX

tEHDX

tSLDX

tDH

Write to Output in High Z (1)

Data to Write Time

tWLQZ

tWHZ

tDVWH

tDVEH

tDVSL

tDW

Output Active from End of Write (1)

tWHQX

tWLZ

1. This parameter is guaranteed by design but not tested.

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

EDI88128C

t_AVAV

FIG. 2

ADDRESS

TIMING WAVEFORM - READ CYCLE

t_AVQV

t_ELQV

t_ELQX

t_EHQZ

t_SLQZ

t_GHQZ

t_AVAV

ADDRESS

DATA I/O

ADDRESS 1

ADDRESS 2

t_SHQV

t_SHQX

t_AVQV

t_AVQX

t_GLQV

t_GLQX

DATA 1

DATA 2

DATA I/O

READ CYCLE 1 (WE HIGH; OE, CS LOW)

READ CYCLE 2 (WE HIGH)

t_AVAV

FIG. 3

WRITE CYCLE 1

ADDRESS

t_AVWH

t_WLWH

t_WHAX

t_AVWL

t_ELWH

t_WHQX

t_WHDX

t_SHWH

t_DVWH

DATA IN

DATA VALID

t_WLQZ

HIGH Z

DATA OUT

WRITE CYCLE 1 - LATE WRITE, WE CONTROLLED

FIG. 4

WRITE CYCLE 3

WRITE CYCLE2

t_AVAV

WS32K32-XHX

ADDRESS

t_SLAX

t_EHAX

t_AVSH

t_AVEL

t_WLSL

t_WLEH

t_SHSL

t_ELEH

CS1

CS2

t_DVSL

t_SLDX

t_DVEH

t_EHDX

DATA IN

DATA VALID

WRITE CYCLE 2 - EARLY WRITE, CS

CONTROLLED

WRITE CYCLE 3 - EARLY WRITE, CS2 CONTROLLED

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

EDI88128C

DATA RETENTION CHARACTERISTICS (EDI88128LP & EDI88130LP ONLY)

(TA = -55°C to +125°C)

Characteristic

Sym

Conditions

Min

Typ

Max

Units

Low Power Version only

Data Retention Voltage

V^DD

ICCDR

T^CDR

T^R

VDD = 2.0V

–

400

–

µA

Data Retention Quiescent Current

Chip Disable to Data Retention Time (1)

Operation Recovery Time (1)

CS1 ≥ VDD -0.2V

VIN ≥ VDD -0.2V

or VIN ≤ 0.2V

–

TAVAV*

–

NOTE:

1. Parameter guaranteed by design, but not tested.

* Read Cycle Time

FIG. 5

DATA RETENTION - CS1 CONTROLLED

Data Retention Mode

WS32K32-XHX

4.5V

Vcc

VDD

t_CDR

t_R

CS1

CS1 ≥ VDD -0.2V

DATA RETENTION, CS1 CONTROLLED

FIG. 6

DATA RETENTION - CS2 CONTROLLED

Data Retention Mode

WS32K32-XHX

4.5V

Vcc

VDD

t_CDR

t_R

CS2

CS2 ≤ 0.2V

DATA RETENTION, CS2 CONTROLLED

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

EDI88128C

PACKAGE 9: 32 PIN SIDEBRAZED CERAMIC DIP (600mils wide)

1.616

1.584

0.620

0.600

0.060

0.040

Pin 1 Indicator

0.175

0.125

0.155

0.115

0.600

NOM

0.020

0.016

0.100

TYP

0.061

0.017

15 x 0.100 = 1.500

ALL DIMENSIONS ARE IN INCHES

PACKAGE 100: 32 LEAD CERAMIC ZIP

1.65 MAX

0.125

MAX

0.500

MAX

0.040

0.020

0.155

0.125

0.100

NOM

0.050

0.040

MIN

31 x 0.050 = 1.550

ALL DIMENSIONS ARE IN INCHES

PACKAGE 140: 32 LEAD CERAMIC SOJ

0.108

0.088

0.840

0.820

0.040

0.030

0.050

TYP

0.440

0.430

0.379

REF

0.155

0.120

ALL DIMENSIONS ARE IN INCHES

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

EDI88128C

ORDERING INFORMATION

EDI 8 8 128 C X X X

WHITE ELECTRONIC DESIGNS

SRAM

ORGANIZATION, 128Kx8

8 130 = Dual Chip Select

TECHNOLOGY:

C = CMOS Standard Power

LP = Low Power

ACCESS TIME (ns)

PACKAGE TYPE:

C = 32 lead Sidebrazed DIP, 600 mil (Package 9)

N = 32 lead Ceramic SOJ (Package 140)

Z = 32 lead Ceramic ZIP (Package 100)

DEVICE GRADE:

B = MIL-STD-883 Compliant

M= Military Screened

I = Industrial

C = Commercial

-55°C to +125°C

-40°C to +85°C

0°C to +70°C

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

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