EDI8F81027C-B6 [ETC]
SRAM Modules ; SRAM模块\n
| 型号： | EDI8F81027C-B6 |
| 厂家： | 
ETC |
| 描述： | SRAM Modules
|
| 文件： | 总6页 (文件大小：444K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EDI8F81027C
1Mx8 CMOS SRAM MONOLITHIC
DESCRIPTION
FEATURES
The EDI8F81027C is an 8Mb CMOS Static RAM based on two
512Kx8 Static RAMs mounted on a multi-layered epoxy laminate
(FR4) substrate.
n 1 Mx8 bit CMOS Static RAM
Access Times 55 through 100ns
Data Retention Function (EDI8F81027LP )
TTL Compatible Inputs and Outputs
Fully Static, No Clocks
A low power version with data retention (EDI8F81027LP) is also
available.
All inputs and outputs are TTL compatible and operate from a
single 5V supply.
n High Density Packaging
Fully asynchronous, the EDI8F81027C requires no clocks or
refreshing for operation.
32 Pin DIP, No. 352
n Single +5V (±10%) Supply Operation
PIN CONFIGURATIONS AND BLOCK DIAGRAM
PIN NAMES
AØ-A19
E
Address Inputs
Chip Enable
W
Write Enable
DQØ-DQ7
VCC
VSS
NC
Common Data Input/Output
Power (+5V±10%)
Ground
No Connection
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
July 2002 Rev. 3A
ECO #15405
1
EDI8F81027C
ABSOLUTE MAXIMUM RATINGS*
RECOMMENDED DC OPERATING CONDITIONS
Voltage on any pin relative to VSS
Operating Temperature TA (Ambient)
Commercial
-0.5V to 7.0V
Parameter
Sym
VCC
VSS
VIH
Min
4.5
0
2.2
-0.3
Typ
5.0
0
--
--
Max
5.5
0
6.0
0.8
Units
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
V
V
V
V
0°C to +70°C
-40°C to +85°C
-55°C to +125°C
1 Watt
Industrial
Storage Temperature
Power Dissipation
Output Current
VIL
20 mA
*Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions greater than those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
VSS to 3.0V
5ns
1.5V
1TTL, CL =100pF
(note: For TEHQZ,TGHQZ and TWLQZ, CL = 5pF)
DC ELECTRICAL CHARACTERISTICS
Parameter
Operating Power Supply Current
Symbol
ICC1
Conditions
W, E = VIL, II/O = 0mA,
Min Cycle
Min
--
Typ*
85
Max
140
Units
mA
Standby (TTL) Power Supply Current
ICC2
ICC3
E ³ VIH, VIN £ VIL
VIN ³ VIH
E ³ VCC-0.2V
--
--
25
55
2
mA
mA
Full Standby Power Supply Current (CMOS)
C
1.5
VIN ³ VCC-0.2V or VIN £
VIN = 0V to VCC
V I/O = 0V to VCC
IOH = -1.0mA
0.2V
LP--
190
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
ILI
ILO
VOH
VOL
-10
-10
2.4
--
--
--
--
--
10
10
--
µA
µA
V
IOL = 2.1mA
0.4
V
*Typical: TA = 25°C, VCC = 5.0V
CAPACITANCE
TRUTH TABLE
(f=1.0MHz, VIN=VCC or VSS)
G
X
H
L
E
H
L
L
L
W
X
H
H
L
Mode
Standby
Output Deselect
Read
Output
High Z
High Z
DOUT
DIN
Power
ICC2, ICC3
ICC1
ICC1
ICC1
Parameter
Address Lines
Data Lines
Chip Enable Line
Write and Output Enable Lines
Sym
CI
CD/Q
CC
Max
Unit
30
43
10
32
pF
pF
pF
pF
X
Write
CW
These parameters are sampled, not 100% tested.
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
July 2002 Rev. 3A
ECO #15405
2
EDI8F81027C
AC CHARACTERISTICS READ CYCLE
Symbol
55ns
70ns
85ns
100ns
Parameter
JEDEC Alt.
Min Max Min Max Min
Max Min Max Units
Read Cycle Time
TAVAV TRC
TAVQV TAA
TELQV TACS
TELQX TCLZ
TEHQZ TCHZ
TAVQX TOH
55
70
85
100
ns
ns
ns
ns
ns
ns
Address Access Time
55
55
70
70
85
85
100
100
Chip Enable Access Time
Chip Enable to Output in Low Z (1)
Chip Disable to Output in High Z (1)
Output Hold from Address Change
5
5
5
5
5
5
5
5
25
30
35
40
Note 1: Parameter guaranteed, but not tested.
READ CYCLE 1 - W HIGH, E LOW
TAVAV
A
ADDRESS 1
ADDRESS 2
TAVQX
TAVQV
Q
DATA 2
DATA 1
READ CYCLE 2 - W HIGH
TAVAV
A
TAVQV
E
TELQV
TELQX
TEHQZ
TGHQZ
G
Q
TGLQV
TGLQX
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
July 2002 Rev. 3A
ECO #15405
3
EDI8F81027C
AC CHARACTERISTICS WRITE CYCLE
Write Cycle
Parameter
Symbol
JEDEC Alt.
55ns
70ns
85ns
100ns
Min Max Min Max Min
Max Min Max Units
Write Cycle Time
TAVAV TWC
55
70
85
100
ns
Chip Enable to End of Write
TELWH TCW
TELEH TCW
50
50
65
65
70
70
80
80
ns
ns
Address Setup Time
Address Valid to End of Write
Write Pulse Width
TAVWL TAS
TAVEL TAS
0
0
0
0
0
0
0
0
ns
ns
TAVWH TAW
TAVEH TAW
50
50
65
65
70
70
80
80
ns
ns
TWLWH TWP
45
65
70
80
ns
TWLEH TWP45
65
70
80
ns
Write Recovery Time
Data Hold Time
TWHAX TWR
TEHAX TWR
5
5
5
5
5
5
5
5
ns
ns
TWHDX TDH
TEHDX TDH
0
0
0
0
0
0
0
0
ns
ns
Write to Output in High Z (1)
Data to Write Time
TWLQZ TWHZ
25
0
30
0
35
0
40
ns
TDVWH TDW
TDVEH TDW
25
25
30
30
35
35
40
40
ns
ns
Output Active from End of Write (1)
TWHQX TWLZ
5
5
5
5
ns
Note 1: Parameter guaranteed, but not tested.
WRITE CYCLE 1 - W CONTROLLED
TAVAV
TELWH
A
E
TWHAX
TAVWH
TWLWH
W
TAVWL
TDVWH
TWHDX
DATA VALID
D
Q
TWHQX
TWLQZ
HIGH Z
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
July 2002 Rev. 3A
ECO #15405
4
EDI8F81027C
WRITE CYCLE 2 E CONTROLLED
TAVAV
A
TAVEL
TELEH
E
TAVEH
TEHAX
TEHDX
TWLEH
W
TDVEH
D
Q
DATA VALID
HIGH Z
DATA RETENTION CHARACTERISTICS (LP VERSION ONLY)
Characteristic
Sym
Test Conditions
VDD
Min
Typ
Max
Unit
70°C
--
85°C
--
Data Retention Voltage
VDD
2
--
V
Data Retention Quiescent Current
ICCDR
E ³ VDD -0.2V
VIN ³ VDD -0.2V
or VIN £ 0.2V
2V
3V
--
100
160
--
130
210
--
µA
µA
ns
--
0
Chip Disable to Data Retention Time TCDR(1)
--
--
Operation Recovery Time
TR (1)
TAVAV*
--
--
ns
Note: Parameter guaranteed, but not tested
* Read Cycle Time
DATA RETENTION - E CONTROLLED
4.5V
4.5V
CC
VDD
TCDR
TR
E=VDD-0.2V
E
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
July 2002 Rev. 3A
ECO #15405
5
EDI8F81027C
ORDERING INFORMATION
Standard Power
Low Power
Speed
(ns)
55
70
85
Package
No.
352
352
352
with Data Retention
EDI8F81027LP55B6C
EDI8F81027LP70B6C
EDI8F81027LP85B6C
EDI8F81027LP100B6C
EDI8F81027C55B6C
EDI8F81027C70B6C
EDI8F81027C85B6C
EDI8F81027C100B6C
100
352
Note: To order an Industrial grade product substitute the letter C in the Suffix with the letter I,
eg. EDI8F81027C70B6C becomes EDI8F81027C70B6I.
PACKAGE DESCRIPTION
PACKAGE NO. 352: 32 PIN DIP
ALL DIMENSIONS ARE IN INCHES
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
July 2002 Rev. 3A
ECO #15405
6
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