EM422M1614VTB_技术文档

16Mb SDRAM

Ordering Information

EM 48 1M 16 2 2 V T A – 6 L

EOREX

Memory

Power

EDO/FPM

: 40

: 41

: 42

: 43

: 46

: 48

Blank : Standard

L : Low power

I : Industrial

D-RAMBUS

DDRSDRAM

DDRSGRAM

SGRAM

F: PB free package

SDRAM

Density

16M : 16 Mega Bits

8M : 8 Mega Bits

4M : 4 Mega Bits

2M : 2 Mega Bits

1M : 1 Mega Bit

Min Cycle Time ( Max Freq.)

-5 : 5ns ( 200MHz )

-6 : 6ns ( 167MHz )

-7 : 7ns ( 143MHz )

-75 : 7.5ns ( 133MHz )

-8 : 8ns ( 125MHz )

-10 : 10ns ( 100MHz )

Organization

8 : x8

9 : x9

16 : x16

18 : x18

32 : x32

Refresh

1 : 1K, 8 : 8K

2 : 2K, 6 :16K

4 : 4K

Bank

Revision

A : 1st B : 2nd

C : 3rd D :4th

2 : 2Bank 6 : 16Bank

4 : 4Bank 3 : 32Bank

8 : 8Bank

Package

Interface

V: 3.3V

R: 2.5V

C: CSP B: uBGA

T: TSOP Q: TQFP

P: PQFP ( QFP )

1/18

Rev.01

16Mb SDRAM

16Mb ( 2Banks ) Synchronous DRAM

EM481M1622VTA (1Mx16)

Description

The EM481M1622VTA is Synchronous Dynamic Random Access Memory (SDRAM) organized as

512K x 2 banks x 16 bits. All inputs and outputs are synchronized with the positive edge of the clock.

The 16Mb SDRAM uses synchronized pipelined architecture to achieve high speed data transfer rates

and is designed to operate at 3.3V low power memory system. It also provides auto refresh with power

saving / down mode. All inputs and outputs voltage levels are compatible with LVTTL .

Feature

• Fully synchronous to positive clock edge

• Single 3.3V +/- 0.3V power supply

• LVTTL compatible with multiplexed address

• Programmable Burst Length (B/ L) - 1,2,4,8 or full page

• Programmable CAS Latency (C/ L) - 2 or 3

• Data Mask (DQM) for Read / Write masking

• Programmable wrap sequence - Sequential ( B/ L = 1/2/4/8/full page )

- Interleave ( B/ L = 1/2/4/8 )

• Burst read with single-bit write operation

• All inputs are sampled at the rising edge of the system clock.

• Auto refresh and self refresh

• 2,048 refresh cycles / 32ms

* EOREX reserves the right to change products or specification without notice.

2/18

Rev.01

16Mb SDRAM

Pin Assignment ( Top View )

1

2

3

4

5

6

7

8

VDD

DQ0

DQ1

V^SSQ

DQ2

DQ3

V^DDQ

DQ4

DQ5

V^SSQ

DQ6

DQ7

V^DDQ

LDQM

/WE

/CAS

/RAS

/CS

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

VSS

DQ15

DQ14

V^SSQ

DQ13

DQ12

V^DDQ

DQ11

DQ10

V^SSQ

DQ9

DQ8

V^DDQ

NC

UDQM

CLK

CKE

NC

A9

A8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

BA

A10

A0

A1

A2

A3

V^DD

A7

A6

A5

A4

V^SS

50pin TSOP-II

3/18

Rev.01

16Mb SDRAM

Pin Descriptions ( Simplified )

CLK

/CS

Name

Pin Function

System Clock

Chip select

Master Clock Input(Active on the Positive rising edge)

Selects chip when active

Activates the CLK when “H” and deactivates when “L”.

CKE should be enabled at least one cycle prior to new

CKE

Clock Enable

command. Disable input buffers for power down in standby.

Row address (A0 to A10) is determined by A0 to A10 level

at the bank active command cycle CLK rising edge.

CA(CA0 to CA7) is determined by A0 to A7 level at the

read or write command cycle CLK rising edge.

And this column address becomes burst access start

address. A10 defines the pre-charge mode. When A10 = High

at the pre-charge command cycle, all banks are pre-charged.

But when A10 = Low at the pre-charge command cycle,

onlythe bank that is selected by BA is pre-charged.

A0 ~ A10

Address

BA

Bank Address

Row address strobe

Column address strobe

Write Enable

Selects which bank is to be active.

Latches Row Addresses on the positive rising edge of the

CLK with /RAS “L”. Enables row access & pre-charge.

/RAS

/CAS

/WE

Latches Column Addresses on the positive rising edge of the

CLK with /CAS low. Enables column access.

Latches Column Addresses on the positive rising edge of the

CLK with /CAS low. Enables column access.

UDQM /LDQM

DQ0 ~ 15

Data input/output Mask

Data input/output

DQM controls I/O buffers.

DQ pins have the same function as I/O pins on a conventional

DRAM.

VDD/VSS

Power supply/Ground

VDD and VSS are power supply pins for internal circuits.

VDDQ and VSSQ are power supply pins for the output buffers.

VDDQ/VSSQ

This pin is recommended to be left No Connection on the

device.

NC

No connection

4/18

Rev.01

16Mb SDRAM

Block Diagram

Auto/Self

Refresh Counter

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

BA

DQM

Memory

Write DQM

Control

Array

Data In

S/A & I/O gating

Col. Decoder

DQi

Data Out

Col. Add. Buffer

Read DQM

Control

Col. Add. Counter

Burst Counter

Mode Register Set

Timing Register

/CS /RAS

CLK

CKE

/CAS

/WE

DQM

5/18

Rev.01

16Mb SDRAM

Simplified State Diagram

Self

Refresh

Mode

CBR

Refresh

MRS

REF

Register

IDLE

Set

Power

Down

↓

CKE

Active

Row

Active

Power

CKE

R

ead Down

te

Wri

E↓

CK

d

Rea

↓

WRITE

Suspend

CKE

READ

Suspend

WRITE

READ

te

Wri

E

CK

CKE

↓

CKE

↓

CKE

WRITEA

Suspend

READA

Suspend

WRITEA

READA

CKE

POWER

ON

rge

cha

Pre

Precharge

ut

al Inp

Manu

nce

Seque

atic

Autom

6/18

Rev.01

16Mb SDRAM

Address Input for Mode Register Set

BA A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Operation Mode CAS Latency BT Burst Length

Burst Length

Sequential Interleave A2

A1

0

A0

0

1

2

4

8

1

2

4

8

0

1

0

1

0

1

Reserved Reserved

Full Page Reserved

0

1

0

1

Burst Type

A3

0

Interleave

Sequential

1

CAS Latency

A6

0

A5

A4

0

Reserved

2

0

1

0

1

0

1

3

0

Reserved

0

1

0

1

0

1

BA

0

A10

0

A9

0

A8

0

A7

0

Operation Mode

Normal

0

1

0

Burst read with Single-bit Write

7/18

Rev.01

16Mb SDRAM

Burst Type ( A3 )

Burst Length

2

A2 A1 A0

Sequential Addressing

0 1

Interleave Addressing

0 1

X X 0

X X 1

X 0 0

X 0 1

X 1 0

X 1 1

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

n n n

1 0

0 1 2 3

1 2 3 0

1 0 3 2

4

2 3 0 1

3 0 1 2

3 2 1 0

0 1 2 3 4 5 6 7

1 2 3 4 5 6 7 0

2 3 4 5 6 7 0 1

3 4 5 6 7 0 1 2

4 5 6 7 0 1 2 3

5 6 7 0 1 2 3 4

6 7 0 1 2 3 4 5

7 0 1 2 3 4 5 6

Cn Cn+1 Cn+2 …...

0 1 2 3 4 5 6 7

1 0 3 2 5 4 7 6

2 3 0 1 6 7 4 5

3 2 1 0 7 6 5 4

4 5 6 7 0 1 2 3

5 4 7 6 1 0 3 2

6 7 4 5 2 3 0 1

7 6 5 4 3 2 1 0

-

8

Full Page *

* Page length is a function of I/O organization and column addressing

x16 (CA0 ~ CA7) : Full page = 256 bits

8/18

Rev.01

16Mb SDRAM

Truth Table

1. Command Truth Table

CKE

Command

Symbol

/CS /RAS /CAS /WE BA A10 A9~A0

n-1

H

n

X

DESL

NOP

H

L

X

H

L

X

H

L

H

L

X

H

L

H

L

H

L

X

V

X

L

X

L

H

L

H

V

L

X

V

X

V

Ignore Command

No operation

BSTH

READ

READA

WRIT

WRITA

ACT

PRE

PA LL

MRS

Burst stop

Read

Read with auto pre-charge

Write

Write with auto pre-charge

Bank activate

H

Pre-charge select bank

Pre-charge all banks

Mode register set

L

H

L

Note : H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input

2. DQM Truth Table

CKE

Command

Symbol

/CS

n-1

n

( EM481M1622VT )

Data w rite / output enable

Data mask / output disable

ENB

MASK

H

X

H

L

( EM481M1622VT )

Upper byte w rite enable / output enable

Read

Read w ith auto pre-charge

Write

Write w ith auto pre-charge

Bank activate

Pre-charge select bank

Pre-charge all banks

Mode register set

BSTH

READ

READA

WRIT

WRITA

ACT

PRE

PA LL

MRS

H

X

L

Note : H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input

3. CKE Truth Table

Command

CKE

Command

Symbol

/CS /RAS /CAS /WE Addr.

n-1

H

L

n

L

H

L

H

L

Clock suspend mode entry

Clock suspend mode

Clock suspend mode exit

CBR refresh command

Self refresh entry

X

L

X

L

X

L

X

H

X

Activating

Any

L

Clock suspend

Idle

REF

SELF

H

L

H

X

H

X

Self refresh exit

Self refresh

L

H

X

Pow er dow n entry

Pow er dow n exit

H

L

Idle

Power down

H

Re m ark H = High level, L = Low level, X = High or Low level (Don't care)

9/18

Rev.01

16Mb SDRAM

4. Operative Command Table

Current

/CS /R /C /W

Addr.

Command

Action

Notes

state

H

L

H

L

H

L

H

L

X

H

L

X

H

L

X

H

L

X

H

L

H

L

H

L

X

H

L

X

DESL

NOP or BST

READ/READA

WRIT/WRITA

ACT

PRE/PA LL

REF/SELF

MRS

Nop or pow er dow n

2

3

X

BA/CA/A10

BA/RA

BA, A10

X

ILLEGAL

Row activating

Nop

L

Idle

H

L

Refresh or self refresh

Mode register accessing

Nop

4

L

Op-Code

X

H

L

DESL

X

NOP or BST

READ/READA

WRIT/WRITA

ACT

PRE/PA LL

REF/SELF

MRS

Nop

BA/CA/A10

BA/RA

BA, A10

X

Begin read : Determine AP

Begin w rite : Determine AP

ILLEGAL

5

3

6

4

L

Row active

H

L

H

L

Precharge

ILLEGAL

H

L

X

H

L

H

L

H

L

H

L

X

H

L

H

L

H

L

H

L

Op-Code

X

H

L

X

H

L

X

H

L

X

DESL

NOP

BST

Continue burst to end → Row active

Burst stop → Row active

Terminate burst, new read : Determine AP

Terminate burst, start w rite : Determine AP

ILLEGAL

BA/CA/A10

BA/RA

BA/A10

X

READ/READA

WRIT/WRITA

ACT

PRE/PA LL

REF/SELF

MRS

7

7, 8

3

Re ad

L

H

L

Terminate burst, pre-charging

ILLEGAL

4

L

Op-Code

ILLEGAL

X

H

L

X

DESL

NOP

BST

Continue burst to end → Write recovering

Burst stop → Row active

Terminate burst, start read : Determine AP 7, 8

Terminate burst, new w rite : Determine AP 7

ILLEGAL

BA/CA/A10

BA/RA

BA/A10

X

READ/READA

WRIT/WRITA

ACT

PRE/PA LL

REF/SELF

MRS

7,8

7

3

Write

L

H

L

Terminate burst, pre-charging

9

L

ILLEGAL

L

Op-Code

Re m ark H = High level, L = Low level, X = High or Low level (Don't care)

10/18

Rev.01

16Mb SDRAM

Current

state

/CS /R /C /W

Addr.

Command

Action

Notes

H

L

X

H

L

X

H

L

X

H

L

H

L

H

L

H

L

X

DESL

NOP

BST

Continue burst to end → Precharging

ILLEGAL

BA/CA/A10

BA/RA

BA, A10

X

READ/READA

WRIT/WRITA

ACT

PRE/PA LL

REF/SELF

MRS

ILLEGAL

3

Re ad w ith AP

L

H

L

Op-Code

burst to end → Write

recovering w ith auto precharge

Continue burst to end → Write

recovering w ith auto precharge

ILLEGAL

Nop → Enter idle after tRP

ILLEGAL

Nop → Enter idle after tRP

ILLEGAL

H

X

DESL

L

H

X

NOP

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

X

BA/CA/A10

BA/RA

BA, A10

X

BST

READ/READA

WRIT/WRITA

ACT

PRE/PA LL

REF/SELF

MRS

Write with AP

3

H

L

Op-Code

X

H

L

X

H

L

X

H

L

X

H

L

H

L

DESL

NOP

BST

X

BA/CA/A10

BA/RA

BA, A10

X

READ/READA

WRIT/WRITA

ACT

PRE/PA LL

REF/SELF

MRS

3

Precharging

L

H

L

H

L

H

L

X

H

L

H

L

H

L

Op-Code

ILLEGAL

X

H

L

X

DESL

NOP

BST

Nop → Enter idle after tRCD

ILLEGAL

BA/CA/A10

BA/RA

BA, A10

X

READ/READA

WRIT/WRITA

ACT

PRE/PA LL

REF/SELF

MRS

3

3,10

Row activating

L

H

L

H

L

3

L

Op-Code

Re m ark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Precharge

11/18

Rev.01

16Mb SDRAM

Current

state

/CS /R /C /W

Addr.

Command

Action

Notes

H

L

H

L

H

L

H

L

X

H

L

X

H

L

X

H

L

X

H

L

H

L

H

L

H

L

X

H

L

H

L

H

L

H

L

X

H

L

X

DESL

NOP

BST

Nop → Enter row active after tDPL

Start read, Determine AP

BA/CA/A10

BA/RA

BA, A10

READ/READA

WRIT/WRITA

ACT

PRE/PA LL

REF/SELF

MRS

Write recovering

L

New w rite, Determine AP

8

3

H

L

ILLEGAL

X

L

Op-Code

X

H

L

X

DESL

NOP

BST

Nop → Enter precharge after tDPL

BA/CA/A10

BA/RA

BA, A10

READ/READA

WRIT/WRITA

ACT

PRE/PA LL

REF/SELF

MRS

ILLEGAL

3,8

3

Write recovering

with AP

L

H

L

X

L

Op-Code

X

H

L

X

H

L

H

L

X

H

L

X

DESL

Nop → Enter idle after tRC

ILLEGAL

NOP/ BST

READ/WRIT

A CT/PRE/PA LL

REF/SELF/MRS

DESL

NOP

BST

READ/WRIT

A CT/PRE/PA LL/

REF/SELF/MRS

Refreshing

ILLEGAL

Nop

ILLEGAL

L

X

H

Mode Register

Accessing

X

L

X

ILLEGAL

Re m ark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Precharge

Notes 1. All entries assume that CKE w as active (High level) during the preceding clock cycle.

2. If all banks are idle, and CKE is inactive (Low level), SDRAM w ill enter Pow er dow n mode.

All input buffers except CKE w ill be disabled.

3. Illegal to bank in specified states;

→ Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank.

4. If all banks are idle, and CKE is inactive (Low level), SDRAM w ill enter Self refresh mode.

All input buffers except CKE w ill be disabled.

5. Illegal if tRCD is not satisfied.

6. Illegal if tRAS is not satisfied.

7. Must satisfy burst interrupt condition.

8. Must satisfy bus contention, bus turn around, and/or w rite recovery requirements.

9. Must mask preceding data w hich don't satisfy tDPL.

10. Illegal if tRRD is not satisfied.

12/18

Rev.01

16Mb SDRAM

5. Command Truth Table for CKE

Current

state

CKE

/CS /R /C /W

Addr.

Action

Notes

n-1

n

X

H

L

H

L

X

H

L

X

H

L

X

H

L

X

H

L

X

H

L

X

H

L

X

H

L

X

H

L

X

H

L

X

H

L

X

H

L

X

INVALID, CLK (n – 1) w ould exit self refresh

Self refresh recovery

ILLEGAL

Maintain self refresh

Idle after tRC

ILLEGAL

Self refresh

L

H

L

Self refresh

recovery

H

L

X

H

L

X

H

L

INVALID, CLK(n-1) w ould exit pow er dow n

Exit pow er dow n → Idle

Maintain pow er dow n mode

Refer to operations in Operative Command Table

Refresh

Refer to operations in Operative Command Table

Self refresh

Refer t o operations in Operative Command Table

Pow er dow n

Power down L

L

H

L

X

L

Op-Code

Both banks

idle

H

L

X

H

L

X

H

L

X

H

L

H

L

X

H

L

H

L

H

L

X

1

2

L

Op-Code

X

Refer to operations in Operative Command Table

Row active

Pow er dow n

H

Refer to operations in Operative Command Table

Begin clock suspend next cycle

Exit clock suspend next cycle

Maintain clock suspend

Any state

X

other than

L

listed above

L

H

L

Re m ark : H = High level, L = Low level, X = High or Low level (Don't care)

Notes 1. Self refresh can be entered only from the both banks idle state.

Pow er dow n can be entered only from both banks idle or row active state.

2. Must be legal command as defined in Operative Command Table.

13/18

Rev.01

16Mb SDRAM

Absolute Maximum Ratings

Symbol

VIN, VOUT

VDD, VDDQ

TOP

Item

Rating

-0.3 ~ 4.6

0 ~ 70

-55 ~ 150

1

Units

V

Input, Output Voltage

Power Supply Voltage

Operating Temperature

Storage Temperature

Power Dissipation

Short Circuit Current

V

°C

TSTG

°C

PD

W

IOS

50

mA

Note : Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause

permanent damage. The device is not meant to be operated under conditions outside the limits

described in the operational section of this specification. Exposure to Absolute Maximum

Rating conditions for extended periods may affect device reliability.

Recommended DC Operation Conditions ( Ta = 0 ~ 70°C )

Symbol

Parameter

Min.

Typical

Max.

Units

VDD

Power Supply Voltage

3.0

3.3

3.6

V

VDDQ

VIH

Power Supply Voltage (for I/O Buffer)

Input logic high voltage

3.0

3.3

3.6

2.0

VDD+0.3

0.8

VIL

Input logic low voltage

-0.3

Note : 1. All voltage referred to VSS.

2. VIH (max) = 5.6V for pulse w idth ≤ 3ns

3. VIL (min) = -2.0V for pulse w idth ≤ 3ns

Capacitance ( Vcc =3.3V, f = 1MHz, Ta = 25°C )

Symbol

Parameter

Min.

Max.

Units

CCLK

Clock capacitance

2.5

4.0

pF

Input capacitance for CLK, CKE, Address, /CS,

/RAS, /CAS, /WE, DQML,DQMU

CI

2.5

4.0

5.0

6.5

pF

CO

Input/Output capacitance

14/18

Rev.01

16Mb SDRAM

Recommended DC Operating Conditions

( VDD = 3.3V +/- 0.3 V, Ta = 0 ~ 70 °C , Ta = -40 to 85°C for 6I)

MAX

Parameter

Symbol

Test condition

Units Notes

6/6I/6L 7/7L

5

Burst length = 1,

tRC ≥ tRC (min), IOL = 0 mA,

One bank active

Operating current

ICC1

100

90

80

mA

1

Precharge standby

current in power down

mode

CKE ≤ VIL (max.), tCk = 15 ns

CKE ≤ VIL (max.), tCk = ∞

ICC2P

2 / 0.7*

mA

5

ICC2PS

CKE ≥ VIL (min.), tCK = 15 ns, /CS ≥ VIH (min.)

Input signals are changed one time during 30ns

ICC2N

20

8

mA

Precharge standby

current in non-power

down mode

CKE ≥ VIL (min.), tCK = ∞

Input signals are stable

ICC2NS

ICC3P

CKE ≤ VIL(max), tCK = 15ns

CKE ≤ VIL(max), tCK = ∞

5

mA

Active standby current

in power down mode

ICC3PS

CKE ≥ VIL(min), tCK = 15ns,/ CS ≥ VIH(min)

Input signals are changed one time during

30ns

ICC3N

30

mA

Active standby current

in non-power down

mode

CKE ≥ VIL(min), tCK = ∞

Input signals are stable

ICC3NS

20

operating current

(Burst mode)

Refresh current

180 160 140

130 120 110

CL=3

CL=2

ICC4

ICC5

ICC6

tCCD = 2CLKs , IOL = 0 mA

tRC ≥ tRC(min.)

mA

2

3

4

5

2

0.3

Self Refresh current

CKE ≤ 0.2V

Note : 1. ICC1 depends on output loading and cycle rates.

Specified values are obtained w ith the output open.

Input signals are changed only one time during tCK(min)

2. ICC4 depends on output loading and cycle rates.

Specified values are obtained w ith the output open.

Input signals are changed only one time during tCK(min)

3. Input signals are changed only one time during tCK(min)

4. Standard pow er version.

5. * Low pow er version.

15/18

Rev.01

16Mb SDRAM

Recommended DC Operating Conditions ( Continued )

Parameter

Symbol

Test condition

Min. Max. Unit

0 ≤ VI ≤ VDDQ, VDDQ=VDD

All other pins not under test=0 V

Input leakage current

IIL

-0.5 +0.5

uA

Output leakage current

High level output voltage

Low level output voltage

IOL

VOH

VOL

0 ≤ VO ≤ VDDQ, DOUT is disabled

Io = -4mA

-0.5 +0.5

uA

V

2.4

0.4

Io = +4mA

V

AC Operating Test Conditions

( VDD = 3.3V +/- 0.3 V, Ta = 0 ~ 70 °C , Ta = -40 to 85°C for 6I )

Output Reference Level

Output Load

1.4V/ 1.4V

See diagram as below

2.4V/ 0.4V

2ns

Input Signal Level

Transition Time of Input Signals

Input Reference Level

1.4V

Vtt = 1.4V

50Ω

Output

Z = 50Ω

50pF

16/18

Rev.01

16Mb SDRAM

Operating AC Characteristics

( VDD = 3.3V +/- 0.3 V, Ta = 0 ~ 70 °C , Ta = -40 to 85°C for 6I)

-5

-6/6I/6L

Min. Max. Min. Max.

-7/7L

Units Notes

Parameter

Symbol

Min. Max.

CL = 3

CL = 2

CL = 3

CL = 2

5

7

6

7.5

7

8

ns

Clock cycle time

tCK

tAC

4.5

5.5

5

5.5

5

Access time from CLK

CLK high level width

CLK low level width

tCH

tCL

1.5

2

2.725

2.75

2

CL = 3

CL = 2

CL = 3

CL = 2

2

Data-out hold time

tOH

2

1.5

5

2

6

7

tHZ

tLZ

Data-out high impedance time

Data-out low impedance time

0

1

Input hold time

Input setup time

1

tIH

tIS

1.5

54

1.5

60

1.5

65

45

18

20

14

2

tRC

ACTIVE to ACTIVE command period

tRAS

tRP

40

18

14

10

100k

42 100k

100k ns

ACTIVE to PRECHARGE command period

PRECHARGE to ACTIVE command period

18

12

ns

ACTIVE to READ/WRITE delay tim e

tRCD

tRRD

ACTIVE(one) to ACTIVE(another) command

READ/WRITE command to READ/WRITE

command

tCCD

CLK

1

Data-in to PRECHARGE command

Data-in to BURST stop command

tDPL

tBDL

2

1

3

2

1

3

2

1

3

2

CLK

ms

CL = 3

Data-out to high impedance from

PRECHA RGE c ommand

tROH

tREF

CL = 2

Refresh time(2,048 cycle)

32

＊ All voltages referenced to Vss.

Note :

1. tHZ defines the time at which the output achieve the open circuit

condition and is not referenced to output voltage levels.

2. These parameters account for the number of clock cycles and

depend on the operating frequencyof the clock, as follows :

The number of clock cycles = Specified value of timing/clock

period

(Count fractions as a whole number)

17/18

Rev.01

16Mb SDRAM

Package Dimension

18/18

Rev.01


型号：	EM422M1614VTB
厂家：	ETC
描述：	16Mb ( 2Banks ) Synchronous DRAM 16MB （ 2Banks ）同步DRAM 动态存储器
文件：	总18页 (文件大小：823K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

EM422M1614VTB [ETC]

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