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EM610FR16AS-70LL [ETC]

128K x16 bit Low Power and Low Voltage Full CMOS Static RAM; 128K X16位低功耗和低电压全CMOS静态RAM
EM610FR16AS-70LL
型号： EM610FR16AS-70LL
厂家： ETC    ETC
描述：

128K x16 bit Low Power and Low Voltage Full CMOS Static RAM
128K X16位低功耗和低电压全CMOS静态RAM
文件： 总11页 (文件大小：434K)
中文：  中文翻译
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EM620FV16B Series  
Low Power, 128Kx16 SRAM  
Document Title  
128K x16 bit Low Power and Low Voltage Full CMOS Static RAM  
Revision History  
Revision No.  
History  
Draft Date  
Remark  
0.0  
Initial Draft  
June 7, 2007  
0.1  
0.2  
0.1 Revision  
0.2 Revision  
Remove BYTE option information  
June 15, 2007  
July 2, 2007  
Revised VOH(2.2v to 2.4v),tOH(15ns to 10ns),  
tOE-55(30ns to 25ns), tWP-55(45ns to 40ns),  
tWP-70(55ns to 50ns), tWHZ-70(25ns to 20ns),  
ICC(2mA to 3mA), ICC1(2mA to 3mA)  
0.3  
0.3 Revision  
VIH level change from 2.0V to 2.2V  
Aug. 16, 2007  
Emerging Memory & Logic Solutions Inc.  
4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Zip Code : 690-719  
Tel : +82-64-740-1712 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com  
The attached data sheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your  
questions about device. If you have any questions, please contact the EMLSI office.  
1
EM620FV16B Series  
Low Power, 128Kx16 SRAM  
128K x16 Bit Low Power and Low Voltage CMOS Static RAM  
FEATURES  
- Process Technology : 0.15µm Full CMOS  
- Organization :128K x16  
29  
56  
- Power Supply Voltage  
=> EM620FV16B : 2.7~3.6V  
- Low Data Retention Voltage : 1.5V  
- Three state output and TTL Compatible  
- Packaged product designed for 45/55/70ns  
EM620FV16B (Dual C/S)  
GENERAL PHYSICAL SPECIFICATIONS  
- Backside die surface of polished bare silicon  
- Typical Die Thickness = 725um +/-15um  
- Typical top-level metallization :  
+
(0.0)  
=> Metal (Ti/AlCu/TiN/ARC SiON/SiO2) : 5.2K Angstroms  
- Topside Passivation :  
=> Passivation (HDP/pNIT/PIQ) : 5.4K Angstroms  
EMLSI LOGO  
- Wafer diameter : 8 inch  
1
28  
OPTIONS  
y
- C1/W1 : DC Probed Die/Wafer @ Hot Temp  
- C2/W2 : DC/AC Probed Die/Wafer @ Hot Temp  
x
Pre-charge Circuit  
A
A
A
A
A
A
A
A
A
A
V
0
1
2
3
4
5
6
7
8
9
CC  
V
SS  
Memory Array  
1024 x 2048  
PAD DESCRIPTIONS  
Name  
CS1,CS2  
OE  
Function  
Name Function  
Chip select inputs  
Output Enable input  
Write Enable input  
Vcc  
Vss  
UB  
Power Supply  
Data  
Cont  
I/O0 ~ I/O7  
I/O Circuit  
Ground  
Data  
Cont  
I/O8 ~ I/O15  
Column Select  
Upper Byte (I/O8~15  
)
WE  
Lower Byte (I/O0~7  
No Connection  
)
A0~A16  
Address Inputs  
LB  
NC  
A
A
A
A
A
A
A
13 14 15  
16  
11  
10  
12  
I/O0~I/O15 Data Inputs/Outputs  
WE  
OE  
UB  
LB  
Control Logic  
CS1  
CS2  
BONDING INSTRUCTIONS  
The 2M full CMOS SRAM die has total 56pads. Refer to the bond pad location and identification table for X, Y coordinates.  
EMLSI recommends using a bond wire on back side of die onto Vss bond pad for improved noise immunity.  
2
EM620FV16B Series  
Low Power, 128Kx16 SRAM  
FUNCTIONAL SPECIFICATIONS  
There are 3 classifications for EMLSI die and wafers products, which are C1 and C2 for die and W1 and W2 for wafer, respectively.  
Each die and wafer support dedicated characteristics and probe the electrical parameters within their specifications. Followings are  
brief information for die and wafer classifications. Please refer to packaged specifications for more information but these parameters  
are not guaranteed at bare die and wafer.  
− C1 LEVEL DIE OR W1 LEVEL WAFER  
The DC parameters are measured by specification for C1 level die or W1 level wafer. The DC parameters measured at 70°C tem-  
perature, which called ‘Hot DC Sorting’ Other parameters are not guaranteed and warranted including device reliability. Please refer  
to qualification report for device reliability and package level datasheets for electrical parameters.  
− C2 LEVEL DIE OR W2 LEVEL WAFER  
The DC parameters and selected AC parameters are measured with for C2 level die or W2 level wafer. The DC characteristics of C2  
die and W2 wafer is tested based on DC specifications of C1 level die and W1 level wafer. The DC and specified AC parameters are  
tested at 70°C temperature, which called ‘Hot DC & Selective AC Sorting’. Other parameters are not guaranteed and warranted  
including device reliability. Please refer to qualification report for device reliability and package level datasheets for electrical param-  
eters.  
C2 level die and W2 level wafer probe following AC parameter.  
− tRC, tAA, tCO  
− tWC, tCW  
PACKAGING  
Individual device will be packed in anti-static trays.  
− Chip Trays : A 2-inch square waffle style carrier for die with separate compartments for each die. Commonly referred to as a waffle  
pack, each tray has a cavity size selected for the device that allows for easy loading and unloading and prevents  
rotation. The tray itself is made of conductive material to reduce the danger of damage to the die from electrostatic  
discharge. The chip carriers will be labeled with the following information :  
− EMLSI wafer lot number  
− EMLSI part number  
− Quantity  
− Jar Packing : Jar packing is made by EMLSI and used by many customers that we deliver the requested die as wafer. The pack is  
consisted of clean paper to wrap the wafer, high cushioned sponge between wafers and hardly fragile plastic box with sponge. Each  
pack has typically 24 wafers and then several packs are put into larger box depending on amounts of wafers.  
Bond Pad #1 at Top  
Die orientation in chip carriers  
STORAGE AND HANDLING  
EMLSI recommends the die stored in a controlled environment with filtered nitrogen. The carrier must be opened at ESD safe  
environment when inspection and assembly.  
3
EM620FV16B Series  
Low Power, 128Kx16 SRAM  
ABSOLUTE MAXIMUM RATINGS *  
Parameter  
Voltage on Any Pin Relative to Vss  
Voltage on Vcc supply relative to Vss  
Power Dissipation  
Symbol  
VIN, VOUT  
VCC  
Minimum  
-0.2 to 4.0V  
-0.2 to 4.0V  
1.0  
Unit  
V
V
PD  
W
oC  
Operating Temperature  
TA  
-40 to 85  
*
Stresses greater than those listed above “Absolute Maximum Ratings” may cause permanent damage to the device. Functional oper-  
ation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods  
may affect reliability.  
FUNCTIONAL DESCRIPTION  
CS1  
CS2  
OE  
WE  
LB  
UB  
I/O0-7  
I/O8-15  
Mode  
Power  
H
X
X
L
L
L
L
L
L
L
L
X
L
X
X
X
H
H
L
X
X
X
H
H
H
H
H
L
X
X
H
L
X
X
H
X
L
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
Data Out  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
Deselected  
Deselected  
Stand by  
Stand by  
Stand by  
Active  
X
H
H
H
H
H
H
H
H
Deselected  
Output Disabled  
Output Disabled  
Lower Byte Read  
X
L
Active  
H
L
Active  
L
H
L
Data Out Upper Byte Read  
Active  
L
L
Data Out Data Out  
Word Read  
Lower Byte Write  
Upper Byte Write  
Word Write  
Active  
X
X
X
L
H
L
Data In  
High-Z  
Data In  
High-Z  
Data In  
Data In  
Active  
L
H
L
Active  
L
L
Active  
Note: X means don’t care. (Must be low or high state)  
4
EM620FV16B Series  
Low Power, 128Kx16 SRAM  
1)  
RECOMMENDED DC OPERATING CONDITIONS  
Parameter  
Supply voltage  
Symbol  
Min  
2.7  
0
Typ  
3.3  
0
Max  
3.6  
0
Unit  
VCC  
V
Ground  
VSS  
VIH  
V
V
VCC + 0.22)  
0.6  
Input high voltage  
2.2  
-
-
-0.23)  
Input low voltage  
VIL  
V
1. TA= -40 to 85oC, otherwise specified  
2. Overshoot: VCC +2.0 V in case of pulse width < 20ns  
3. Undershoot: -2.0 V in case of pulse width < 20ns  
4. Overshoot and undershoot are sampled, not 100% tested  
.
1)  
o
CAPACITANCE (f =1MHz, T =25 C)  
A
Item  
Input capacitance  
Symbol  
Test Condition  
Min  
Max  
Unit  
CIN  
CIO  
VIN=0V  
-
8
pF  
Input/Ouput capacitance  
VIO=0V  
-
10  
pF  
1. Capacitance is sampled, not 100% tested  
DC AND OPERATING CHARACTERISTICS  
Parameter  
Symbol  
Test Conditions  
Min  
Typ Max  
Unit  
ILI  
V
=V to V  
SS CC  
Input leakage current  
-1  
-1  
-
-
-
-
1
1
3
uA  
IN  
CS1=V or CS2=V or OE=V or WE=V or LB=UB=V  
IH  
IL  
IH  
IL  
IH  
ILO  
ICC  
Output leakage current  
Operating power supply  
uA  
V
=V to V  
SS CC  
IO  
I
=0mA, CS1=V , CS2=WE=V , V =V or V  
IL  
mA  
IO  
IL  
IH  
IN  
IH  
Cycle time=1µs, 100% duty, I =0mA,  
IO  
ICC1  
CS1<0.2V, LB<0.2V or/and UB<0.2V, CS2>V -0.2V,  
CC  
-
-
3
mA  
mA  
V
<0.2V or V >V -0.2V  
IN CC  
IN  
45ns  
55ns  
70ns  
-
-
-
-
-
-
-
-
35  
30  
25  
0.4  
Average operating current  
Cycle time = Min, I =0mA, 100% duty,  
IO  
ICC2  
CS1=V , CS2=V LB=V or/and UB=V  
IL ,  
IL  
IH,  
IL  
V
I
=V or V  
IN  
IL  
IH  
VOL  
VOH  
ISB  
= 2.1mA  
Output low voltage  
Output high voltage  
Standby Current (TTL)  
V
V
OL  
I
= -1.0mA  
2.4  
-
-
-
-
OH  
CS1=V , CS2=V , Other inputs=V or V  
IL  
0.3  
mA  
IH  
IL  
IH  
CS1>V -0.2V, CS2>V -0.2V (CS1 controlled)  
CC  
CC  
or 0V<CS2<0.2V (CS2 controlled),  
Other inputs = 0~V  
CC  
11)  
ISB1  
Standby Current (CMOS)  
LF  
-
10  
uA  
o
(Typ. condition : V =3.3V @ 25 C)  
CC  
o
(Max. condition : V =3.6V @ 85 C)  
CC  
NOTES  
1. Typical values are measured at Vcc=3.3V, TA=25oC and not 100% tested.  
5
EM620FV16B Series  
Low Power, 128Kx16 SRAM  
3)  
AC OPERATING CONDITIONS  
Test Conditions (Test Load and Test Input/Output Reference)  
VTM  
2)  
R1  
Input Pulse Level : 0.4 to 2.2V  
Input Rise and Fall Time : 5ns  
Input and Output reference Voltage : 1.5V  
Output Load (See right) : CL1) = 100pF + 1 TTL  
CL1) = 30pF + 1 TTL (only 45ns part)  
1. Including scope and Jig capacitance  
2)  
R2  
CL1)  
2. R1=3070 ohm  
3. VTM=2.8V  
,
R2=3150 ohm  
o
o
READ CYCLE (V =3.0 to 3.6V, Gnd = 0V, T = -40 C to +85 C)  
cc  
A
45ns  
55ns  
70ns  
Max  
Symbol  
Parameter  
Unit  
Min  
Max  
Min  
Max  
Min  
Read cycle time  
tRC  
tAA  
tCO1, tCO2  
tOE  
45  
-
55  
-
70  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address access time  
-
-
-
45  
45  
25  
45  
-
-
-
-
55  
55  
25  
55  
-
-
-
-
70  
70  
35  
70  
-
Chip select to output  
Output enable to valid output  
UB, LB access time  
tBA  
Chip select to low-Z output  
UB, LB enable to low-Z output  
Output enable to low-Z output  
Chip disable to high-Z output  
UB, LB disable to high-Z output  
Output disable to high-Z output  
Output hold from address change  
t
LZ1, tLZ2  
tBLZ  
10  
5
10  
10  
5
10  
10  
5
-
-
-
tOLZ  
5
-
-
-
tHZ1, tHZ2  
tBHZ  
0
20  
15  
15  
-
0
20  
20  
20  
-
0
25  
25  
25  
-
0
0
0
tOHZ  
0
0
0
tOH  
10  
10  
10  
o
o
WRITE CYCLE (V =3.0 to 3.6V, Gnd = 0V, T = -40 C to +85 C)  
cc  
Parameter  
Write cycle time  
A
45ns  
55ns  
70ns  
Unit  
Symbol  
Min  
Max  
Min  
Max  
Min  
Max  
tWC  
tCW1, tCW2  
tAS  
45  
-
-
55  
-
-
70  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Chip select to end of write  
Address setup time  
45  
0
45  
0
60  
0
-
-
-
-
Address valid to end of write  
UB, LB valid to end of write  
Write pulse width  
tAW  
45  
45  
35  
0
-
45  
45  
40  
0
-
60  
60  
50  
0
-
tBW  
-
-
-
tWP  
-
-
-
Write recovery time  
tWR  
-
-
-
Write to ouput high-Z  
tWHZ  
tDW  
0
15  
0
20  
0
20  
Data to write time overlap  
Data hold from write time  
End write to output low-Z  
25  
0
25  
0
30  
0
tDH  
-
-
-
-
-
-
tOW  
5
5
5
6
EM620FV16B Series  
Low Power, 128Kx16 SRAM  
TIMING DIAGRAMS  
TIMING WAVEFORM OF READ CYCLE(1). (Address Controlled, CS1=OE=VIL, CS2=WE=VIH, UB or/and LB=VIL  
)
tRC  
Address  
tAA  
tOH  
Previous Data Valid  
Data Valid  
Data Out  
TIMING WAVEFORM OF READ CYCLE(2) (WE = VIH)  
tRC  
Address  
tAA  
tOH  
tCO  
CS1  
CS2  
tHZ  
tBA  
UB,LB  
tBHZ  
tOE  
OE  
tOHZ  
tOLZ  
High-Z  
Data Out  
Data Valid  
tBLZ  
tLZ  
tWHZ  
NOTES (READ CYCLE)  
1. tHZ and tOHZ are defined as the outputs achieve the open circuit conditions and are not referenced to output voltage levels.  
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device  
interconnection.  
7
EM620FV16B Series  
Low Power, 128Kx16 SRAM  
TIMING WAVEFORM OF WRITE CYCLE(1) (WE CONTROLLED)  
tWC  
Address  
tCW(2)  
tWR(4)  
CS1  
CS2  
tAW  
tBW  
UB,LB  
tWP(1)  
WE  
tDH  
tAS(3)  
tDW  
High-Z  
High-Z  
Data in  
Data Valid  
tWHZ  
tOW  
Data out  
Data Undefined  
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 CONTROLLED)  
tWC  
Address  
t
AS(3)  
tCW(2)  
tWR(4)  
CS1  
CS2  
tAW  
tBW  
UB,LB  
tWP(1)  
WE  
tDH  
tDW  
Data in  
Data Valid  
High-Z  
High-Z  
Data out  
8
EM620FV16B Series  
Low Power, 128Kx16 SRAM  
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 CONTROLLED)  
tWC  
Address  
tCW(2)  
tWR(4)  
CS1  
t
AS(3)  
CS2  
WE  
tAW  
tWP(1)  
tDH  
tDW  
Data in  
Data Valid  
High-Z  
High-Z  
Data out  
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB CONTROLLED)  
tWC  
Address  
tCW(2)  
tWR(4)  
CS1  
CS2  
tAW  
tBW  
UB,LB  
tWP(1)  
tAS(3)  
WE  
tDH  
tDW  
Data in  
Data Valid  
High-Z  
High-Z  
Data out  
NOTES (WRITE CYCLE)  
1. A write occurs during the overlap(tWP) of low CS1 a high CS2 and low WE. A write begins at the lastest transition among CS1  
goes low, CS2 goes high and WE goes low. A write ends at the earliest transition when CS1 goes high, CS2 goes high and WE  
goes high. The tWP is measured from the beginning of write to the end of write.  
2. tCW is measured from the CS1 going low to end of write.  
3. tAS is measured from the address valid to the beginning of write.  
4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS1 or WE going high.  
9
EM620FV16B Series  
Low Power, 128Kx16 SRAM  
DATA RETENTION CHARACTERISTICS  
Parameter  
VCC for Data Retention  
Symbol  
VDR  
Test Condition  
Min  
Typ2) Max  
Unit  
ISB1 Test Condition  
(Chip Disabled) 1)  
1.5  
-
3.6  
-
V
VCC=1.5V, ISB1 Test Condition  
(Chip Disabled) 1)  
IDR  
Data Retention Current  
-
0.5  
µA  
Chip Deselect to Data Retention Time  
Operation Recovery Time  
tSDR  
tRDR  
0
-
-
-
-
See data retention wave form  
ns  
tRC  
NOTES  
1. See the ISB1 measurement condition of data sheet page 5.  
2. Typical value is measured at TA=25oC and not 100% tested.  
DATA RETENTION WAVE FORM  
tRDR  
tSDR  
Data Retention Mode  
Vcc  
3.0V  
2.2V  
VDR  
CS1 > Vcc-0.2V  
CS1  
GND  
Data Retention Mode  
Vcc  
3.0V  
CS2  
tRDR  
tSDR  
VDR  
0.4V  
CS2 < 0.2V  
GND  
10  
EM620FV16B Series  
Low Power, 128Kx16 SRAM  
SRAM PART CODING SYSTEM  
EM X XX X X X XX X X - XX XX  
1. EMLSI Memory  
2. Product Type  
3. Density  
11. Power  
10. Speed  
4. Function  
9. Package  
8. Generation  
7. Organization  
5. Technology  
6. Operating Voltage  
1. Memory Component  
7. Organization  
EM --------------------- Memory  
8 ---------------------- x8 bit  
16 ---------------------- x16 bit  
2. Product Type  
6 ------------------------ SRAM  
8. Generation  
Blank ----------------- 1st generation  
A ----------------------- 2nd generation  
B ----------------------- 3rd generation  
C ----------------------- 4th generation  
D ----------------------- 5th generation  
E ----------------------- 6th generation  
F ----------------------- 7th generation  
G ---------------------- 8th generation  
3. Density  
1 ------------------------- 1M  
2 ------------------------- 2M  
4 ------------------------- 4M  
8 ------------------------- 8M  
4. Function  
0 ----------------------- Dual CS  
1 ----------------------- Single CS  
9. Package  
2 ----------------------- Multiplexed  
Blank ---------------- KGD, 48&36FpBGA  
S ---------------------- 32sTSOP1  
T ---------------------- 32 TSOP1  
U ---------------------- 44 TSOP2  
3 ------------- Single CS / LBB, UBB(tBA=tOE)  
4 ------------- Single CS / LBB, UBB(tBA=tCO)  
5 ------------- Dual CS / LBB, UBB(tBA=tOE)  
6 ------------- Dual CS / LBB, UBB(tBA=tCO)  
10. Speed  
5. Technology  
F ------------------------- Full CMOS  
45 ---------------------- 45ns  
55 ---------------------- 55ns  
70 ---------------------- 70ns  
85 ---------------------- 85ns  
10 ---------------------- 100ns  
12 ---------------------- 120ns  
6. Operating Voltage  
T ------------------------- 5.0V  
V ------------------------- 3.3V  
U ------------------------- 3.0V  
S ------------------------- 2.5V  
R ------------------------- 2.0V  
P ------------------------- 1.8V  
11. Power  
LL ---------------------- Low Low Power  
LF ---------------------- Low Low Power(Pb-Free & Green)  
L ---------------------- Low Power  
S ---------------------- Standard Power  
11  

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 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9137DB

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9137LG

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9122E

 500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers

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