EM9270C/D [ETC]
Telephone Answering Device Digital & Shuttle Type ; 电话应答设备数字和飞梭型\n
| 型号： | EM9270C/D |
| 厂家： | 
ETC |
| 描述： | Telephone Answering Device Digital & Shuttle Type
|
| 文件： | 总10页 (文件大小：68K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM 9270C/D
DTMF RECEIVER
General Description
The HM 9270C/D is a complete DTMF receiver integrating both the bandsplit filter and digital decoder
functions. The filter section uses switched capacitor techniques for high- and low-group filters and dial-tone
rejection. Digital counting techniques are employed in the decoder to detect and decode all 16 DTMF tone-
pairs into a 4-bit code. External component count is minimized by on-chip provision of a differential input
amplifier, clock-oscillator and latched 3-state bus interface.
Features
• Complete receiver in an 18-pin package.
• Excellent performance.
• CMOS, single 5 volt operation.
• Minimum board area.
• Central office quality.
• Low power consumption.
• Power-Down mode (HM9270D only).
• Inhibit-mode (HM9270D only).
Pin Configurations
HM9270C
HM9270D
V
V
DD
IN+
IN
GS
REF
IC*
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
DD
IN+
IN
GS
REF
INH
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
St/GT
St/GT
ESt
StD
Q4
Q3
Q2
Q1
ESt
StD
Q4
Q3
Q2
Q1
V
V
PWDN
OSC1
OSC2
IC*
OSC1
OSC2
10
10
V
V
TOE
TOE
SS
SS
* Connect to VSS
- 1 -
HM 9270C/D
DTMF RECEIVER
Block Diagram (Figure 1)
INH
DIGITAL
HIGH
GROUP
FILTER
CODE
Q1
ZERO
CROSSING
DETECTORS
CONVERTER
AND
Q2
Q3
DETECTION
ALGORITHM
IN+
IN
DIAL
TONE
FILTER
+
-
LOW
GROUP
FILTER
LATCH
Q4
GS
CHIP
POWERBIAS REF
CHIP CHIP
CHIP
CLOCKS
OSC2
+
-
BIAS
CIRCUIT
STEERING
LOGIC
OSC1
VREF
TOE
V
V
ESt
StD
St/GT
PWDN
DD
SS
Pin Description
Function
Pin
Sym.
Non-Inverting input
Invering Input
1
2
IN+
IN-
Connections to the front-end differential amplifier.
Gain select. Gives access to output of front-end differential amplifier for connection of
feedback resistor.
3
4
5
6
GS
Reference voltage output,nominally VDD/2. May be used to bias the inputs at midrail (see
application diagram).
VREF
INH
Inhibit (input) logic high inhibit the detection of 1633Hz internal built-in pull down resistor.
(HM9270D only).
Power down (input). Active high power down the device and inhibit the oscillator internal
built-in pull down resistor. (HM9270D only).
PWDN
Clock Input
Output
Clock
3.579545 MHz crystal connected between these pins completes
internal oscillator.
7
8
OSC1
OSC2
Negative power supply, normally connected to 0V.
9
VSS
3-state data output enable (input). Logic high enables the outputs Q1-Q4. Internal pull-up.
10
TOE
- 2 -
HM 9270C/D
DTMF RECEIVER
Function
Pin
Sym.
3-state data outputs. When enabled by TOE, provide the code corresponding to the last valid
tone-pair received (see code table).
11
12
13
14
Q1
Q2
Q3
Q4
Delayed steering output. Presents a logic high when a received tone-pair has been registered
and the output latch updated; returns to logic low when the voltage on St/GT falls below
VTSt.
15
16
17
StD
Early steering output. Presents a logic high immediately when the digital algorithm detects a
recognizable tone-pair (signal condition). Any momentary loss of signal condition will cause
ESt to return to a logic low.
ESt
Steering input/guard time output (bi-directional). A voltage greater than VTSt detected at St
causes the device to register the detected tone-pair and update the output latch. A voltage
less than VTSt frees the device to accept a new tone-pair. The GT output acts to reset the
external steering time-constant; its state is a function of ESt and the voltage on St (see truth
table).
St/GT
Positive power supply, +5Volts.
18
VDD
Absolute Maximum Ratings (Notes 1, 2 and 3)
Parameters
Min.
Max.
Units
Power Supply Voltage, VDD - VSS
Voltage on any pin
Current at any pin
Operating temperature
Storage temperature
Package power dissipation
6
V
V
VSS - 0.3
VDD+ 0.3
10
+85
+150
500
mA
-40
-65
oC
oC
mW
Note 1. Absolute maximum ratings are those values beyond which damage to the device may
occur.
2. Unless otherwise specified, all voltages are referenced to ground.
/
3. Power dissipation temperature derating: -12 mV oC from 65oC to 85oC
DC Electrical Characteristics
Parameter Description
Test Conditions
Min. Typ. Max. Units
SUPPLY:
VDD
Icc
Po
Operating Supply Voltage
4.75
-
5.25
7
35
V
Operating Supply Current
Power Consumption
Standby Current
3.0
15
-
mA
mW
µA
f=3.579MHz; VDD=5V
PWDN pin = VDD
IS
100
INPUTS:
VIL
Low Level Input Voltage
High Level Input Voltage
Input Leakage Current
Pull Up (Source) Current
1.5
15
V
V
uA
uA
MΩ
VIH
IIH/IIL
Iso
3.5
VIN=Vss or VDD
TOE (Pin 10)=OV
@ 1kHz
0.1
7.5
10
RIN
Input
Signal
Impedance Inputs 1,2
VTSt
Steering Threshold Voltage
2.35
V
- 3 -
HM 9270C/D
DTMF RECEIVER
Parameter
Description
Test Conditions
Min. Typ. Max. Units
OUTPUTS:
No Load
No Load
VOUT=0.4V
VOUT=4.6V
No Load
0.03
4.97
2.5
V
V
mA
mA
V
KΩ
VOL
VOH
IOL
IOH
VREF
ROR
Low Level Output Voltage
High Level Output Voltage
Output Low (Sink) Current
Output High (Source) Current
1.0
0.4
2.4
0.8
2.7
Output Voltage
VREF
10
Output Resistance
Operating Characteristics
Gain Setting Amplifier
Parameter
Description
Test Conditions
Min.
Typ. Max. Units
IIN
RIN
Input Leakage Current
Input Resistance
Input Offset Voltage
VSS < VIN < VDD
±100
10
±25
60
60
65
1.5
4.5
100
50
nA
MΩ
mV
dB
dB
dB
MHz
VPP
pF
KΩ
VPP
VOS
PSRR
CMRR
AVOL
fC
VO
CL
RL
VCM
Power Supply Rejection
Common Mode Rejection
DC Open Loop Voltage Gain
Open Loop Unity Gain Bandwidth
Output Voltage Swing
Tolerable capacitive load(GS)
Tolerable resistive load(GS)
Common Mode Range
1kHz
-3.0V <VIN< 3.0V
RL³100KΩ to VSS
No Load
3.0
Notes : 1.All voltages referenced to VDD unless otherwise noted.
2.VDD= 5.0V, VSS = 0V, TA = 25oC .
AC Characteristics
All voltages referenced to VSS unless otherwise noted. VDD=5.0V, VSS=0V, TA = 25OC, FCLK=3.579545 MNz, using
test circuit of figure 2.
Parameter
SIGNAL COITIONS:
Valid Input Signal level (each
tone signal):MIN
Description
Min. Typ.
Max. Units
Notes
-40
dBm
1,2,3,5,6,9,11
1,2,3,5,6,9,11
7.75
mVRMS
dBm
+1
883
MAX
1,2,3,5,6,9,11
mVRMS
10
10
dB
dB
2,3,6,9,11
Twist Accept Limit: Positive
Negative
±1.5%±2 Hz Nom.
2,3,5,9,11
2,3,5,11
2,3,4,5,9,10,11
2,3,4,5,7,9,10,11
2,3,4,5,8,9,10,11
Freq. Deviation Accept Limit
Freq. Deviation Reject Limit
Third Tone Tolerance
Noise Tolerance
±3.5%
Nom.
-16
-12
+18
dB
dB
Dial Tone Tolerance
- 4 -
HM 9270C/D
DTMF RECEIVER
Parameter
Description
Min. Typ. Max. Units
Notes
TIMING:
tDP
Tone Present Detection Time
Tone Absent Detection Time
Tone Duration Accept
Tone Duration Reject
Interdigit Pause Accept
Interdigit Pause Reject
5
0.5
14
4
16
8.5
40
ms
ms
ms
ms
ms
Refer to Fig. 4
tDA
tREC
tREC
tID
(User Adjustable)
20
40
Refer to "Guard Time 20
tDO
ms
Adjustment"
OUTPUTS:
tPQ
Propagation Delay (St to Q)
Propagation Delay (St to StD)
Output Data Set Up (Q to Std)
8
11
60
µs
µs
µs
ns
ns
TOE= VDD
tPSED
tQSED
tPTE
12
4.5
50
300
Propagation
ENABLE
RL=10kΩ
CL=50pf
tPTD
Delay (TOE to Q) DISABLE
CLOCK:
fCLK
Crystal/Clock Frequency
Clock Output Capacitive
3.5759 3.5795 3.581 MHz
30 pf
CLO
(OSC2)
Load
Notes: 1.dBm = decibels above or below a reference power of 1mW into a 600 Ohm load.
2.Digit sequences consists of all 16 DTMF tones.
3.Tone duration = 40mS Tone pause = 40mS.
4.Nominal DTMF frequencies are used.
5.Both tones in the composite signal have an equal amplitude.
6.Tone pair is deviated by ±1.5% ±2Hz.
7.Bandwidth limited (3kHz) Gaussian Noise.
8.The precise dial tone frequencies are (350Hz and 440Hz) ±2%.
9.For an error rate of less than 1 in 10,000.
10.Referenced to the lowest level frequency component in DTMF signal.
11.Added A 0.1µf capacitor between VDD and VSS.
Function Description
HM9270C
5V
0.1µf
100NF
V
IN+
IN
DD
NF
100
St/GT
ESt
300KΩ
100KΩ
GS
V
StD
100 KΩ
REF
Q4
IC
IC
Q3
Q2
OSC1
3.58
MHz
OSC2
Q1
V
SS
TOE
FIGURE 2. SINGLE ENDED INPUT CONFIGURATION
- 5 -
HM 9270C/D
DTMF RECEIVER
HM9270D
5V
0.1µf
100NF
V
IN+
IN
DD
NF
100
Vin
St/GT
ESt
300KΩ
100KΩ
GS
StD
100 KΩ
V
5V
REF
Q4
INH
PWDN
OSC1
Q3
Q2
3.58
MHz
OSC2
Q1
V
SS
TOE
FIGURE 3. SINGLE ENDED INPUT CONFIGURATION
The HM9270C/D monolithic DTMF receiver offers small size, low power consumption and high performance. Its
architecture consists of a bandsplit filter section, which separates the high and low tones of receiver pair, followed by
a digital counting section which verifies the frequency and duration of the received tones before passing the
corresponding code to the output bus.
FILTER SECTION
Separation of the low-group and high-group tones is achieved by applying the dual tone signal to the inputs of two
filters a sixth order for the high group and an eighth order for the low group. The bandwidths of which correspond
to the bands enclosing the low-group and high-group tones (see Fig. 4). The filter section also in corporates
notches at 350Hz and 440 Hz for exceptional dial-tone rejection. Each filter output is followed by a second-order
switched-capacitor section which smooths the signals prior to limiting. Limiting is performed by high-gain com-
parators which are provided with hysteresis to prevent detection of unwanted low-level signals and noise; the
outputs of the comparators provide full-rail logic swings at the frequencies of the incoming tones.
Flow Fhigh KEY TOE Q4
Q3 Q2 Q1
697 1209
697 1336
697 1477
770 1209
770 1336
770 1477
852 1209
852 1336
852 1477
941 1336
941 1209
941 1477
697 1633
770 1633
852 1633
941 1633
1
2
3
4
5
6
7
8
9
0
*
#
A
B
C
D
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
Z
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
Z
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
Z
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Z
Decoder Section
The decoder used digital counting techniques to
determine the frequencies of the limited tones and to
verify that they correspond to standard DTMF
frequencies. A complex averaging algorithm(protects)
against tone simulation by extraneous signals, such as
voice, while providing tolerance to smalll frequency
deviations and variations. This averaging algorithm has
been developed to ensure an optimum combination of
immunity to "talk-off" and tolerance to the presence of
interfering signals ("third tones") and noise. When the
detector recognizes the simultaneous presence of two
valid tones (referred to as "signal condition" in some
industry specifications), it raises the "early steering"
flag (ESt). Any subsequent loss of signal condition will
cause ESt to fall.
-
-
ANY L
L = LOGIC LOW , H = LOGIC HIGH, Z = HIGH
IMPEDANCE
FIGURE 4. LOGIC TABLE
- 6 -
HM 9270C/D
DTMF RECEIVER
FIGURE 5. TIMING DIAGRAM
D
A
B
C
E
F
G
EVENTS
TONE DROPOUT
TONE#n+1
t
INTERDIGIT
PAUSE
DO
t
t
ID
REC
t
REC
TONE # n
TONE #n+1
t
t
DA
DP
V
Ts t
ESt
t
t
GTP
GTA
St/GT
t
PQ
DATA
OUTPUTS
DECODED
TONE#n
DECODE TONE n-1
DECODED TONE # n + 1
HIGH
IMPEDANCE
Q1-Q4
t
t
PS
D
StD
OUTPUT
t
t
PTD
PTE
TOE
A. Short tone bursts: detected. Tone duration is invalid.
B. Tone #n is detected. Tone duration is valid. Decoded
to outputs.
C. End of tone #n is dectected and validated.
D. 3 State outputs disabled (high impedance).
E. Tone #n + 1 is detected. Tone duration is valid. De
coded to outputs.
F. Tristate outputs are enabled. Acceptable drop out of
tone #n + 1 does not negister at outputs.
G. End of tone #n + 1 is detected and validated.
0
10
20
30
40
50
60
70
80
FIGURE 5. TIMING DIAGRAM
STEERING CIRCUIT
Before registration of a decoded tone-pair, the receiver checks
for a valid signal duration (referred to as "character-recogni-
tion-condition"). This check is per-
formed by an external RC time-constant driven by ESt.
A logic high on ESt causes VC (see Fig. 5) to rise as the
capacitor discharges. Provided signal-condition is main-
tained (ESt remains high) for the validation period (tGTP), Vc
reaches the threshold (VTSt) of the steering logic to register the
tone-pair, latching its corresponding 4-bit code (see Fig. 3)
into the output latch. At this point,
1K
0
2K
FIGURE 6. TYPICAL FILTER
CHARACTERISTIC
the GT output is activated and drives VC to VDD. GT continues to drive high as long as ESt remains high. Finally
after a short delay to allow the output latch to settle, the "delayed-steering" output flag, StD, goes high, signaling
that a recieved tone-pair has been registered. The contents of the output lacth are made available on the 4-bit
output bus by raising the 3-state control input (TOE) to a logic high. The steering circuit works in reverse to
validate the interdigit paues between signals. Thus, as well as rejecting signals too short to be considered valid, the
receiver will tolerate signal interruptions ("drop-out") too short to be considered a valid pause. The facility, together
with the capability of selecting the steering time-constants externally, allows the designer to tailor performance to
meet a wide variety of system requiremetns.
- 7 -
HM 9270C/D
DTMF RECEIVER
V
t
DD
C
C
0.1µf
V
V
DD
DD
=(RC) ln (
=(RC) ln (
)
GTA
V
TST
V
St/GT
V
DD
t
)
GTP
V
-
V
DD
TST
ESt
S
R
tD
FIGURE 7. BASIC STEERING CIRCUIT
Guard Time Adjustment
In many situations not requiring independent selection of receive and pause, the simple steering circuit of Fig. 7 is
applicable. Component values are chosen according to the following formulae:
tREC = tDP + tGTP
tID = tDA + tGTA
The value of tDP is a parameter of the device (see table) and tREC is the minimum signal duration to be recognized by
the receiver. A value for C of 0.1 µF is recommended for most applications, leaving R to be selected by the
designer. For example, a suitable value of R for a tREC of 40mS would be 300k.
Different steering arrangements may be used to select independently the guard-times for tone-present (tGTP) and
tone-absent (tGTA). This may be necessary to meet system specifications which place both accept and reject limits on
both tone duration and interdigital pause.
Guard-time adjustment also allows the designer to tailor system parameters such as talk off and noise immunity.
Increasing tREC improves talk-off performance, since it reduces the probability that tones simulated by speech will
maintain signal condition for long enough to be registered. On the other hand, a relatively short tREC with a long tDO
would be appropriate for extremely noisy environments where fast acquisition time and immunity to drop - outs
would be required. Design information for guard-time adjustment is shown in Fig. 8.
V
V
DD
DD
C
C
S
S
/ GT
/
GT
t
t
R1
R2
R1
R2
ES
ES
t
t
V
DD
V
DD
tGTP=(Rp C) In (
)
tGTP=(Rp C) In (
tGTA=(R1 C) In (
)
V
DD - VTST
DD
V
DD - VTST
DD
V
V
tGTA=(R1 C) In (
)
)
VTST
VTST
R1R2
Rp=
R1R2
Rp=
R1+R2
R1+R2
a) Decreasing tGTP (tGTP < tGTA
)
b) Decreasing tGTP (tGTP > tGTA)
FIGURE 8. GUARD TIME ADJUSTMENT
- 8 -
HM 9270C/D
DTMF RECEIVER
Input Configuration
The input arrangement of the HM9270C/D provides a differential-input operational amplifier as well as a
bias source (VREF ) which is used to bias the inputs at mid-rail.
Provision is made for connection of a feedback resistor to the op-amp output (GS) for adjustment of gain.
In a single-ended configuration, the input pins are connected as shown in Fig. 2 with the op-amp connected
for unity gain and VREF biasing the input at 1/2VDD.
Fig. 9 shows the differential configuration, which permits the adjustment of gain with the feedback resistor
R5.
C1
HM9270C/D
R1
+
-
R4
C2
GS
R5
R3
R2
V
REF
FIGURE 9. DIFFERENTIAL INPUT CONFIGURATION
Power - down and inhibit mode
A logic high applied to pin 6 (PWDN) will power the device to minimize the power consumption in a standby
mode. It stops the oscillator and the functions of the filters.
Inhibit mode is enabled by a logic high input to the pin 5 (INH). It inhibits the detection of 1633 Hz. The output
code will remain the same as the previous detected code (see table 1).
fLow Fhigh Key
TOE Q4
Q3 Q2 Q1
fLow Fhigh Key
TOE Q4
Q3 Q2 Q1
697 1209
697 1336
697 1477
770 1209
770 1336
770 1477
852 1209
852 1336
852 1477
941 1336
941 1209
941 1477
1
2
3
4
5
6
7
8
9
0
*
#
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
Z
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
Z
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
Z
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
Z
697 1209
697 1336
697 1477
770 1209
770 1336
770 1477
852 1209
852 1336
852 1477
941 1336
941 1209
941 1477
1
2
3
4
5
6
7
8
9
0
*
#
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
L
L
L
H
H
H
H
L
L
L
L
H
L
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
697
1633
770 1633
852 1633
941 1633
A
B
C
D
ANY
697
1633
770 1633
852 1633
941 1633
A
B
C
D
ANY
PREVIOUS DATA
-
-
-
-
Z
Z
Z
Z
Table 1: Truth table
INH =VSS
(Z: high impedance)
INH=VDD
- 9 -
HM 9270C/D
DTMF RECEIVER
SPECIAL PACKAGE PIN CONFIGURATIONS
HM9270DM
IN+
IN-
GS
VREF
INH
PWDN
OSC1
OSC2
VDD
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
St/GT
EST
StD
Q
Q
Q
4
3
2
1
Q
V
SS
TOE
NC
10
NC
- 10 -
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