EMP202 [ETC]
Single-Chip Dual-Channel AC’97 Audio Codec for PC Audio Systems; 单芯片双通道AC'97音频编解码器的PC音频系统
| 型号： | EMP202 |
| 厂家： | 
ETC |
| 描述： | Single-Chip Dual-Channel AC’97 Audio Codec for PC Audio Systems |
| 文件： | 总28页 (文件大小：237K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EMP202
Single-Chip Dual-Channel AC’97
Audio Codec for PC Audio Systems
1. Features....................................................................2
2. General Description.................................................2
3. Block Diagram..........................................................3
4. Pin Assignments......................................................4
5. Pin Description.........................................................5
5.1. Digital I/O Pins ....................................................5
5.2. Analog I/O Pins...................................................5
5.3. Filter/References.................................................6
5.4. Power/Ground.....................................................6
5.5. Crystal Selection.................................................6
6. Registers...................................................................7
6.1. Mixer Registers...................................................8
6.1.1. MX00 Reset.................................................8
6.1.2. MX02 Master Volume ..................................8
6.1.3. MX04 Headphone Volume...........................9
6.1.4. MX06 MONO_OUT Volume.........................9
6.1.5. MX0A PC BEEP Volume .............................9
6.1.6. MX0C PHONE Volume..............................10
6.1.7. MX0E MIC Volume ....................................10
6.1.8. MX10 LINE_IN Volume..............................10
6.1.9. MX12 CD Volume......................................11
6.1.10. MX14 VIDEO Volume ................................11
6.1.11. MX16 AUX Volume....................................12
6.1.12. MX18 PCM_OUT Volume..........................12
6.1.13. MX1A Record Select..................................13
6.1.14. MX1C Record Gain....................................13
6.1.15. MX20 General Purpose Register...............14
6.1.16. MX22 3D Control .......................................14
6.1.17. MX26 Powerdown Control/Status..............15
6.1.18. MX28 Extended Audio ID...........................16
6.1.19. MX2A Extended Audio Status and Control 16
6.1.20. MX2C PCM Output Sample Rate ..............17
6.1.21. MX32 PCM Input Sample Rate..................17
6.1.22. MX3A S/PDIF Output Channel
6.2.1. MX3E Extended Modem Status and Control18
6.2.2. MX4C GPIO Pin Configuration................. 19
6.2.3. MX4E GPIO Pin Polarity/Type ................. 19
6.2.4. MX50 GPIO Pin Sticky ............................. 19
6.2.5. MX50 GPIO Pin Status............................. 19
6.3. Extended Registers.......................................... 20
6.3.1. MX6A SPDIF Output Select ...................... 20
6.3.2. MX72 Antipop............................................ 20
6.3.3. MX74 EAPD Access.................................. 20
6.3.4. MX7C VENDOR ID1 ................................. 20
6.3.5. MX7E VENDOR ID2.................................. 21
7. Electrical Characteristics...................................... 21
7.1. DC Characteristics ........................................... 21
7.2. AC Timing Characteristics................................ 21
7.2.1. Cold Reset ................................................ 21
7.2.2. Warm Reset .............................................. 22
7.2.3. AC-Link Clocks.......................................... 22
7.2.4. Data Output and Input Times .................... 23
7.2.5. Signal Rise and Fall Times........................ 23
7.2.6. AC-Link Low Power Mode Timing............. 24
7.2.7. ATE Test Mode ......................................... 24
7.2.8. AC-Link IO Pin Capacitance and Loading. 24
7.2.9. BIT-CLK and SDATA-IN State .................. 24
8. Analog Performance Characteristics................... 25
9. Design Suggestions.............................................. 26
9.1. Clocking............................................................ 26
9.2. AC-Link............................................................. 26
9.3. Reset................................................................ 26
9.4. CD Input ........................................................... 27
9.5. Odd Addressed Register Access...................... 27
9.6. Power-down Mode ........................................... 27
9.7. Test Mode ........................................................ 27
9.7.1. ATE In Circuit Test Mode .......................... 27
9.7.2. Vendor Specific Test Mode ....................... 27
10. Package Dimensions............................................. 28
Status and Control.................................................18
6.2. GPIO Registers.................................................18
1
8/7/2003
Single-Chip Dual-Channel AC’97 Audio Codec
EMP202
EMPIA Technology
Features
High performance CODEC with high S/N ratio (>90 dB).
Compliant with AC’97 2.2 specifications
20-bit stereo Digital-to-Analog Converter with variable sampling rate.
20-bit stereo Analog-to-Digital Converter with variable sampling rate.
4 analog line-level stereo inputs with 5-bit volume control: LINE_IN, CD,
VIDEO, AUX.
2 analog line-level mono inputs: PC_BEEP, PHONE_IN.
Mono output with 5-bit volume control.
Stereo output with 5-bit volume control.
2 MIC inputs are software selectable.
Power management capabilities.
3D Stereo Enhancement
Embedded 50mW/20 Ω OP at LINE output.
External amplifier power down capability.
Digital S/PDIF output.
Built in 14.318M 24.576MHz PLL to save external 24.576MHz crystal
Supports 2 general-purpose I/O pins.
Power supply: Digital: 3.3V; Analog: 5V/3.3V
Standard 48-Pin LQFP Package
1. General Description
The EMP202 is a 2 channel, 20-bit DAC and 20-bit ADC, full duplex AC'97 2.2 compatible stereo
audio CODEC designed for PC multimedia systems, including soft/host audio and riser card based
designs. The EMP202 incorporates proprietary converter technology. The EMP202 AC'97 CODEC
supports with independent variable hardware sampling rates. The EMP202 CODEC provides two
pairs of stereo outputs with independent volume controls, a mono output, a headphone output, and
multiple stereo and mono inputs, along with flexible mixing, gain and mute functions to provide a
complete integrated audio solution for PCs. The EMP202 CODEC operates from a 3.3V power supply
with EAPD (External Amplifier Power Down) control for use in notebook and PC applications. To save
BOM costs, the EMP202 integrates a 50mW/20 Ω headset audio amplifier into the CODEC with
Headphone Output. The EMP202 also supports an AC’97 2.2 compliant SPDIF out function which
allows easy connection from the PC to consumer electronic products. The EMP202 CODEC supports
soft/host audio from Intel 810/815/820/845 chipsets as well as audio controller based VIA/SIS/ALI
chipsets. Windows WDM drivers that support Win95/98.ME/2K/NT and XP provide a complete
solution. Finally, internal PLL circuits generate required timing signals, eliminating the need for
external clocking devices.
7/15/2002
2
Single-Chip Dual-Channel AC’97 Audio Codec
EMP202
EMPIA Technology
2. Block Diagram
MUX
Mixer Functional Diagram
7/15/2002
3
Single-Chip Dual-Channel AC’97 Audio Codec
EMP202
EMPIA Technology
3. Pin Assignments
1
2
36
35
34
33
32
31
30
29
28
27
26
25
DVDD1
XTL-IN
LINE-OUT-R
LINE-OUT-L
NC
3
XTL-OUT
DVSS1
4
NC
5
SDATA-OUT
BIT-CLK
DVSS2
CAP2
6
NC
EMP202
7
AFILT2
AFILT1
VREFOUT
VREF
8
SDATA-IN
DVDD2
9
10
11
12
SYNC
RESET#
PC-BEEP
AVSS1
AVDD1
Pin Assignment Diagram
7/15/2002
4
Single-Chip Dual-Channel AC’97 Audio Codec
EMP202
EMPIA Technology
4. Pin Description
4.1. Digital I/O Pins
Name
Type Pin No
Description
Characteristic Definition
RESET#
I
11
AC'97 master H/W reset
Schmitt input, VL=0.3Vdd,
VH=0.4Vdd
XTL-IN
XTL-OUT
SYNC
I
O
I
2
3
Crystal input pad (24.576Mhz)
Crystal output pad
Crystal input pad
Crystal output pad
Schmitt input, VL=0.3Vdd,
VH=0.4Vdd
10
Sample Sync (48Khz)
BIT-CLK
IO
I
6
5
8
Bit clock output (12.288Mhz)
Serial TDM AC’97 output
Serial TDM AC’97 input
CMOS input/output, Vt=0.35Vdd,
internal pull low by a 100K resistor.
Schmitt input, VL=0.3Vdd,
VH=0.4Vdd
SDATA-OUT
SDATA-IN
O
CMOS output, internal pull low by a
100K resistor.
GPIO0
GPIO1
ID1
I/O
I/O
I
43
44
46
45
47
General Purpose Input/Output
General Purpose Input/Output
XTAL Elim Select
Digital input/output
Digital input/output
Digital input
ID0
I
XTAL Elim Select
Digital input
EAPD
I/O
External Amplifier power down
control/GPIO
Digital output
SPDIFOUT
O
48
S/PDIF output
Digital output
TOTAL: 13 Pins
4.2. Analog I/O Pins
Name
PC-BEEP
PHONE
AUX-L
Type
Pin No
12
13
14
15
16
17
18
19
20
21
22
23
24
35
36
37
39
40
41
Description
Characteristic Definition
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog output (1Vrms ~ 1.7Vrms)
Analog output (1Vrms ~ 1.7Vrms)
Analog output (1Vrms)
Analog output (1Vrms)
Analog output (1Vrms)
Analog output (1Vrms)
I
I
PC speaker input
Speaker phone input
AUX Left channel
I
AUX-R
I
AUX Right channel
VIDEO-L
VIDEO-R
CD-L
I
Video audio Left channel
Video audio Right channel
CD audio Left channel
CD audio analog GND
CD audio Right channel
First Mic input
I
I
CD-GND
CD-R
I
I
MIC1
I
MIC2
I
Second Mic input
LINE-L
I
Line-In Left channel
LINE-R
I
Line-In Right channel
Line-Out Left channel
Line-Out Right channel
Speaker Phone output
Headphone Out Left channel
Headphone Ground Return
Headphone Out Right channel
LINE-OUT-L
LINE-OUT-R
MONO-OUT
HP-OUT-L
HP-COMM
HP-OUT-R
O
O
O
O
O
O
TOTAL: 19 Pins
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Single-Chip Dual-Channel AC’97 Audio Codec
EMP202
EMPIA Technology
4.3. Filter/References
Name
Type Pin No
Description
Characteristic Definition
VREF
O
O
O
27
28
29
Reference voltage
Analog output
VREFOUT
AFILT1
Ref. voltage out with 5mA drive
ADC left anti-aliasing filter
capacitor
Analog output
Analog output
AFILT2
O
30
ADC right anti-aliasing filter
capacitor
Analog output
CAP2
O
-
32
ADC reference Cap
No Connect
Analog output
NC
31,33,34
TOTAL: 8 Pins
4.4. Power/Ground
Name Type Pin No
Description
Characteristic Definition
AVDD1
AVDD2
AVSS1
AVSS2
VDD1
I
I
I
I
I
25
38
26
42
1
Analog VDD (5.0V) The minimum value is 3.0V, the maximum value is 5.5V
Analog VDD (5.0V) The minimum value is 3.0V, the maximum value is 5.5V
Analog GND
Analog GND
Digital VDD (3.3V) The minimum value is 3.0V (DVdd-0.3), the maximum value is
3.6V (DVdd+0.3)
VDD2
I
9
Digital VDD (3.3V) The minimum value is 3.0V (DVdd-0.3), the maximum value is
3.6V (DVdd+0.3)
Digital GND
VSS1
VSS2
I
I
4
7
Digital GND
TOTAL: 8 Pins
4.5. Crystal Selection
XTL-OUT Status
XTAL connected
ID1 Config
ID0 Config
Float
Input Clock Source
24.576MHz XTAL
Float
Float
XTAL connected or open
XTAL connected or open
XTAL connected or open
XTAL shorted to GND
XTAL shorted to GND
XTAL shorted to GND
XTAL shorted to GND
Pulldown
Float
12.2888MHz BIT-CLK
12.2888MHz BIT-CLK
12.2888MHz BIT-CLK
14.31818MHz Source
27MHz Source
Pulldown
Pulldown
Float
Pulldown
Float
Float
Pulldown
Float
Pulldown
Pulldown
48MHz Source
Pulldown
24.576MHz Source
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Single-Chip Dual-Channel AC’97 Audio Codec
EMP202
EMPIA Technology
5. Registers
Access to registers with an odd number will return a 0. Reading unimplemented registers will also return a 0.
REG.
NAME
D15
D14
D13 D12 D11 D10 D9
D8 D7 D6
D5
D4
ID4
MR4 MR3 MR2 MR1
D3
D2
D1
D0 DEFAULT
(HEX)
00h Reset
X
SE4
SE3
X
SE2
ML4
SE1 SE0 ID9
ID8
ID7
X
ID6
X
ID5
ID3
ID2
ID1
ID0
6A90h
02h Master Volume
Mute
Mute
Mute
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ML3 ML2 ML1 ML0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MR0 8000h
HEADPHONE
04H
X
HPL4 HPL3 HPL2 HPL1 HPL0
X
X
HPL4 HPL3 HPL2 HPL1 HPL0 8000h
MM4 MM3 MM2 MM1 MM0 8000h
0000h
PH0 8008h
MI0 8008h
Volume
06h Mono-Out Volume
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0Ah PC_BEEP Volume Mute
X
X
X
X
X
PB3
PH4
MI4
NR4
CR4
VR4
AR4
PR4
X
PB2 PB1
PH3 PH2
PB0
PH1
MI1
X
0Ch PHONE Volume
0Eh MIC Volume
10h Line-In Volume
12h CD Volume
Mute
Mute
Mute
Mute
Mute
Mute
Mute
X
X
X
X
X
X
X
X
X
X
MI3
MI2
20dB
X
X
NL4
CL4
VL4
AL4
PL4
X
NL3 NL2 NL1
CL3 CL2 CL1
VL3 VL2 VL1
AL3 AL2 AL1
PL3 PL2 PL1
NL0
CL0
VL0
AL0
PL0
X
NR3 NR2 NR1
CR3 CR2 CR1
NR0 8808h
CR0 8808h
VR0 8808h
AR0 8808h
PR0 8808h
X
X
X
X
X
X
X
X
X
X
X
X
X
14h Video Volume
16h Aux Volume
X
X
VR3 VR2
AR3 AR2
PR3 PR2
VR1
AR1
PR1
X
X
18h PCM Out Volume
1Ah Record Select
1Ch Record Gain
20h General Purpose
22h 3D Control
X
X
X
X
LRS2 LRS1 LRS0
X
X RRS2 RRS1 RRS0 0000h
RRG3 RRG2 RRG1 RRG0 8000h
Mute
POP
X
X
X
LRG3 LRG2 LRG1 LRG0 X
X
3D
X
X
X
X
X
X
MIX
X
MS
X
LBK
X
X
X
X
X
X
0000h
0000h
X
X
DP3 DP2
REF ANL
Power Down
26h
EAPD PR6
PR5
X
PR4
X
PR3 PR2 PR1 PR0
REV1 REV0 AMAP X
X
X
DAC
ADC 000Fh
VRA 0605h
VRA 0400h
Ctrl/Status
28h Extended Audio ID ID1
Extended Audio
ID0
X
DSA1 DSA0 SPDIF X
SPSA1 SPSA0 X SPDIF X
2Ah
2Ch
32h
X
X
X
X
X
SPCV X
X
X
Status
PCM Out Sample
Rate
PCM Input Sample
Rate
FSR
15
FSR1 FSR1 FSR1 FSR1
FSR1 4
FSR9 FSR8 FSR7 FSR6 FSR5 FSR4 FSR3 FSR2 FSR1 FSR0 BB80h
ISR 9 ISR 8 ISR 7 ISR 6 ISR 5 ISR 4 ISR 3 ISR 2 ISR 1 ISR 0 BB80h
3
2
1
0
ISR
11
ISR
10
ISR 15 ISR 14
ISR 13 ISR 12
3Ah S/PDIF Ctl
V
X
X
X
X
X
X
DRS
X
SPSR1 SPSR0 L
CC6 CC5 CC4 CC3 CC2 CC1
CC0
X
PRE COPY /AUDIO PRO 2000h
Ext’d Modem
3Eh
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
X
1
PRA
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
X
1
X
X
GPIO 0100h
GC0 0300h
GP0 FFFFh
GS0 0000h
GW0 0000h
Stat/Ctrl
4Ch GPIO Pin Config
X
X
X
GC1
GP1
GS1
GW1
GI1
DO1
X
GPIO Pin
4Eh
X
X
X
X
Polarity/Type
50h GPIO Pin Sticky
X
X
X
X
52h GPIO Mask
X
X
X
X
54h GPIO Pin Status
X
X
X
X
GI0
X
0000h
0000h
0000H
0800H
FFFFh
FFFFh
6Ah SPDIF Output Select X
72h Antipop
74h EAPD/GPIO Access EAPD
X
X
X
X
X
X
X
APOP X
X
X
X
EAPD
OEN
1
GPIO GPIO
X
X
X
1
1
X
1
1
X
INTDIS
ACC
1
SLT12
1
7Ch Vendor ID1
7Eh Vendor ID2
X: Reserved bit
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
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Single-Chip Dual-Channel AC’97 Audio Codec
EMP202
EMPIA Technology
5.1. Mixer Registers
5.1.1.MX00 Reset
Default: 6A90H
Writing any value to this register will start a register reset, and causes all of the registers to revert to
their default values. The written data is ignored. Reading this register returns the ID code of the
specific part.
Bit
Type
Function
15
-
Reserved
14:10
R
R
R
R
R
R
R
R
R
R
R
3D Code
9
8
7
6
5
4
3
2
1
0
Read as 0
5.1.2.MX02 Master Volume
Default: 8000H
These registers control the overall volume level of the output functions. Each step on the left and right
channels corresponds to 1.5dB in increase/decrease in volume.
Bit
Type
R/W
Function
15
Mute Control:
0: Normal
1: Mute (- ‡dB)
Reserved
14:13
12:8
7:5
-
R/W
-
Master Left Volume: (ML[4:0]) in 1.5 dB steps
Reserved
4:0
R/W
Master Right Volume: (MR[4:0]) in 1.5 dB steps
1) For MR/ML: 00h
1Fh
0 dB attenuation
46.5 dB attenuation
2) MR/ML are 5-bit R/W variables. The 6th bit implementation is optional. For this reason, when the 6th bit is
written with a 1, it is the equivalent to writing the low 5-bits with 1. For example, writing 1xxxxx will read back
01111.
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Single-Chip Dual-Channel AC’97 Audio Codec
EMP202
EMPIA Technology
5.1.3.MX04 Headphone Volume
Default: 8000H
These registers control the overall volume level of the output functions. Each step on the left and right
channels corresponds to 1.5dB in increase/decrease in volume.
Bit
Type
R/W
Function
15
Mute Control:
0: Normal
1: Mute (- ‡dB)
Reserved
14:13
12:8
7:5
-
R/W
-
Headphone Left Volume: (HPL[4:0]) in 1.5 dB steps
Reserved
4:0
R/W
Headphone Right Volume: (HPR[4:0]) in 1.5 dB steps
0 dB attenuation
1) For HPL/HPR:
00h
1Fh
46.5 dB attenuation
2 HPL/HPR are 5-bit R/W variables. The 6th bit implementation is optional. For this reason, when the 6th bit is
written with a 1, it is the equivalent to writing the low 5-bits with 1. For example, writing 1xxxxx will read
back 01111.
5.1.4.MX06 MONO_OUT Volume
Default: 8000H
Mono output is the same data sent on all output channels. Each step in bits 4:0 corresponds to 1.5dB
in increase/decrease in volume, allowing 32 levels of volume from 00000 to 11111.
Bit
Type
R/W
Function
15
Mute Control:
0: Normal
1: Mute (- ‡dB)
Reserved
14:5
4:0
-
R/W
00h
1Fh
Mono Master Volume: (MM[4:0]) in 1.5 dB steps
1) For MM:
0 dB attenuation
46.5 dB attenuation
2) Implements 5-bit volume control only. Writing 1xxxxx will be interpreted as x11111 and will respond, when read,
with x11111.
5.1.5.MX0A PC BEEP Volume
Default: 8000H
This register controls the input volume for the PC beep signal. Each step in bits 4:1 corresponds to a
3dB increase/decrease in volume. 16 levels of volume are available, from 0000 to 1111.
The purpose of this register is to allow the PC Beep signals to pass through the EMP202, eliminating
the need for an external system speaker/buzzer. The PC BEEP pin is directly routed (internally
hardwired) to the LINE-OUTL & R pins. If the PC speaker/buzzer is eliminated, it is recommended to
connect the external speakers at all times so the POST codes can be heard during reset.
Bit
Type
Function
15
R/W
Mute Control:
0: Normal
1: Mute (- ‡dB)
Reserved
14:5
-
4:1
R/W
-
PC Beep Volume: (PB[3:0]) in 3 dB steps
Reserved
0
1) For PB:
00h
0Fh
0 dB attenuation
45 dB attenuation
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Single-Chip Dual-Channel AC’97 Audio Codec
EMP202
EMPIA Technology
5.1.6.MX0C PHONE Volume
Default: 8008H
Register 0Ch controls the telephone input volume for software modem applications. Because
software modem applications may not have a speaker, the CODEC can offer a speaker-out service.
Each step in bits 4:0 corresponds to 1.5dB in increase/decrease in volume, allowing 32 levels of
volume, from 00000 to 11111.
Bit
Type
Function
15
R/W
Mute Control:
0: Normal
1: Mute (- ‡dB)
Reserved
14:5
4:0
-
R/W
Phone Volume: (PV[4:0]) in 1.5 dB steps
1) For PV:
00h
+12 dB Gain
0dB gain
08h
1Fh
-34.5dB Gain
5.1.7.MX0E MIC Volume
Default: 8008H
Register 0Eh controls the microphone input volume. Each step in bits 4:0 corresponds to 1.5dB in
increase/decrease in volume, allowing 32 levels of volume, from 00000 to 11111. Each step in bit 6
corresponds to a magnification of 20dB increase in volume.
Bit
Type
Function
15
R/W
Mute Control:
0: Normal
1: Mute (- ‡dB)
Reserved
14:7
6
-
R/W
Mic Boost
0 0dB
1 20dB
5
-
Reserved
4:0
R/W
Mic Volume: (MV[4:0]) in 1.5 dB steps
+12 dB Gain
0dB gain
1) For MV:
00h
08h
1Fh
-34.5dB Gain
5.1.8.MX10 LINE_IN Volume
Default: 8808H
Each step in bits 0..4 correspond to 1.5dB in increase/decrease in volume for the right channel,
allowing 32 levels of volume, from 00000 to 11111. Each step in bits 12:8 correspond to 1.5dB in
increase/decrease in volume for the left channel, allowing 32 levels of volume, from 00000 to 11111.
Bit
Type
Function
15
R/W
Mute Control:
0: Normal
1: Mute (- ‡dB)
Reserved
14:13
12:8
7:5
-
R/W
-
Line-In Left Volume: (NL[4:0]) in 1.5 dB steps
Reserved
4:0
R/W
Line-In Right Volume: (NR[4:0]) in 1.5 dB steps
1) For NL/NR: 00h
+12 dB Gain
0dB gain
08h
1Fh
-34.5dB Gain
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EMPIA Technology
5.1.9.MX12 CD Volume
Default: 8808H
Each step in bits 44:0 correspond to 1.5dB in increase/decrease in volume for the right channel,
allowing 32 levels of volume, from 00000 to 11111. Each step in bits 12:8 correspond to 1.5dB in
increase/decrease in volume for the left channel, allowing 32 levels of volume, from 00000 to 11111.
Bit
Type
Function
15
R/W
Mute Control:
0: Normal
1: Mute (- ‡dB)
Reserved
14:13
12:8
7:5
-
R/W
-
CD Left Volume: (CL[4:0]) in 1.5 dB steps
Reserved
4:0
R/W
CD Right Volume: (CR[4:0]) in 1.5 dB steps
1) For CL/CR: 00h
+12 dB Gain
0dB gain
08h
1Fh
-34.5dB Gain
5.1.10. MX14 VIDEO Volume
Default: 8808H
Each step in bits 4:0 correspond to 1.5dB in increase/decrease in volume for the right channel,
allowing 32 levels of volume, from 00000 to 11111. Each step in bits 12:8 correspond to 1.5dB in
increase/decrease in volume for the left channel, allowing 32 levels of volume, from 00000 to 11111.
Bit
Type
Function
15
R/W
Mute Control:
0: Normal
1: Mute (- ‡dB)
Reserved
14:13
12:8
7:5
-
R/W
-
Video Left Volume: (VL[4:0]) in 1.5 dB steps
Reserved
4:0
R/W
Video Right Volume: (VR[4:0]) in 1.5 dB steps
1) For VL/VR: 00h
+12 dB Gain
0dB gain
08h
1Fh
-34.5dB Gain
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EMPIA Technology
5.1.11. MX16 AUX Volume
Default: 8808H
Each step in bits 4:0 correspond to 1.5dB in increase/decrease in volume for the right channel,
allowing 32 levels of volume, from 00000 to 11111. Each step in bits 12:8 correspond to 1.5dB in
increase/decrease in volume for the left channel, allowing 32 levels of volume, from 00000 to 11111.
Bit
Type
Function
15
R/W
Mute Control:
0: Normal
1: Mute (- ‡dB)
Reserved
14:13
12:8
7:5
-
R/W
-
AUX Left Volume: (AL[4:0]) in 1.5 dB steps
Reserved
4:0
R/W
AUX Right Volume: (AR[4:0]) in 1.5 dB steps
1) For AL/AR: 00h
+12 dB Gain
0dB gain
08h
1Fh
-34.5dB Gain
5.1.12. MX18 PCM_OUT Volume
Default: 8808H
Each step in bits 4:0 correspond to 1.5dB in increase/decrease in volume for the right channel,
allowing 32 levels of volume, from 00000 to 11111. Each step in bits 12:8 correspond to 1.5dB in
increase/decrease in volume for the left channel, allowing 32 levels of volume, from 00000 to 11111.
Bit
Type
Function
15
R/W
Mute Control:
0: Normal
1: Mute (- ‡dB)
Reserved
14:13
12:8
7:5
-
R/W
-
PCM Left Volume: (PL[4:0]) in 1.5 dB steps
Reserved
4:0
R/W
PCM Right Volume: (PR[4:0]) in 1.5 dB steps
1) For PL/PR: 00h
+12 dB Gain
0dB gain
08h
1Fh
-34.5dB Gain
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EMPIA Technology
5.1.13. MX1A Record Select
Default: 0000H
Each step in bits 2:0 correspond to 1.5dB in increase/decrease in volume for the right channel,
allowing 7 levels of volume, from 000 to 111. Each step in bits 10:8 correspond to 1.5dB in
increase/decrease in volume for the left channel, allowing 7 levels of volume, from 000 to 111.
Bit
15:11
10:8
Type
Function
-
Reserved
R/W
-
Left Record Source Select: (LRS[2:0])
Reserved
7:3
2:0
R/W
Right Record Source Select: (RRS[2:0])
1) For LRS:
0 MIC
1 CD LEFT
2 VIDEO LEFT
3 AUX LEFT
4 LINE LEFT
5 STEREO MIXER OUTPUT LEFT
6 MONO MIXER OUTPUT
7 PHONE
2) For RRS:
0 MIC
1 CD RIGHT
2 VIDEO RIGHT
3 AUX RIGHT
4 LINE RIGHT
5 STEREO MIXER OUTPUT RIGHT
6 MONO MIXER OUTPUT
7 PHONE
5.1.14. MX1C Record Gain
Default: 8000H
Each step in bits 3:0 correspond to 1.5dB in increase/decrease in gain for the right channel, allowing
16 levels of gain, from 0000 to 1111. Each step in bits 11:8 correspond to 1.5dB in increase/decrease
in gain for the left channel, allowing 16 levels of gain, from 0000 to 1111.
Bit
Type
Function
15
R/W
Mute Control:
0: Normal
1: Mute (- ‡dB)
Reserved
14:12
11:8
7:4
-
R/W
-
Left Record Gain Select: (LRG[3:0]) in 1.5 dB steps
Reserved
3:0
R/W
Right Record Gain Select: (RRG[3:0]) in 1.5 dB steps
1) For LRG/RRG:
0Fh
00h
+22.5dB
0 dB (No Gain)
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EMPIA Technology
5.1.15. MX20 General Purpose Register
Default: 0000H
Bit
Type
Function
15:14
-
Reserved, read as 0
13
R/W
3D Control: Used to enable or disable 3D effects.
1: On
0: Off
12:10
9
-
Reserved, Read as 0
Mono Output Select:
0: MIX
R/W
1: MIC
8
R/W
R/W
-
Mic Select:
0: Mic 1
1: Mic 2
7
AD to DA Loop-back Control: Used to enable or disable ADC to front DAC loop-back.
0: Disable
1: Enable
Reserved
6:0
5.1.16. MX22 3D Control
Default: 0000H
Type
Bit
Function
15:4
3:2
-
Reserved, read as 0
LINE_OUT Separation Ration
00 0(off)
R/W
01 3(low)
10 4.3(med)
11 6(high)
1:0
-
Reserved, read as 0
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EMPIA Technology
5.1.17. MX26 Powerdown Control/Status
Default: 0000H
This read/write register is used to program powerdown states and monitor subsystem readiness. The
lower half of this register is read only status; a “1” indicating that the subsection is “ready.” Ready is
defined as the subsection’s ability to perform in its nominal state. When this register is written, the bit
values that come in on AC-Link will have no effect on read only bits 0-7 and bit 15.
When the AC-Link “CODEC Ready” indicator bit (SDATA_IN slot 0, bit 15) is a 1, it indicates that the
AC-Link and AC’97 control and status registers are in a fully operational state. The AC’97 controller
must further probe this powerdown control/status register to determine exactly which subsections, if
any are ready.
Bit
15
Type
Function
R/W
PR7 External Amplifier Power Down: (EAPD).
0: EAPD output low (enable external amplifier).
1: EAPD output high (shut down external amplifier)
14
13
12
11
10
9
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PR6:
0: Normal
1: Power down Headphone
PR5:
0: Normal.
1: Disable internal clock usage (BITCLK still be output for modem CODEC)
PR4:
0: Normal
1: Power down AC-Link
R3:
0: Normal
1: Power down Mixer (VREF off)
PR2:
0: Normal
1: Power down Mixer (VREF on)
PR1:
0: Normal
1: Power down PCM DAC
PR0:
8
0: Normal
1: Power down PCM ADC and input MUX
Reserved, read as 0
VREF Status:
1: VREF normal level
0: Not yet
7:4
3
-
R
2
1
0
R
R
R
Analog Mixer Status:
1: Ready
0: Not yet
DAC Status:
1: Ready
0: Not yet
ADC Status:
1: Ready
0: Not yet
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5.1.18. MX28 Extended Audio ID
Default: 0607H
Type
Bit
Function
15:14
R
ID[1:0]: 00=XTAL Out grounded
ID13, ID0#=XTAL OUT crystal or floating
Reserved, read as 0
13:12
11:10
9
-
R
REV[1:0]=01 to indicates EMP202 is AC’97 rev2.2 compliant.
AMAP: Read as 1 (DAC mapping base on CODEC ID)
Reserved, read as 0
R
8:6
NA
R/W
5:4
DSA{1:0], DAC Slot Assignment
ID[1:0]=00 – DSA[1:0] reset =00 where left slot 3, right slot 4
ID[1:0]=01 – DSA[1:0] reset =01 where left slot 7, right slot 8
ID[1:0]=10 – DSA[1:0] reset =01 where left slot 6, right slot 9
ID[1:0]=11 – DSA[1:0] reset =10 where left slot 10, right slot 11
Reserved, read as 0
3
2
1
0
-
R
R
R
SPDIF: Read as 1 (S/PDIF is supported)
DRA: Read as 1 (Double Rate Audio is supported)
VRA: Read as 1 (Variable Rate Audio is supported)
5.1.19. MX2A Extended Audio Status and Control
Default: 01F0H
This register contains two active bits for powerdown and status of the surrounding DACs. Bits 0, 1 & 2
are read/write bits which are used to enable or disable VRA, DRA and SPDIF respectively. Bits 4 & 5
are read/write bits used to determine the AC-LINK slot assignment of the S/PDIF. Bit 10 is a read only
bit which tells the controller if the S/PDIF configuration is valid.
Bit
15:11
10
Type
NA
R
Function
Reserved
SPCV: (S/PDIF Configuration Valid).
0: Current S/PDIF configuration {SPSA,SPSR,DAC/slot rate} is not valid.
1: Current S/PDIF configuration {SPSA,SPSR,DAC/slot rate} is valid
9:6
5:4
NA
Reserved
R/W
SPSA[1:0]: (S/PDIF Slot Assignment).
00: S/PDIF source data assigned to AC-LINK slot3/4.
01: S/PDIF source data assigned to AC-LINK slot7/8.
10: S/PDIF source data assigned to AC-LINK slot6/9.
11: S/PDIF source data assigned to AC-LINK slot10/11 (default).
3
2
-
Reserved
R/W
SPDIF Enable:
1: Enable
0: Disable (Hi-Z)
Reserved
1
0
-
R/W
VRA Enable:
1: Enable
0: Disable
1) If VRA = 0, the EMP202 AD/DA operates at a fixed 48KHz sampling rate. Otherwise, it operates with variable
sampling rates as defined in MX2C and MX32.
2.) If pin 48 is held high at power up, SPDIF is not available and D15:D1 cannot be written and will read back 0.
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EMPIA Technology
5.1.20. MX2C PCM Output Sample Rate
Default: BB80H
Bit
15:0
Type
Function
R/W
FOSR[15:0]: Output sampling rate
1) The EMP202 supports the following sampling rates as required in the PC99/PC2001 design guide.
Sampling rate
8000
FOSR[15:0]
1F40h
11025
2B11h
12000
2EE0h
3E80h
16000
22050
5622h
24000
5DC0h
7D00h
AC44h
BB80h
32000
44100
48000
If the value written is not supported, the closest value is returned.
5.1.21. MX32 PCM Input Sample Rate
Default: BB80H
Type
Bit
15:0
Function
R/W
ISR[15:0]: Output sampling rate
1) The EMP202 supports the following sampling rates as required in the PC99/PC2001 design guide.
Sampling rate
8000
1F40h
2B11h
2EE0h
3E80h
5622h
11025
12000
16000
22050
24000
5DC0h
7D00h
AC44h
BB80h
32000
44100
48000
If the value written is not supported, the closest value is returned.
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5.1.22. MX3A S/PDIF Output Channel Status and Control
Default: 2000H
Bit
Type
Function
15
14
R/W
Validity Control: (control V bit in Sub-Frame).
0: The V bit (valid flag) in sub-frame depends on whether or not the S/PDIF data is
under-run.
1: The V bit in sub-frame is always sent as 1 to indicate the invalid data is not suitable
for the receiver.
Double Rate S/PDIF: (DRS) This bit is always 0.
S/PDIF Sample Rate: (SPSR[1:0]).
00: Sample rate set to 44.1KHz, Fs[0:3]=0000.
01: Reserved.
R
13:12
R/W
10: Sample rate set to 48.0KHz, Fs[0:3]=0100 (default).
11: Sample rate set to 32.0KHz, Fs[0:3]=1100.
Generation Level: (LEVEL)
11
10:4
3
R/W
R/W
R/W
Category Code: (CC[6:0])
Preemphasis: (PRE).
0: None
1: Filter preemphasis is 50/15 µsec
Copyright: (COPY).
2
1
0
R/W
R/W
R
0: Asserted
1: Not asserted
Non-Audio Data Type: (/AUDIO).
0: PCM data
1: AC3 or other digital non-audio data.
Professional or Consumer Format: (PRO).
0: Consumer format
1: Professional format.
1) To ensure the control and status information started up correctly at the beginning of S/PDIF transmission,
MX3A.[14:0] should only be written to when S/PDIF transmitter is disabled (MX2A.2=0).
2) If validity control is set (MX3A.15=1), those data bits (bit 8 ~ bit 27) should be forced to 0 to obtain better
compatibility with mini disc devices.
5.2. GPIO Registers
5.2.1.MX3E Extended Modem Status and Control
Default: 0100H
Bit
Type
Function
15:9
-
Reserved
8
R/W
PRA
0 GPIO powered up/enabled
1 GPIO powered down/disabled
Reserved
7:1
0
R
R
GPIO
0 GPIO not ready (powered down)
1 GPIO Ready (powered up)
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5.2.2.MX4C GPIO Pin Configuration
Default: 0003H
Type
Bit
Function
Function
Function
Function
15:2
-
Reserved
1
R/W
GC1
0 GPIO1 configured as output
1 GPIO1 configured as input
GC0
0
R/W
0 GPIO0 configured as output
1 GPIO0 configured as input
5.2.3.MX4E GPIO Pin Polarity/Type
Default: FFFFH
Type
Bit
15:2
1
-
Reserved
R/W
GP1
0 GPIO1 polarity inverted
1 GPIO1 polarity inverted
GP0
0
R/W
0 GPIO0 polarity inverted
1 GPIO0 polarity inverted
5.2.4.MX50 GPIO Pin Sticky
Default: 0000H
Type
Bit
15:2
1
-
Reserved
R/W
GS1
0 GPIO1 non sticky
1 GPIO1 sticky
GS0
0
R/W
0 GPIO1 non sticky
1 GPIO1 sticky
5.2.5.MX50 GPIO Pin Status
Default: 0000H
Type
Bit
15:2
1:0
-
Reserved
R/W
GI1 (GPIO1/0)
As output, use with MX74:D0 to set
If D0=0, the respective register value placed on pad (D1 for GPIO1, D0 for
GPIO0)
If D0=1, pad get value from slot 12
As input and sticky
0 clears this bit
1 does nothing
As input and non sticky
This register gives GPIO1 value from pad.
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EMPIA Technology
5.3. Extended Registers
5.3.1.MX6A SPDIF Output Select
Default: 0000H
Type
Bit
Function
Function
Function
15:2
-
Reserved
1
R/W
SPDIF Output Source Select
0 PCM data from ACLINK to SPDIF
1 ADC record data to SPDIF
Reserved
0
-
5.3.2.MX72 Antipop
Default: 0000H
Type
Bit
15:8
7
-
Reserved
R/W
Internal Antipop
0 enabled
1 disabled
Reserved
6:0
-
5.3.3.MX74 EAPD Access
Default: 0800H
Type
Bit
15
R/W
EAPD, Use with D11
If D11=1, EAPD data output
If D11=0, EAPD data input
Reserved
14:12
11
-
R/W
EAPD Pin Enable
0 EAPD as input
1 EAPD as output
10:3
2
-
Reserved
R/W
Interrupt Disable
0 clear GPIO interrupts
1 clear GPIO interrupts with MX54
GPIO Access
1
0
R/W
R/W
0 ACLINK access from GPIO pad
1 ACLINK access from MX54
GPIOSLT12
0 GPIO0 and GPIO1 access from MX54, if GPIO is set as output, input Slot 12
will be 0h.
1 GPIO0 and GPIO1 access from Slot 12, if GPIO is set as output, input MX54
not updated.
5.3.4.MX7C VENDOR ID1
Default: FFFFH
Type
Bit
Function
15:0
R
Vendor ID: FFFFH
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EMPIA Technology
5.3.5.MX7E VENDOR ID2
Default: FFFFH
Bit
15:0
Type
Function
R
Vendor ID: FFFFH
6. Electrical Characteristics
6.1. DC Characteristics
Dvdd= 3.3V ±5%, Tambient=25 0 C, with 50pF external load.-
Parameter
Symbol
Min
Typical
Max
Units
Input voltage range
Vin
-0.30
-
DVdd+0.30
V
V
Low level input voltage
SYNC,SDATA_OUT,RESET#
XTAL_IN,BIT_CLK ID1#,ID0#
High level input voltage
SYNC,SDATA_OUT,RESET#
XTAL_IN,BIT_CLK ID1#,ID0#
High level output voltage
Low level output voltage
Pull up resistance
VIL
-
1.2 / 0.7
0.30*DVdd
-
1.7 / 1.0
-
-
2.0 / 1.2
-
VIH
0.40*DVdd
2.1 / 1.7
-
V
-
3.2 / 2.2
-
-
2.5 / 1.7
-
VOH
VOL
0.90DVdd
-
-
0.1DVdd
200K
10
V
V
-
-
50K
-10
-10
-
100K
ꢀ
Input leakage current
-
-
-
-
-
uA
uA
mA
Output leakage current (Hi-Z)
Output buffer drive current
10
5
-
6.2. AC Timing Characteristics
6.2.1.Cold Reset
Parameter
Symbol
Trst_low
Trst2clk
Min
1.0
Typical
Max
Units
us
RESET# active low pulse width
RESET# inactive to BIT_CLK Startup
delay
-
-
-
-
162.8
ns
Trst2clk
Tres_low
RESET#
Ttri2actv
Ttri2actv
BIT_CLK
SDATA_IN
Cold reset timing diagram
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EMPIA Technology
6.2.2.Warm Reset
Tsync_high
Tsync_2clk
SYNC
BIT_CLK
Warm reset timing diagram
Parameter
Symbol
Tsync_high
Tsync2clk
Min
1.0
Typical
Max
Units
us
SYNC active high pulse width
SYNC inactive to BIT_CLK Startup
delay
1.3
-
-
-
162.8
ns
6.2.3.AC-Link Clocks
Tsync_high
Tsync_2clk
SYNC
BIT_CLK
BIT_CLK and SYNC timing diagram
Parameter
Symbol
Min
Typical
12.288
81.4
750
Max
Units
MHz
ns
BIT_CLK frequency
BIT_CLK period
-
-
-
Tclk_period
-
750
45
45
-
BIT_CLK output jitter
BIT_CLK high pulse width (note 1)
BIT_CLK low pulse width (note 1)
SYNC frequency
-
ps
Tclk_high
Tclk_low
36
36
-
40.7
40.7
48.0
20.8
1.3
ns
ns
KHz
us
SYNC period
Tsync_period
Tsync_high
Tsync_low
-
-
SYNC high pulse width
SYNC low pulse width
-
-
us
-
19.5
-
us
Note 1: Worse case duty cycle restricted to 45/55.
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EMPIA Technology
6.2.4.Data Output and Input Times
tco
Tsetup
BIT_CLK
Vih
Vil
SDATA_OUT
SDATA_IN
SYNC
Voh
Vol
Thold
Data Output and Input timing diagram
Parameter
Symbol
tco
Min
-
Typical
Max
Units
ns
Output Valid Delay from rising edge of BIT_CLK
Input Setup to falling edge of BIT_CLK
Input Hold from falling edge of BIT_CLK
-
-
-
15
-
tsetup
thold
10
10
ns
-
ns
Note 1: Timing is for SDATA and SYNC outputs with respect to BIT_CLK at the Device driving the output.
Note 2: 50pF external load
Note 3: Timing is for SDATA and SYNC outputs with respect to BIT_CLK at the device driving the output.
6.2.5.Signal Rise and Fall Times
BIT_CLK
Triseclk
Tfallclk
Tfalldin
SDATA_IN
Trisedin
Signal Rise and Fall timing diagram
Parameter
Symbol
Triseclk
Tfallclk
Min
Typical
Max Units
BIT_CLK rise time
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
6
6
6
6
6
6
6
6
ns
ns
ns
ns
ns
ns
ns
ns
BIT_CLK fall time
SYNC rise time
Trisesync
Tfallsync
Trisedin
Tfalldin
SYNC fall time
SDATA_IN rise time
SDATA_IN fall time
SDATA_OUT rise time
SDATA_OUT fall time
Trisedout
Tfalldout
Note 1: 75pF external load
Note 2: rise is from 10% to 90% of Vdd (Vol to Voh)
Note 3: fall is from 90% to 10% of Vdd (Voh to Vol)
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6.2.6.AC-Link Low Power Mode Timing
Slot 1
Slot 2
SYNC
BIT_CLK
Write to
0x20
Don't care
Ts2_pdown
Data PR4
SDATA_OUT
SDATA_IN
Note: BIT_CLK not to scale
AC-Link low power mode timing diagram
Parameter
Symbol
Min
Typical
Max
1.0
Units
End of slot 2 to BIT_CLK, SDATA_IN low
Ts2_pdown
-
-
us
6.2.7.ATE Test Mode
RESET#
SDATA_OUT
Tsetup2rst
Hi-Z
SDATA_IN, BIT_CLK
Toff
ATE test mode timing diagram
To meet AC’97 rev2.2 requirements, EAPD, SPDIFO, BIT_CLK and SDATA_IN should be floating in
test mode.
Parameter
Symbol
Min Typical
Max
Units
Setup to trailing edge of RESET# (also applies to
SYNC)
Tsetup2rst
15.0
-
-
ns
Rising edge of RESET# to Hi-Z delay
Toff
-
-
25.0
ns
6.2.8.AC-Link IO Pin Capacitance and Loading
Output Pin
1 CODEC
47.5pF
2 CODEC
62.5pF
55pF
3 CODEC
4 CODEC
85pF
BIT_CLK (must support ≥ 2 CODECs)
SDATA_IN
75pF
60pF
47.5pF
62.5pF
6.2.9.BIT-CLK and SDATA-IN State
When RESET# is active, BIT-CLK and SDATA-IN must be floating by internal pull low 100K resistors.
The ac-link signals are driven by another AC’97 on CNR board. This requirement is not mentioned in
AC’97 specifications Rev 2.1. Please refer to CNR (Communication Network Riser) specifications
Rev. 1.0 pages 23~25 or AC’97 Rev. 2.2 for detailed information.
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Single-Chip Dual-Channel AC’97 Audio Codec
EMP202
EMPIA Technology
7. Analog Performance Characteristics
Standard test condition:
Tambient=25 0 C, Dvdd=5.0 or 3.3V ±5%,Avdd=5.0V ±5%
Input Voltage Level: Logic Low=0.35*Vdd, Logic High=0.65Vdd
1KHz input sine wave; Sampling frequency=48KHz; 0dB=1Vrms
10K §Ù/50pF load; Testbench Characterization BW:20Hz~20KHz
0dB attenuation; tone and 3D disabled
Parameter
Min
Typical
Max
Units
Full scale input voltage
Mixer (except for MIC)
-
-
-
-
-
1.6
1.6
-
-
-
-
Vrms
Vrms
Vrms
Vrms
Mic input (gain=0dB)
Mic input (gain=20dB)
ADC
0.16
1.0
Full scale output voltage
DAC
1.0
95
92
85
88
1.41
Vrms
S/N (A weighted)
-
-
-
-
-
-
-
-
dB FSA
dB FSA
dB FSA
dB FSA
dB FS
CD to LINE_OUT
Other to LINE_OUT
ADC DAC
Total Harmonic Distortion + Noise
ADC
-
-
-80
-80
-
-
dB FS
DAC
Frequency Response
Mixers
Hz
20
20
-
-
20,000
ADC & DAC
-
19,200
Power Supply Rejection (DAC,ADC)
Total Out-of-Band Noise (28.8K~100KHz)
Mic 20dB gain is selected
Crosstalk between inputs channels
Attenuation, Gain Step Size
Input impedance (gain=0dB)
PC_BEEP only
-68
-63
20
-
-
-
dB
dB
dB
dB
dB
Kꢀ
-
18
-
22
-70
-
-
1.5
-
-
-
32
32
16
-
-
-
Others (PHONE,LINE,CD,AUX,VIDEO)
MIC1 and MIC2
Power Supply Current (normal operation)
VA=5v
mA
mA
-
-
50
20
-
-
VD=3.3v
Power Supply Current (power down mode)
VA=5v
-
-
1
2
mA
mA
VD=3.3v
VREFOUT
2.25
2.50
2.75
V
Digital Filter Characteristics
ADC Low pass Filter
Pass band
0
-
-
19.2
KHz
KHz
dB
Stop band
28.8
-
-
-
Stop band Rejection
Pass band Frequency Response
DAC Low pass Filter
Pass band
-
-
-76.0
+- 0.15
dB
0
-
-
19.2
KHz
KHz
dB
Stop band
28.8
-
-
-
Stop band Rejection
Pass band Frequency Response
-
-
-78.5
+- 0.15
dB
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Single-Chip Dual-Channel AC’97 Audio Codec
EMP202
EMPIA Technology
8. Design Suggestions
8.1. Clocking
The clock source for different configurations is listed below.
CODEC ID[1:0]
BIT-CLK
Clock source
00
Output
Crystal or external clock (XTAL-IN) BITCLK is output
BIT CLK always an input, XTAL-IN (pin 2) ignored
01,10,11
BIT CLK
8.2. AC-Link
When the EMP202 takes serial data from the AC’97 controller, it samples SDATA_OUT on the falling
edge of BIT_CLK. When the EMP202 sends serial data to the AC’97 controller, it starts to drive
SDATA_IN on the rising edge of BIT_CLK.
The EMP202 will return any uninstalled bits or registers with 0 for read operations. The EMP202 also
stuffs the unimplemented slot or bit with 0 in SDATA-IN. Note that AC-LINK is MSB-justified.
Please refer to “Audio CODEC ’97 Component Specification Revision 2.2” for details
SYNC
CMD
ADR
CMD
PCM
LEFT
PCM
RT
PCM
CTR
PCM
PCM
PCM
LFE
PCM
LALT
PCM
TAG
NA
RSVD
RSVD
RSURR
DATA
LSURR
RALT
OUTGOING STREAMS
INCOMING STREAMS
TAG PHASE
STATUS STATUS
ADR DATA
PCM
LEFT
PCM
RT
TAG
NA
NA
RSVD
RSVD
RSVD
RSVD
RSVD
DATA PHASE
5.1 Channel Slot Arrangement Defined in AC’97 Specification rev2.2
8.3. Reset
There are 3 types of reset operations: Cold, Warm and Register reset, which are listed below:
Reset Type
Cold
Trigger condition
CODEC response
Assert RESET# for a specified period
Reset all hardware logic and all registers to their
default value.
Warm
Driven SYNC high for specified period
without BIT_CLK
Reactivates AC-LINK, no change to register
values.
Register
Write register indexed 00h
Reset all registers to their default value.
The AC’97 controller should drive SYNC and SDATA-OUT low during the period of RESET#
assertion to guarantee that the EMP202 resets successfully.
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Single-Chip Dual-Channel AC’97 Audio Codec
EMP202
EMPIA Technology
8.4. CD Input
Pay attention to differential CD input. Below is an example of differential CD input.
Example of differential CD input
8.5. Odd Addressed Register Access
The EMP202 will return “0000h” when odd-addressed registers and unimplemented registers are
read.
8.6. Power-down Mode
PR0=1
PR1=1
PR2=1
PR4=1
Analog off
Digital I/F off
PR4
Shut off
AC-Link
Normal
ADCs off PR0
DACs off PR1
PR2 or PR3
PR0=0 & ADC=1 PR1=0 & DAC=1 PR2=0 & ANL=1
Warm Reset
Default
Ready =1
Cold Reset
Example of the EMP202 power-down/power-up flow
8.7. Test Mode
8.7.1.ATE In Circuit Test Mode
SDATA_OUT is sampled high at the trailing edge of RESET#. In this mode, the EMP202 will drive
BIT_CLK, SDATA_IN, EAPD, GPIOs, IDs, and SPDIFO to high impedance.
8.7.2.Vendor Specific Test Mode
All other modes are reserved.
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Single-Chip Dual-Channel AC’97 Audio Codec
EMP202
EMPIA Technology
9. Package Dimensions
SYMBOL
MIN.
MILLIMETER
TYPICAL
MAX.
1.60
0.15
1.45
0.20
A
A1
A2
c
0.05
1.35
0.09
1.40
D
9.00 BSC
7.00 BSC
5.50
D1
D2
E
9.00 BSC
7.00BSC
5.50
E1
E2
b
0.17
0.20
0.27
e
0.50 BSC
3.5º
TH
L
0º
7º
0.45
0.60
0.75
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