FM24C256LN [ETC]
I2C Serial EEPROM ; I2C串行EEPROM\n
| 型号： | FM24C256LN |
| 厂家： | 
ETC |
| 描述： | I2C Serial EEPROM
|
| 文件： | 总13页 (文件大小：98K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 2001
FM24C256 – 256K-Bit Standard 2-Wire Bus
Interface Serial EEPROM
General Description
Features
FM24C256 is a 256Kbit CMOS non-volatile serial EEPROM
organized as 32K x 8 bit memory. This device confirms to
ExtendedIIC2-wireprotocolthatallowsaccessingofmemoryin
excessof16KbitonanIICbus.Thisserialcommunicationprotocol
usesaClocksignal(SCL)andaDatasignal(SDA)tosynchro-
nouslyclockdatabetweenamaster(e.g.amicrocontroller)anda
slave(EEPROM).FM24C256isdesignedtominimizepincount
andsimplifyPCboardlayoutrequirements.
I Extendedoperatingvoltage:2.7Vto5.5V
I Upto400KHzclockfrequencyat2.7Vto5.5V
I Lowpowerconsumption
—0.5mAactivecurrenttypical
—10µAstandbycurrenttypical
—1µAstandbycurrenttypical(Lversion)
—0.1µAstandbycurrenttypical(LZversion)
I Schmitttriggerinputs
FM24C256offershardwarewriteprotectionwherebytheentire
memoryarraycanbewriteprotectedbyconnectingWPpintoV
I 64bytepagewritemode
.
CC
I Selftimedwritecycle(6msmax)
I HardwareWriteProtectionfortheentirearray
I Endurance:upto100Kdatachanges
I DataRetention:Greaterthan40years
I Packages:8-PinDIPand8-PinSO
TheentirememorythenbecomesunalterableuntiltheWPpinis
switchedtoV
.
SS
“LZ”and“L”versionsofFM24C256offerverylowstandbycurrent
makingthemsuitableforlowpowerapplications.Thisdeviceis
offeredinSOandDIPpackages.
Fairchild EEPROMs are designed and tested for applications
requiringhighendurance,highreliabilityandlowpowerconsump-
tion.
I Temperaturerange
—Commercial:0 °Cto+70°C
—Industrial(E):-40 °Cto+85°C
—Automotive(V):-40 °Cto+125°C
Block Diagram
V
SS
WRITE
LOCKOUT
V
CC
H.V. GENERATION
TIMING &CONTROL
WP
START
STOP
SDA
LOGIC
CONTROL
LOGIC
SLAVE ADDRESS
REGISTER &
COMPARATOR
2
E
PROM
ARRAY
XDEC
SCL
A2
A1
A0
WORD
ADDRESS
COUNTER
R/W
YDEC
CK
D
OUT
DATA REGISTER
D
IN
1
©2001FairchildSemiconductorCorporation
FM24C256 Rev. D.1
www.fairchildsemi.com
Connection Diagram
Dual-in-Line Package (N) and SO Package (M8)
A0
A1
1
2
3
4
8
7
6
5
VCC
WP
FM24C256
A2
SCL
SDA
VSS
See Package Number N08E and M08A
Pin Names
VSS
Ground
SerialDataI/O
SDA
SCL
SerialClockInput
WriteProtect
WP
VCC
PowerSupply
A0, A1, A2
DeviceAddressInputs
2
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FM24C256 Rev. D.1
Ordering Information
FM 24 XX
C
F
LZ
E
YY
X
Letter Description
Blank
X
Tube
Tape and Reel
Package
Temp. Range
N
M8
8-pinDIP
8-pinSOIC
Blank
E
V
0 to 70 °C
-40 to +85°C
-40 to +125°C
Voltage Operating Range
Blank
L
4.5V to 5.5V
2.7V to 5.5V
LZ
2.7V to 5.5V and
<1µAStandbyCurrent
SCL Clock Frequency
Density
Blank
F
100KHz
400KHz
256
C
256Kwithwriteprotect
CMOS
Interface
24
IIC - 2 Wire
FM
Fairchild Non-Volatile
Memory
3
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FM24C256 Rev. D.1
Product Specifications
Operating Conditions
Absolute Maximum Ratings
AmbientOperatingTemperature
FM24C256
AmbientStorageTemperature
–65°C to +150°C
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
AllInputorOutputVoltages
withRespecttoGround
FM24C256E
FM24C256V
6.5V to –0.3V
LeadTemperature
PositivePowerSupply
FM24C256
(Soldering,10seconds)
+300°C
4.5V to 5.5V
2.7V to 5.5V
2.7V to 5.5V
FM24C256L
FM24C256LZ
ESDRating
2000Vmin.
Standard VCC (4.5V to 5.5V) DC Electrical Characteristics
Symbol
Parameter
Test Conditions
Limits
Typ
Units
Min
Max
(Note 1)
ICCA
ActivePowerSupplyCurrent
fSCL = 400 KHz
fSCL = 100 KHz
0.5
1.0
mA
ISB
ILI
StandbyCurrent
VIN = GND or VCC
VIN = GND to VCC
VOUT = GND to VCC
10
0.1
0.1
50
µA
µA
µA
V
InputLeakageCurrent
OutputLeakageCurrent
InputLowVoltage
1
1
ILO
VIL
VIH
VOL
–0.3
VCC x 0.3
VCC + 0.5
0.4
InputHighVoltage
OutputLowVoltage
VCC x 0.7
V
IOL = 2.1 mA
V
Low VCC (2.7V to 5 .5V) DC Electrical Characteristics
Symbol
Parameter
Test Conditions
Limits
Units
Min
Typ
Max
(Note 1)
ICCA
ActivePowerSupplyCurrent
StandbyCurrent
fSCL = 400 KHz
fSCL = 100 KHz
0.5
1.0
mA
ISB
(Note 3)
VIN = GND VCC = 2.7V - 4.5V (L)
1
0.1
10
10
1
50
µA
µA
µA
or VCC
VCC = 2.7V - 4.5V (LZ)
VCC = 4.5V - 5.5V
ILI
ILO
InputLeakageCurrent
OutputLeakageCurrent
InputLowVoltage
VIN = GND to VCC
VOUT = GND to VCC
0.1
0.1
1
1
µA
µA
V
VIL
VIH
VOL
–0.3
VCC x 0.3
VCC + 0.5
0.4
InputHighVoltage
VCC x 0.7
V
OutputLowVoltage
IOL = 2.1 mA
V
Capacitance TA = +25°C, f = 100/400 KHz, VCC = 5V (Note 2)
Symbol
CI/O
Test
Conditions
VI/O = 0V
Max Units
Input/OutputCapacitance(SDA)
InputCapacitance(A0,A1,A2,SCL)
8
6
pF
pF
CIN
VIN = 0V
Note 1: TypicalvaluesareT A =25°Candnominalsupplyvoltage(5V).
Note 2: Thisparameterisperiodicallysampledandnot100%tested.
Note 3: The"L"and"LZ"versionscanbeoperatedinthe2.7Vto5.5VV
CC range.HowevertheI SB valuesforLandLZareapplicableonlywhenV CC isinthe2.7Vto4.5Vrange.
4
www.fairchildsemi.com
FM24C256 Rev. D.1
AC Testing Input/Output Waveforms
AC Test Conditions
InputPulseLevels
VCC x 0.1 to VCC x 0.9
10 ns
0.9VCC
0.7VCC
0.3VCC
InputRiseandFallTimes
Input&OutputTimingLevels
OutputLoad
0.1VCC
VCC x 0.3 to VCC x 0.7
1 TTL Gate and C L = 100 pF
Read and Write Cycle Limits (Standard and Low VCC Range 2.7V - 5.5V)
Symbol
Parameter
100 KHz
400 KHz
Units
Min
Max
Min
Max
fSCL
TI
SCL Clock Frequency
100
100
3.5
400
KHz
ns
Noise Suppression Time Constant at
SCL,SDAInputs(MinimumV
Pulsewidth)
50
IN
tAA
SCLLowtoSDADataOutValid
0.3
4.7
0.1
1.3
0.9
µs
µs
tBUF
TimetheBusMustBeFreebefore
aNewTransmissionCanStart
tHD:STA
tLOW
StartConditionHoldTime
ClockLowPeriod
4.0
4.7
4.0
4.7
0.6
1.5
0.6
0.6
µs
µs
µs
µs
tHIGH
ClockHighPeriod
tSU:STA
StartConditionSetupTime
(foraRepeatedStartCondition)
tHD:DAT
tSU:DAT
tR
DatainHoldTime
0
0
ns
ns
DatainSetupTime
250
120
SDA and SCL Rise Time
SDAandSCLFall Time
StopConditionSetupTime
Data Out Hold Time
Write Cycle Time
1
0.3
µs
ns
tF
300
300
tSU:STO
tDH
4.7
0.6
50
µs
ns
ms
`100
tWR
6
6
Note 4: The write cycle time (t WR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle,
the FM24C256 bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave
address. Refer "Write Cycle Timing" diagram.
Bus Timing
t
t
R
F
t
HIGH
t
t
LOW
LOW
SCL
t
SU:STO
t
t
t
SU:DAT
SU:STA
HD:DAT
t
HD:STA
SDA
IN
t
BUF
t
t
AA
DH
SDA
OUT
5
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FM24C256 Rev. D.1
Write Cycle Timing
SCL
SDA
8th BIT
WORD n
ACK
t
WR
STOP
START
CONDITION
CONDITION
Note:
Thewritecycletime(t WR)isthetimefromavalidstopconditionofawritesequencetotheendoftheinternalerase/programcycle.
Typical System Configuration
VCC
VCC
SDA
SCL
Master
Transmitter/
Receiver
Slave
Transmitter/
Receiver
Master
Transmitter/
Receiver
Master
Transmitter
Slave
Receiver
Note:
DuetoopendrainconfigurationofSDAandSCL,abus-levelpull-upresistoriscalledfor,(typicalvalue=4.7k
Ω)
6
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FM24C256 Rev. D.1
Device Type
Background Information (IIC Bus)
IICbusisdesignedtosupportavarietyofdevicessuchasRAMs,
EPROMsetc.,alongwithEEPROMS.Hencetoproperlyidentify
variousdevicesontheIICbus,a4-bit“DeviceType”identifier
stringisused.ForEEPROMS,this4-bitstringis1-0-1-0.EveryIIC
deviceonthebusinternallycomparesthis4-bitstringtoitsown
“DeviceType”stringtoensureproperdeviceselection.
ExtendedIICspecificationisanextensionofStandardIICspeci-
ficationtoallowaddressingofEEPROMswithmorethan16Kbits
of memory on an IIC bus. The difference between the two
specificationsisthatExtendedIICspecificationdefinestwobytes
of“ArrayAddress”informationwhileStandardIICspecification
definesonlyone.Allotheraspectsareidenticalbetweenthetwo
specifications.UsingtwobytesofArrayAddressand3address
signals(A2,A1andA0),itisnowpossibletoaddressupto4Mbits
(28 * 28 * 23 * 8 = 4 Mbits) of memory on an IIC bus.
Device/Page Block Selection
Whenmultipledevicesofthesametype(e.g.multipleEEPROMS)
are present on the IIC bus, then the A2, A1 and A0 address
informationbitsareusedindeviceselection.EveryIICdeviceon
thebusinternallycomparesthis3-bitstringtoitsownphysical
configuration (A2, A1 and A0 pins) to ensure proper device
selection.Thiscomparisonisinadditiontothe“DeviceType”
comparison.
Note that due to format difference, it is not possible to have
peripheralswhichfollowStandardIICspecification(e.g.16Kbit
EEPROM)andperipheralswhichfollowExtendedIICspecifica-
tion(e.g. 256KbitEEPROM)onacommonIICbus.
IICbusallowssynchronousbi-directionalcommunicationbe-
tweenaTRANSMITTERandaRECEIVERusingaClocksignal
(SCL)andaDatasignal(SDA).Additionallythereareuptothree
Addresssignals(A2,A1andA0)whichcollectivelyserveas“chip
selectsignal”toadevice(e.g.EEPROM)onthebus.
InadditiontoselectinganEEPROM,these3bitsarealsousedto
selecta“pageblock”withintheselectedEEPROM.Eachpage
blockis512Kbit(64KBytes)insize.IfanEEPROMcontainsmore
thanonepagebockthentheselectionofapageblockwithinthe
EEPROMisbyusingA2, A1andA0bits.
All communication on the IIC bus must be started with a valid
STARTcondition(byaMASTER),followedbytransmittal(bythe
MASTER)ofbyte(s)ofinformation(Address/Data).Foreverybyte
ofinformationreceived,theaddressedRECEIVERprovidesa
validACKNOWLEDGEpulsetofurthercontinuethecommunica-
tionunlesstheRECEIVERintendstodiscontinuethecommunica-
tion.Dependingonthedirectionoftransfer(WriteorRead),the
RECEIVER can be a SLAVE or the MASTER. A typical IIC
communicationconcludeswithaSTOPcondition(bytheMAS-
TER).
Read/Write Bit
LastbitoftheSlaveAddressindicatesiftheintendedaccessis
ReadorWrite.Ifthebitis"1,"thentheaccessisRead,whereas
ifthebitis"0,"thentheaccessisWrite.
Acknowledge
AcknowledgeisanactiveLOWpulseontheSDAlinedrivenbyan
addressed receiver to the addressing transmitter to indicate
receiptof8-bitsofdata.ThereceiverprovidesanACKpulsefor
every8-bitsofdatareceived.Thishandshakemechanismisdone
asfollows:Aftertransmitting8-bitsofdata,thetransmitterre-
leasestheSDAlineandwaitsfortheACKpulse.Theaddressed
receiver,ifpresent,drivestheACKpulseontheSDAlineduring
the9thclockandreleasestheSDAlineback(tothetransmitter).
Refer Figure3 .
AddressinganEEPROMmemorylocationinvolvessendinga
commandstringwiththefollowinginformation:
[DEVICETYPE]—[DEVICE/PAGEBLOCKSELECTION]—[R/W
BIT]—[ARRAYADDRESS#1]—[ARRAYADDRESS#0]
Slave Address
SlaveAddressisan8-bitinformationconsistingofaDevicetype
field(4bits),Device/Pageblockselectionfield(3bits)andRead/
Writebit(1bit).
Array Address#1
Thisisan8-bitinformationcontainingthemostsignificant8-bitsof
16-bitmemoryarrayaddressofalocationtobeselectedwithina
pageblockofthedevice.
Slave Address Format
Array Address#0
Device Type
Identifier
Device/Page Block
Selection
Thisisan8-bitinformationcontainingtheleastsignificant8-bitsof
16-bitmemoryarrayaddressofalocationtobeselectedwithina
pageblockofthedevice.
1
0
1
0
A2
A1
A0 R/W (LSB)
7
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FM24C256 Rev. D.1
Pin Descriptions
Device Operation
TheFM24C256supportsabi-directionalbusorientedprotocol.
Theprotocoldefinesanydevicethatsendsdataontothebusas
atransmitterandthereceivingdeviceasthereceiver.Thedevice
controlling the transfer is the master and the device that is
controlled is the slave. The master will always initiate data
transfers and provide the clock for both transmit and receive
operations.Therefore,theFM24C256willbeconsideredaslave
inallapplications.
Serial Clock (SCL)
TheSCLinputisusedtoclockalldataintoandoutofthedevice.
Serial Data (SDA)
SDAisabi-directionalpinusedtotransferdataintoandoutofthe
device.Itisanopendrainoutputandmaybewire–ORedwithany
numberofopendrainoropencollectoroutputs.
Write Protect (WP)
Clock and Data Conventions
IftiedtoV CC,PROGRAMoperationsontotheentirememorywill
not be executed. READ operations are possible. If tied to V
normaloperationisenabled,READ/WRITEovertheentirememory
ispossible.
DatastatesontheSDAlinecanchangeonlyduringSCLLOW.
SDAstatechangesduringSCLHIGHarereservedforindicating
startandstopconditions.Refer Figure1 .
,
SS
Start Condition
ThisfeatureallowstheusertoassigntheentirememoryasROM
whichcanbeprotectedagainstaccidentalprogramming.When
writeisdisabled,slaveaddressandwordaddresswillbeacknowl-
edgedbutdatawillnotbeacknowledged.
All commands are preceded by the start condition, which is a
HIGHtoLOWtransitionofSDAwhenSCLisHIGH.TheFM24C256
continuouslymonitorstheSDAandSCLlinesforthestartcondi-
tionandwillnotrespondtoanycommanduntilthisconditionhas
beenmet.Refer Figure2 .
Thispinhasaninternalpull-downcircuit.However,onsystems
wherewriteprotectionisnotrequireditisrecommendedthatthis
Stop Condition
pinistiedtoV
.
SS
Allcommunicationsareterminatedbyastopcondition,whichisa
LOW to HIGH transition of SDA when SCL is HIGH. The stop
conditionisalsousedbytheFM24C256toplacethedeviceinthe
standbypowermode.Refer Figure2 .
Device Selection Inputs A2, A1 and A0 (as
appropriate)
These inputs collectively serve as “chip select” signal to an
EEPROMwhenmultipleEEPROMsarepresentonthesameIIC
FM24C256 Array Addressing
bus.HencetheseinputsshouldbeconnectedtoV
CC orVSS ina
uniquemannertoallowproperselectionofanEEPROMamongst
multipleEEPROMs.Duringatypicaladdressingsequence,every
EEPROM on the IIC bus compares the configuration of these
inputs to the respective 3 bit “Device/Page block selection”
information(partofslaveaddress)todetermineavalidselection.
Fore.g.ifthe3bit“Device/Pageblockselection”is1-0-1,thenthe
EEPROMwhose“DeviceSelectioninputs”(A2,A1andA0)are
connectedtoV CC-VSS-VCCrespectively,isselected.
DuringRead/Writeoperations,addressingtheEEPROMmemory
arrayinvolvesinproviding2addressbytes,“WordAddress1”and
“Word Address 0." However on FM24C256 only the 7 least
significant bits (LSB) of “Word Address 1” byte are used in
decodingtheaccesslocation.Theremaining1bitisnotusedand
isrecommendedtobesetto“0."All8bitsofthe“WordAddress
0”byteareusedindecodingtheaccesslocation.
8
www.fairchildsemi.com
FM24C256 Rev. D.1
Data Validity (Figure 1)
SCL
SDA
DATA STABLE
DATA
CHANGE
Start and Stop Definition (Figure 2)
SCL
SDA
START
STOP
CONDITION
CONDITION
Acknowledge Response from Receiver (Figure 3)
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM
TRANSMITTER
t
DH
t
AA
DATA OUTPUT
FROM
RECEIVER
START
CONDITION
ACKNOWLEDGE
PULSE
9
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FM24C256 Rev. D.1
Page Write is initiated in the same manner as the Byte Write
operation;butinsteadofterminatingthecycleaftertransmitting
thefirstdatabyte,themastercanfurthertransmitupto63more
bytes.Afterthereceiptofeachbyte,FM24C256willrespondwith
anacknowledgepulse,incrementtheinternaladdresscounterto
thenextaddress,andisreadytoacceptthenextdata.Ifthemaster
shouldtransmitmorethan64bytespriortogeneratingtheSTOP
condition, theaddresscounterwill“rollover”andpreviously
loadeddatawillbere-loaded.AswiththeByteWriteoperation,all
inputsaredisableduntilcompletionoftheinternalwritecycle.
Refer Figure5 fortheaddress,acknowledge,anddatatransfer
sequence.
Write Operations
BYTE WRITE
Forbytewriteoperation,twobytesofaddressarerequiredafter
the slave address. These two bytes select 1 out of the 32K
locationsinthememory.Themasterprovidesthesetwoaddress
bytesandforeachaddressbytereceived,FM24C256responds
withanacknowledgepulse.Masterthenprovidesabyteofdata
tobewrittenintothememory.Uponreceiptofthisdata,FM24C256
respondswithanacknowledgepulse.Themasterthenterminates
the transfer by generating a stop condition, at which time the
FM24C256beginstheinternalwritecycletothememory.While
theinternalwritecycleisinprogresstheFM24C256inputsare
disabled,andthedevicewillnotrespondtoanyrequestsfromthe
master for the duration of t WR. Refer Figure 4 for the address,
acknowledgeanddatatransfersequence.
Acknowledge Polling
Oncethestopconditionisissuedtoindicatetheendofthehost’s
writeoperation,theFM24C256initiatestheinternalwritecycle.
ACKpollingcanbeinitiatedimmediately.Thisinvolvesissuingthe
startconditionfollowedbytheslaveaddressforawriteoperation.
IftheFM24C256isstillbusywiththewriteoperation,noACKwill
bereturned.IftheFM24C256hascompletedthewriteoperation,
anACKwillbereturnedandthehostcanthenproceedwiththe
nextreadorwriteoperation.
PAGE WRITE
To minimize write cycle time, FM24C256 offers Page Write
feature, which allows simultaneous programming of up to 64
contiguousbytes.Tofacilitatethisfeature,thememoryarrayis
organizedintermsof“Pages”.APageconsistsof64contiguous
bytelocationsstartingatevery64-Byteaddressboundary(for
example,startingatarrayaddress0x0000,0x0040,0x0080etc.).
PageWriteoperationisconfinedtoasinglepage.Inotherwords
aPageWriteoperationwillnotcrossovertolocationsonthenext
page but will “roll over” to the beginning of the same page
wheneverendofpageisreachedandadditionaldatabytesarea
continuedtobeprovided.APageWriteoperationcanbeinitiated
tobeginatanylocationwithinapage(startingaddressofthePage
WriteoperationneednotbethestartingaddressofaPage).
Write Protection
ProgrammingoftheentirememorywillnottakeplaceiftheWPpin
of the FM24C256 is connected to V
. The FM24C256 will
CC
respondtoslaveandbyteaddresses;butifthememoryaccessed
iswriteprotectedbytheWPpin,theFM24C256willnotgenerate
an acknowledge after the first byte of data has been received.
Thustheprogramcyclewillnotbestartedwhenthestopcondition
isasserted.
Byte Write (Figure 4)
S
S
SLAVE
ADDRESS
WORD
ADDRESS (1)
WORD
ADDRESS (0)
DATA
T
A
R
T
T
O
P
Bus Activity:
Master
SDA Line
A
C
K
A
C
K
A
C
K
A
C
K
Bus Activity:
EEPROM
Page Write (Figure 5)
S
S
T
O
P
SLAVE
ADDRESS
WORD
ADDRESS (1)
WORD
ADDRESS (0)
DATA n
DATA n+63
T
A
R
T
Bus Activity:
Master
1
0 1 0
SDA Line
A
C
K
A
C
K
A
C
K
A
C
K
Bus Activity
10
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FM24C256 Rev. D.1
will not acknowledge the transfer but does generate the stop
condition,andthereforetheFM24C256discontinuestransmis-
sion. Refer Figure 7 for the address, acknowledge, and data
transfersequence.
Read Operations
Read operations are initiated in the same manner as write
operations, with the exception that the R/W bit of the slave
addressissettoaone.Therearethreebasicreadoperations:
currentaddressread,randomread,andsequentialread.
Sequential Read
Sequentialreadscanbeinitiatedaseitheracurrentaddressread
orrandomaccessread.Thefirstwordistransmittedinthesame
manner as the other read modes; however, the master now
respondswithanacknowledge,indicatingitrequiresadditional
data.TheFM24C256continuestooutputdataforeachacknowl-
edgereceived.Thereadoperationisterminatedbythemasternot
respondingwithanacknowledgeorbygeneratingastopcondi-
tion.
Current Address Read
InternallytheFM24C256containsanaddresscounterthatmain-
tainstheaddressofthelastbyteaccessed,incrementedbyone.
Therefore,ifthelastaccess(eitherareadorwrite)wastoaddress
n,thenextreadoperationwouldaccessdatafromaddressn+1.
Upon receipt of the slave address with R/W set to "1," the
FM24C256issuesanacknowledgeandtransmitstheeightbit
word. The master will not acknowledge the transfer but does
generateastopcondition,andthereforetheFM24C256discon-
tinuestransmission.Refer Figure 6forthesequenceofaddress,
acknowledgeanddatatransfer.
The data output is sequential with the data from address n
followed by the data from n + 1. The address counter for read
operationsincrementsallwordaddressbits,allowingtheentire
memorycontentstobeseriallyreadduringoneoperation.After
theentirememoryhasbeenread,thecounter"rollsover"tothe
beginningofthememory.FM24C256continuestooutputdatafor
each acknowledge received. Refer Figure 8 for the address,
acknowledge,anddatatransfersequence.
Random Read
Randomreadoperationsallowthemastertoaccessanymemory
locationinarandommanner.Priortoissuingtheslaveaddress
with the R/W bit set to "1," the master must first perform a
“dummy”writeoperation.Themasterissuesthestartcondition,
slave address with the R/W bit set to "0" and then the byte
address.Afterthebyteaddressacknowledge,themasterimme-
diatelyissuesanotherstartconditionandtheslaveaddresswith
theR/Wbitsettoone.Thiswillbefollowedbyanacknowledge
fromtheFM24C256andthenbytheeightbitword.Themaster
Current Address Read (Figure 6)
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
Bus Activity:
Master
1 0 1
0
1
SDA Line
A
C
K
NO
A
C
K
Bus Activity:
EEPROM
DATA
Random Read (Figure 7)
S
T
A
R
T
S
S
T
O
P
T
A
R
T
SLAVE
ADDRESS
WORD
ADDRESS (1)
WORD
ADDRESS (0)
SLAVE
ADDRESS
Bus Activity:
Master
DATA
0
1
SDA Line
A
C
K
A
C
K
A
C
K
A
C
K
NO
Bus Activity:
EEPROM
A
C
K
Sequential Read (Figure 8)
S
T
O
P
A
C
K
A
C
K
A
C
K
Bus Activity:
Slave
Master
Address
SDA Line
A
C
K
NO
DATA n +1
DATA n +1
DATA n + 2
DATA n + x
A
C
K
Bus Activity:
EEPROM
11
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FM24C256 Rev. D.1
PhysicalDimensionsinches(millimeters)unlessotherwisenoted
0.189 - 0.197
(4.800 - 5.004)
8
7
6
5
0.228 - 0.244
(5.791 - 6.198)
1
2
3
4
Lead #1
IDENT
0.150 - 0.157
0.053 - 0.069
(3.810 - 3.988)
0.010 - 0.020
(0.254 - 0.508)
(1.346 - 1.753)
0.004 - 0.010
(0.102 - 0.254)
x 45¡
8¡ Max, Typ.
All leads
Seating
Plane
0.004
(0.102)
All lead tips
0.0075 - 0.0098
(0.190 - 0.249)
Typ. All Leads
0.014
(0.356)
0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads
0.050
(1.270)
0.014 - 0.020
Typ.
(0.356 - 0.508)
8-Pin Molded Small Outline PackageT(yMp 8)
Package Number M08A
12
www.fairchildsemi.com
FM24C256 Rev. D.1
PhysicalDimensionsinches(millimeters)unlessotherwisenoted
0.373 - 0.400
(9.474 - 10.16)
0.090
(2.286)
8
7
0.032 0.005
(0.813 0.127)
RAD
8
7
6
3
5
4
0.092
(2.337)
DIA
0.250 - 0.005
(6.35 0.127)
Pin #1
IDENT
+
Pin #1 IDENT
1
Option 1
1
2
Option 2
0.280
MIN
0.040
(1.016)
Typ.
(7.112)
0.030
0.145 - 0.200
(3.683 - 5.080)
0.039
(0.991)
MAX
(0.762)
0.300 - 0.320
(7.62 - 8.128)
20° 1°
0.130 0.005
(3.302 0.127)
0.125 - 0.140
95° 5°
(3.175 - 3.556)
0.065
(1.651)
0.125
(3.175)
DIA
0.020
90° 4°
Typ
0.009 - 0.015
(0.229 - 0.381)
(0.508)
Min
0.018 0.003
(0.457 0.076)
NOM
+0.040
-0.015
0.325
0.100 0.010
+1.016
-0.381
8.255
(2.540 0.254)
0.045 0.015
(1.143 0.381)
0.060
(1.524)
0.050
(1.270)
Molded Dual-In-Line Package (N)
Package Number N08E
Life Support Policy
Fairchild'sproductsarenotauthorizedforuseascriticalcomponentsinlifesupportdevicesorsystemswithouttheexpresswritten
approvalofthePresidentofFairchildSemiconductorCorporation.Asusedherein:
1.Lifesupportdevicesorsystemsaredevicesorsystemswhich,
(a)areintendedforsurgicalimplantintothebody,or(b)support
orsustainlife,andwhosefailuretoperform,whenproperly
usedinaccordancewithinstructionsforuseprovidedinthe
labeling,canbereasonablyexpectedtoresultinasignificant
injurytotheuser.
2.Acriticalcomponentisanycomponentofalifesupportdevice
or system whose failure to perform can be reasonably ex-
pectedtocausethefailureofthelifesupportdeviceorsystem,
ortoaffectitssafetyoreffectiveness.
Fairchild Semiconductor
Americas
Fairchild Semiconductor
Europe
Fairchild Semiconductor
Hong Kong
Fairchild Semiconductor
Japan Ltd.
Customer Response Center
Tel. 1-888-522-5372
Fax:
Tel:
Tel:
Tel:
Tel:
+44 (0) 1793-856858
8/F,Room808,EmpireCentre
68ModyRoad,TsimshatsuiEast
Kowloon.HongKong
Tel;+852-2722-8338
Fax:+852-2722-8383
4F,NatsumeBldg.
Deutsch
English
Français
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+49 (0) 8141-6102-0
+44 (0) 1793-856856
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Tokyo,113-0034Japan
Tel:81-3-3818-8840
Fax: 81-3-3818-8841
Fairchilddoesnotassumeanyresponsibilityforuseofanycircuitrydescribed,nocircuitpatentlicensesareimpliedandFairchildreservestherightatanytimewithoutnoticetochangesaidcircuitryandspecifications.
13
www.fairchildsemi.com
FM24C256 Rev. D.1
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