FT240XQ-R_技术文档

FT240X USB 8-BIT FIFO IC Datasheet

Version 1.3

Document No.: FT_000626 Clearance No.: FTDI# 259

Future Technology

Devices International Ltd

.

FT240X

(USB 8-BIT FIFO IC)



USB Battery Charger Detection. Allows for USB

peripheral devices to detect the presence of a higher

power source to enable improved charging.

The FT240X is a USB to parallel FIFO

interface with the following advanced

features:



Device supplied pre-programmed with unique USB

serial number.



Single chip USB to parallel FIFO bidirectional

data transfer interface.



USB Power Configurations; supports bus- powered,

self-powered and bus-powered with power

switching.

Entire USB protocol handled on the chip. No

USB specific firmware programming required.

Fully integrated 2048 byte multi-time-

programmable (MTP) memory, storing device

descriptors and FIFO I/O configuration.



Integrated +3.3V level converter for USB I/O.

True 3.3V CMOS drive output and TTL input;

operates down to 1V8 with external pull-ups.

Tolerant of 5V input.



Fully integrated clock generation with no

external crystal required plus optional clock

output selection enabling glue-less interface to

external MCU or FPGA.



Configurable I/O pin output drive strength; 4

mA(min) and 16 mA(max).



Integrated power-on-reset circuit.



Data transfer rates up to 1Mbyte / second.

Fully integrated AVCC supply filtering - no external

filtering required.

512 byte receive buffer and 512 byte transmit

buffer utilising buffer smoothing technology to

allow for high data throughput.



+5V Single Supply Operation.



FTDI’s royalty-free Virtual Com Port (VCP) and

Direct (D2XX) drivers eliminate the

requirement for USB driver development in

most cases.

Internal 3V3/1V8 LDO regulators

Low operating and USB suspend current; 8mA

(active-typ) and 125uA (suspend-typ).



UHCI/OHCI/EHCI host controller compatible.

USB 2.0 Full Speed capable.



Configurable FIFO interface I/O pins.

Synchronous and asynchronous bit bang

interface options.

Extended operating temperature range; -40 to 85⁰C.

Available in compact Pb-free 24 Pin SSOP and QFN-

24 packages (both RoHS compliant).

Neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or reproduced

in any material or electronic form without the prior written consent of the copyright holder. This product and its documentation are

supplied on an as-is basis and no warranty as to their suitability for any particular purpose is either made or implied. Future Technology

Devices International Ltd will not accept any claim for damages howsoever arising as a result of use or failure of this product. Your

statutory rights are not affected. This product or any variant of it is not intended for use in any medical appliance, device or system in

which the failure of the product might reasonably be expected to result in personal injury. This document provides preliminary

information that may be subject to change without notice. No freedom to use patents or other intellectual property rights is implied by

the publication of this document. Future Technology Devices International Ltd, Unit 1, 2 Seaward Place, Centurion Business Park,

Glasgow G41 1HH United Kingdom. Scotland Registered Company Number: SC136640

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FT240X USB 8-BIT FIFO IC Datasheet

Version 1.3

Document No.: FT_000626 Clearance No.: FTDI# 259

1 Typical Applications



Upgrading Legacy Peripherals to USB

Utilising USB to add system modularity



USB Industrial Control

USB MP3 Player Interface

Incorporate USB interface to enable PC

transfers for development system

communication

USB FLASH Card Reader and Writers

Set Top Box PC - USB interface

USB Digital Camera Interface



Cellular and Cordless Phone USB data transfer

cables and interfaces

USB Software and Hardware Encryption

Dongles

Interfacing MCU/PLD/FPGA based designs to

USB



USB Instrumentation

USB Audio and Low Bandwidth Video data

transfer

USB dongle implementations for Software/

Hardware Encryption and Wireless Modules

USB Smart Card Readers



Provides detection of dedicated charging ports

for charging batteries in portable devices.

1.1 Driver Support

Royalty free VIRTUAL COM PORT

(VCP) DRIVERS for...

Royalty free D2XX Direct Drivers

(USB Drivers + DLL S/W Interface)



Windows 8 32,64-bit

Windows 7 32,64-bit

Windows Vista and Vista 64-bit

Windows XP and XP 64-bit

Windows XP Embedded

Server 2003, XP and Server 2008

Windows CE 4.2, 5.0 and 6.0

Mac OS-X



Windows 8 32,64-bit

Windows 7 32,64-bit

Windows Vista and Vista 64-bit

Windows XP and XP 64-bit

Windows XP Embedded

Server 2003, XP and Server 2008

Windows CE 4.2, 5.0 and 6.0

Mac OS-X

Linux 3.2 and greater

Android

Linux 2.6 and greater

Android

The drivers listed above are all available to download for free from FTDI website (www.ftdichip.com).

Various 3rd party drivers are also available for other operating systems - see FTDI website

(www.ftdichip.com) for details. For driver installation, please refer to the application note AN232B-10.

For driver installation, please refer to http://www.ftdichip.com/Documents/InstallGuides.htm

1.2 Part Numbers

Part Number

Package

FT240XQ-x

24 Pin QFN

24 Pin SSOP

FT240XS-x

Note: Packaging codes for x is:

-R: Taped and Reel, (SSOP is 3,000pcs per reel, QFN is 5,000pcs per reel).

- U: Tube packing, 58pcs per tube (SSOP only)

- T: Tray packing, 490pcs per tray (QFN only)

For example: FT240XQ-R is 5,000pcs taped and reel packing

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FT240X USB 8-BIT FIFO IC Datasheet

Version 1.3

Document No.: FT_000626 Clearance No.: FTDI# 259

1.3 USB Compliant

The FT240X is fully compliant with the USB 2.0 specification and has been given the USB-IF Test-ID (TID)

40001466 (Rev D).

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FT240X USB 8-BIT FIFO IC Datasheet

Version 1.3

Document No.: FT_000626 Clearance No.: FTDI# 259

2 FT240X Block Diagram

VCC

1V8 Internal

Core Supply

3.3 Volt LDO

Regulator

1.8 Volt LDO

Regulator

3V3OUT

FIFO RX Buffer

(512 bytes)

VCCIO

DATA[0]

DATA[1]

DATA[2]

DATA[3]

DATA[4]

DATA[5]

DATA[6]

DATA[7]

USB

Transceiver

with

Integrated

1.5k pullups

and battery

charge

USBDP

USBDM

Serial Interface

Engine

USB

Protocol Engine

(SIE)

FIFO Interface

Controller

RXF#

TXE#

RD#

detection

WR

SIWUA

CBUS5

CBUS6

Internal MTP

Memory

USB DPLL

FIFO TX Buffer

(512 bytes)

3V3OUT

RESET#

Internal

12MHz

Oscillator

X4 Clock

Multiplier

Reset

Generator

48MHz

To USB Transceiver Cell

GND

Figure 2.1 FT240X Block Diagram

For a description of each function please refer to Section 4.

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FT240X USB 8-BIT FIFO IC Datasheet

Version 1.3

Document No.: FT_000626 Clearance No.: FTDI# 259

Table of Contents

1

Typical Applications...................................................................... 2

1.1 Driver Support.................................................................................... 2

1.2 Part Numbers...................................................................................... 2

1.3 USB Compliant.................................................................................... 3

FT240X Block Diagram ................................................................. 4

Device Pin Out and Signal Description.......................................... 7

3.1 24-LD SSOP Package .......................................................................... 7

3.2 SSOP Package Pin Out Description...................................................... 7

3.3 QFN-24 Package ................................................................................. 9

3.4 QFN-24 Package Signal Description.................................................... 9

3.5 CBUS Signal Options ......................................................................... 11

3.6 FT240X FIFO READ Timing Diagrams................................................ 12

3.7 FT240X FIFO WRITE Timing Diagrams.............................................. 13

Function Description................................................................... 14

4.1 Key Features..................................................................................... 14

4.2 Functional Block Descriptions........................................................... 15

Devices Characteristics and Ratings........................................... 16

5.1 Absolute Maximum Ratings............................................................... 16

5.2 ESD and Latch-up Specifications....................................................... 16

5.3 DC Characteristics............................................................................. 17

5.4 MTP Memory Reliability Characteristics ............................................ 21

5.5 Internal Clock Characteristics........................................................... 21

USB Power Configurations.......................................................... 22

6.1 USB Bus Powered Configuration ...................................................... 22

6.2 Self Powered Configuration .............................................................. 23

6.3 USB Bus Powered with Power Switching Configuration .................... 24

Application Examples ................................................................. 25

7.1 USB to MCU FIFO Interface............................................................... 25

7.2 Battery Charge Detection.................................................................. 26

Internal MTP Memory Configuration........................................... 28

8.1 Default Values .................................................................................. 28

2

3

4

5

6

7

8

8.2 Methods of Programming the MTP Memory....................................... 29

8.2.1 Programming the MTP memory over USB...................................................................... 29

8.3 Memory Map ..................................................................................... 30

9

Package Parameters................................................................... 31

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FT240X USB 8-BIT FIFO IC Datasheet

Version 1.3

Document No.: FT_000626 Clearance No.: FTDI# 259

9.1 SSOP-24 Package Mechanical Dimensions ........................................ 31

9.2 SSOP-24 Package Markings .............................................................. 32

9.3 QFN-24 Package Mechanical Dimensions.......................................... 33

9.4 QFN-24 Package Markings ................................................................ 34

9.5 Solder Reflow Profile ........................................................................ 35

10 Contact Information................................................................... 36

Appendix A - References............................................................................ 37

Appendix B - List of Figures and Tables..................................................... 38

Appendix C - Revision History.................................................................... 40

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FT240X USB 8-BIT FIFO IC Datasheet

Version 1.3

Document No.: FT_000626 Clearance No.: FTDI# 259

3 Device Pin Out and Signal Description

3.1 24-LD SSOP Package

15

24

4

2

9

1

7

8

5

3V3OUT

DATA0

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

14

13

USBDM

USBDP

16

RESET#

21

20

11

12

10

23

22

RXF#

TXE#

RD#

WR#

SI/WU#

CBUS5

CBUS6

Figure 3.1 SSOP Package Pin Out and Schematic Symbol

3.2 SSOP Package Pin Out Description

Note: The convention used throughout this document for active low signals is the signal name followed by

a #

Pin No. Name

Type

I/O

Description

USB Data Signal Plus, incorporating 1.5kΩ pull up resistor to 3.3V.

13

14

USBDP

USBDM

USB Data Signal Minus.

I/O

Table 3.1 USB Interface Group

Pin No. Name

Type

PWR

Description

1V8 - 3V3 supply for the IO cells

3

VCCIO

GND

Device ground supply pins

6, 19

3V3 output at 50mA. May be used to power VCCIO.

**

15

Output

When VCC is 3V3; pin 15 is an input pin and should be connected to pin

18.

3V3OUT

**

+5V (or 3V3) supply to the device core.

18

17

PWR

VCC

+1V8 Output. May be left unterminated

VCORE

Table 3.2 Power and Ground Group

** If VCC is 3V3 then 3V3OUT must also be driven with 3V3 input

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FT240X USB 8-BIT FIFO IC Datasheet

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Document No.: FT_000626 Clearance No.: FTDI# 259

Pin No.

Name

Type

Description

Active low reset pin. This can be used by an external device to reset the

FT240X. If not required can be left unconnected, or pulled up to VCC.

16

RESET# Input

Active low input. May be used to flush the IC buffer back to the PC (Send

Immediate) or if the PC is in suspend mode it can be used as a Wake Up

signal.

10

SIWU#

Input

Configurable CBUS I/O Pin. Function of this pin is configured in the

device MTP memory. See CBUS Signal Options, Table 3.9.

23

22

CBUS5

CBUS6

I/O

Configurable CBUS I/O Pin. Function of this pin is configured in the

device MTP memory. See CBUS Signal Options, Table 3.9.

Table 3.3 Miscellaneous Signal Group

Pin No.

Name

D0

Type

I/O

Description

FIFO Data Bus Bit 0

FIFO Data Bus Bit 1

FIFO Data Bus Bit 2

FIFO Data Bus Bit 3

FIFO Data Bus Bit 4

FIFO Data Bus Bit 5

FIFO Data Bus Bit 6

FIFO Data Bus Bit 7

24

4

D1

2

D2

9

D3

1

D4

7

D5

8

D6

5

D7

Enables the current FIFO data byte on D0...D7 when low. Fetched the next FIFO

data byte (if available) from the receive FIFO buffer when RD# goes from high to

low. See Section 3.6 for timing diagram.

11

12

20

RD#

WR

Input

Output

Writes the data byte on the D0...D7 pins into the transmit FIFO buffer when WR

goes from high to low. See Section 3.7 for timing diagram.

When high, do not write data into the FIFO. When low, data can be written into

the FIFO by strobing WR high, then low. During reset this signal pin is tri-state.

See Section 3.7 for timing diagram.

TXE#

When high, do not read data from the FIFO. When low, there is data available in

the FIFO which can be read by strobing RD# low, then high again. During reset

this signal pin is tri-state. See Section 3.6 for timing diagram.

21

RXF#

Output

If the Remote Wakeup option is enabled in the internal MTP memory, during USB

suspend mode (PWREN# = 1) RXF# becomes an input. This can be used to wake

up the USB host from suspend mode by strobing this pin low for a minimum of

20ms which will cause the device to request a resume on the USB bus.

Table 3.4 FIFO Interface Group (see note 2)

Notes:

When used in Input Mode, the input pins are pulled to VCCIO via internal 200kΩ resistors. These

pins can be programmed to gently pull low during USB suspend (PWREN# = “1”) by setting an

option in the internal MTP memory.

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FT240X USB 8-BIT FIFO IC Datasheet

Version 1.3

Document No.: FT_000626 Clearance No.: FTDI# 259

3.3 QFN-24 Package

12

21

1

23

6

22

4

3V3OUT

DATA0

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

11

USBDM

10

USBDP

13

5

2

RESET#

18

17

8

9

7

20

19

RXF#

TXE#

RD#

WR#

SI/WU#

CBUS5

CBUS6

Figure 3.2 QFN-24 Package Pin Out and schematic symbol

3.4 QFN-24 Package Signal Description

Note: The convention used throughout this document for active low signals is the signal name followed by

a #

Pin No. Name

Type

I/O

Description

USB Data Signal Plus, incorporating 1.5kΩ pull up resistor to 3.3V.

10

11

USBDP

USBDM

USB Data Signal Minus.

I/O

Table 3.5 USB Interface Group

Pin No. Name

Type

PWR

Description

1V8 - 3V3 supply for the IO cells

24

VCCIO

GND

Device ground supply pins

3, 16

3V3 output at 50mA. May be used to power VCCIO.

**

12

Output

When VCC is 3V3; pin 12 is an input pin and should be connected to

pin 15.

3V3OUT

**

+5V (or 3V3) supply to the device core.

15

14

PWR

VCC

+1V8 Output. May be left unterminated

VCORE

Table 3.6 Power and Ground Group

*Pin 25 is the centre pad on package base. Connect to GND.

**If VCC is 3V3 then 3V3OUT must also be driven with 3V3 input

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FT240X USB 8-BIT FIFO IC Datasheet

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Document No.: FT_000626 Clearance No.: FTDI# 259

Pin No.

Name

Type

Description

Active low reset pin. This can be used by an external device to reset the

FT240X. If not required can be left unconnected, or pulled up to VCC.

13

RESET# Input

Active low input. May be used to flush the IC buffer back to the PC (Send

Immediate) or if the PC is in suspend mode it can be used as a Wake Up

signal.

7

SIWU#

Input

Configurable CBUS I/O Pin. Function of this pin is configured in the

device MTP memory. See CBUS Signal Options, Table 3.9.

20

19

CBUS5

CBUS6

I/O

Configurable CBUS I/O Pin. Function of this pin is configured in the

device MTP memory. See CBUS Signal Options, Table 3.9.

Table 3.7 Miscellaneous Signal Group

Pin No.

Name

D0

Type

I/O

Description

FIFO Data Bus Bit 0

FIFO Data Bus Bit 1

FIFO Data Bus Bit 2

FIFO Data Bus Bit 3

FIFO Data Bus Bit 4

FIFO Data Bus Bit 5

FIFO Data Bus Bit 6

FIFO Data Bus Bit 7

21

1

D1

23

6

D2

D3

22

4

D4

D5

5

D6

2

D7

Enables the current FIFO data byte on D0...D7 when low. Fetched the next FIFO

data byte (if available) from the receive FIFO buffer when RD# goes from high to

low. See Section 3.6 for timing diagram.

8

RD#

WR

Input

Output

Writes the data byte on the D0...D7 pins into the transmit FIFO buffer when WR

goes from high to low. See Section 3.7 for timing diagram.

9

When high, do not write data into the FIFO. When low, data can be written into

the FIFO by strobing WR high, then low. During reset this signal pin is tri-state.

See Section 3.7 for timing diagram.

17

TXE#

When high, do not read data from the FIFO. When low, there is data available in

the FIFO which can be read by strobing RD# low, then high again. During reset

this signal pin is tri-state. See Section 3.6 for timing diagram.

18

RXF#

Output

If the Remote Wakeup option is enabled in the internal MTP memory, during USB

suspend mode (PWREN# = 1) RXF# becomes an input. This can be used to wake

up the USB host from suspend mode by strobing this pin low for a minimum of

20ms which will cause the device to request a resume on the USB bus.

Table 3.8 FIFO Interface Group (see note 2)

Notes:

When used in Input Mode, the input pins are pulled to VCCIO via internal 200kΩ resistors. These

pins can be programmed to gently pull low during USB suspend (PWREN# = “1”) by setting an

option in the internal MTP memory.

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FT240X USB 8-BIT FIFO IC Datasheet

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Document No.: FT_000626 Clearance No.: FTDI# 259

3.5 CBUS Signal Options

The following options can be configured on the CBUS I/O pins. CBUS signal options are common to both

package versions of the FT240X. These options can be configured in the internal MTP memory using the

software utility FT_PPROG, which can be downloaded from the FTDI Utilities (www.ftdichip.com). The

default configuration is described in Section 8.

CBUS

Signal

Option

Available On CBUS Pin

Description

TRI-STATE

DRIVE 1

DRIVE 0

CBUS5, CBUS6

IO Pad is tri-stated

Output a constant 1

Output a constant 0

Output is low after the device has been configured by

USB, then high during USB suspend mode. This output can

be used to control power to external logic P-Channel logic

level MOSFET switch. Enable the interface pull-down

option when using the PWREN# in this way.

PWREN#

SLEEP#

CBUS5, CBUS6

Goes low during USB suspend mode. Typically used to

power down an external TTL to RS232 level converter IC

in USB to RS232 converter designs.

CLK24MHz

CLK12MHz

CLK6MHz

CBUS5, CBUS6

24 MHz Clock output.*

12 MHz Clock output.*

6 MHz Clock output.*

Battery charge Detect, indicates when the device is

connected to a dedicated battery charger host. Active high

output.

BCD Charger

CBUS5, CBUS6

BCD

Charger#

CBUS5, CBUS6

Inverse of BCD Charger

Synchronous and asynchronous bit bang mode WR#

strobe output.

BitBang_WR#

Synchronous and asynchronous bit bang mode RD# strobe

output.

BitBang_RD#

VBUS Sense

Time Stamp

CBUS5, CBUS6

Input to detect when VBUS is present.

Toggle signal which changes state each time a USB SOF is

received

Prevents the device from entering suspend state when

unplugged.

Keep_Awake#

CBUS5, CBUS6

Table 3.9 CBUS Configuration Control

*When in USB suspend mode the outputs clocks are also suspended.

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FT240X USB 8-BIT FIFO IC Datasheet

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3.6 FT240X FIFO READ Timing Diagrams

T6

T2

T5

T4

RXF#

RD#

T1

T3

Valid Data

D[7...0]

Figure 3.3 FIFO Read Cycle

Time

T1

Description

Minimum Maximum Unit

RD# Active Pulse Width

50

-

ns

T2

RD# to RD# Pre-Charge Time

RD# Active to Valid Data*

50 + T6

20

-

T3

50

Valid Data Hold Time from RD#

Inactive*

T4

0

-

ns

T5

T6

RD# Inactive to RXF#

0

25

-

ns

RXF# Inactive After RD Cycle

80

Table 3.10 FIFO Read Cycle Timings

*Load = 30pF

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FT240X USB 8-BIT FIFO IC Datasheet

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3.7 FT240X FIFO WRITE Timing Diagrams

T12

T11

TXE#

WR

T8

T7

T9

T10

Valid Data

D[7...0]

Figure 3.4 FIFO Write Cycle

Time

T7

Description

Minimum Maximum Unit

WR Active Pulse Width

WR to WR Pre-Charge Time

50

-

ns

T8

Valid data setup to WR falling

edge*

T9

20

0

-

ns

Valid Data Hold Time from WR

Inactive*

T10

T11

T12

WR Inactive to TXE#

5

25

-

ns

TXE# Inactive After WR Cycle

80

Table 3.11 FIFO Write Cycle

*Load = 30pF

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FT240X USB 8-BIT FIFO IC Datasheet

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4 Function Description

The FT240X is a USB to parallel FIFO interface device which simplifies USB implementations and reduces

external component count by fully integrating into the device an MTP memory and an integrated clock

circuit which requires no external crystal. It has been designed to operate efficiently with USB host

controllers by using as little bandwidth as possible when compared to the total USB bandwidth available.

4.1 Key Features

Functional Integration. Fully integrated MTP memory, clock generation, AVCC filtering, power-on-reset

(POR) and LDO regulator.

Configurable CBUS I/O Pin Options. The fully integrated MTP memory allows configuration of the

Control Bus (CBUS) functionality and drive strength selection. There are 2 configurable CBUS I/O options.

The configurable options are defined in section 3.5.

The CBUS lines can be configured with any one of these output options by setting bits in the internal MTP

memory. The device is shipped with the most commonly used pin definitions pre-programmed - see

Section 8 for details.

Asynchronous Bit Bang Mode. In asynchronous bit-bang mode, the eight FIFO lines can be switched

from the regular interface mode to an 8-bit general purpose I/O port. Data packets can be sent to the

device and they will be sequentially sent to the interface at a rate controlled by an internal timer

(equivalent to the baud rate pre-scaler. This option will be described more fully in a separate application

note available from FTDI website (www.ftdichip.com).

Synchronous Bit Bang Mode. The FT240X supports synchronous bit bang mode. This mode differs from

asynchronous bit bang mode in that the interface pins are only read when the device is written to. This

makes it easier for the controlling program to measure the response to an output stimulus as the data

returned is synchronous to the output data. An application note, AN232R-01, available from FTDI website

(www.ftdichip.com) describes this feature.

High Output Drive Option. The parallel FIFO interface and the four FIFO handshake pins can be made

to drive out at three times the standard signal drive level thus allowing multiple devices to be driven, or

devices that require a greater signal drive strength to be interfaced to the FT240X. This option is

configured in the internal MTP memory.

Programmable FIFO RX Buffer Timeout. The FIFO RX buffer timeout is used to flush remaining data

from the receive buffer. This timeout defaults to 16ms, but is programmable over USB in 1ms increments

from 2ms to 255ms, thus allowing the device to be optimised for protocols that require fast response

times from short data packets.

Wake Up Function. If USB is in suspend mode, and remote wake up has been enabled in the internal

MTP memory (it is enabled by default). Strobing the SIWU# pin low for a minimum of 20ms will cause

the FT240X to request a resume from suspend on the USB bus. Normally this can be used to wake up the

host PC from suspend.

Source Power and Power Consumption. The FT240X is capable of operating at a voltage supply

between +3.3V and +5.25V with a nominal operational mode current of 8mA and a nominal USB suspend

mode current of 125µA. This allows greater margin for peripheral designs to meet the USB suspend mode

current limit of 2.5mA. An integrated level converter within allows the FT240X to interface to logic

running at +1.8V to +3.3V (5V tolerant).

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FT240X USB 8-BIT FIFO IC Datasheet

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4.2 Functional Block Descriptions

The following paragraphs detail each function within the FT240X. Please refer to the block

diagram shown in Figure 2.1.

Internal MTP Memory. The internal MTP memory in the FT240X is used to store USB Vendor ID (VID),

Product ID (PID), device serial number, product description string and various other USB configuration

descriptors. The FT240X is supplied with the internal MTP memory pre-programmed as described in

Section 8. A user area of the internal MTP memory is available to system designers to allow storing

additional data from the user application over USB. The internal MTP memory descriptors can be

programmed in circuit, over USB without any additional voltage requirement. The descriptors can be

programmed using the FTDI utility software called FT_PROG, which can be downloaded from FTDI Utilities

on the FTDI website (www.ftdichip.com).

+1.8V LDO Regulator. The +1.8 LDO regulator generates the +1.8V reference voltage for driving the

internal core of the IC.

+3.3V LDO Regulator. The +3.3V LDO regulator generates the +3.3V reference voltage for driving the

USB transceiver cell output buffers. It requires an external decoupling capacitor to be attached to the

3V3OUT regulator output pin. It also provides +3.3V power to the 1.5kΩ internal pull up resistor on

USBDP. The main function of the LDO is to power the USB Transceiver and the Reset Generator Cells

rather than to power external logic. However, it can be used to supply external circuitry requiring a

+3.3V nominal supply with a maximum current of 50mA.

USB Transceiver. The USB Transceiver Cell provides the USB 1.1 / USB 2.0 full-speed physical interface

to the USB cable. The output drivers provide +3.3V level slew rate control signalling, whilst a differential

input receiver and two single ended input receivers provide USB data in, Single-Ended-0 (SE0) and USB

reset detection conditions respectfully. This function also incorporates a 1.5kΩ pull up resistor on USBDP.

The block also detects when connected to a USB power supply which will not enumerate the device but

still supply power and may be used for battery charging.

USB DPLL. The USB DPLL cell locks on to the incoming NRZI USB data and generates recovered clock

and data signals for the Serial Interface Engine (SIE) block.

Internal 12MHz Oscillator. The Internal 12MHz Oscillator cell generates a 12MHz reference clock. This

provides an input to the x4 Clock Multiplier function. The 12MHz Oscillator is also used as the reference

clock for the SIE, USB Protocol Engine and FIFO controller blocks.

Clock Multiplier / Divider. The Clock Multiplier / Divider takes the 12MHz input from the Internal

Oscillator function and generates the 48MHz. The 48Mz clock reference is used by the USB DPLL and the

Baud Rate Generator blocks.

Serial Interface Engine (SIE). The Serial Interface Engine (SIE) block performs the parallel to serial

and serial to parallel conversion of the USB data. In accordance with the USB 2.0 specification, it

performs bit stuffing/un-stuffing and CRC5/CRC16 generation. It also verifies the CRC on the USB data

stream.

USB Protocol Engine. The USB Protocol Engine manages the data stream from the device USB control

endpoint. It handles the low level USB protocol requests generated by the USB host controller and the

commands for controlling the functional parameters of the FIFO in accordance with the USB 2.0

specification Section 9.

FIFO RX Buffer (512 bytes). Data sent from the USB host controller to the FIFO via the USB data OUT

endpoint is stored in the FIFO RX (receive) buffer and is removed from the buffer by reading the contents

of the FIFO using the RD# pin. (Rx relative to the USB interface).

FIFO TX Buffer (512 bytes). Data written into the FIFO using the WR pin is stored in the FIFO TX

(transmit) Buffer. The USB host controller removes data from the FIFO TX Buffer by sending a USB

request for data from the device data IN endpoint. (Tx relative to the USB interface).

FIFO Controller with Programmable High Drive. The FIFO Controller handles the transfer of data

between the FIFO RX, the FIFO TX buffers and the external FIFO interface pins (D0 - D7).

Additionally, the FIFO signals have a configurable high drive strength capability which is configurable in

the MTP memory.

RESET Generator. The integrated Reset Generator Cell provides a reliable power-on reset to the device

internal circuitry at power up. The RESET# input pin allows an external device to reset the FT240X.

RESET# can be tied to VCC or left unconnected if not being used.

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5 Devices Characteristics and Ratings

5.1 Absolute Maximum Ratings

The absolute maximum ratings for the FT240X devices are as follows. These are in accordance with the

Absolute Maximum Rating System (IEC 60134). Exceeding these may cause permanent damage to the

device.

Parameter

Value

Unit

Conditions

Storage Temperature

-65°C to 150°C

168 Hours

Degrees C

Floor Life (Out of Bag) At Factory Ambient

(30°C / 60% Relative Humidity)

(IPC/JEDEC J-

STD-033A MSL

Level 3

Hours

Compliant)*

Ambient Operating Temperature (Power

Applied)

-40°C to 85°C

Degrees C

MTTF FT240XS

MTTF FT240XQ

TBD

Hours

TBD

Hours

VCC Supply Voltage

-0.3 to +5.5

-0.3 to +4.0

-0.5 to +3.63

V

VCCIO IO Voltage

DC Input Voltage – USBDP and USBDM

DC Input Voltage – High Impedance

-0.3 to +5.8

22

V

Bi-directionals (powered from VCCIO)

DC Output Current – Outputs

mA

Table 5.1 Absolute Maximum Ratings

* If devices are stored out of the packaging beyond this time limit the devices should be baked before

use. The devices should be ramped up to a temperature of +125°C and baked for up to 17 hours.

5.2 ESD and Latch-up Specifications

Description

Specification

Human Body Mode (HBM)

Machine mode (MM)

> ± 2kV

> ± 200V

> ± 500V

> ± 200mA

Charged Device Mode (CDM)

Latch-up

Table 5.2 ESD and Latch-Up Specifications

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5.3 DC Characteristics

DC Characteristics (Ambient Temperature = -40°C to +85°C)

Parameter

Description

Minimum

2.97

1.62

8

Typical

Maximum

5.5

Units

V

Conditions

VCC Operating Supply

Voltage

VCC

5

---

8

Normal Operation

VCCIO Operating

Supply Voltage

VCC2

Icc1

3.63

V

Operating Supply

Current

8.4

mA

μA

Normal Operation

USB Suspend

Operating Supply

Current

Icc2

125

VCC must be

greater than 3V3

otherwise 3V3OUT

is an input which

must be driven

with 3.3V

3V3

3.3v regulator output

2.97

3.3

3.63

V

Table 5.3 Operating Voltage and Current

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FT240X USB 8-BIT FIFO IC Datasheet

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Parameter

Description

Minimum

Typical

Maximum Units

Conditions

Ioh = +/-2mA

2.97

VCCIO

V

I/O Drive strength*

= 4mA

I/O Drive strength*

= 8mA

2.97

VCCIO

V

Voh

Output Voltage High

I/O Drive strength*

= 12mA

I/O Drive strength*

= 16mA

Iol = +/-2mA

V

0

0.4

I/O Drive strength*

= 4mA

I/O Drive strength*

= 8mA

V

0

0.4

0.8

Vol

Output Voltage Low

I/O Drive strength*

= 12mA

I/O Drive strength*

= 16mA

Input low Switching

Threshold

Vil

LVTTL

Input High Switching

Threshold

Vih

LVTTL

2.0

Vt

Switching Threshold

V

1.49

1.15

Schmitt trigger negative

going threshold voltage

Vt-

Schmitt trigger positive

going threshold voltage

Vt+

Rpu

Rpd

Iin

V

1.64

75

Input pull-up resistance

40

190

10

KΩ

μA

Vin = 0

Vin =VCCIO

Vin = 0

Input pull-down

resistance

75

Input Leakage Current

-10

+/-1

Tri-state output leakage

current

Ioz

10

Vin = 5.5V or 0

Table 5.4 FIFO I/O Pin Characteristics VCCIO = +3.3V, (except USB PHY pins)

* The I/O drive strength and slow slew-rate are configurable in the MTP memory.

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FT240X USB 8-BIT FIFO IC Datasheet

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Parameter

Description

Minimum

Typical

Maximum Units

Conditions

Ioh = +/-2mA

2.25

VCCIO

V

I/O Drive strength*

= 4mA

I/O Drive strength*

= 8mA

2.25

VCCIO

V

Voh

Output Voltage High

I/O Drive strength*

= 12mA

I/O Drive strength*

= 16mA

Iol = +/-2mA

V

0

0.4

I/O Drive strength*

= 4mA

I/O Drive strength*

= 8mA

V

0

0.4

0.8

Vol

Output Voltage Low

I/O Drive strength*

= 12mA

I/O Drive strength*

= 16mA

Input low Switching

Threshold

Vil

LVTTL

Input High Switching

Threshold

Vih

LVTTL

0.8

Vt

Switching Threshold

V

1.1

0.8

Schmitt trigger negative

going threshold voltage

Vt-

Schmitt trigger positive

going threshold voltage

Vt+

Rpu

Rpd

Iin

V

1.2

75

Input pull-up resistance

40

190

10

KΩ

μA

Vin = 0

Vin =VCCIO

Vin = 0

Input pull-down

resistance

75

Input Leakage Current

-10

+/-1

Tri-state output leakage

current

Ioz

10

Vin = 5.5V or 0

Table 5.5 FIFO I/O Pin Characteristics VCCIO = +2.5V, (except USB PHY pins)

* The I/O drive strength and slow slew-rate are configurable in the MTP memory.

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FT240X USB 8-BIT FIFO IC Datasheet

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Parameter

Description

Minimum

Typical

Maximum Units

Conditions

Ioh = +/-2mA

1.62

VCCIO

V

I/O Drive strength*

= 4mA

I/O Drive strength*

= 8mA

1.62

VCCIO

V

Voh

Output Voltage High

I/O Drive strength*

= 12mA

I/O Drive strength*

= 16mA

Iol = +/-2mA

V

0

0.4

I/O Drive strength*

= 4mA

I/O Drive strength*

= 8mA

V

0

0.4

0.77

Vol

Output Voltage Low

I/O Drive strength*

= 12mA

I/O Drive strength*

= 16mA

Input low Switching

Threshold

Vil

LVTTL

Input High Switching

Threshold

Vih

LVTTL

1.6

Vt

Switching Threshold

V

0.77

Schmitt trigger negative

going threshold voltage

Vt-

0.557

Schmitt trigger positive

going threshold voltage

Vt+

Rpu

Rpd

Iin

V

0.893

75

Input pull-up resistance

40

190

10

KΩ

μA

Vin = 0

Vin =VCCIO

Vin = 0

Input pull-down

resistance

75

Input Leakage Current

-10

+/-1

Tri-state output leakage

current

Ioz

10

Vin = 5.5V or 0

Table 5.6 FIFO I/O Pin Characteristics VCCIO = +1.8V (except USB PHY pins)

* The I/O drive strength and slow slew-rate are configurable in the MTP memory

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FT240X USB 8-BIT FIFO IC Datasheet

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Document No.: FT_000626 Clearance No.: FTDI# 259

Parameter

Description

Minimum

Typical

Maximum Units

Conditions

Voh

Vol

Output Voltage High

Output Voltage Low

VCC-0.2

V

0.2

0.8

V

Input low Switching

Threshold

Vil

-

Input High Switching

Threshold

Vih

2.0

V

Table 5.7 USB I/O Pin (USBDP, USBDM) Characteristics

5.4 MTP Memory Reliability Characteristics

The internal 2048 Byte MTP memory has the following reliability characteristics:

Parameter

Data Retention

Write Cycle

Value

10

Unit

Years

Cycles

2,000

Read Cycle

Unlimited

Table 5.8 MTP Memory Characteristics

5.5 Internal Clock Characteristics

The internal Clock Oscillator has the following characteristics:

Value

Parameter

Unit

Minimum

11.98

Typical

12.00

Maximum

12.02

Frequency of Operation

(see Note 1)

MHz

Clock Period

83.19

45

83.33

50

83.47

55

ns

%

Duty Cycle

Table 5.9 Internal Clock Characteristics

Note 1: Equivalent to +/-1667ppm

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FT240X USB 8-BIT FIFO IC Datasheet

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6 USB Power Configurations

The following sections illustrate possible USB power configurations for the FT240X. The illustrations have

omitted pin numbers for ease of understanding since the pins differ between the FT240XS and FT240XQ

package options.

All USB power configurations illustrated apply to both package options for the FT240X device. Please refer

to Section 0 for the package option pin-out and signal descriptions.

6.1 USB Bus Powered Configuration

VCC

Ferrite

Bead

1

VCC

27R

2

USBDM

27R

3

4

USBDP

47pF

FT240X

5

47pF

RESET#

VCCIO

SHIELD

10nF

GND

3V3OUT

D

N

D

GND

N

G

A

G

VCC

100nF

+

4.7uF

100nF

GND

Figure 6.1 Bus Powered Configuration

Figure 6.1 illustrates the FT240X in a typical USB bus powered design configuration. A USB bus powered

device gets its power from the USB bus. Basic rules for USB bus power devices are as follows –

i)

ii)

iii)

On plug-in to USB, the device should draw no more current than 100mA.

In USB Suspend mode the device should draw no more than 2.5mA.

A bus powered high power USB device (one that draws more than 100mA) should use the

PWREN# to keep the current below 100mA on plug-in and 2.5mA on USB suspend.

A device that consumes more than 100mA cannot be plugged into a USB bus powered hub.

No device can draw more than 500mA from the USB bus.

iv)

v)

The power descriptors in the internal MTP memory of the FT240X should be programmed to match the

current drawn by the device.

A ferrite bead is connected in series with the USB power supply to reduce EMI noise from the FT240X and

associated circuitry being radiated down the USB cable to the USB host. The value of the Ferrite Bead

depends on the total current drawn by the application. A suitable range of Ferrite Beads is available from

Steward (www.steward.com), for example Steward Part # MI0805K601R-10.

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FT240X USB 8-BIT FIFO IC Datasheet

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6.2 Self Powered Configuration

VCC(3.3-5.25V)

1

VCC

27R

2

3

USBDM

27R

USBDP

4

47pF

FT240X

4k7

5

VBUS_SENSE

SHIELD

VCCIO

RESET#

GND

10k

GND

3V3OUT

D

N

G

A

G

GND

VCC

100nF

+

4.7uF

GND

Figure 6.2 Self Powered Configuration

Figure 6.2 illustrates the FT240X in a typical USB self powered configuration. A USB self powered device

gets its power from its own power supply, VCC, and does not draw current from the USB bus. The basic

rules for USB self powered devices are as follows –

i)

A self powered device should not force current down the USB bus when the USB host or hub

controller is powered down.

ii)

iii)

A self powered device can use as much current as it needs during normal operation and USB

suspend as it has its own power supply.

A self powered device can be used with any USB host, a bus powered USB hub or a self

powered USB hub.

The power descriptor in the internal MTP memory of the FT240X should be programmed to a value of

zero (self powered).

In order to comply with the first requirement above, the USB bus power (pin 1) is used to control the

VBUS_Sense pin of the FT240X device. When the USB host or hub is powered up an internal 1.5kΩ

resistor on USBDP is pulled up to +3.3V, thus identifying the device as a full speed device to the USB

host or hub. When the USB host or hub is powered off, VBUS_Sense pin will be low and the FT240X is

held in a suspend state. In this state the internal 1.5kΩ resistor is not pulled up to any power supply

(hub or host is powered down), so no current flows down USBDP via the 1.5kΩ pull-up resistor. Failure to

do this may cause some USB host or hub controllers to power up erratically.

Figure 6.3 illustrates a self powered design which has a +3.3V to +5.25V supply.

Note:

1. When the FT240X is in reset, the interface I/O pins are tri-stated. Input pins have internal 200kΩ

pull-up resistors to VCCIO, so they will gently pull high unless driven by some external logic.

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FT240X USB 8-BIT FIFO IC Datasheet

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6.3 USB Bus Powered with Power Switching Configuration

P Channel Power

MOSFET

Switched 5V Power to

External Logic

0.1uF

10k

1k

PWREN#

Ferrite

Bead

1

VCC

27R

2

3

USBDM

USBDP

4

47pF

FT240X

5

RESET#

VCCIO

SHIELD

10nF

3V3OUT

CBUS5

D

N

D

N

GND

G

A

G

VCC

100nF

+

4.7uF

100nF

GND

Figure 6.4 Bus Powered with Power Switching Configuration

A requirement of USB bus powered applications, is when in USB suspend mode the application draws a

total current of less than 2.5mA. This requirement includes external logic. Some external logic has the

ability to power itself down into a low current state by monitoring the PWREN# signal. For external logic

that cannot power itself down in this way, the FT240X provides a simple but effective method of turning

off power during the USB suspend mode.

Figure 6.4 shows an example of using a discrete P-Channel MOSFET to control the power to external

logic. A suitable device to do this is an International Rectifier (www.irf.com) IRLML6402, or equivalent. It

is recommended that a “soft start” circuit consisting of a 1kΩ series resistor and a 0.1μF capacitor is used

to limit the current surge when the MOSFET turns on. Without the soft start circuit it is possible that the

transient power surge, caused when the MOSFET switches on, will reset the FT240X or the USB host/hub

controller. The soft start circuit example shown in Figure 6.4 powers up with a slew rate of

approximaely12.5V/ms. Thus supply voltage to external logic transitions from GND to +5V in

approximately 400 microseconds.

As an alternative to the MOSFET, a dedicated power switch IC with inbuilt “soft-start” can be used. A

suitable power switch IC for such an application is the Micrel (www.micrel.com) MIC2025-2BM or

equivalent.

With power switching controlled designs the following should be noted:

i) The external logic to which the power is being switched should have its own reset circuitry to

automatically reset the logic when power is re-applied when moving out of suspend mode.

ii) Set the Pull-down on Suspend option in the internal FT240X MTP memory.

iii) The PWREN# pin should be used to switch the power to the external circuitry.

iv) For USB high-power bus powered applications (one that consumes greater than 100mA, and up

to 500mA of current from the USB bus), the power consumption of the application must be set in

the Max Power field in the internal FT240X MTP memory. A high-power bus powered application

uses the descriptor in the internal FT240X MTP memory to inform the system of its power

requirements.

v) PWREN# gets its VCC from VCCIO. For designs using 3V3 logic, ensure VCCIO is not powered

down using the external logic. In this case use the +3V3OUT.

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7 Application Examples

The following sections illustrate possible applications of the FT240X. The illustrations have omitted pin

numbers for ease of understanding since the pins differ between the FT240XS and FT240XQ package

options.

7.1 USB to MCU FIFO Interface

VCC

Ferrite

D0

D1

D2

D3

D4

D5

D6

D7

I/O10

I/O11

I/O12

I/O13

Bead

1

2

3

4

VCC

27R

USBDM

USBDP

+

FT240X

VCCIO

I/O14

I/O15

10nF

5

RESET#

SHIELD

I/O16

I/O17

GND

Vcc

100nF

4.7uF

RXF#

TXE#

RD#

I/O20

I/O21

I/O22

+

3V3OUT

A

G

N

D

GND

G

N

D

USBDP

USBDM

WR#

I/O23

I/O24

100nF

GND

PWREN#

Vcc

47pF

10k

GND

Figure 7.1 USB to MCU FIFO Interface

A typical example of using the FT240X as a USB to Microcontroller (MCU) FIFO interface is illustrated in

Figure 7.1. This example uses two MCU I/O ports: one port (8 bits) to transfer data and the other port (4

or 5 bits) to monitor the TXE# and RXF# status bits and generate the RD# and WR strobes to the

FT240X, when required.

Using PWREN# for this function is optional.

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7.2 Battery Charge Detection

A recent addition to the USB specification (http://www.usb.org/developers/devclass_docs/BCv1.2_011912.zip)

is to allow for additional charging profiles to be used for charging batteries in portable devices. These

charging profiles do not enumerate the USB port of the peripheral. The FT240X device will detect that a

USB compliant dedicated charging port (DCP) is connected. Once detected while in suspend mode a

battery charge detection signal is provided to allow external logic to switch to charging mode as opposed

to operation mode.

VBUS

3V3OUT

VBUS 3V3OUT

VBUS

3V3OUT

0.1uF

600R/2A

3V3OUT

CN USB

VBUS

1

2

3

4

5

GND

D-

D+

ID

DM

DP

27R

GND

RESET#

10nF

N.F.

BCD

0.1uF

CBUS0

FT240X

0R

SLD GND

GND

VBUS VBUS

VBUS

VBATT

4.7uF

0.1uF

1

2

3

4

5

10

9

8

7

6

CHRG

VCC

FAULT

TIMER

GND

ACPR

GND GND

BAT

SHDN

PROG

NTC

1

+

NCT

-

BCD

NTC

TB3.5mm

LTC4053EDD

0.1uF

1uF

1R

2K2

1K5

GND

GND GND

1A when connected to a dedicated charger port

0A when enumerated

0A when not enumerated and not in sleep

0A when in sleep

EEPROM Setting

VBUS

Battery Options

X-Chip Pin

CBUS0

Function

BCD

Battery Charger Enable

Force Power Enable

X

NTC

JP1

NCT Available

4K32 1%

De-acticate Sleep

1-2 NCT Enabled

2-3 NCT Disabled (Default)

JP1

SIP-3

JUMPER-2mm

GND

Figure 7.2 USB Battery Charging Detection (1 pin)

To use the FT240X with battery charging detection the CBUS pins must be reprogrammed to allow for the

BCD Charger output to switch the external charger circuitry on. The CBUS pins are configured in the

internal MTP memory with the free utility FTPROG. If the charging circuitry requires an active low signal

to enable it, the CBUS pin can be programmed to BCD Charger# as an alternative.

When connected to a USB compliant dedicated charging port (DCP, as opposed to a standard USB host)

the device USB signals will be shorted together and the device suspended. The BCD charger signal will

bring the LTC4053 out of suspend and allow battery charging to start. The charge current in the example

above is 1A as defined by the resistance on the PROG pin.

Alternatively the PWREN# And SLEEP pins may be used to control the LTC4053 such that a battery may

be charged from a standard host (low current) or from a dedicated charging port (high current). In such

a design as shown above the charge current would need to be limited to 0.4A to ensure that the USB

host power limit is not exceeded.

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VBUS

3V3OUT

VBUS 3V3OUT

U1

3V3OUT

0.1uF

600R/2A

CN USB

VBUS

1

2

3

4

5

GND

D-

D+

ID

DM

DP

27R

GND

RESET#

10nF

N.F.

0.1uF

0R

SLEEP#

PWREN#

CBUS5

CBUS6

SLD GND

GND

FT240X

GND

VBUS VBUS

VBUS

VBATT

4.7uF

0.1uF

1

2

3

4

5

10

CHRG

VCC

FAULT

TIMER

GND

ACPR

BAT

SHDN

PROG

NTC

9

8

7

6

GND GND

1

+

NCT

-

SLEEP#

NTC

TB3.5mm

LTC4053EDD

0.1uF

1uF

2K2

16K5 1%

4K32 1%

PWREN#

1R

GND

GND GND

0.4A when connected to a dedicated charger port

0.4A when enumerated

0.1A when not enumerated and not in sleep mode

0A when in sleep mode

EEPROM Setting

VBUS

Battery Options

X-Chip Pin

CBUS5

CBUS6

Function

SLEEP#

PWREN#

Battery Charger Enable

Force Power Enable

De-acticate Sleep

X

NTC

JP1

NCT Available

4K32 1%

1-2 NCT Enabled

2-3 NCT Disabled (Default)

X

JP1

SIP-3

JUMPER-2mm

GND

Figure 7.3 USB Battery Charging Detection (2 pin)

In the example above the FT240X SLEEP pin is used to enable/disable the LTC4053, while the PWREN#

signal alters the charging current by altering the resistance on the LTC4053 PROG pin.

To calculate the equivalent resistance on the LTC4053 PROG pin select a charge current, then Res =

1500V/I_chg

For more configuration options of the LTC4053 refer to:

AN_175_Battery Charging Over USB

Note: If the FT240X is connected to a standard host port such that the device is enumerated the battery

charge detection signal is inactive as the device will not be in suspend.

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8 Internal MTP Memory Configuration

The FT240X includes an internal MTP memory which holds the USB configuration descriptors, other

configuration data for the chip and also user data areas. Following a power-on reset or a USB reset the

FT240X will scan its internal MTP memory and read the USB configuration descriptors stored there.

In many cases, the default values programmed into the MTP memory will be suitable and no re-

programming will be necessary. The defaults can be found in Section 8.1.

The MTP memory in the FT240X can be programmed over USB if the values need to be changed for a

particular application. Further details of this are provided from section 8.2 onwards.

Users who do not have their own USB Vendor ID but who would like to use a unique Product ID in their

design can apply to FTDI for a free block of unique PIDs. See TN_100 – USB Vendor ID/Product ID

Guidelines for more details.

8.1 Default Values

The default factory programmed values of the internal MTP memory are shown in Table 8.1.

Parameter

Value

Notes

USB Vendor ID (VID)

USB Product UD (PID)

Serial Number Enabled

0403h

6015h

Yes

FTDI default VID (hex)

FTDI default PID (hex)

A unique serial number is generated and

programmed into the MTP memory during device

final test.

Serial Number

See Note

Disabled

Enabling this option will make the device pull down

on the FIFO interface lines when in USB suspend

mode (PWREN# is high).

Pull down I/O Pins in USB

Suspend

Manufacturer Name

Product Description

Max Bus Power Current

Power Source

FTDI

FT240X USB FIFO

90mA

Bus Powered

FT240X

Device Type

Returns USB 2.0 device description to the host.

Note: The device is a USB 2.0 Full Speed device

(12Mb/s) as opposed to a USB 2.0 High Speed

device (480Mb/s).

USB Version

0200

Taking SIWU# low will wake up the USB host

controller from suspend in approximately 20 ms.

When enabled.

Remote Wake Up

Disabled

DBUS Drive Current

Strength

4mA

Slow

Options are 4mA, 8mA, 12mA, 16mA

Options are slow or fast

DBUS slew rate

28

FT240X USB 8-BIT FIFO IC Datasheet

Version 1.3

Document No.: FT_000626 Clearance No.: FTDI# 259

Parameter

Value

Notes

DBUS Schmitt Trigger

Enable

Normal

Options are normal or Schmitt

CBUS Drive Current

Strength

4mA

Options are 4mA, 8mA, 12mA, 16mA

Options are slow or fast

CBUS slew rate

Slow

CBUS Schmitt Trigger

Enable

Normal

Options are normal or Schmitt

Enables the high drive level on the FIFO data bus

and control I/O pins.

High Current I/Os

Load VCP Driver

CBUS5

Disabled

Enabling this will load the VCP driver interface for

the device.

Disabled

Used to detect when the device is connected to a

USB host and power is available.

VBUS_Sense

Keep_Awake#

Prevents the device from entering suspend state

when unplugged.

CBUS6

Table 8.1 Default Internal MTP Memory Configuration

8.2 Methods of Programming the MTP Memory

8.2.1 Programming the MTP memory over USB

The MTP memory on all FT-X devices can be programmed over USB. This method is the same as for the

EEPROM on other FTDI devices such as the FT232R. No additional hardware, connections or programming

voltages are required. The device is simply connected to the host computer in the same way that it would

be for normal applications, and the FT_Prog utility is used to set the required options and program the

device.

The FT_Prog utility is provided free-of-charge from the FTDI website, and can be found at the link below.

The user guide is also available at this link. Note that the FT-X devices require FT_Prog version 2.5 or

later.

http://www.ftdichip.com/Support/Utilities.htm#FT_Prog

Additionally, D2XX commands can be used to program the MTP memory from within user applications.

For more information on the commands available, please see the D2XX Programmers Guide below.

http://www.ftdichip.com/Support/Documents/ProgramGuides/D2XX_Programmer's_Guide(FT_000071).p

df

29

FT240X USB 8-BIT FIFO IC Datasheet

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Document No.: FT_000626 Clearance No.: FTDI# 259

8.3 Memory Map

The FT-X family MTP memory has various areas which come under three main categories:



User Memory Area

Configuration Memory Area (writable)

Configuration Memory Area (non-writable)

Memory Area Description

Word Address

0x3FF - 0x80

User Memory Area 2

Accessible via USB

Configuration Memory Area

Accessible via USB

0x7E - 0x50

0x4E - 0x40

0x3E - 0x12

0x10 - 0x00

Configuration Memory Area

Cannot be written

User Memory Area 1

Accessible via USB

Configuration Memory Area

Accessible via USB

Figure 8.1: Simplified memory map for the FT-X

User Memory Area

The User Memory Areas are highlighted in Green on the memory map. They can be read and written via

USB on the FT240X. All locations within this range are freely programmable; no areas have special

functions and there is no checksum for the user area.

Note that the application should take into account the specification for the number of write cycles in

Section 5.4 if it will be writing to the MTP memory multiple times.

Configuration Memory Area (writable)

This area stores the configuration data for the device, including the data which is returned to the host in

the configuration descriptors (e.g. the VID, PID and string descriptions) and also values which set the

hardware configuration (the signal assigned to each CBUS pin for example).

These values can have a significant effect on the behaviour of the device. Steps must be taken to ensure

that these locations are not written to un-intentionally by an application which is intended to access only

the user area.

This area is included in a checksum which covers configuration areas of the memory, and so changing

any value can also cause this checksum to fail.

Configuration Memory Area (non-writable)

This is a reserved area and the application should not write to this area of memory. Any attempt to write

these locations will fail.

30

FT240X USB 8-BIT FIFO IC Datasheet

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Document No.: FT_000626 Clearance No.: FTDI# 259

9 Package Parameters

The FT240X is available in two different packages. The FT240XS is the SSOP-24 option and the FT240XQ

is the QFN-24 package option. The solder reflow profile for both packages is described in Section 9.5.

9.1 SSOP-24 Package Mechanical Dimensions

Figure 9.1 SSOP-24 Package Dimensions

The FT240XS is supplied in a RoHS compliant 24 pin SSOP package. The package is lead (Pb) free and

uses a ‘green’ compound. The package is fully compliant with European Union directive 2002/95/EC.

This package is nominally 8.66mm x 3.91 mm body (8.66mm x 5.99mm including pins). The pins are on

a 0.635 mm pitch. The above mechanical drawing shows the SSOP-24 package.

The date code format is YYXX where XX = 2 digit week number, YY = 2 digit year number.

The code XXXXXXXXXXXX is the manufacturing LOT code.

31

FT240X USB 8-BIT FIFO IC Datasheet

Version 1.3

Document No.: FT_000626 Clearance No.: FTDI# 259

9.2 SSOP-24 Package Markings

24

13

Line 1 – FTDI Logo

-B

Line 2 – Date Code, Revision

Line 3 – Wafer Lot Number

FT240XS

Line 4 – FTDI Part Number

1

12

Figure 9.2 SSOP-24 Package Markings

Notes:

1. YYWW = Date Code, where YY is year and WW is week number

2. Marking alignment should be centre justified

3. Laser Marking should be used

4. All marking dimensions should be marked proportionally. Marking font should be using Greatek

standard font (Roman Simplex)

32

FT240X USB 8-BIT FIFO IC Datasheet

Version 1.3

Document No.: FT_000626 Clearance No.: FTDI# 259

9.3 QFN-24 Package Mechanical Dimensions

Figure 9.3 QFN-24 Package Dimensions

The FT240XQ is supplied in a RoHS compliant leadless QFN-24 package - WQFN(X424), with pad size

114x114. The package is lead ( Pb ) free, and uses a ‘green’ compound. The package is fully compliant

with European Union directive 2002/95/EC.

This package is nominally 4.0mm x 4.0mm. The solder pads are on a 0.50mm pitch. The above

mechanical drawing shows the QFN-24 package. All dimensions are in millimetres.

The centre pad on the base of the FT240XQ is internally connected to GND, and the PCB should not have

tracking on the top layer in this area.

The date code format is YYXX where XX = 2 digit week number, YY = 2 digit year number.

The code XXXXXXX is the manufacturing LOT code.

33

FT240X USB 8-BIT FIFO IC Datasheet

Version 1.3

Document No.: FT_000626 Clearance No.: FTDI# 259

9.4 QFN-24 Package Markings

19

1

18

Line 1 – FTDI Logo

FTD

XXXXXXXXXX

FT240XQ

Line 2 – Wafer Lot Number

Line 3 – FTDI Part Number

Line 4 – Date Code, Revision

YYWW-B

7

12

Figure 9.4 QFN-24 Package Markings

Notes:

1. YYWW = Date Code, where YY is year and WW is week number

2. Marking alignment should be centre justified

3. Laser Marking should be used

4. All marking dimensions should be marked proportionally. Marking font should be using Greatek

standard font (Roman Simplex)

34

FT240X USB 8-BIT FIFO IC Datasheet

Version 1.3

Document No.: FT_000626 Clearance No.: FTDI# 259

9.5 Solder Reflow Profile

The FT240X is supplied in Pb free 24 LD SSOP and QFN-24 packages. The recommended solder reflow

profile for both package options is shown in 9.5.

t_p

T

p

Critical Zone: when

T is in the range

Ramp Up

T to T

p

L

T

L

t_L

T Max

S

Ramp

Down

T Min

S

t_S

Preheat

25

T = 25º C to T_P

Time, t (seconds)

Figure 9.5 FT240X Solder Reflow Profile

The recommended values for the solder reflow profile are detailed in Table 9.1. Values are shown for both

a completely Pb free solder process (i.e. the FT240X is used with Pb free solder), and for a non-Pb free

solder process (i.e. the FT240X is used with non-Pb free solder).

Profile Feature

Pb Free Solder Process

Non-Pb Free Solder Process

Average Ramp Up Rate (T_sto T_p)

3°C / second Max.

3°C / Second Max.

Preheat

- Temperature Min (T_sMin.)

- Temperature Max (T_sMax.)

- Time (t_sMin to t_sMax)

100°C

150°C

60 to 120 seconds

150°C

200°C

60 to 120 seconds

Time Maintained Above Critical

Temperature T_L:

- Temperature (T_L)

217°C

60 to 150 seconds

183°C

60 to 150 seconds

- Time (t_L)

Peak Temperature (T_p)

260°C

240°C

Time within 5°C of actual Peak

Temperature (t_p)

20 to 40 seconds

6°C / second Max.

8 minutes Max.

20 to 40 seconds

6°C / second Max.

6 minutes Max.

Ramp Down Rate

Time for T= 25°C to Peak Temperature,

T_p

Table 9.1 Reflow Profile Parameter Values

35

FT240X USB 8-BIT FIFO IC Datasheet

Version 1.3

Document No.: FT_000626 Clearance No.: FTDI# 259

10 Contact Information

Branch Office – Hillsboro, Oregon, USA

Head Office – Glasgow, UK

Future Technology Devices International Limited

(USA)

7130 SW Fir Loop

Tigard, OR 97223

USA

Tel: +1 (503) 547 0988

Fax: +1 (503) 547 0987

Future Technology Devices International Limited

Unit 1, 2 Seaward Place, Centurion Business Park

Glasgow G41 1HH

United Kingdom

Tel: +44 (0) 141 429 2777

Fax: +44 (0) 141 429 2758

E-mail (Sales)

E-mail (Support)

E-mail (General Enquiries) admin1@ftdichip.com

sales1@ftdichip.com

support1@ftdichip.com

E-Mail (Sales)

E-Mail (Support)

E-Mail (General Enquiries)

us.sales@ftdichip.com

us.support@ftdichip.com

us.admin@ftdichip.com

Branch Office – Shanghai, China

Branch Office – Taipei, Taiwan

Future Technology Devices International Limited

(China)

Room 408, 317 Xianxia Road,

Shanghai, 200051

Future Technology Devices International Limited

(Taiwan)

2F, No. 516, Sec. 1, NeiHu Road

Taipei 114

Taiwan , R.O.C.

Tel: +886 (0) 2 8791 3570

Fax: +886 (0) 2 8791 3576

China

Tel: +86 21 62351596

Fax: +86 21 62351595

E-mail (Sales)

E-mail (Support)

E-mail (General Enquiries)

cn.sales@ftdichip.com

cn.support@ftdichip.com

cn.admin@ftdichip.com

E-mail (Sales)

E-mail (Support)

E-mail (General Enquiries) tw.admin1@ftdichip.com

tw.sales1@ftdichip.com

tw.support1@ftdichip.com

Web Site

http://ftdichip.com

System and equipment manufacturers and designers are responsible to ensure that their systems, and any Future Technology

Devices International Ltd (FTDI) devices incorporated in their systems, meet all applicable safety, regulatory and system-level

performance requirements. All application-related information in this document (including application descriptions, suggested

FTDI devices and other materials) is provided for reference only. While FTDI has taken care to assure it is accurate, this

information is subject to customer confirmation, and FTDI disclaims all liability for system designs and for any applications

assistance provided by FTDI. Use of FTDI devices in life support and/or safety applications is entirely at the user’s risk, and the

user agrees to defend, indemnify and hold harmless FTDI from any and all damages, claims, suits or expense resulting from

such use. This document is subject to change without notice. No freedom to use patents or other intellectual property rights is

implied by the publication of this document. Neither the whole nor any part of the information contained in, or the product

described in this document, may be adapted or reproduced in any material or electronic form without the prior written consent

of the copyright holder. Future Technology Devices International Ltd, Unit 1, 2 Seaward Place, Centurion Business Park,

Glasgow G41 1HH, United Kingdom. Scotland Registered Company Number: SC136640

36

FT240X USB 8-BIT FIFO IC Datasheet

Version 1.3

Document No.: FT_000626 Clearance No.: FTDI# 259

Appendix A - References

Useful Application Notes

http://www.ftdichip.com/Documents/AppNotes/AN232R-01_FT232RBitBangModes.pdf

http://www.ftdichip.com/Documents/AppNotes/AN_107_AdvancedDriverOptions_AN_000073.pdf

http://www.ftdichip.com/Documents/AppNotes/AN_121_FTDI_Device_EEPROM_User_Area_Usage.pdf

http://www.ftdichip.com/Documents/AppNotes/AN_120_Aliasing_VCP_Baud_Rates.pdf

http://www.ftdichip.com/Documents/AppNotes/AN_100_Using_The_FT232_245R_With_External_Osc(FT_

000067).pdf

http://www.ftdichip.com/Resources/Utilities/AN_126_User_Guide_For_FT232_Factory%20test%20utility.

pdf

http://www.ftdichip.com/Documents/AppNotes/AN232B-05_BaudRates.pdf

http://www.ftdichip.com/Documents/InstallGuides.htm

http://www.ftdichip.com/Support/Documents/TechnicalNotes/TN_100_USB_VID-PID_Guidelines.pdf

http://www.ftdichip.com/Support/Documents/AppNotes/AN_175_Battery%20Charging%20Over%20USB

%20with%20FTEX%20Devices.pdf

http://www.usb.org/developers/devclass_docs/BCv1.2_011912.zip

37

FT240X USB 8-BIT FIFO IC Datasheet

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Document No.: FT_000626 Clearance No.: FTDI# 259

Appendix B - List of Figures and Tables

List of Figures

Figure 2.1 FT240X Block Diagram ...................................................................................................4

Figure 3.1 SSOP Package Pin Out and Schematic Symbol...................................................................7

Figure 3.2 QFN-24 Package Pin Out and schematic symbol ................................................................9

Figure 3.3 FIFO Read Cycle.......................................................................................................... 12

Figure 3.4 FIFO Write Cycle ......................................................................................................... 13

Figure 6.1 Bus Powered Configuration ........................................................................................... 22

Figure 6.2 Self Powered Configuration........................................................................................... 23

Figure 6.3 illustrates a self powered design which has a +3.3V to +5.25V supply. .............................. 23

Figure 6.4 Bus Powered with Power Switching Configuration ............................................................ 24

Figure 7.1 USB to MCU FIFO Interface........................................................................................... 25

Figure 7.2 USB Battery Charging Detection (1 pin).......................................................................... 26

Figure 7.3 USB Battery Charging Detection (2 pin).......................................................................... 27

Figure 8.1: Simplified memory map for the FT-X ............................................................................ 30

Figure 9.1 SSOP-24 Package Dimensions....................................................................................... 31

Figure 9.2 SSOP-24 Package Markings .......................................................................................... 32

Figure 9.3 QFN-24 Package Dimensions......................................................................................... 33

Figure 9.4 QFN-24 Package Markings ............................................................................................ 34

Figure 9.5 FT240X Solder Reflow Profile......................................................................................... 35

List of Tables

Table 3.1 USB Interface Group .......................................................................................................7

Table 3.2 Power and Ground Group.................................................................................................7

Table 3.3 Miscellaneous Signal Group..............................................................................................8

Table 3.4 FIFO Interface Group (see note 2) ....................................................................................8

Table 3.5 USB Interface Group .......................................................................................................9

Table 3.6 Power and Ground Group.................................................................................................9

Table 3.7 Miscellaneous Signal Group............................................................................................ 10

Table 3.8 FIFO Interface Group (see note 2) .................................................................................. 10

Table 3.9 CBUS Configuration Control ........................................................................................... 11

Table 3.10 FIFO Read Cycle Timings ............................................................................................. 12

Table 3.11 FIFO Write Cycle......................................................................................................... 13

Table 5.1 Absolute Maximum Ratings............................................................................................ 16

Table 5.2 ESD and Latch-Up Specifications .................................................................................... 16

Table 5.3 Operating Voltage and Current ....................................................................................... 17

Table 5.4 FIFO I/O Pin Characteristics VCCIO = +3.3V, (except USB PHY pins) .................................. 18

Table 5.5 FIFO I/O Pin Characteristics VCCIO = +2.5V, (except USB PHY pins) .................................. 19

Table 5.6 FIFO I/O Pin Characteristics VCCIO = +1.8V (except USB PHY pins) ................................... 20

Table 5.7 USB I/O Pin (USBDP, USBDM) Characteristics .................................................................. 21

Table 5.8 MTP Memory Characteristics........................................................................................... 21

Table 5.9 Internal Clock Characteristics......................................................................................... 21

38

FT240X USB 8-BIT FIFO IC Datasheet

Version 1.3

Document No.: FT_000626 Clearance No.: FTDI# 259

Table 8.1 Default Internal MTP Memory Configuration ..................................................................... 29

Table 9.1 Reflow Profile Parameter Values ..................................................................................... 35

39

FT240X USB 8-BIT FIFO IC Datasheet

Version 1.3

Document No.: FT_000626 Clearance No.: FTDI# 259

Appendix C - Revision History

Document Title:

USB 8-BIT FIFO IC FT240X

Document Reference No.:

Clearance No.:

FT_000626

FTDI# 259

Product Page:

http://www.ftdichip.com/FT-X.htm

Send Feedback

Document Feedback:

Version 1.0

Version 1.1

Initial Datasheet Created

Replaced VCC_CORE with VCORE

07/02/12

Updated 24 pin SSOP dimensions

22/02/12

17/04/12

Version 1.2

Version 1.3

Clarified MTP Reliability in table 5.8

Edited Table 8.1, changed “Load VCP Driver” to

Disabled

Removed references to LED signals on the CBUS pins

in table 3.9 as these are not available on the FT240X.

24/09/2012

14/02/2013

updated fron t page to clarify 5V tolerant

Updated TID

Updated US address

40


型号：	FT240XQ-R
厂家：	ETC
描述：	Future Technology Devices International Ltd
文件：	总40页 (文件大小：754K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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