FT24C08A-UDR-B [ETC]

Two-Wire Serial EEPROM 4K, 8K and 16K (8-bit wide);


型号：	FT24C08A-UDR-B
厂家：	ETC
描述：	Two-Wire Serial EEPROM 4K, 8K and 16K (8-bit wide) 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
文件：	总20页 (文件大小：322K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

24C04A, 24C08A, 24C16A

Two-Wire Serial EEPROM

4K, 8K and 16K (8-bit wide)

FEATURES



Low voltage and low power operations:

FT24C04A/08A/16A: V_CC= 1.8V to 5.5V





Maximum Standby current < 1µA (typically 0.02µA and 0.06µA @ 1.8V and 5.5V respectively).

16 bytes page write mode.

Partial page write operation allowed.

Internally organized: 512  8 (4K), 1024  8 (8K), 2048  8 (16K).

Standard 2-wire bi-directional serial interface.

Schmitt trigger, filtered inputs for noise protection.

Self-timed Write Cycle (5ms maximum).

1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) Compatibility.

Automatic erase before write operation.

Write protect pin for hardware data protection.

High reliability: typically 1, 000,000 cycles endurance.

100 years data retention.

Industrial temperature range (-40^oC to 85^oC).

Standard 8-pin DIP/SOP/TSSOP/DFN/MSOP and 5-pin SOT-23/TSOT-23 Pb-free packages.

DESCRIPTION

The FT24C04A/08A/16A series are 4096/8192/16384 bits of serial Electrical Erasable and Programmable Read Only

Memory, commonly known as EEPROM. They are organized as 512/1024/2048 words of 8 bits (1 byte) each. The

devices are fabricated with proprietary advanced CMOS process for low power and low voltage applications. These

devices are available in standard 8-lead DIP, 8-lead SOP, 8-lead TSSOP, 8-lead DFN, 8-lead MSOP, and 5-lead SOT-

23/TSOT-23 packages. A standard 2-wire serial interface is used to address all read and write functions. Our

extended V_CCrange (1.8V to 5.5V) devices enables wide spectrum of applications.

PIN CONFIGURATION

Pin Name

A2, A1, A0

SDA

Pin Function

Device Address Inputs

Serial Data Input / Open Drain Output

Serial Clock Input

SCL

Write Protect

No-Connect

DS3001M-page1

24C04A, 24C08A, 24C16A

All these packaging types come in conventional or Pb-free certified.

FT24C04A/08A/16A

VCC

SCL

GND

SDA

SCL

SDA

VCC

GND

8L DIP

SOT-23-5

8L SOP

TSOT-23-5

8L TSSOP

8L DFN

8L MSOP

ABSOLUTE MAXIMUM RATINGS

Industrial operating temperature:

Storage temperature:

-40^oC to 85^oC

-50^oC to 125^oC

Input voltage on any pin relative to ground:

Maximum voltage:

-0.3V to V_CC+ 0.3V

ESD protection on all pins:

>2000V

* Stresses exceed those listed under “Absolute Maximum Rating” may cause permanent damage to the device.

Functional operation of the device at conditions beyond those listed in the specification is not guaranteed. Prolonged

exposure to extreme conditions may affect device reliability or functionality.

DS3001M-page2

24C04A, 24C08A, 24C16A

PIN DESCRIPTIONS

(A) SERIAL CLOCK (SCL)

The rising edge of this SCL input is to latch data into the EEPROM device while the falling edge of this clock is to

clock data out of the EEPROM device.

(B) DEVICE / CHIP SELECT ADDRESSES (A2, A1, A0)

These are the chip select input signals for the serial EEPROM devices. Typically, these signals are hardwired to

either V_IHor V_IL. If left unconnected, they are internally recognized as V_IL. FT24C04A has A0 pin as no-connect.

FT24C08A has both A0 and A1 pins as no-connect. For FT24C16A, all device address pins (A0-A2) are no-

connect.

SDA data line is a bi-directional signal for the serial devices. It is an open drain output signal and can be wired-

OR with other open-drain output devices.

(D) WRITE PROTECT (WP)

The FT24C04A/08A/16A devices have a WP pin to protect the whole EEPROM array from programming.

Programming operations are allowed if WP pin is left un-connected or input to V_IL. Conversely all programming

functions are disabled if WP pin is connected to V_IHor V_CC. Read operations is not affected by the WP pin’s input

level.

Table A

Chip Select/Device

Address Pins Used

Max number of similar

devices on the same bus

Device

No-Connect Pins

FT24C04A

FT24C08A

FT24C16A

A2, A1

A2,

A1, A0

(None)

A2, A1, A0

MEMORY ORGANIZATION

The FT24C04A/08A/16A devices have 32/64/128 pages respectively. Since each page has 16 bytes, random word

addressing to FT24C04A/08A/16A will require 9/10/11 bits data word addresses respectively.

DEVICE OPERATION

(A) SERIAL CLOCK AND DATA TRANSITIONS

The SDA pin is typically pulled to high by an external resistor. Data is allowed to change only when Serial clock

SCL is at V_IL. Any SDA signal transition may interpret as either a START or STOP condition as described below.

(B) START CONDITION

With SCL  V_IH, a SDA transition from high to low is interpreted as a START condition. All valid commands

must begin with a START condition.

DS3001M-page3

24C04A, 24C08A, 24C16A

With SCL  V_IH, a SDA transition from low to high is interpreted as a STOP condition. All valid read or write

commands end with a STOP condition. The device goes into the STANDBY mode if it is after a read command.

A STOP condition after page or byte write command will trigger the chip into the STANDBY mode after the self-

timed internal programming finish.

(D) ACKNOWLEDGE

The 2-wire protocol transmits address and data to and from the EEPROM in 8 bit words. The EEPROM

acknowledges the data or address by outputting a "0" after receiving each word. The ACKNOWLEDGE signal

occurs on the 9^thserial clock after each word.

(E) STANDBY MODE

The EEPROM goes into low power STANDBY mode after a fresh power up, after receiving a STOP bit in read

mode, or after completing a self-time internal programming operation.

Figure 1: Timing diagram for START and STOP conditions

SCL

SDA

START

Data

STOP

Condition

Valid Transition

Figure 2: Timing diagram for output ACKNOWLEDGE

START Condition

SCL

Data in

Data out

ACK

DS3001M-page4

24C04A, 24C08A, 24C16A

DEVICE ADDRESSING

The 2-wire serial bus protocol mandates an 8 bits device address word after a START bit condition to invoke valid read

or write command. The first four most significant bits of the device address must be 1010, which is common to all

serial EEPROM devices. The next three bits are device address bits. These three device address bits (5^th, 6^thand 7^th) are

to match with the external chip select/address pin states. If a match is made, the EEPROM device outputs an

ACKNOWLEDGE signal after the 8^thread/write bit, otherwise the chip will go into STANDBY mode. However,

matching may not be needed for some or all device address bits (5^th, 6^thand 7^th) as noted below. The last or 8th bit is a

read/write command bit. If the 8th bit is at V_IHthen the chip goes into read mode. If a “0” is detected, the device enters

programming mode.

FT24C04A uses A2 (5^th) and A1 (6^th) device address bits. Only four FT24C04A devices can be wired-OR on the same

2-wire bus. Their corresponding chip select address pins A2 and A1 must be hard wired and coded from 00 (b) to 11

(b). Chip select address pin A0 is not used.

FT24C08A uses only A2 (5^th) device address bit. Only two FT24C08A devices can be wired-OR on the same 2-wire

bus. Their corresponding chip select address pin A2 must be hard-wired and coded from 0 (b) to 1 (b). Chip select

address pins A1 and A0 are not used.

FT24C16A does not use any device address bit. Only one FT24C16A device can be used on the on 2-wire bus. Chip

Select address pins A2, A1, and A0 are not used.

WRITE OPERATIONS

(A) BYTE WRITE

A byte write operation starts when a micro-controller sends a START bit condition, follows by a proper EEPROM

device address and then a write command. If the device address bits match the chip select address, the EEPROM

device will acknowledge at the 9^thclock cycle. The micro-controller will then send the rest of the lower 8 bits word

address. At the 18^thcycle, the EEPROM will acknowledge the 8-bit address word. The micro-controller will then

transmit the 8 bit data. Following an ACKNOWLDEGE signal from the EEPROM at the 27^thclock cycle, the

micro-controller will issue a STOP bit. After receiving the STOP bit, the EEPROM will go into a self-timed

programming mode during which all external inputs will be disabled. After a programming time of T_WC, the byte

programming will finish and the EEPROM device will return to the STANDBY mode.

(B) PAGE WRITE

A page write is similar to a byte write with the exception that one to sixteen bytes can be programmed along the

same page or memory row. All FT24C04A/08A/16A are organized to have 16 bytes per memory row or page.

With the same write command as the byte write, the micro-controller does not issue a STOP bit after sending the

1^stbyte data and receiving the ACKNOWLEDGE signal from the EEPROM on the 27^thclock cycle. Instead it

sends out a second 8-bit data word, with the EEPROM acknowledging at the 36^thcycle. This data sending and

EEPROM acknowledging cycle repeats until the micro-controller sends a STOP bit after the n  9^thclock cycle.

After which the EEPROM device will go into a self-timed partial or full page programming mode. After the page

programming completes after a time of T_WC, the devices will return to the STANDBY mode.

DS3001M-page5

24C04A, 24C08A, 24C16A

The least significant 4 bits of the word address (column address) increments internally by one after receiving each

data word. The rest of the word address bits (row address) do not change internally, but pointing to a specific

memory row or page to be programmed. The first page write data word can be of any column address. Up to 16

data words can be loaded into a page. If more then 16 data words are loaded, the 17^thdata word will be loaded to

the 1st data word column address. The 18^thdata word will be loaded to the 2^nddata word column address and so on.

In other word, data word address (column address) will “roll” over the previously loaded data.

ACKNOWLEDGE polling may be used to poll the programming status during a self-timed internal programming.

By issuing a valid read or write address command, the EEPROM will not acknowledge at the 9^thclock cycle if the

device is still in the self-timed programming mode. However, if the programming completes and the chip has

returned to the STANDBY mode, the device will return a valid ACKNOWLEDGE signal at the 9^thclock cycle.

READ OPERATIONS

The read command is similar to the write command except the 8^thread/write bit in address word is set to “1”. The three

read operation modes are described as follows:

(A) CURRENT ADDRESS READ

The EEPROM internal address word counter maintains the last read or write address plus one if the power supply

to the device has not been cut off. To initiate a current address read operation, the micro-controller issues a

START bit and a valid device address word with the read/write bit (8^th) set to “1”. The EEPROM will response

with an ACKNOWLEDGE signal on the 9^thserial clock cycle. An 8-bit data word will then be serially clocked out.

The internal address word counter will then automatically increase by one. For current address read the micro-

controller will not issue an ACKNOWLEDGE signal on the 18^thclock cycle. The micro-controller issues a valid

STOP bit after the 18^thclock cycle to terminate the read operation. The device then returns to STANDBY mode.

(B) SEQUENTIAL READ

The sequential read is very similar to current address read. The micro-controller issues a START bit and a valid

device address word with read/write bit (8^th) set to “1”. The EEPROM will response with an ACKNOWLEDGE

signal on the 9^thserial clock cycle. An 8-bit data word will then be serially clocked out. Meanwhile the internally

address word counter will then automatically increase by one. Unlike current address read, the micro-controller

sends an ACKNOWLEDGE signal on the 18^thclock cycle signaling the EEPROM device that it wants another byte

of data. Upon receiving the ACKNOWLEDGE signal, the EEPROM will serially clocked out an 8-bit data word

based on the incremented internal address counter. If the micro-controller needs another data, it sends out an

ACKNOWLEDGE signal on the 27^thclock cycle. Another 8-bit data word will then be serially clocked out. This

sequential read continues as long as the micro-controller sends an ACKNOWLEDGE signal after receiving a new

data word. When the internal address counter reaches its maximum valid address, it rolls over to the beginning of

the memory array address. Similar to current address read, the micro-controller can terminate the sequential read

by not acknowledging the last data word received, but sending a STOP bit afterwards instead.

Random read is a two-steps process. The first step is to initialize the internal address counter with a target read

address using a “dummy write” instruction. The second step is a current address read.

To initialize the internal address counter with a target read address, the micro-controller issues a START bit first,

follows by a valid device address with the read/write bit (8^th) set to “0”. The EEPROM will then acknowledge.

The micro-controller will then send the address word. Again the EEPROM will acknowledge. Instead of

sending a valid written data to the EEPROM, the micro-controller performs a current address read instruction to

read the data. Note that once a START bit is issued, the EEPROM will reset the internal programming process and

continue to execute the new instruction - which is to read the current address.

DS3001M-page6

24C04A, 24C08A, 24C16A

DS3001M-page7

24C04A, 24C08A, 24C16A

Figure 8: SCL and SDA Bus Timing

AC CHARACTERISTICS

1.8 V

Min

2.5-5.0 V

Symbol

Parameter

Unit

Max

Min

Max

Clock frequency, SCL

Clock pulse width low

Clock pulse width high

Noise suppression time⁽¹⁾

Clock low to data out valid

400

1000

kHz

µs

f_SCL

t_LOW

t_HIGH

t_I

1.3

0.6

0.4

µs

180

0.9

120

0.3

1.3

0.2

0.5

0.55

t_AA

Time the bus must be free before a

new transmission can start⁽¹⁾

µs

t_BUF

START hold time

START set-up time

Data in hold time

Data in set-up time

Input rise time⁽¹⁾

Input fall time⁽¹⁾

0.6

0.25

µs

t_HD.STA

t_SU.STA

t_HD.DAT

t_SU.DAT

t_R

µs

100

0.3

µs

300

100

t_F

STOP set-up time

Date out hold time

Write cycle time

0.6

0.25

µs

t_SU.STO

t_DH

Endurance⁽¹⁾25^oC, Page Mode, 3.3V

1,000,000

Write Cycles

Notes: 1. This Parameter is expected by characterization but are not fully screened by test.

2. AC Measurement conditions:

R_L(Connects to Vcc): 1.3KΩ

Input Pulse Voltages: 0.3Vcc to 0.7Vcc

Input and output timing reference Voltages: 0.5Vcc

DS3001M-page8

24C04A, 24C08A, 24C16A

DC CHARACTERISTICS

Symbol

Parameter

Test Conditions

Min

Typical

Max

Units

V_CC1

I_CC

1.8

5.5

1.0

µA

24CA supply V_CC

Supply read current

Supply write current

Supply current

_CC@ 5.0V SCL = 400 kHz

_CC@ 1.8V, V_IN= V_CCor V_SS

_CC@ 2.5V, V_IN= V_CCor V_SS

_CC@ 5.0V, V_IN= V_CCor V_SS

0.5

2.0

I_CC

3.0

I_SB1

I_SB2

I_SB3

I_IL

1.0

Supply current

1.0

Supply current

0.07

1.0

Input leakage current

V_IN= V_CCor V_SS

3.0

I_LO

Output leakage current V_IN= V_CCor V_SS

Input low level

3.0

V_IL

V_IH

V_OL1

V_OL2

-0.6

V_CC 0.3

V_CC+ 0.5

0.2

Input high level

V_CC0.7

Output low level

_CC@ 1.8V, I_OL= 0.15 mA

_CC@ 3.0V, I_OL= 2.1 mA

0.4

DS3001M-page9

24C04A, 24C08A, 24C16A

ORDER CODE:

FT24CXXA – XXX - X

Packaging

B: Tube

T: Tape and Reel

Temperature Range

U: -40 to 85 ^oC

Package

D: DIP

S: SOP

Option

M: MSOP

T: TSSOP

L: SOT23

P: TSOT23

N: DFN

G: Green Package RoHS Compliant

R: RoHS Compliant

ORDER INFORMATION

Order code

Temperature

Range

Vcc

Package

Option

Packaging

FT24C04A-UDG-B

FT24C04A-UDR-B

FT24C04A-USG-B

FT24C04A-USG-T

FT24C04A-USR-B

FT24C04A-USR-T

FT24C04A-UTG-B

Green Package

RoHS

Tube

T/R

DIP8

Green Package

RoHS

SOP8

Tube

T/R

RoHS

Green Package

RoHS

Tube

T/R

1.8v-5.5v

-40-85⁰C

FT24C04A-UTG-T

FT24C04A-UTR-B

FT24C04A-UTR-T

FT24C04A-ULG-T

FT24C04A-ULR-T

FT24C04A-UPG-T

FT24C04A-UPR-T

TSSOP8

Tube

T/R

RoHS

Green Package

RoHS

T/R

SOT23-5

T/R

Green Package

RoHS

T/R

TSOT23-5

T/R

DS3001M-page10

24C04A, 24C08A, 24C16A

ORDER INFORMATION（CONTINUED）

Temperature

Order code

Vcc

Package

Option

Packaging

Range

FT24C08A-UDG-B

FT24C08A-UDR-B

FT24C08A-USG-B

FT24C08A-USG-T

FT24C08A-USR-B

FT24C08A-USR-T

FT24C08A-UTG-B

FT24C08A-UTG-T

FT24C08A-UTR-B

FT24C08A-UTR-T

FT24C08A-ULG-T

FT24C08A-ULR-T

FT24C08A-UPG-T

FT24C08A-UPR-T

FT24C16A-UDG-B

FT24C16A-UDR-B

FT24C16A-USG-B

FT24C16A-USG-T

FT24C16A-USR-B

FT24C16A-USR-T

FT24C16A-UTG-B

FT24C16A-UTG-T

FT24C16A-UTR-B

FT24C16A-UTR-T

FT24C16A-ULG-T

FT24C16A-ULR-T

FT24C16A-UPG-T

FT24C16A-UPR-T

Green Package

RoHS

Tube

T/R

DIP8

Green Package

RoHS

SOP8

Tube

T/R

RoHS

Green Package

RoHS

Tube

T/R

TSSOP8

Tube

T/R

RoHS

Green Package

RoHS

T/R

SOT23-5

TSOT23-5

DIP8

T/R

Green Package

RoHS

T/R

1.8v-5.5v

-40-85⁰C

T/R

Green Package

RoHS

Tube

T/R

Green Package

RoHS

SOP8

Tube

T/R

RoHS

Green Package

RoHS

Tube

T/R

TSSOP8

Tube

T/R

RoHS

Green Package

RoHS

T/R

SOT23-5

T/R

Green Package

RoHS

T/R

TSOT23-5

T/R

DS3001M-page11

24C04A, 24C08A, 24C16A

DIP8 PACKAGE OUTLINE DIMENSIONS

Dimensions In Millimeters

Symbol

Dimensions In Inches

Min

3.710

0.510

3.200

0.380

Max

Min

0.146

0.020

0.126

0.015

Max

4.310

0.170

3.600

0.570

0.142

0.022

1.524（BSC）

0.060（BSC）

0.100（BSC）

0.204

9.000

6.200

7.320

0.360

9.400

6.600

7.920

0.008

0.354

0.244

0.288

0.014

0.370

0.260

0.312

2.540 (BSC)

3.000

8.400

3.600

9.000

0.118

0.331

0.142

0.354

DS3001M-page12

24C04A, 24C08A, 24C16A

SOP8 PACKAGE OUTLINE DIMENSIONS

Dimensions In Millimeters

Dimensions In Inches

Min

Max

Min

Max

Symbol

1.350

0.100

1.350

0.330

0.170

4.700

3.800

5.800

1.750

0.250

1.550

0.510

0.250

5.100

4.000

6.200

0.053

0.004

0.053

0.013

0.006

0.185

0.150

0.228

0.069

0.010

0.061

0.020

0.010

0.200

0.157

0.244

1.270 (BSC)

0.050 (BSC)

0.400

0°

1.270

8°

0.016

0°

0.050

8°

DS3001M-page13

24C04A, 24C08A, 24C16A

TSSOP8 PACKAGE OUTLINE DIMENSIONS

Dimensions In Millimeters

Symbol

Dimensions In Inches

Min

2.900

4.300

0.190

0.090

6.250

Max

3.100

4.500

0.300

0.200

6.550

1.100

1.000

0.150

Min

0.114

0.169

0.007

0.004

0.246

Max

0.122

0.177

0.012

0.008

0.258

0.043

0.039

0.006

0.800

0.020

0.031

0.001

0.65 (BSC)

0.25 (TYP)

0.026 (BSC)

0.01 (TYP)

0.500

1°

0.700

0.020

1°

0.028

7°

MSOP8 PACKAGE OUTLINE DIMENSIONS

DS3001M-page14

24C04A, 24C08A, 24C16A

Dimensions In Millimeters

Dimensions In Inches

Symbol

Min

0.820

0.020

0.750

0.250

0.090

2.900

Max

1.100

0.150

0.950

0.380

0.230

3.100

Min

Max

0.043

0.006

0.037

0.015

0.009

0.122

0.320

0.001

0.030

0.010

0.004

0.114

0.65 (BSC)

0.026 (BSC)

2.900

4.750

0.400

0°

3.100

5.050

0.800

6°

0.114

0.187

0.016

0°

0.122

0.199

0.031

6°

DFN8 PACKAGE OUTLINE DIMENSIONS

DS3001M-page15

24C04A, 24C08A, 24C16A

Dimensions In Millimeters

Symbol

Nom

0.75

0.02

0.25

0.20

2.00

Min

0.70

Max

0.80

0.05

0.03

0.25

2.10

0.18

1.90

1.50REF

0.50BSC

1.50BSC

3.00

2.90

3.10

1.60REF

0.40

0.30

0.20

0.50

0.30

0.25

L/F Surface Electroplate

Dimension（mil）

NIPdAu (Nickel, Pd, Metal)

67*75

DS3001M-page16

24C04A, 24C08A, 24C16A

SOT-23-5 PACKAGE OUTLINE DIMENSIONS

Dimensions In Millimeters

Symbol

Dimensions In Inches

Min

Max

1.250

0.100

1.150

0.500

0.200

3.020

1.700

2.950

Min

Max

0.049

0.004

0.045

0.020

0.008

0.119

0.067

0.116

1.050

0.000

1.050

0.300

0.100

2.820

1.500

2.650

0.041

0.000

0.041

0.012

0.004

0.111

0.059

0.104

0.95 (BSC)

0.037 (BSC)

1.800

0.300

0°

2.000

0.600

8°

0.071

0.012

0°

0.079

0.024

6°



DS3001M-page17

24C04A, 24C08A, 24C16A

TSOT-23-5 PACKAGE OUTLINE DIMENSIONS

Dimensions In Millimeters

Symbol

Dimensions In Inches

Min

Max

Min

Max

0.700

0.000

0.700

0.350

0.080

2.820

1.600

2.650

0.900

0.100

0.800

0.500

0.200

3.020

1.700

2.950

0.028

0.000

0.028

0.014

0.003

0.111

0.063

0.104

0.035

0.004

0.031

0.020

0.008

0.119

0.067

0.116

0.95 (BSC)

1.90 (BSC)

0.037 (BSC)

0.075 (BSC)

0.300

0°

0.600

8°

0.012

0°

0.024

8°



DS3001M-page18

24C04A, 24C08A, 24C16A

DS3001M-page19

24C04A, 24C08A, 24C16A

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any infringement of patents of other rights of third parties which may result from its use. No license is

granted by implication or otherwise under any patent rights of Fremont Micro Devices.,Ltd.(FMD).

Specifications mentioned in this publication are subject to change without notice. This publication

supersedes and replaces all information previously supplied. Fremont Micro Devices.,Ltd.(FMD)

products are not authorized for use as critical components in life support devices or systems without

express written approval of Fremont Micro Devices.,Ltd.(FMD).

The FMD logo is a registered trademark of Fremont Micro Devices.,Ltd.

All other names are the property of their respective owners

www.fremontmicro.com

DS3001M-page20

FT24C08A-UDR-B [ETC]

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