GD16547-48BA [ETC]
CLOCK/DATA RECOVERY|BIPOLAR|QFP|48PIN|PLASTIC ; 时钟/数据恢复|双极| QFP | 48PIN |塑料\n
| 型号： | GD16547-48BA |
| 厂家： | 
ETC |
| 描述： | CLOCK/DATA RECOVERY|BIPOLAR|QFP|48PIN|PLASTIC
|
| 文件： | 总9页 (文件大小：130K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.5 Gbit/s
Clock and Data
Recovery
GD16547
an Intel company
General Description
Features
l
The GD16547 is a high performance
monolithic integrated Clock and Data Re-
covery (CDR) device applicable for opti-
cal communication systems including:
The device meets all ITU-T jitter require-
ments when used with the recommended
loop filter (jitter tolerance, -transfer and
-generation).
Clock and Data Recovery for
2.488 Gbit/s.
l
SDH STM-16, SONET OC-48
compatible.
u
SDH STM-16
SONET OC-48
u
The 2.5 GHz output clock is maintained
within 500 ppm tolerance even in ab-
sence of data.
l
Differential Data inputs with 8 mV
sensitivity.
The CDR contains all circuits needed for
reliable acquisition and lock of the VCO
phase to the incoming data-stream.
l
The GD16547 is available in a 48 lead
7 × 7 mm TQFP power enhanced plastic
package.
Differential ECL Data and Clock
outputs.
The electrical input sensitivity is better
than 8 mV (BER <10-10). Optical re-
ceivers with sensitivity better than
-34 dBm have been obtained without op-
tical pre-amplifiers.
l
Acquisition time: < 500 ms.
l
Few external passive components
needed.
l
50 W Loop-through data inputs for
higher sensitivity.
l
Single supply operation: -5 V.
l
Power dissipation: less than 1 W.
Limiter
DIREFN
D
l
Bang
Available in a 48 lead 7 × 7 mm
TQFP plastic package
DIN
DI
CKO
CKON
CK
Bang
Phase
DO
DON
DO
DIREF
U
Detector
D
RESET
TCK
R
REFCK
REFCKN
U
Applications
Phase
Frequency
Detector
D
SELTCK
V
l
Clock and Data Recovery for optical
communication systems including:
VDD
Charge
Pump
VCO
VEE
–
–
SDH STM-16
SONET OC-48
VDDA
VDDL
Lock
SEL1
SEL2
Detect
LOCK
PCTL
VCTL
Data Sheet Rev.: 12
Functional Details
The main application of the GD16547 is
as a receiver for:
VCO clock leads or lags the data. Hence
the PLL is controlled by the bit transition
point, thereby ensuring that data is sam-
pled in the middle of the eye, once the
system is in CDR mode. The external
loop filter components control the chara-
cteristics of the PLL.
Inputs
u
SDH STM-16
SONET OC-48 optical communica-
tion systems.
The input amplifier (pins DI / DIN) is de-
signed as a limiting amplifier with a sen-
sitivity better than 8 mV (differential).
u
It integrates:
u
The inputs may be either AC or DC cou-
pled. In both cases input termination is
made through pins DIREF / DIREFN. If
the inputs are AC coupled the amplifier
features an internal offset cancelling DC
feedback. Notice that the offset cancella-
tion will only work when the input is dif-
ferential and AC-coupled as shown in the
Figures on page 3.
a Voltage Controlled Oscillator (VCO)
a Lock Detect Circuit
u
The binary output of either the PFD or
the Bang-Bang phase detector (depend-
ing of the mode of the lock-detection cir-
cuit) is fed to a charge pump capable of
sinking or sourcing current or tristating.
The output of the charge pump is filtered
through the loop filter and controls the
tune-voltage of the VCO.
u
a Frequency Detector (PFD)
a Bang-Bang Phase Detector
u
into a Phase Locked Loop (PLL) - based
clock and data recovery circuit with differ-
ential ECL data and clock outputs.
VCO
As a result of the continuous monitoring
lock-detect circuit the VCO frequency
never deviates more than 500 ppm
(2000 ppm) from the reference clock be-
fore the PLL is considered to be ’Out of
Lock’. Hence the acquisition time is pre-
dictable and short and the output clock
CKOUT is always kept within the
Following the CDR block the data is out-
put together with a 2.5 GHz clock. The
data and clock outputs are differential
ECL outputs that should be terminated
via 50 W to -2 V.
The VCO is a low noise LC-type differen-
tial oscillator with a tuning range from 2.3
to 2.7 GHz. Tuning is done by applying a
voltage to the VCTL pin.
Lock Detect Circuit
Package
500 ppm (2000 ppm) limits, ensuring
safe clocking of down stream circuitry.
The lock detect circuit continuously moni-
tors the difference between the reference
clock and the divided VCO clock. If the
reference clock and the divided VCO fre-
quency differs by more than 500 ppm (or
2000 ppm, selectable), it switches the
PFD into the PLL in order to pull the VCO
back inside the lock-in range. This mode
is called the acquisition mode.
The GD16547 is provided in a 48 lead
power enhanced TQFP.
The LOCK Signal
The status of the lock-detection circuit is
given by the LOCK signal. In CDR mode
LOCK is steady high. In acquisition mode
LOCK is alternating indicating the con-
tinuous shifts between the Bang-Bang
Detector (high) and the PFD (low).
The PFD is used to ensure predictable
lock up conditions for the GD16547 by
locking the VCO to an external reference
clock source. It is only used during acqui-
sition and pulls the VCO into the lock
range where the Bang-Bang phase de-
tector is capable of acquiring lock. The
PFD is made with digital set/reset cells
giving it a true phase and frequency
characteristic.
The LOCK output may be used to gener-
ate Loss Of Signal (LOS). The time for
LOCK to assert is predictable and short,
equal to the time to go into lock, but the
time for LOCK to de-assert must be con-
sidered. When the line is down (i.e. no in-
formation received) the optical receiver
circuit may produce random noise. It is
possible that this random noise will keep
the GD16547 within the 500 ppm
(2000 ppm) range of the line frequency,
hence LOCK will remain asserted for a
non-deterministic time. This may be pre-
vented by injecting a small current at the
loop filter node, which actively pulls the
PLL out of the lock range when the out-
put of the phase detector acts randomly.
Once the VCO is inside the lock-range
the lock-detection circuit switches the
Bang-Bang phase detector into the PLL
in order to lock to the data signal. This
mode is called CDR mode.
The reference clock input, REFCK, to the
PFD is at 1/64 of the data rate.
The negligible penalty paid is a static
phase error on the sampling time in the
decision gate. However, due to the na-
ture of the phase detector the error will
be small (few degrees), forcing the loop
to be at one edge of the error-function
shaped transfer characteristic of the de-
tector.
Bang-Bang Phase Detector
The Bang-Bang phase detector is used
in CDR mode as a true digital type de-
tector, producing a binary output. It sam-
ples the incoming data twice each bit
period: once in the transition of the (pre-
vious) bit period and once in the middle
of the bit period. When a transition oc-
curs between 2 consecutive bits - the
value of the sample in the transition be-
tween the bits will show whether the
Data Sheet Rev.: 12
GD16547
Page 2 of 9
DI
From LINE
8k
DIREF
DIREFN
DIN
50R
50R
+
26dB
VTT
VTT
-
8k
From LINE
Figure 1. DC Coupled Input (Ignoring internal offset
compensation)
DI
From LINE
8k
DIREF
50R
+
26dB
VTT
VTT
DIREFN
DIN
50R
-
8k
From LINE
Figure 2. AC Coupled Input (Using internal offset
compensation)
VDDA
PCTL VCTL
33R
2.2mF
VDDA
Charge
Pump
Ext.
Loop Filter
VCO
VEEA
Figure 3. Loop Filter
Data Sheet Rev.: 12
GD16547
Page 3 of 9
Pin List
Mnemonic:
Pin no.:
Pin Type:
ECL OUT
ECL IN
Description:
DO, DON
31, 32
Data output, differential 2.5 Gbit/s.
Differential 38 MHz reference clock input.
REFCK, REFCKN
18
19
SEL1, SEL2
16, 15
ECL IN
Clock and Data recovery set-up.
SEL1 SEL2
0
0
1
1
0
1
0
1
Auto lock, 500 ppm.
Auto Lock, 2000 ppm.
Manual Phase Freq. detector PFC.
Manual Bang-Bang phase detector.
DI, DIN
8, 6
Data IN
Differential AC or DC coupled 2.5 Gbit/s Data input.
DIREF, DIREFN
9
5
Termination
Termination for DI and DIN. Normally terminated to VDD through
47 nF. For DC connected inputs connect to reference voltage.
CKO, CKON
LOCK
29, 28
22
ECL OUT
ECL OUT
Clock output, differential 2.5 GHz.
Lock-detect output. When low, the divided VCO frequency
deviates more than 500/2000 ppm from REFCK / REFCKN.
PCTL
42
46
21
Analog OUT
Analog IN
ECL IN
Charge pump control.
VCTL
VCO voltage control input.
RESET
Not needed on power up. Connect to VEE. Only used for test
purposes.
TCK
38
35
ECL IN
ECL IN
Leave open for normal operation. Only used at DC test.
SELTCK
Test-clock select. Connect to VDD for normal operation. Only
used for test purposes.
VDD
1, 7, 12, 13, 24,
25, 27, 30, 33, 36,
37, 48
PWR
Positive supply voltage.
VDDA
VDDL
VEE
44, 47
4, 11
PWR
PWR
PWR
Positive supply voltage for PLL section.
Positive supply voltage.
2, 10, 14, 17, 26,
34, 39, 43, 45
Negative supply voltage.
NC
3, 20, 23, 40, 41
NC
Not connected.
Heat sink
Connected to VDD.
Data Sheet Rev.: 12
GD16547
Page 4 of 9
Pin Outline
1
2
36
35
34
33
32
31
30
29
28
27
26
25
VDD
VEE
NC
VDD
SELTCK
VEE
3
4
VDDL
VDD
DON
DO
5
DIREFN
DIN
6
7
VDD
DI
VDD
CKO
CKON
VDD
VEE
8
9
DIREF
VEE
10
11
12
VDDL
VDD
VDD
Figure 4. 48 Lead TQFP, Top View
Maximum Ratings
These are the limits beyond which the component may be damaged.
All voltages in the table are referred to VDD.
All currents in the table are defined positive out of the pin.
Symbol:
VEE, VEEA
V0 MAX
I0 MAX, ECL
I0 MAX, PCTL
VI MAX
II MAX
Characteristic:
Supply voltage
Output voltage
Output current
Conditions:
MIN.:
TYP.:
MAX.:
0
UNIT.:
V
-6
VEE - 0.5
0.5
30
V
mA
mA
V
Output current
0.5
0.5
1.0
125
150
Input voltage
VEE - 0.5
-1.0
Input current
mA
°C
T0
Operating temperature
Storage temperature
Junction
-55
TS
-65
°C
Data Sheet Rev.: 12
GD16547
Page 5 of 9
DC Characteristics
TCASE = -5 °C to 95 °C, VEE = -4.5 V to -5.5 V
All voltages in the table are referred to VDD.
All inputs signal and power currents in the table are defined positive into the pin.
All output signal currents are defined positive out of the pin.
Symbol:
VEE
CharacteristIcs:
Conditions:
MIN.:
TYP.:
-5.0
180
5
MAX.:
-4.5
240
8
UNIT:
V
Supply voltage
-5.50
IEE
Supply current
mA
mV
mV
mV
V
Vdiff DI/DIN
Vdiff DI/DIN
Vdiff MAX, DI/DIN
VCM DI/DIN
VIH ECL
VIL ECL
Data sensitivity, differential/single-ended
Necessary input amplitude to stay locked
Maximum input voltage, differential
Data common mode
Note 1, 5
Note 1, 5
Note 7
2
3
500
-1
Note 6
-2
-1.3
ECL input high voltage
ECL input low voltage
ECL input high current
ECL input low current
VCO control voltage
-1.1
VEE
0
V
-1.5
30
V
IIH ECL
VI = -1.1 V
mA
mA
V
IIL ECL
VI = -1.5 V
30
V1 VCTL
VOH ECL
VOH ECL
VOH ECL
VOL ECL
VOL ECL
VOL ECL
VPP ECL
IOH PCTL
IOL PCTL
IVCTL < 30 mA
VEE
-1.1
-1.02
-0.94
VTT
-1
ECL output high voltage
ECL output high voltage
ECL output high voltage
ECL output low voltage
ECL output low voltage
ECL output low voltage
ECL output amplitude, peak to peak
Source current
Note 2, TCASE =-40 °C
Note 2, TCASE =25 °C
Note 2, TCASE =85 °C
Note 2, TCASE =-40 °C
Note 2, TCASE =25 °C
Note 2, TCASE =85 °C
Note 2, 8
-1
V
-0.91
-0.82
-1.7
-1.62
-1.56
1150
V
V
V
-1.97
-1.92
650
85
V
V
800
100
-100
mV
mA
mA
Note 3
Sink current
Note 3
-85
Note 1: AC-coupled, p-p voltage for differential coupling, BER 10-10
Data eye diagram in accorcance with ITU G.957, 223 -1 PRBS, terminated via loop through 50 W.
Note 2: VTT = -2.0 V ±5 %.
Note 3: RL = 50 W to VTT
Note 4: Output terminated to -2.5 V during test.
.
Note 5:
Note 6:
V
V
diff = V
P
- V
.
N
V
P
+V
N
CM
=
.
2
VP
VN
Note 7: AC coupled input, p-p voltage.
Note 8: Guaranteed swing within VOH/VOL range.
Data Sheet Rev.: 12
GD16547
Page 6 of 9
AC Characteristics
TCASE = -5 °C to 95 °C, VEE = -4.5 to -5.5 V
DO
CKO
Td
Symbol:
Characteristic:
Conditions:
MIN.:
TYP.:
MAX.:
UNIT.:
J TOL
Jitter tolerance
f < 100 kHz
f > 1 MHz
1.5
>2
UI p-p
UI p-p
Note 1, 2. See Figure 5.
0.15
>0.35
J TRF
Jitter transfer/Jitter gain
Note 1. See Figure 6.
f < 2 MHz
0.08
0.1
dB
J OUT
Output clock intrinsic jitter
Note 1, 2
5 kHz < f < 20 MHz
1 MHz < f < 20 MHz
5 kHz < f < 20 MHz
0.125
0.05
0.01
UI p-p
UI p-p
UI RMS
TA
Acquisition time
223 – 1 PRBS
50
500
ms
LCID
Consecutive identical bits
# of bits with
no transistion
400
1000
bits
DC
Input data / REFCK frequency deviation Note 3
-200
40
200
60
ppm
%
CDUTY, REFCK
FVCO
REFCK clock duty cycle
VCO tuning range
Vthr = -1.3 V
2.3
45
2.488
2.7
55
GHz
%
CDUTY, CKO
Output clock duty cycle
Vthr = -1.3 V,
50 W to -2.0 V
TRISE/FALL, DO/DON
ECL output rise/fall time
20 - 80%,
120
100
50
160
120
100
ps
ps
ps
50 W to -2.0 V
TRiISE/FALL, CKO/CKON ECL output rise/fall time
80 - 20%,
50 W to -2.0 V
TD, DO
Data output from CKO
See figure above
20
Note 1: Jitter parameters acquired at VEE = 5.0 V ±5 %, R = 33 W, and C = 2.2 mF.
When shifting the VEE range and tolerance, R and C values should be changed to accommodate for changed loop gain
parameters.
Note 2: 1 UI p-p = 402 ps.
Note 3: Maximum allowable deviation between reference clock and divided VCO clock when locked to data.
UI
UI
ITU-T Specs.
ITU-T Specs.
1.5
0.1
0.0
20dB/dec.
0.35
0.15
F
F
2M
20M
100k
1M
Figure 5. Jitter Tolerance, Typical
Figure 6. Jitter Transfer, Typical
Data Sheet Rev.: 12
GD16547
Page 7 of 9
Package Outline
Figure 7. 48 Lead TQFP, Power Enhanced (All Dimensions are mm)
External References
ITU-T G.825 (03/93) Control of Jitter and Wander within digital networks based on SDH
ITU-T G.957 (07/95) Optical interfaces for equip. and systems relating to SDH
ITU-T G.958 (11/94) Digital line systems based on SDH for use on optical fibre cables
Data Sheet Rev.: 12
GD16547
Page 8 of 9
Device Marking
GD16547
<Wafer ID>-<Wafer Lot#>
<Assembly Lot#>-<YYWW>
<Design ID>
Pin 1 - Mark
Figure 8. Device Marking, Top View
Ordering Information
To order, please specify as shown below:
Product Name:
Intel Order Number:
Package Type:
Case Temperature Range:
GD16547-48BA
FAGD1654748BA
MM#: 836072
48 lead TQFP, EDQUAD
-5..95 °C
GD16547, Data Sheet Rev.: 12 - Date: 30 July 2001
an Intel company
Mileparken 22, DK-2740 Skovlunde
Denmark
Phone : +45 7010 1062
Distributor:
The information herein is assumed to be
reliable. GIGA assumes no responsibility
for the use of this information, and all such
information shall be at the users own risk.
Prices and specifications are subject to
change without notice. No patent rights or
licenses to any of the circuits described
herein are implied or granted to any third
party. GIGA does not authorise or warrant
any GIGA Product for use in life support
devices and/or systems.
Fax : +45 7010 1063
E-mail : sales@giga.dk
Web site : http://www.intel.com/ixa
Copyright © 2001 GIGA ApS
An Intel company
All rights reserved
Please check our Internet web site
for latest version of this data sheet.
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