GD16555B/622-68AB [INTEL]

ATM/SONET/SDH IC, Bipolar, PQFP68,;


型号：	GD16555B/622-68AB
厂家：	INTEL
描述：	ATM/SONET/SDH IC, Bipolar, PQFP68, ATM 异步传输模式
文件：	总20页 (文件大小：247K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

10 Gbit/s

Transmitter MUX

with Re-timing

GD16555B

Preliminary

General Description

Features

GD16555B is a 9.95328 Gbit/s transmit-

ter chip for use in SDH STM-64 and

SONET OC-192 optical communication

systems.

The output of the MUX stage is retimed

by the 10 GHz clock and the output

driver is a Current Mode Logic (CML)

output with internal 50 Ω termination re-

sistors.

On-chip low noise 10 GHz VCO with

a wide tuning range.

Automated capture of the VCO

frequency by a true phase and

frequency detector.

GD16555B integrates all the main func-

tions of the transmitter, which is clock

generation, PLL circuits and multiplexer

in a single monolithic IC. Hence only an

external loop filter is required.

The 16 bit wide parallel input interface is

differential CML with 50 Ω internal load

termination, and with a 622 MHz clock

output mastering the timing at the STM-4

interface. The phase of the output clock

is selected in four phases: 0°, 90°, 180°,

and 270° by two select pins.

Retiming of MUX stage output with

10 GHz clock.

Clock failure detection NLDET.

The main functions of GD16555B are

shown in the figure below. The clock

generation is made on-chip by a low

noise and tuneable 10 GHz VCO. The

VCO centre frequency is controlled by a

PLL with an external loop filter, allowing

the user to control the loop characteristic.

16:1 MUX with differential 622 Mbit/s

CML data input.

GD16555B is manufactured in a Silicon

Bipolar process.

CML data input with 50 Ω internal

load termination.

GD16555B uses a single -5.2 V supply

voltage.

622 MHz clock output for counter

clocking.

The clock synchronisation is controlled

by the Phase and Frequency Detector

with a 155 MHz or 622 MHz reference

clock input (package bonding option).

The power dissipation is 2 W, typical.

Clock output is selectable in four

phases: 0°, 90°, 180°, or 270°.

GD16555B is delivered in a Multi Layer

Ceramic (MLC) package, with internal

high-speed 50 Ω transmission lines.

GD16555B multiplexes a 16 bit parallel

622 Mbit/s interface into a serial

9.9553 Gbit/s data stream.

155 MHz or 622 MHz reference clock

input (package bonding option).

All high-speed signals is bonded with

GiGA’s proprietary Flexguide® Bonding

Technique.

Single supply operation: -5.2 V

Low Power dissipation: 2 W (typ.).

Silicon Bipolar process.

DI0

DIN0

68 pin Multi Layer Ceramic (MLC)

package.

Flexguide

OUT

16:1

Parallel

Input Data

OUTN

Multiplexer

DI15

DIN15

CKOUT

CKOUTN

Flexguide® Bonding Technique.

NLDET

Timing

Control

SEL1

SEL2

Phase

PCLT

POUT

Frequency

Applications

Detector

VCO

PHIGH

VCTL

Telecommunication systems:

PLOW

–

SDH STM-64

SONET OC-192.

VCUR

(only /155 vers.)

Fibre optic test equipment.

TCK

(*)

VDD VDDO VDDA VEE

(*) = Package Bonding Option

Submarime transmission systems.

Functional Details

The main function of GD16555B is as

transmitter in STM-64 and SONET

OC-192 optical communication systems.

with 50 Ω internal resistors. The 16 bits

are multiplexed starting with DI0,

DI1...DI15.

should always be terminated as shown in

Figure 1 also even though they are not

actively used in the PLL.

It integrates:

All CML inputs have 50 Ω internal termi-

nation resistors to a separated power pin

(VCMLT). With VCMLT connected to 0 V

all inputs are configured as CML inputs

(high/low equal 0/-0.4 V) or with VCMLT

connected to –2 V all inputs are confi-

gured as ECL compatible inputs (high/

low equal -0.8/ -1.8 V). With ECL inputs

the maximum current out of VCMLT is

400 mA and proper de- coupling of

VCMLT is required.

POUT is a high impendance input and

will be destroyed if connected directly

(low-ohmic, <25 kΩ) to -3.6 V to 0 V.

Voltage Controlled Oscillator (VCO)

Phase and Frequency Detector (PFD)

16:1 Multiplexer

Re-timing of output data.

The Outputs

VCO

The 10 Gbit/s output driver is internal ter-

minated with 50 Ω resistors to 0 V and

bonded with Flexguides from the die to

the package edge. This bonding tech-

nique insures a true 50 Ω transmission

line environment from the outside edge

of the package through the package to

the die. The output should be terminated

externally with 50 Ω at the receive end

and should be used differential. Both

OUT and OUTN are best terminated with

the same load resistor e.g. 50 Ω, an

asymmetrically loading will decrease the

performance of the output due to refle-

ctions. When terminated externally with

The VCO is an LC-type differential

10 GHz oscillator controlled by pin VCTL

and with a tuning range of ±5 %. The

VCO and the clock divider circuit gener-

ates the clock signal and load pulses

needed for multiplexing. It also generates

the output clock (CKOUT/ CKOUTN) and

the clock used in the phase and fre-

quency detector.

The select inputs (SEL1-2 and TCK) are

low-speed inputs, that can be connected

directly to the supply rails (0 / -5.2 V).

Loop Filter

With the VCTL voltage at -3 V the VCO

frequency is fixed at 9.953 GHz and by

changing the voltage from 0 to –5.2 V the

frequency is controlled from 9 GHz to

10.2 GHz (See VCO Measurements on

page 17). The modulation bandwidth of

VCTL is 90 MHz.

The external loop filter is made using an

operational amplifier connected to output

pins (PHIGH and PLOW). The character-

istics of the phase lock loop are con-

trolled by the loop filter components

hence the op-amp is designed as an inte-

grator by a feedback capacitor and a re-

sistor. The gain-bandwidth of the op-amp

need to be larger than the required PLL

bandwidth in order not to limit it. The rec-

ommended op-amp is Analog Devices

(AD8042) with a gain-bandwidth of

160 MHz sufficient for PLL bandwidths

up to 50 MHz. The op-amp is used single

supplied by -5.2 V. See Figure 1 for ap-

plication information.

50 Ω, the output voltage is 650 mV_PP

Both outputs OUT/OUTN are not ESD

protected and extra precautions should

be taken when handling the outputs (the

internal 50 Ω resistor provides some

ESD hardness making the input low im-

pedance).

PFD

The PFD is made with digital set/reset

cells giving it a true phase and frequency

characteristic. The reference clock

(REFCK/REFCKN) to the PFD is 155 or

622 MHz (package bonding option, two

different product numbers).

The clock outputs (CKOUT/N) are differ-

ential open collector outputs with a 8 mA

output current. They are terminated ex-

ternally with a resistor (R) to 0 V and the

output voltage swing is

The phase information from the PFD is

high frequency pulses at output pins

(PHIGH and PLOW). They are open col-

lector outputs with an 8 mA current drive

and are terminated externally by 220 Ω

to 0 V. A pre-filtering of the phase pulses

are applied by a parallel 10 pF capacitor.

V = -50 × 8 mA = -400 mV with R = 50 Ω.

Increasing the resistor increases the out-

put voltage swing and reduces the band-

width.

A No Lock DETection signal (NLDET) is

provided as a status signal of the PLL. It

compares the VCO clock with the refer-

ence clock and is high whenever they dif-

fer. Using NLDET the situation of clock

failure, i.e. loss of signal can be detected.

Counter Clocking Timing

The reference clock input has 50 Ω inter-

nal termination resistors to pin VCMLT

and should be used differential.

The PCB layout of the external loop filter

and the connecting lines to PHIGH,

PLOW and VCTL are critical for the jitter

performance of the component. The art-

work for the op-amp and the passive

components should be placed very close

to the pins of GD16555B in order to have

connecting lines as short as possible.

Ideally the loop filter components are

placed on the opposite side of the PCB

directly underneath GD16555B. For more

layout suggestions see the 10 Gbit/s

evaluation board GD90244/255.

When the counter clocking timing is used

to control the timing between GD16555B

and the system ASIC, the output clock

(CKOUT/CKOUTN) is feed to the system

ASIC and clocks valid output data from

the ASIC into GD16555B. For easy inter-

facing of the system ASIC, the output

clock is selectable in four phases (0°,

90°, 180° or 270°) by SEL1-2. The maxi-

mum variation in the round trip delay

should be less than 1.1 ns when using

the counter clocking timing. This leaves

0.5 ns of valid data time for the

GD16555B . The roundtrip delay is the

total delay from clock in, to data out of

the system ASIC and the board delay for

clock and data. The setup and hold times

between CKOUT and input data are

specified for all four phases (see AC

Characteristics on page 14). The valid

time (e.g. the period of time where the in-

The PLL will synchronize the 10 GHz

VCO to the external reference clock.

Noise from the reference clock, within the

PLL bandwidth will be multiplied and

added to the 10 Gbit/s output by the di-

vider ratio between VCO and reference

clock i.e. N = 16 / 64 or in terms of noise

as 20Log(16) = 24 dB or 36 dB. A low

noise reference clock with high frequency

stability is required in order to fulfill the

ITU-T jitter requirements.

Alternatively the phase information is

also available at output pins (PCTL and

POUT) and they can be used with an ex-

ternal passive loop filter in applications

with a low PLL bandwidth (< 1 MHz) in-

stead of the above recommended active

loop filter. The PCTL and POUT pins

Inputs

The parallel input interface is 622 Mbit/s

differential Current Mode Logic (CML)

Data Sheet Rev. 04

GD16555B

Page 2 of 20

put data is not allowed to change) is

given by adding the setup and hold

times. The setup time is defined positive

before the rising edge of CKOUT. The

hold time is defined positive after the ris-

ing edge.

Package

the opposite side of the component with

very short connections to the pins of

GD16555B. The 100 Ω resistors and

10 pF capacitor connected from PHIGH

and PLOW to 0 V should be placed very

close to the package pin no. 50 and 53.

GD16555B is packaged in a 68 pin Multi

Layer Ceramic package with internal

50 Ω transmission lines. The package is

a cavity-down type, which gives effective

cooling using the mounted heat

spreader.

If the variation is bigger than 1.1 ns an-

other type of different clocking timing is

needed e.g. forward clocking timing.

The environment around the loop filter

and the 10 Gbit/s outputs is noise sensi-

tive and no noise generating lines are

allowed in this area.

The 10 Gbit/s outputs are bonded with

GiGA’s Flexguide® Bonding Technique.

These are flexible 50 Ω transmission

lines bonded from the die to the internal

package pin. With the use of Flexguide®

distortion free transmission is ensured

throughout the package.

It is recommended to use all data inputs

differential for best performance.

The power supply to GD16555B should

be separated from other noise generation

components on the board and de-cou-

pled as shown on Figure 2. DC-DC con-

verters are only allowed on the same

board if proper noise filtering is applied.

Forward Clocking Timing

With the forward clocking timing both the

data and the clock is applied to

External Circuits

GD16555B with the clock as a reference

clock input (REFCK/REFCKN). See AC

Characteristics on page 15. It is impor-

tant for the jitter performance that the

clock is clean with no spurious frequency

noise and no noise injection from data

transitions. If the clock is generated from

a CMOS ASIC an additional PLL is

needed to clean up the clock before be-

ing applied as reference to GD16555B.

When using GD16555B with forward

clocking, the 622 MHz reference clock

option should be ordered.

Thermal Condition

The main external circuits needed to

make GD16555B work as a 10 Gbit/s

transmitter IC with re-timing and multi-

plexer are:

The component dissipates 2.0 W with a

–5.2 V voltage supply and need forced

cooling with a heat sink thermally con-

nected to the heat spreader. The thermal

connection should ensure the case tem-

perature in the range from 0 to 70 °C with

the given ambient conditions e.g. tempe-

rature and air flow.

An active loop filter with op-amp

A reference clock at 155 MHz or

622 MHz with high frequency stability

Pull up resistors and de-coupling ca-

pacitors

Mounting and Layout of PCB Power Noise Rejection

The component can be mounted on a

standard FR4 epoxy printed circuit board

when special attention is taken in the lay-

out and in the mounting of the compo-

nent.

In a noisy environment special attention

must be taken as described above to op-

timize the jitter performance and to re-

duce the input sensitivity penalty from

injected noise. The Power Supply Rejec-

tion Ratio (PSRR) is improved by adding

a serial resistor (3.3 kΩ) and capacitor

(33 nF) from the positive input of the

op-amp to the power pin (VEE) as shown

in Figure 1.

The Output Voltage Control

For the GD16555B version with a

155 MHz reference clock (GD16555B/

155-XX) a control signal (VCUR) is avail-

able at pin 41.

It is important for the performance of the

component that the leads of pin OUT and

OUTN (10 Gbit/s outputs) are made very

short (<1 mm) when mounted on the

board. Best way to make the leads short

are to cut a hole in the PCB and to mount

the component inside the hole. The

length of the two critical leads is reduced

to less than 0.5 mm whereas the rest of

the leads are kept at 2 - 4 mm in order

for mechanical stability. On the back side

the head spreader on the package is

thermally mounted to a metal block with

heat sink compound (see paragraph

“Mounting of Component on PCB” on

page 18).

By controlling the voltage at VCUR the

DC output voltage at OUT/OUTN is ad-

justed in the range form 0.1 V to 0.8 V.

The VCUR can be operated from 0 V to

VEE.

For the GD16555B version with a

622 MHz reference clock (GD16555B/

622-XX) the control signal (VCUR) is not

available at pin 41.

GD16555B versus GD16255A

GD16555B is plug compatible and offers

the same or even better performance

compared with GD16255A. The pinouts

and the configurations of I/O´s are the

same except of the three differences as

described below:

In cases where the above mounting tech-

nical is not applicable, the component

can be mounted directly on the board

with bend leads accepting longer leads

for the 10 Gbit/s outputs. The component

is available with straight leads and with

gull wing leads (see the package outline

drawings on page 19).

No RESET pin

SEL 1/2 do not affect the timing rela-

tion between the reference clock and

the internal sampling of input data.

The values of one resistor and capa-

In the layout of the PCB the 10 Gbit/s in-

puts are connected with 50 Ω Micro Strip

Lines (MSL) to the high- speed connec-

tor. The MSL should be as short as pos-

sible (< 30 mm) with a plain and solid

ground plan below. The layout artwork

for the loop filter is placed preferable on

citor in the recommended loop filter.

Data Sheet Rev. 04

GD16555B

Page 3 of 20

Application

VDDO / 51

VDD

TCK / 45

VCMLT

50Ω MSL

SEL1 / 54

SEL2 / 56

61 / DI0

622 Mbit/s

CML Driver

-5.2V

62 / DIN0

50Ω MSL

39 / DI15

622 Mbit/s

CML Driver

50Ω MSL

VDD

OUT / 42

40 / DIN15

10 Gbit/s

Output

OUTN / 44

50Ω MSL

15 / CKOUT

16 / CKOUTN

50Ω

VDD

100nF

50Ω MSL

59 / NLDET

REFCK / 57

RECKN / 58

330

100nF

VDD

500Ω

47 / PCTL

49 / POUT

-5.2V

100Ω 100nF

3.3kΩ

53 / PLOW

50 / PHIGH

VCTL / 46

VEE 17/34/52

33nF

-5.2V

3.3kΩ

1kΩ

AD8042

0.1µF

10pF

-5.2V

220Ω

1kΩ

0.1µF

1kΩ

Figure 1. Application Information

Pin4

Pin9

Pin1

Pin14

Pin21

Pin26

Pin31

Pin36

Pin43

Pin48

Pin55

Pin60

Pin65

VDD

VEE

10µF

Pin51

Pin35

Pin18

Pin68

VDDO

VEE

VDDA

10µF

VCMLT

VEE

10µF

C is 10nF parallel with 100pF.

VEE pins 17/34/52

Figure 2. De-coupling Supply

Data Sheet Rev. 04

GD16555B

Page 4 of 20

10 Gbit/s Output Interface

GD16555B

Driver

50Ω

OUT

50Ω MSL

OUTN

-5.2V

Figure 3. 10 Gbit/s Outputs (OUT/OUTN), DC Coupled

GD16555B

Driver

50Ω

OUT

100nF

OUTN

50Ω MSL

-5.2V

Figure 4. 10 Gbit/s Outputs (OUT/OUTN), AC Coupled

Data Sheet Rev. 04

GD16555B

Page 5 of 20

622 Mbit/s Output Interface

GD16544 or

GD16555B

50Ω

50Ω MSL

8mA

-5.2V

Figure 5. Open Collector Output

Open collector outputs should always be terminated at the receiver end, preferably 50 Ω .

GD16544 or

GD16555B

100nF

120Ω

(-1V)

50Ω

ECL 100k/10k

-5.2V

MC100EL16

MC10EL16

8mA

-5.2V

Figure 6. ECL 100k or 10k Output.

ECL 100k or 10k output using ECL driver MC100EL16/ MC10EL16.

GD16544 or

GD16555B

95Ω

50Ω / 75Ω MSL

-1.0V (high)

-1.6V (low)

365Ω

-5.2V

8mA

-5.2V

Figure 7. ECL Compatible Output

ECL compatible output with a voltage swing of 600 mV (single-ended) or 1200 mV (differential).

Data Sheet Rev. 04

GD16555B

Page 6 of 20

GD16544 or

GD16555B

100nF

120Ω

(-1V)

50Ω

+3.3V

LVPECL 100k/10k

-5.2V

MC100LVEL90

MC10LVEL90

8mA

-5.2V

Figure 8. Low Voltage PECL Output

Low voltage PECL output using PECL driver MC100LVEL90/ MC10LVEL90.

GD16544 or

GD16555B

+3.3V

500Ω

LVDS Input

50Ω MSL

100Ω

500Ω

+3.3V

8mA

-5.2V

Figure 9. LVDS Compatible Output

Reference Clock Input

GD16555B

VCMLT

-5.2V

50Ω

220Ω

REFCK

REFCKN

100nF

220Ω

-5.2V

Figure 10. Reference Clock Input (REFCK/REFCKN), Differential AC Coupled.

Data Sheet Rev. 04

GD16555B

Page 7 of 20

622 Mbit/s Input Interface

GD16555B

VCMLT

50Ω

CML Driver

50Ω MSL

-5.2V

Figure 11. CML input interface with a 0/-0.4 V input voltage swing (DC coupled) by connecting VCMLT to 0 V.

GD16555B

VCMLT

50Ω

CML or LVDS

Output Driver

100nF

50Ω MSL

220Ω

-5.2V

Figure 12. CML or LVDS input interface with a 0/-0.4 V input voltage swing (AC coupled) by connecting VCMLT to 0 V.

Data Sheet Rev. 04

GD16555B

Page 8 of 20

Pin List

Mnemonic:

Pin No.:

Pin Type:

Description:

DI0,

DI1,

DI2,

DI3,

DI4,

DI5,

DI6,

DI7,

DI8,

DI9,

DIN0

61, 62

63, 64

66, 67

2, 3

CML In

Data input, differential 622 Mbit/s. Multiplexed to serial output

starting with DI0, DI1...DI15.

DIN1

DIN2

DIN3

DIN4

DIN5

DIN6

DIN7

DIN8

DIN9

5, 6

7, 8

10, 11

12, 13

19, 20

22, 23

24, 25

27, 28

29, 30

32, 33

36, 37

39, 40

DI10, DIN10

DI11, DIN11

DI12, DIN12

DI13, DIN13

DI14, DIN14

DI15, DIN15

REFCK, REFCKN

57, 58

CML In

ECL In

Reference clock input, differential 155 MHz or 622 MHz (package

bonding option).

SEL1, SEL2

54, 56

Select the phase of CKOUT.

SEL1 SEL2

T_D=0°

T_D=90°

T_D=180°

T_D=270°

OUT, OUTN

42, 44

15, 16

CML Out

Data output, differential 10 Gbit/s. No internal ESD output pro-

tection.

CKOUT, CKOUTN

Open Collector

Clock output, differential 622 MHz. Should always be terminated

with a resistor.

PCTL, POUT

47, 49

50, 53

Analogue Out/In Phase-Frequency detector outputs.

PHIGH, PLOW

Open Collector

Phase-Frequency detector outputs. Should always be terminated

with 50 Ω to VDD.

VCTL

Analogue In

VCO input voltage control.

NLDET

Open Collector

No Lock DETect output. Should always be terminated with a re-

sistor.

TCK

ECL In

PWR

Connect to VDD. Used for test purpose.

VCO Ground 0 V. For test purpose connect to VEE.

CML input resistor termination voltage.

Digital Ground 0 V.

VDDO

VCMLT

VDD

18, 68

4, 9, 14, 21, 26, 31,

38, 43, 48, 55, 60,

VDDA

VEE

1, 35

17, 34, 52

PWR

PLL Ground 0 V.

-5.2 V Digital supply voltage.

VCUR

Analogue In

Output voltage control in GD16555B/155-XX versions.

Connect to VEE in GD16555B/622-XX versions.

Data Sheet Rev. 04

GD16555B

Page 9 of 20

Package Pinout

VCMLT

DIN2

DI2

DI8

DIN8

VDD

DI9

DIN1

DI1

DIN9

DI10

DIN0

DI0

DIN10

VDD

DI11

NLDET

REFCKN

REFCK

SEL2

VDD

DIN11

DI12

DIN12

VDD

DI13

SEL1

PLOW

VEE

DIN13

VEE

Figure 13. Package Pinout, Top View

Note:

VDD = Cavity

Data Sheet Rev. 04

GD16555B

Page 10 of 20

Maximum Ratings

These are the limits beyond which the component may be damaged.

All voltages in table are referred to VDD/VDDA.

All currents are defined positive out of the pin.

VDD is 0 V or GND

Symbol:

V_EE

Characteristic:

Conditions:

MIN.:

TYP.:

MAX.:

-6

UNIT:

Negative Supply

V_CMLT

V_OCML

I_OCML

V_ICML

I_ICML

P_OUT

CML Resistor Termination Voltage

CML Output Voltage

CML Output Current

CML Input Voltage

CML Input Current

POUT Voltage

+0.7

V_EE

Note 1

-12

V_CMLT-1.5

-25

0.5

V_EE

-3.6

+125

+150

T_J

Junction Temperature

Storage Temperature

-55

^oC

T_S

-65

Note 1: Nominal supply voltages.

Data Sheet Rev. 04

GD16555B

Page 11 of 20

DC Characteristics

T_CASE= 0 °C to 70 °C.

All voltages in table are referred to VDD.

All currents are defined positive out of pin.

VDD is 0 V or GND

Symbol:

V_EE

Characteristic:

Conditions:

MIN.:

-5.0

TYP.:

MAX.:

-5.4

-2

UNIT:

Negative Supply Voltage

-5.2

V_CMLT

CML Resistor Termination Voltage

Supply Current

Note 4

I_EE

330

-0.1

-0.25

-1.0

-1.6

-0.05

-0.3

-0.1

-7

400

480

+0.1

-1.0

-0.5

-2.0

+0.05

-0.5

+0.1

-9

V_IHCML

V_ILCML

V_IHECL

V_ILECL

V_OHOC

V_OLOC

I_OHOC

CML Input Voltage High, (50 Ω Input)

CML Input Voltage Low, (50 Ω Input)

ECL Input Voltage High, (50 Ω Input)

ECL Input Voltage Low, (50 Ω Input)

Open Collector Output Voltage High

Open Collector Output Voltage Low

Open Output Current High

V_CMLT= 0V, Note 3

V_CMLT= -2V, Note 3

Note 1, 5

-0.4

-0.8

-1.8

Note 1, 5

-0.4

V_CMLT= 0V, 50Ω Input

Note 1, 10 MHz

Note 1

I_OLOC

Open Output Current Low

-8

V_OHOUT

V_OLOUT

I_OHOUT

I_OLOUT

V_IHSEL1-2, TCK

V_ILSEL1-2, TCK

R_INCML

OUT/OUTN Voltage High

-0.1

-0.6

-0.05

-0.7

+0.05

-0.8

OUT/OUTN Voltage Low

OUT/OUTN Current High

OUT/OUTN Current Low

Note 1

-14

SEL1-2 and TCK Input Voltage High

SEL1-2 and TCK Input Voltage Low

CML Input Resistor Termination

Note 2

V_EE+ 2

V_EE+ 0.8

Note 2

V_EE

Ω

Note 1: Output externally terminated by 50 Ω to 0 V.

Note 2: SEL1-2 and TCK can be connected directly to VDD or VEE.

Note 3: DI0/DIN0 to DI15/DIN15 are internally terminated by 50 Ω to V_CMLT

Note 4: The CML inputs can be configured as ECL compatible by connecting V_CMLTto -2 V, hence all data inputs and REFCK/

REFCKN have to be ECL.

Note 5: All open collector outputs should be terminated with a resistor to VDD even though they are not used.

Data Sheet Rev. 04

GD16555B

Page 12 of 20

AC Characteristics, General

T_CASE= 0 °C to 70 °C, VEE = -5.2 V.

Symbol:

Characteristic:

Conditions:

MIN.:

TYP.:

MAX.:

UNIT:

J_TRF

Jitter transfer

12 kHz < F < 2 MHz

Note 1

0.1

J_GEN

Jitter generation

12 kHz < F < 80 MHz

Note 1

0.1

UI_PP

V_OUT

10 Gbit/s output voltage

Note 4

600

200

650

100

-10

mV_PP

V_I,CML

G OUT

F REFCK

CML input voltage sensitivity

OUT/OUTN output reflection coefficient Note 2

REFCK/REFCKN frequency, stability F_REF= 155 MHz, Note 3

-10

+10

ppm

D _CYCLE,CKOUT/N CKOUT/CKOUTN duty cycle

Differential

D _CYCLE,REFCK

F _MAX,REFCK

REFCK duty cycle

Maximum REFCK frequency

622 MHz reference option

635

MHz

Note 1: Measured with the recommended loop filter in the GD90244/255 evaluation board (1 UI = 100 ps).

Note 2: From DC to 6 GHz, measured on the GD90244/255 evaluation board. Depends on lead length, board, soldering, etc. of

the component.

Note 3: 622 MHz is provided as a package bonding option.

Note 4: VEE = -5.2 V. Measured on the GD90244/255 evaluation board with the compound component mounted in a high speed

socket.

Data Sheet Rev. 04

GD16555B

Page 13 of 20

AC Characteristics, Counter Clocking Timing

T_CASE= 0 °C to 70 °C, VEE = -5.2 V.

GD16555B

ASIC System

DI0

Shift

16 bit @ 622 Mbit/s

DI15

Differential Clock 622 MHz

CKOUT

CKOUTN

Figure 14. Counter Clocking Timing.

CKOUT

DI0-15

T_sd

T_hd

T_sc

T_hc

T_sb

T_hb

T_sa

T_ha

Figure 15. Timing relation between input data and output clock.

Symbol:

T_sa

Characteristic:

Conditions:

MIN.:

TYP.:

100

MAX.:

200

UNIT:

DI0-15 setup before CKOUT

DI0-15 hold from CKOUT

DI0-15 setup before CKOUT

DI0-15 hold from CKOUT

DI0-15 setup before CKOUT

DI0-15 hold from CKOUT

DI0-15 setup before CKOUT

DI0-15 hold from CKOUT

SEL1,2: 0,0; Note 1

SEL1,2: 1,1; Note 1

SEL1,2: 0,1; Note 1

SEL1,2: 1,0; Note 1

T_ha

T_sb

460

-400

860

-800

1260

-1200

500

600

T_hb

-390

900

-350

1000

-750

1400

-1150

T_sc

T_hc

-790

1300

-1190

T_sd

T_hd

Note 1: Setup time is defined positive before the falling edge of CKOUT and the hold time is defined positive after the falling

edge of CKOUT.

Data Sheet Rev. 04

GD16555B

Page 14 of 20

AC Characteristics, Forward Clocking Timing

T_CASE= 0 °C to 70 °C, VEE = -5.2 V.

GD16555B

ASIC System

DI0

Shift

16 bit @ 622 Mbit/s

DI15

Differential Reference

Clock 622 MHz

REFCK

PLL

REFCKN

Figure 16. Forward Clocking Timing.

REFCK

DI0-15

T_S,RF

T_H,RF

Figure 17. Timing relation between input data and reference clock.

Symbol:

T_S,RF

Characteristic:

Conditions:

MIN.:

100

TYP.:

MAX.:

UNIT:

DI0-15 setup before REFCK

DI0-15 hold from REFCK

VEE = -5.2V, T_C=70°, Note 1, 2

T_H,RF

250

Note 1: 622 MHz reference clock option.

Note 2: Setup time is defined positive before the falling edge of CKOUT and the hold time is defined positive after the falling

edge of CKOUT.

Data Sheet Rev. 04

GD16555B

Page 15 of 20

Jitter Transfer Measurement

Figure 18. Jitter transfer curve when connected with the recommended loop filter (see Figure 1) on the evaluation board

GD90244/255. The case temperature -5 °C to 85 °C and power supply -5.0 V and -5.4 V.

Data Sheet Rev. 04

GD16555B

Page 16 of 20

VCO Measurement

Figure 19. VCO tuning curves.

The tuning curves are measured at -5 °C and 85 °C and at supply voltages of -5 V and -5.4 V.

Data Sheet Rev. 04

GD16555B

Page 17 of 20

Mounting of Component on PCB

50 Ω MSL

Heat sink compound

0.5 mm

2 - 4 mm

PCB

GD16555B

SMA

Connector

Metal Block

Figure 20. Example 1.

Mounting of the component inside a hole in the PCB with short leads for the 10 GBit/s inputs. The headspreader is down side to-

wards the metal side for best cooling of the component.

Heat sink

Heat sink compound

50 Ω MSL

GD16555B

PCB

Loop Filter

SMA

Connector

Figure 21. Example 2.

Mounting of the component on the PCB with bend leads (gullwings) The headspreader is thermal mounted to a heat sink.

Data Sheet Rev. 04

GD16555B

Page 18 of 20

Package Outline

0.056" +- 0.006"

0.086" +- 0.01"

0.750" +- 0.007" SQ

Pin 1

0.010"

0.950" +- 0.02" SQ

0.040"

Figure 22. Package with Straight Leads (68AB)

Figure 23. Package with Gullwings Leads (68BA)

Data Sheet Rev. 04

GD16555B

Page 19 of 20

Device Marking

GD16555B-<Option>

WWYY

GD16555B

Figure 24. Device marking, bottom and top view

Ordering Information

To order, please specify as shown below:

Product Name:

Reference Clock:

Package Type:

Case Temperature Range:

0...70^oC

GD16555B/155-68AB

155 MHz

622 MHz

155 MHz

622 MHz

68 pin Straight Lead,

Multi Layer Ceramic, (MLC)

GD16555B/622-68AB

GD16555B/155-68BA

GD16555B/622-68BA

68 pin Straight Lead,

Multi Layer Ceramic, (MLC)

0...70^oC

68 pin Gullwing Lead,

Multi Layer Ceramic, (MLC)

68 pin Gullwing Lead,

Multi Layer Ceramic, (MLC)

GD16555B, Data Sheet Rev. 04 - Date: 24 September 1999

Distributor:

The information herein is assumed to be

reliable. GIGA assumes no responsibility

for the use of this information, and all such

information shall be at the users own risk.

Prices and specifications are subject to

change without notice. No patent rights or

licenses to any of the circuits described

herein are implied or granted to any third

party. GIGA does not authorise or warrant

any GIGA Product for use in life support

devices and/or systems.

Mileparken 22, DK-2740 Skovlunde

Denmark

Telephone : +45 4492 6100

Telefax

E-mail

Web site

: +45 4492 5900

: sales@giga.dk

: http://www.giga.dk

Please check our Internet web site

for latest version of this data sheet.

GD16555B/622-68AB [INTEL]

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