GM71CS18160CLT-5 [ETC]

x16 Fast Page Mode DRAM ; X16快速页模式DRAM\n


型号：	GM71CS18160CLT-5
厂家：	ETC
描述：	x16 Fast Page Mode DRAM X16快速页模式DRAM\n 内存集成电路光电二极管动态存储器
文件：	总10页 (文件大小：112K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

GM71C18160C

GM71CS18160CL

1,048,576 WORDS x 16 BIT

CMOS DYNAMIC RAM

Description

F eatur es

T h e G M 7 1 C ( S ) 1 8 1 6 0 C /C L i s t h e n e w

generation dynamic RAM organized 1,048,576

x 16 bit. GM71C(S)18160C/CL has realized

higher density, higher performance and various

functions by utilizing advanced CMOS process

technology. The GM71C(S)18160C/CL offers

Fast Page Mode as a high speed access mode.

Multiplexed address inputs permit the

G M 7 1 C ( S ) 1 8 1 6 0 C /CL to be packaged in

standard 400 mil 42pin plastic SOJ, and

standard 400mil 44(50)pin plastic TSOP II. The

package size provides high system bit densities

and is compatible with widely available

automated testing and insertion equipment.

* 1 ,048,576 Words x 16 Bit Organization

* Fast Page Mode Capability

* S ingle Power Supply (5V+/-10%)

* Fast Access Time & Cycle Time

(Unit: ns)

tRAC

tCAC

tR C

tPC

110

130

GM71C(S)18160C/CL-5

GM71C(S)18160C/CL-6

GM71C(S)18160C/CL-7

* Low Power

Active : 1045/935/825mW (MAX )

Standby : 11mW (CMOS level : MAX )

0.83mW (L-version : MAX )

* RAS Only Refresh, CAS before RAS Refresh,

Hidden Refresh Capability

* All inputs and outputs TTL Compatible

* 1024 Refresh Cycles/16ms

* 1024 Refresh Cycles/128ms (L-version)

* Self Refresh Operation (L-version)

* B attery B ack Up Operation (L-version)

* 2 CAS byte Control

Pin Configuration

42 SOJ

44(50) TSOP II

V S S

5 0

V CC

4 2

4 1

V S S

V CC

I/O0

I/O1

I/O2

I/O3

V CC

I/O4

I/O5

I/O6

I/O7

4 9

I/O0

I/O1

I/O2

I/O3

V CC

I/O15

^{4 8}I/O14

4 0 I/O14

3 9 I/O13

4 7

I/O13

^{4 6}I/O12

^{4 5}V S S

3 8

I/O12

3 7

V S S

4 4

I/O4

I/O5

I/O11

3 6

I/O11

^{4 3}I/O10

^{4 2}I/O9

^{4 1}I/O8

3 5

I/O10

I/O6

I/O7

1 0

1 1

3 4

3 3

3 2

3 1

3 0

I/O9

I/O8

4 0

1 0

1 1

1 2

1 3

LCAS

UCAS

W E

NC 1 5

3 6 NC

3 5

1 6

LCAS

3 4

1 4

1 5

2 9

2 8

1 7

1 8

R A S

W E

UCAS

3 3

R A S

3 2

1 9

2 0

A11

A10

1 6

1 7

1 8

1 9

2 7

3 1

2 6 A7

3 0

2 1

2 2

2 3

2 5

2 9

2 4

^{2 8}A5

^{2 7}A4

2 0

2 1

2 3 A4

2 4

2 5

2 6

2 2

V S S

V CC

V S S

(Top View)

Rev 0.1 / Apr’01

GM71C18160C

GM71CS18160CL

Pin Descr iption

P in

A0-A9

F unction

Address Inputs

P in

W E

F unction

Read/W rite Enable

Output Enable

Power (+5V)

A0-A9

Refresh Address Inputs

Data-In/Out

I/O0-I/O15

R A S

C C

S S

Ground

Row Address Strobe

Column Address Strobe

UCAS, LCAS

No Connection

Ordering Information

T ype No.

Access Time

Package

GM71C(S)18160CJ/CLJ -5

GM71C(S)18160CJ/CLJ -6

GM71C(S)18160CJ/CLJ -7

50ns

60ns

70ns

400 Mil

42 Pin

Plastic SOJ

GM71C(S)18160CT/CLT -5

GM71C(S)18160CT/CLT -6

GM71C(S)18160CT/CLT -7

50ns

60ns

70ns

400 Mil

44(50) Pin

Plastic TSOP II

Absolute Maximum Ratings*

Symbol

Parameter

Ambient Temperature under B ias

Rating

0 ~ +70

Unit

STG

IN/OUT

S torage Temperature (Plastic)

Voltage on any Pin Relative to VS S

Voltage on VC C Relative to V S S

Short Circuit Output Current

-55 ~ +125

-1.0 ~ +7.0V

OUT

1.0

Power Dissipation

Note: Operation at or above Absolute Maximum Ratings can adversely affect device reliability.

Rev 0.1 / Apr’01

GM71C18160C

GM71CS18160CL

R ecommended DC Operating Conditions (TA = 0 ~ +70C)

Symbol

Parameter

M in

4.5

T yp

Max

5.5

Unit

VCC

VIH

VIL

S upply Voltage

5.0

Input High Voltage

Input Low Voltage

2.4

6.0

-1.0

0.8

Note: All voltage referred to V ss.

T he supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be

on the same level.

T r uth Table

RAS

LCAS UCAS

W E

O E

Output

Open

Operation

Notes

1,3

S tandby

Valid

Lower byte

1,3

Valid

Read cycle

Upper byte

Valid

Word

Open

Lower byte

Open

Early write cycle

Upper byte

1,2,3

1,3

Open

Word

Undefined

Lower byte

Upper byte

Delayed Write

cycle

Undefined

Valid

Word

Lower byte

H to L

L to H

Read-modify

-write cycle

Upper byte

Valid

H to L

L to H

Valid

Open

Word

H to L

CBR Refresh

Self Refresh

(L-series)

Open

Word

1,3

RAS-only

Refresh cycle

Open

Word

1,3

Read cycle

(Output disabled)

Notes: 1. H: High (inactive) L: Low(active) D: H or L

2. tW C S >= 0ns Early write cycle

tW C S <= 0ns Delayed write cycle

3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by earliest of

UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However

write OPERATION and output High-Z control are done independently by each UCAS,LCAS.

ex) if RAS = H to L, UCAS = H, LCAS = L, then CAS-before-RAS refresh cycle is selected.

Rev 0.1 / Apr’01

GM71C18160C

GM71CS18160CL

DC Electrical Characteristics (VCC = 5V+/-10%, Vss = 0V, TA = 0 ~ 70C)

Symbol

Parameter

M in Max Unit Note

Output Level

Output "H" Level Voltage (IO U T = -5mA)

2.4

C C

Output Level

O L

0.4

Output "L" Level Voltage (IO U T = 4.2mA)

50ns

60ns

70ns

190

170

Operating Current

C C 1

Average Power Supply Operating Current

(RAS, UCAS or LCAS Cycling: tR C = tR C min)

1, 2

150

C C 2

S tandby Current (TTL)

Power Supply Standby Current

(RAS, UCAS, LCAS = VIH, D OUT = High-Z)

C C 3

RAS Only Refresh Current

50ns

60ns

70ns

50ns

60ns

190

170

Average Power Supply Current

RAS Only Refresh Mode

(tR C = tR C min)

150

185

165

C C 4

Fast Page Mode Current

Average Power Supply Current

Fast Page Mode

1, 3

(tPC = tPC min)

70ns

145

S tandby Current (CMOS)

C C 5

Power Supply Standby Current

150

(RAS, UCAS or LCAS >= VCC - 0.2V, DOUT = High-Z)

CAS-before-RAS Refresh Current

(tR C = tR C min)

C C 6

50ns

60ns

70ns

190

170

150

500

B attery B ack Up Operating Current

(Standby with CBR Refresh)

(tR C =125us, tR A S <=0.3us, DO U T =High-Z)

C C 7

4,5

S tandby Current RAS = VIH

UCAS, LCAS = VIL

C C 8

O U T = Enable

Self-Refresh Mode Current

C C 9

300

(RAS, UCAS or LCAS<=0.2V, DO U T =High-Z)

L(I)

Input Leakage Current

Any Input (0V<=V IN<= 6V)

-10

Output Leakage Current

L(O)

-10

(DOUT is Disabled, 0V<=V O U T <= 6V)

Note: 1. IC C depends on output load condition when the device is selected.

C C (max) is specified at the output open condition.

2. Address can be changed once or less while RAS = VI L

3. Address can be changed once or less while LCAS and UCAS = VIH

4. UCAS = L (<=0.2) and LCAS = L (<=0.2) while RAS = L (<=0.2).

5. L-version.

Rev 0.1 / Apr’01

GM71C18160C

GM71CS18160CL

Capacitance (VCC = 5V+/-10%, TA = 25C)

Symbol

Parameter

Input Capacitance (Address)

Input Capacitance (Clocks)

Output Capacitance (Data-In/Out)

M in

Max

Unit

Note

I/O

1, 2

Note: 1. Capacitance measured with B oonton Meter or effective capacitance measuring method.

2. UCAS and LCAS = VIH to disable DOUT

AC Characteristics (VCC = 5V+/-10%, TA = 0 ~ +70C, Note 1, 2, 18)

Test Conditions

Input rise and fall times : 5 ns

Output timing reference levels : 0.4V, 2.4V

Output load : 2TTL gate + CL (100 pF)

(Including scope and jig)

Input timing reference levels : 0.8V , 2.4V

R ead, W r ite, Read-Modify-W r ite and Refr esh Cycles (Common Parameters)

GM71C(S)18160 GM71C(S)18160 GM71C(S)18160

C/CL-5

C/CL-6

C/CL-7

Unit

Note

Symbol

Parameter

Min Max Min Max Min Max

Random Read or Write Cycle Time

R A S Precharge Time

110

130

R C

tRP

CAS Precharge Time

tR A S

RAS Pulse Width

50 10,000

13 10,000

10,000

tCAS

CAS Pulse Width

15 10,000

18 10,000

tA S R

Row Address Set up Time

Row Address Hold Time

Column Address Set-up Time

tRAH

tASC

tCAH

Column Address Hold Time

RAS to CAS Delay Time

RAS to Column Address Delay Time

RAS Hold Time

tRCD

tR A D

tRSH

CAS Hold Time

tCSH

CAS to RAS Precharge Time

OE to DIN Delay Time

tCRP

tODD

tDZO

OE Delay Time from DIN

CAS Delay Time from DIN

T ransition Time (Rise and Fall)

tDZC

Rev 0.1 / Apr’01

GM71C18160C

GM71CS18160CL

R ead Cycle

GM71C(S)18160 GM71C(S)18160 GM71C(S)18160

C/CL-5 C/CL-6 C/CL-7

Unit

Note

Symbol

Parameter

Min Max Min Max Min Max

Access Time from RAS

8,9

RAC

Access Time from CAS

tCAC

9,10,17

9,11,17

9,25

Access Time from Address

Access Time from OE

tAA

tOAC

Read Command Setup Time

Read Command Hold Time to CAS

Read Command Hold Time to RAS

Column Address to RAS Lead Time

Column Address to CAS Lead Time

CAS to Output in Low-Z

tR C S

12,22

tRCH

tRRH

tRAL

tCAL

tCLZ

Output Data Hold Time

tOH

Output Data Hold Time from OE

Output B uffer Turn-off Time

Output B uffer Turn-off Time to OE

CAS to DIN Delay Time

tOHO

tO F F

tOEZ

tCDD

W r ite Cycle

GM71C(S)18160 GM71C(S)18160 GM71C(S)18160

C/CL-5 C/CL-6 C/CL-7

Unit

Note

Symbol

Parameter

Min Max Min Max Min Max

Write Command Setup Time

Write Command Hold Time

Write Command Pulse Width

Write Command to RAS Lead Time

Write Command to CAS Lead Time

Data-in Setup Time

14,21

W C S

tWCH

tR W L

tC W L

15,23

tD S

Data-in Hold Time

tDH

Rev 0.1 / Apr’01

GM71C18160C

GM71CS18160CL

R ead- Modify-W r ite Cycle

GM71C(S)18160 GM71C(S)18160 GM71C(S)18160

C/CL-5 C/CL-6 C/CL-7

Unit

Note

Symbol

Parameter

Min Max Min Max Min Max

R W C

Read-Modify-Write Cycle Time

RAS to WE Delay Time

131

155

181

tR W D

tC W D

CAS to WE Delay Time

tAWD

Column Address to WE Delay Time

OE Hold Time from WE

tOEH

R efresh Cycle

GM71C(S)18160 GM71C(S)18160 GM71C(S)18160

C/CL-5 C/CL-6 C/CL-7

Unit

Note

Symbol

Parameter

Min Max Min Max Min Max

tC S R

CAS Setup Time

(CAS-before-RAS Refresh Cycle)

CHR

CAS Hold Time

(CAS-before-RAS Refresh Cycle)

R A S Precharge to CAS Hold Time

tRPC

F a st Page Mode Cycle

GM71C(S)18160 GM71C(S)18160 GM71C(S)18160

C/CL-5 C/CL-6 C/CL-7

Unit

Note

Symbol

Parameter

Min Max Min Max Min Max

Fast Page Mode Cycle Time

100,000

Fast Page Mode RAS Pulse Width

tR A S P

Access Time from CAS Precharge

RAS Hold Time from CAS Precharge

9,17,22

tACP

tRHCP

F a st Page Mode Read-Modify-W r ite Cycle

GM71C(S)18160 GM71C(S)18160 GM71C(S)18160

C/CL-5 C/CL-6 C/CL-7

Unit

Note

Symbol

Parameter

Min Max Min Max Min Max

PRWC

Fast Page Mode Read-Modify-Write

Cycle Time

tCPW

WE Delay Time from CAS Precharge

14,22

Rev 0.1 / Apr’01

GM71C18160C

GM71CS18160CL

Self Refr esh Mode

GM71CS18160

C L - 5

GM71CS18160

C L - 6

GM71CS18160

C L - 7

Symbol

Parameter

Unit

Note

Min Max Min Max Min Max

R A S S

RAS Pulse Width(Self-Refresh)

100

110

-50

100

130

-50

tR P S

R A S Precharge Time(Self-Refresh)

CAS Hold Time(Self-Refresh)

-50

tCHS

Notes:

1. AC measurements assume tT = 5ns.

2. An initial pause of 200us is required after power up followed by a minimum of eight initialization

cycles(any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh).

If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are

required.

3. Operation with the tRCD(max)limit insures that tRAC(max)can be met, tRCD(max)is specified as a

reference point only; if tRCD >= tRAD(max) + tAA(max) - tCAC(max), then access time is controlled

exclusively by tCAC

4. Operation with the tRAD(max) limit insures that tRAC(max)can be met, tRAD(max)is specified as a

reference point only; if tRAD is greater than the specified tRAD(max)limit, then access time is

controlled exclusively by tAA

5. Either tODD or tCDD must be satisfied.

6. Either tDZO or tDZC must be satisfied.

7. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Also,

transition times are measured between V IH(min) and VIL(max).

8. Assumes that tRCD <= tRCD(max) and tRAD <= tRAD(max). If tRCD or tRAD is greater than the

maximum recommended value shown in this table, tRAC exceeds the value shown.

9. Measured with a load circuit equivalent to 2 TTL load and 100pF.

10. Assumes that tRCD >= tRCD(max) and tRCD + tCAC(max) >= tRAD + tAA(max).

11. Assumes that tRAD >= tR A D (max) and tRCD + tCAC(max) <= tRAD + tAA(max).

12. Either tRCH or tRRH must be satisfied for a read cycles.

13. tOFF(max) and tOEZ(max) define the time at which the outputs achieve the open circuit

condition and are not referred to output voltage levels.

14. tW C S , tR W D , tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in

the data sheet as electrical characteristics only; if tW C S >= tW C S (min), the cycle is an early write

cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle

; if tR W D >= tR W D (min), tCWD >=tCWD(min), and tAWD >= tAWD(min), or tCWD >= tC W D (min),tAWD

>= tAWD(min) and tCPW >= tCPW(min), the cycle is a read-modify-write and the data output will

contain data read from the selected cell; if neither of the above sets of conditions is satisfied,

the condition of data out (at access time)is indeterminate.

Rev 0.1 / Apr’01

GM71C18160C

GM71CS18160CL

15. These parameters are referred to UCAS and LCAS leading edge in early write cycles and to

WE leading edge in delayed write or read-modify-write cycles.

16. tRASP defines RAS pulse width in fast page mode cycles.

17. Access time is determined by the longest among tAA,tCAC,and tACP

18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying

data to the device. After RAS is reset, if tOEH >= tCWL, the I/O pin will remain open circuit

(high impedance); if tOEH< tCWL, invalid data will be out at each I/O.

19. When both UCAS and LCAS go low at the same time, all 16-bit data are written into the device.

UCAS and LCAS cannot be staggered within the same write/read cycles.

20. All the VCC and VS S pins shall be supplied with the same voltages.

21. tASC, tCAH, tR C S , tW C S ,tWCH,tCSR and tRPC are determined by the earlier falling edge of UCAS

or LCAS.

22. tCRP,tCHR, tRCH, tACP and tCPW are determined by the later rising edge of UCAS or LCAS.

23. tCWL, tDH,tD S and tCSH should be satisfied by both UCAS and LCAS.

24. tCP is determined by that time the both UCAS and LCAS are high.

25. When output buffers are enabled once, sustain the low impedance state until valid data is

obtained.

When output buffer is turned on and off within a very short time, generally it causes large

CC/VS S line noise, which causes to degrade VIH min/VIL max level.

26. Please do not use tR A S S timing, 10us <= tR A S S <=100us. During this period, the device is in

transition state from normal operation mode to self refresh mode. If tR A S S >=100us, then

RAS precharge time should use tR P S instead of tRP

27. H or L (H: VIH(min) <= VIN <= VIH(max), L: VIL(min) <= VIN <= VIL(max))

Rev 0.1 / Apr’01

GM71C18160C

GM71CS18160CL

Unit: Inches (mm)

Package Dimension

42 SOJ

0.025(0.64)

MIN

0.093(2.38)

MIN

1.058(26.89) MAX

1.072(27.23) MAX

0.128(3.25) MIN

0.148(3.75) MAX

0.050(1.27)

TYP

0.026(0.66) MIN

0.032(0.81) MAX

0.015(0.38) MIN

0.020(0.50) MAX

44(50) TSOP I

0.016(0.40) MIN

0.024(0.60) MAX

_{0 ~ 5}¡ £

0.004(0.12) MIN

0.008(0.21) MAX

0.820(20.82) MIN

0.830(21.08) MAX

0.037(0.95) MIN

0.041(1.05) MAX

0.047(1.20)

MAX

0.012(0.30) MIN

0.017(0.45) MAX

0.031(0.80)

TYP

0.002(0.05) MIN

0.006(0.15) MAX

Rev 0.1 / Apr’01

GM71CS18160CLT-5 [ETC]

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