GM71V16163CT-5 [ETC]
x16 EDO Page Mode DRAM ; X16 EDO页模式DRAM\n
| 型号： | GM71V16163CT-5 |
| 厂家： | 
ETC |
| 描述： | x16 EDO Page Mode DRAM
|
| 文件： | 总13页 (文件大小：130K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GM71V16163C
GM71VS16163CL
1,048,576 WORDS x 16 BIT
CMOS DYNAMIC RAM
Description
Features
The GM71V(S)16163C/CL is the new generation
dynamic RAM organized 1,048,576 x 16 bit.
GM71V(S)16163C/CL has realized higher density,
higher performance and various functions by utilizing
advanced CMOS process technology. The
GM71V(S)16163C/CL offers Extended Data
out(EDO) Mode as a high speed access mode.
M u l t p l e x e d a d d r e s s i n p u t s p e r m i t t h e
GM71V(S)16163C/CL to be packaged in standard
400 mil 42pin plastic SOJ, and standard 400mil
44(50)pin plastic TSOP II. The package size provides
high system bit densities and is compatible with
widely available automated testing and insertion
equipment.
* 1,048,576 Words x 16 Bit Organization
* Extended Data Out Mode Capability
* Single Power Supply (3.3V+/-0.3V)
* Fast Access Time & Cycle Time
(Unit: ns)
tRAC
tCAC
tRC
tHPC
50
60
70
80
13
84
20
25
30
35
GM71V(S)16163C/CL-5
GM71V(S)16163C/CL-6
GM71V(S)16163C/CL-7
GM71V(S)16163C/CL-8
15 104
18 124
20 144
* Low Power
Active : 396/360/324/288mW (MAX)
Standby : 7.2mW (MAX)
0.83mW (L-series : MAX)
* RAS Only Refresh, CAS before RAS Refresh,
Hidden Refresh Capability
* All inputs and outputs TTL Compatible
* 4096 Refresh Cycles/64ms
* 4096 Refresh Cycles/128ms (L-series)
* Self Refresh Operation (L-version)
* Battery Back Up Operation (L-series)
* 2 CAS byte Control
Pin Configuration
42 SOJ
44(50) TSOP II
1
VSS
50
VCC
1
42
41
VSS
VCC
I/O0
I/O1
I/O2
I/O3
VCC
49
2
3
4
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
I/O15
48 I/O14
I/O13
2
3
4
5
6
I/O15
40 I/O14
39 I/O13
47
5
6
7
8
9
46 I/O12
45 VSS
38
I/O12
37
VSS
44
I/O11
7
36
I/O11
I/O4
I/O5
I/O6
I/O7
NC
43 I/O10
42 I/O9
41 I/O8
8
35
I/O10
10
11
9
34
33
32
31
30
29
28
I/O9
I/O8
NC
40
NC
10
11
12
13
14
15
LCAS
UCAS
OE
NC
WE
RAS
A11
A10
A0
NC 15
36 NC
NC
35
16
LCAS
34
17
18
WE
UCAS
33
RAS
A9
OE
A9
A8
A7
A6
28 A5
27 A4
32
19
A11
A10
A0
A1
A2
16
17
18
19
20
21
27
A8
31
20
21
22
23
26 A7
30
25
A6
A1
A2
29
24
A5
23 A4
A3
24
25
A3
VCC
26
22
VSS
VCC
VSS
(Top View)
Rev 0.1 / Apr’01
GM71V16163C
GM71VS16163CL
Pin Description
Pin
A0-A11
A0-A11
I/O0-I/O15
RAS
Function
Pin
WE
OE
Function
Address Inputs
Write Enable
Refresh Address Inputs
Data-In/Out
Output Enable
Power (+3.3V)
Ground
V
CC
V
SS
Row Address Strobe
Column Address Strobe
CAS
NC
No Connection
Ordering Information
Type No.
Access Time
Package
GM71V(S)16163CJ/CLJ -5
GM71V(S)16163CJ/CLJ -6
GM71V(S)16163CJ/CLJ -7
GM71V(S)16163CJ/CLJ -8
50ns
60ns
70ns
80ns
400 Mil
42 Pin
Plastic SOJ
GM71V(S)16163CT/CLT -5
GM71V(S)16163CT/CLT -6
GM71V(S)16163CT/CLT -7
GM71V(S)16163CT/CLT -8
50ns
60ns
70ns
80ns
400 Mil
44(50) Pin
Plastic TSOP II
(Normal Type)
Absolute Maximum Ratings*
Symbol
TA
Parameter
Rating
Unit
C
Ambient Temperature under Bias
0 ~ 70
Storage Temperature
-55 ~ 125
C
TSTG
VT
-0.5 ~ Vcc+0.5
(<=4.6V(MAX))
Voltage on any Pin Relative to VSS
V
Supply Voltage Relative to VSS
Short Circuit Output Current
Power Dissipation
-0.5 ~ 4.6
50
V
VCC
IOUT
PT
mA
W
1.0
Recommended DC Operating Conditions (TA = 0 ~ 70C)
Symbol
VCC
Parameter
Min
3.0
Typ
Max
3.6
Unit
Supply Voltage
3.3
V
V
V
Input High Voltage
Input Low Voltage
2.0
-
-
V
CC + 0.3
0.8
VIH
-0.3
VIL
*Note: All voltage referred to Vss.
Rev 0.1 / Apr’01
GM71V16163C
GM71VS16163CL
Truth Table
Output
Open
Operation
RAS
H
LCAS UCAS
WE
D
OE
D
Notes
D
L
H
L
L
H
L
D
H
L
L
H
L
L
H
L
L
H
1,3
Standby
L
H
L
Valid
Lower byte
Upper byte
L
1,3
L
H
Valid
Read cycle
L
Valid
H
L
L
L
L
L
L
L
Word
D
L
Open
Lower byte
L
Open
Early write cycle
D
D
H
H
H
Upper byte
1,2,3
1,2,3
1,3
L
Open
Word
L
Undefined
Undefined
L
Lower byte
Upper byte
Delayed Write
cycle
H
L
L
L
Undefined
Valid
Word
Lower byte
L
L
L
H to L L to H
H to L L to H
H to L L to H
Read-modify
-write cycle
H
L
L
Upper byte
Valid
L
H
L
L
L
Valid
Open
Word
Word
D
D
D
D
D
D
H to L
H to L
H to L
L
CBR Refresh
or
Self Refresh
(L-series)
H
Open
Open
Word
Word
1,3
L
LAS-only
Refresh cycle
Open
Open
Word
D
H
D
H
H
L
H
L
L
1,3
1,3
Read cycle
(Output disabled)
L
Notes: 1. H: High (inactive) L: Low(active) D: H or L
2. tWCS >= 0ns
tWCS < 0ns
Early write cycle
Delayed write cycle
3. Mode is determined by the OR fuction of the UCAS and LCAS. (Mode is set by earliest of
UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edgs.) However
write OPERATION and output HIZ control are done independently by each UACS,LCAS.
ex. if RAS = H to L, UCAS = H, LCAS = L, then CAS-before-RAS refresh cycle is selected.
Rev 0.1 / Apr’01
GM71V16163C
GM71VS16163CL
DC Electrical Characteristics (VCC = 3.3V+/-0.3V, Vss = 0V, TA = 0 ~ 70C)
Symbol
Parameter
Min Max Unit Note
V
OH
Output Level
Output "H" Level Voltage (IOUT = -2mA)
2.4
0
V
CC
V
V
Output Level
Output "L" Level Voltage (IOUT = 2mA)
V
OL
0.4
Operating Current
Average Power Supply Operating Current
(RAS, CAS Cycling: tRC = tRC min)
50ns
-
-
-
-
110
100
90
I
CC1
60ns
70ns
80ns
mA
mA
mA
1, 2
80
I
I
CC2
CC3
Standby Current (TTL)
Power Supply Standby Current
(RAS, CAS = VIH, DOUT = High-Z)
-
2
50ns
-
-
-
-
110
100
90
RAS Only Refresh Current
Average Power Supply Current
RAS Only Refresh Mode
(tRC = tRC min)
60ns
70ns
80ns
2
80
I
CC4
50ns
60ns
70ns
80ns
-
-
-
105
EDO Page Mode Current
Average Power Supply Current
EDO Page Mode
95
85
75
mA
1, 3
(tHPC = tHPC min)
-
-
I
CC5
CC6
Standby Current (CMOS)
Power Supply Standby Current
(RAS, CAS >VCC - 0.2V, Dout = High-Z)
1
mA
uA
-
150
5
I
CAS-before-RAS Refresh Current
(tRC = tRC min)
50ns
60ns
70ns
80ns
-
-
-
110
100
mA
90
80
5
Standby Current RAS = VIH
CAS = VIL
I
CC7
CC8
-
-
mA
uA
1
D
OUT = Enable
Battery Back Up Operating Current(Standby with CBR Ref.)
(CBR refresh, tRC=31.3us, tRAS<=0.3us,
I
400
4,5
D
OUT=High-Z,CMOS interface)
Self-Refresh Mode Current
(RAS, CAS<=0.2V, DOUT=High-Z, CMOS interface)
I
CC9
-
250
10
uA
uA
uA
5
I
LI
Input Leakage Current
Any Input (0V<=VIN<= 4.6V)
-10
-10
ILO
Output Leakage Current
(DOUT is Disabled, 0V<=VOUT<= 4.6V)
10
Note: 1. ICC depends on output load condition when the device is selected. ICC(max) is specified at the output open
condition.
2. Address can be changed once or less while RAS = VIL
.
3. Address can be changed once or less while CAS = VIH
4. CAS = L (<=0.2V) while RAS = L (<=0.2V).
5. L - Series.
.
Rev 0.1 / Apr’01
GM71V16163C
GM71VS16163CL
Capacitance (VCC = 3.3V+/ - 0.3V, TA = 25C)
Symbol
Parameter
Input Capacitance (Address)
Input Capacitance (Clocks)
Output Capacitance (Data-In/Out)
Min
Max
Unit
pF
Note
1
CI1
-
-
-
5
7
7
pF
CI2
1
pF
CI/O
1, 2
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. CAS = VIH to disable DOUT
.
AC Characteristics (VCC = 3.3V+/-0.3V, TA = 0 ~ +70C, Vss = 0V) Note 1, 2, 18, 19, 20
Test Conditions
Input rise and fall times : 2 ns
Input timing reference levels : 0.8V, 2.0V
Output timing reference levels : 0.8V, 2.0V
Output load : 1TTL gate + CL (100 pF)
(Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)
GM71V(S)16163 GM71V(S)16163 GM71V(S)16163 GM71V(S)16163
C/CL-5
C/CL-6
C/CL-7
C/CL-8
Unit Note
Symbol
Parameter
Min Max Min Max Min Max Min Max
Random Read or Write Cycle Time
RAS Precharge Time
84
30
-
-
104
40
-
-
124
50
-
-
144
60
-
-
ns
ns
t
RC
tRP
CAS Precharge Time
8
-
10
60
-
13
70
-
15
80
-
ns
ns
t
CP
t
RAS
CAS
ASR
RAH
ASC
CAH
RCD
RAD
RSH
CSH
CRP
OED
DZO
DZC
RAS Pulse Width
50 10,000
8 10,000
10,000
10,000
10,000
t
CAS Pulse Width
10 10,000
13 10,000
15 10,000 ns
t
Row Address Set up Time
Row Address Hold Time
Column Address Set-up Time
0
8
0
8
-
-
-
-
0
10
0
-
-
-
-
0
10
0
-
-
-
-
0
10
0
-
-
-
-
ns
ns
t
t
ns
ns
ns
21
t
Column Address Hold Time
RAS to CAS Delay Time
RAS to Column Address Delay Time
RAS Hold Time
10
13
15
21
3
12 37
10 25
14 45
12 30
14 52
12 35
20 60
t
t
15 40 ns
4
t
10
35
5
-
-
13
40
5
-
-
13
45
5
-
-
18
50
5
-
-
ns
ns
ns
ns
ns
ns
ns
CAS Hold Time
23
22
t
CAS to RAS Precharge Time
OE to DIN Delay Time
-
-
-
-
t
t
13
0
-
15
0
-
18
0
-
20
0
-
5
6
6
7
t
OE Delay Time from DIN
CAS Delay Time from DIN
TransitionTime (Rise and Fall)
-
-
-
-
0
-
0
-
0
-
0
-
t
tT
2
50
2
50
2
50
2
50
Rev 0.1 / Apr’01
GM71V16163C
GM71VS16163CL
Read Cycle
GM71V(S)16163 GM71V(S)16163 GM71V(S)16163 GM71V(S)16163
C/CL-5 C/CL-6 C/CL-7 C/CL-8
Unit Note
Symbol
Parameter
Min Max Min Max Min Max Min Max
Access Time from RAS
-
-
-
-
50
13
25
13
-
-
-
-
-
60
15
30
15
-
-
-
-
-
70
18
35
18
-
-
-
-
-
80 ns 8,9
t
RAC
CAC
AA
OEA
RCS
RCH
9,10,17
9,11,17
9
Access Time from CAS
20
40
20
-
ns
ns
ns
t
Access Time from Address
Access Time from OE
t
t
Read Command Setup Time
Read Command Hold Time to CAS
0
0
0
0
ns 21
t
0
0
-
0
-
0
-
-
ns 12,22
t
ns
-
-
-
-
-
-
-
-
Read Command Hold Time to RAS
Column Address to RAS Lead Time
5
5
5
5
12
t
RRH
RAL
CAL
CLZ
OH
OHO
OFF
OEZ
CDD
25
-
30
35
40
28
0
t
ns
ns
ns
-
Column Address to CAS Lead Time
CAS to Output in Low-Z
15
0
18
0
-
-
23
0
-
-
-
-
t
-
-
-
t
3
-
27
ns
Output Data Hold Time
3
-
3
3
t
3
-
Output Data Hold Time from OE
Output Buffer Turn-off Time
Output Buffer Turn-off Time to OE
CAS to DIN Delay Time
3
-
3
3
-
t
ns
-
-
13
13
-
15
15
-
-
15
15
-
-
15
15
-
13,27
ns
t
-
-
-
-
13
ns
t
13
50
3
15
60
18
20
80
3
5
t
ns
tRCHR
tOHR
tOFR
-
-
-
-
-
70
3
ns
Read Command Hold Time from RAS
Output Data hold Time from RAS
Output Buffer turn off to RAS
Output Buffer turn off to WE
-
-
-
27
ns
3
-
-
ns
-
-
27
-
15
15
13
15
-
tWEZ
tWED
-
-
ns
ns
13
-
15
-
15
-
15
-
13
15
18
20
WE to DIN Deray Time
RAS to DIN Delay Time
-
tROD
13
15
-
-
-
ns
18
20
Rev 0.1 / Apr’01
GM71V16163C
GM71VS16163CL
Write Cycle
GM71V(S)16163 GM71V(S)16163 GM71V(S)16163 GM71V(S)16163
C/CL-5 C/CL-6 C/CL-7 C/CL-8
Unit Note
Symol
Parameter
Min Max Min Max Min Max Min Max
Write Command Setup Time
Write Command Hold Time
Write Command Pulse Width
Write Command to RAS Lead Time
Write Command to CAS Lead Time
Data-in Setup Time
14,21
21
0
8
8
8
8
0
8
-
-
-
-
-
-
-
0
10
10
10
10
0
-
-
-
-
-
-
-
0
13
10
13
13
0
-
-
-
-
-
-
-
0
15
10
15
15
0
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
t
WCS
tWCH
t
t
WP
RWL
CWL
23
t
15,23
15,23
tDS
Data-in Hold Time
10
13
15
tDH
Read- Modify-Write Cycle
GM71V(S)16163 GM71V(S)16163 GM71V(S)16163 GM71V(S)16163
C/CL-5 C/CL-6 C/CL-7 C/CL-8
Unit Note
Symbol
Parameter
Min Max Min Max Min Max Min Max
t
RWC
RWD
CWD
AWD
OEH
Read-Modify-Write Cycle Time
RAS to WE Delay Time
111
67
-
-
-
-
-
136
79
-
-
-
-
-
161
92
-
-
-
-
-
185
104
44
-
-
-
-
-
ns
t
ns
ns
ns
ns
14
14
14
t
CAS to WE Delay Time
30
34
40
t
Column Address to WE Delay Time
OE Hold Time from WE
42
49
57
64
t
13
15
18
20
Rev 0.1 / Apr’01
GM71V16163C
GM71VS16163CL
Refresh Cycle
GM71V(S)16163 GM71V(S)16163 GM71V(S)16163 GM71V(S)16163
C/CL-5 C/CL-6 C/CL-7 C/CL-8
Unit Note
Symbol
Parameter
Min Max Min Max Min Max Min Max
t
CSR
CAS Setup Time
(CAS-before-RAS Refresh Cycle)
21
22
5
8
0
-
-
-
5
10
0
-
-
-
5
10
0
-
-
-
5
10
0
-
-
-
ns
ns
ns
tCHR
CAS Hold Time
(CAS-before-RAS Refresh Cycle)
tWRP
WE Setup Time
(CAS-before-RAS Refresh Cycle)
t
WRH
WE Hold Time
(CAS-before-RAS Refresh Cycle)
10
5
-
-
10
5
-
-
10
5
-
-
10
5
-
-
ns
ns
21
tRPC
RAS Precharge to CAS Hold Time
EDO Page Mode Cycle
GM71V(S)16163 GM71V(S)16163 GM71V(S)16163 GM71V(S)16163
C/CL-5 C/CL-6 C/CL-7 C/CL-8
Unit Note
Symbol
Parameter
Min Max Min Max Min Max Min Max
t
HPC
EDO Page Mode Cycle Time
20
-
-
25
-
-
30
-
-
35
-
-
ns
ns
25
16
100,000
100,000
100,000
100,000
EDO Page Mode RAS Pulse Width
Access Time from CAS Precharge
RAS Hold Time from CAS Precharge
tRASP
-
30
-
-
35
-
-
40
-
-
45
-
ns 9,17,22
ns
tACP
30
35
40
45
tRHCP
ns
9
Output data Hold Time from CAS low
3
t
DOH
3
8
-
-
3
-
-
3
-
-
-
10
13
15
ns
ns
CAS Hold Time referred OE
CAS to OE Setup Time
t
COL
-
-
-
-
t
COP
5
5
5
5
Read command Hold Time
from CAS Precharge
30
35
ns
40
t
RCHP
45
-
Rev 0.1 / Apr’01
GM71V16163C
GM71VS16163CL
EDO Page Mode Read-Modify-Write Cycle
GM71V(S)16163 GM71V(S)16163 GM71V(S)16163 GM71V(S)16163
C/CL-5 C/CL-6 C/CL-7 C/CL-8
Unit Note
Symbol
Parameter
Min Max Min Max Min Max Min Max
t
HPRWC EDO Page Mode Read-Modify-Write
57
45
-
-
68
54
-
-
79
62
-
-
88
69
-
-
ns
Cycle Time
ns
14,22
tCPW
WE Delay Time from CAS Precharge
Refresh
GM71V(S)16163 GM71V(S)16163 GM71V(S)16163 GM71V(S)16163
C/CL-5 C/CL-6 C/CL-7 C/CL-8
Unit Note
Symbol
Parameter
Min Max Min Max Min Max Min Max
4096
cycles
-
-
-
-
t
REF
Refresh period
64
64
-
-
64
64
ms
4096
cycles
t
REF
Refresh period (L -Series)
-
128
-
128
128
128 ms
Self Refresh Mode ( L-version )
GM71V(S)16163 GM71V(S)16163 GM71V(S)16163 GM71V(S)16163
C/CL-5 C/CL-6 C/CL-7 C/CL-8
Note
Symbol
Unit
Parameter
Min Max Min Max Min Max Min Max
29
t
RASS
-
-
-
-
-
-
-
-
-
-
-
-
us
ns
RAS Pulse Width(Self-Refresh)
100
90
100
110
-50
100
130
-50
100
150
-50
tRPS
RAS Precharge Time(Self-Refresh)
CAS Hold Time(Self-Refresh)
-50
tCHS
ns
Rev 0.1 / Apr’01
GM71V16163C
GM71VS16163CL
Notes:
1. AC measurements assume tT = 5ns.
2. An intial pause of 200us is required after power up followd by a minimum of eight initialization
cycles(any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh).
If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are
required.
3. Operation with the tRCD(max)limit insures that tRAC(max)can be met, tRCD(max)is specified as a
reference point only; if tRCD >= tRAD(max) + tAA(max) - tCAC(max), then access time is controlled
exclusively by tCAC
.
4. Operation with the tRAD(max) limit insures that tRAC(max)can be met, tRAD(max)is specified as a
reference point only; if tRAD is greater than the specified tRAD(max)limit, then access time is
controlled exclusively by tAA
.
5. Either tOED or tCDD must be satisfied.
6. Either tDZO or tDZC must be satisfied.
7. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Also,
transition times are measured between VIH(min) and VIL(max).
8. Assumes that tRCD <= tRCD(max) and tRAD <= tRAD(max). If tRCD ot tRAD is greater than the
maximum recommended value shown in this table, tRAC exceeds the value shown.
9. Measured with a load circuit equivalent to 1 TTL load and 100pF.
10. Assumes that tRCD >= tRCD(max) and tRCD + tCAC(max) >= tRAD + tAA(max).
11. Assumes that tRAD >= tRAD(max) and tRCD + tCAC(max) <= tRAD + tAA(max).
12. Either tRCH or tRRH must be satisfied for a read cycles.
13. tOFF(max) and tOEZ(max) define the time at which the outputs achieve the open circuit
condition and are not referred to output voltage levels.
14. tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operationg parameters. They are included in
the data sheet as electrical characteristics only; if tWCS >= tWCS(min), the cycle is an early write
cycle and the data out pin will remain open circuit (high impedence) throughout the entire cycle
; if tRWD >= tRWD(min), tCWD >=tCWD(min), and tAWD >= tAWD(min), or tCWD >= tCWD(min),tAWD
>= tAWD(min) and tCPW >= tCPW(min), the cycle is a read-modify-write and the data output will
contain data read from the selected cell; if neither of the above sets of conditions is satisfied,
the condition of data out (at access time)is indeterminate.
15. These parameters are referred to UCAS and LCAS leading edge in early write cycles and to
WE leading edge in delayed write or read-modify-write cycles.
16. tRASP defines RAS pulse width in EDO page mode cycles.
17. Access time is determined by the longest among tAA,tCAC,and tACP
.
18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying
data to the device. After RAS is reset, if tOEH >= tCWL, the I/O pin will remain open circuit
(high impedence); if tOEH< tCWL, invalid data will be out at each I/O.
19. When both UCAS and LCAS go low at the same time, all 16-bit data are written into the device.
UCAS and LCAS cannot be staggered within the same write/read cycles.
20. All the VCC and VSS pins shall be supplied with the same voltages.
Rev 0.1 / Apr’01
GM71V16163C
GM71VS16163CL
21. tASC, tCAH, tRCS, tWCS,tWCH,tCSR and tRPC are determined by the earlier falling edge of UCAS
or LCAS.
22. tCRP,tCHR, tRCH, tACP and tCPW are determned by the later rising edge of UCAS or LCAS.
23. tCWL, tDH,tDS and tCSH should be satisfied by both UCAS and LCAS.
24. tCP is determined by that time the both UCAS and LCAS are high.
25. When output buffers are enabled once, sustain the low impedence state until valid data is
obtained.
When output buffer is turned on and off within a very short time, generally it causes large
VCC/VSS line noise, which causes to degrade VIH min/VIL max level.
26. Please do not use tRASS timing, 10us <= tRASS <=100us. During this period, the device is in
transition state from normal operation mode to self refresh mode. If tRASS >=100us, then
RAS precharge time should use tRPS instead of tRP.
27. If you use distributed CBR refresh within 15.6us inteval in normal read/write cycle, CBR
refresh should be executed within 15.6us immediately after exiting from and before entering
into self refresh mode.
28. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle,4096 or
1024 cycles of distributed CBR refresh with 15.6us interval should be executed within 64 or
16ms immediately after exiting from and before entering into the self refresh mode.
29. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from
self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode
again.
30. H or L (H: VIH(min) <= VIN <= VIH(max), L: VIL(min) <= VIN <= VIL(max))
Rev 0.1 / Apr’01
GM71V16163C
GM71VS16163CL
Notes concerning 2CAS control
Please do not separate the UCAS / LCAS operation timing intentionally. However skew between
UCAS / LCAS are allowed under the following conditions.
1. Each of the UCAS / LCAS should satisfy the timing specifications individually.
2. Different operation mode for upper/lower byte is not allowed;such as following.
RAS
Delayed write
Early write
UCAS
LCAS
WE
3. Closely separated upper/lower byte control is not allowed. However when the condition
(tcp < tUL)is satisfied,EDO page mode can be performed.
RAS
UCAS
LCAS
tUL
4. Byte control operation by remaining UCAS or LCAS high is guaranteed.
Rev 0.1 / Apr’01
GM71V16163C
GM71VS16163CL
Unit : Inches (mm)
Package Dimensions
42 SOJ
0.025(0.64) MIN
1.058(26.89) MIN
0.093(2.38) MIN
1.072(27.23) MAX
0.128(3.25) MIN
0.148(3.75) MAX
0.050(1.27)
TYP
0.026(0.66) MIN
0.032(0.81) MAX
0.015(0.38) MIN
0.020(0.50) MAX
44(50) TSOP (TYPE II)
0~5 o
0.016(0.40) MIN
0.024(0.60) MAX
0.819(20.82) MIN
0.829(21.08) MAX
0.004(0.12) MIN
0.008(0.21) MAX
0.037(0.95) MIN
0.041(1.05) MAX
0.047(1.20)
MAX
0.011(0.30) MIN
0.017(0.45) MAX
0.031(0.80
0.001(0.05) MIN
0.005(0.15) MAX
)
TYP
Rev 0.1 / Apr’01
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