GM71V64403CJ-5 [ETC]
x4 EDO Page Mode DRAM ; X4 EDO页模式DRAM\n
| 型号： | GM71V64403CJ-5 |
| 厂家： | 
ETC |
| 描述： | x4 EDO Page Mode DRAM
|
| 文件： | 总25页 (文件大小：450K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GM71V64403C
GM71VS64403CL
16,777,216 WORDS x 4 BIT
CMOS DYNAMIC RAM
Description
Pin Configuration
32 SOJ / TSOP II
The GM71V(S)64403C/CL is the new generation
dynamic RAM organized 16,777,216 words by 4bits.
The GM71V(S)64403C/CL utilizes advanced CMOS
Silicon Gate Process Technology as well as
advanced circuit techniques for wide operating
margins, both internally and to the system user.
System oriented features include single power supply
of 3.3V+/-10% tolerance, direct interfacing
capability with high performance logic families such
as Schottky TTL.
1
2
3
32
31 IO3
VSS
VCC
IO0
IO1
NC
30
IO2
4
5
6
7
29
28
27
26
NC
NC
NC
NC
VSS
VCC
/CAS
The GM71V(S)64403C/CL offers Extended Data
Out(EDO) Mode as a high speed access mode.
25
8
9
/OE
/WE
/RAS
24 A12
23 A11
22 A10
Features
10
A0
* 16,777,216 Words x 4 Bit
* Extended Data Out (EDO) Mode Capability
* Fast Access Time & Cycle Time
11
12
A1
A2
A3
A9
21
A8
20
13
14
15
(Unit: ns)
A4
A5
19
18
A7
A6
tRAC
tAA
tCAC
tRC
tHPC
84
20
25
50
60
25
30
13
15
GM71V(S)64403C/CL-5
GM71V(S)64403C/CL-6
16
17 VSS
VCC
104
(Top View)
*Power dissipation
- Active : 432mW/396mW(MAX)
- Standby : 1.8 mW ( CMOS level : MAX )
0.54mW ( L-Version : MAX)
*EDO page mode capability
*Access time : 50ns/60ns (max)
*Refresh cycles
- RAS only Refresh
8192 cycles/64 § Â(GM71V64403C)
8192 cycles/128§ Â(GM71VS64403CL)(L_Version)
*CBR & Hidden Refresh
4096 cycles/64 § Â(GM71V64403C)
4096cycles/128 § Â(GM71VS64403CL)( L-Version )
*4 variations of refresh
-RAS-only refresh
-CAS-before-RAS refresh
-Hidden refresh
-Self refresh (L-Version)
*Single Power Supply of 3.3V+/-10 % with a built-in VBB generator
*Battery Back Up Operation ( L-Version )
Rev 0.1 / Apr’01
1
GM71V64403C
GM71VS64403CL
Pin Description
Pin
Function
Address Inputs
Pin
WE
Function
A0-A12
A0-A12
RAS
Write Enable
I/O0 - I/O3
VCC
Data Input / Output
Power (+3.3V)
Ground
Refresh Address Inputs
Row Address Strobe
Column Address Strobe
Output Enable
VSS
CAS
OE
NC
No Connection
Ordering Information
Type No.
Access Time
Package
400 Mil
32Pin
Plastic SOJ
GM71V(S)64403C/CLJ-5
GM71V(S)64403C/CLJ-6
50§ À
60§ À
400 Mil
32Pin
Plastic TSOP II
GM71V(S)64403C/CLT-5
GM71V(S)64403C/CLT-6
50§ À
60§ À
Absolute Maximum Ratings*
Symbol
Parameter
Storage Temperature (Plastic)
Rating
Unit
TSTG
-55 to 125
C
-0.5 to VCC + 0.5
(MAX ; 4.6V)
Voltage on any Pin Relative to VSS
VT
V
VCC
IOUT
PT
Voltage on VCC Relative to VSS
Short Circuit Output Current
Power Dissipation
-0.5 to 4.6
V
50
mA
W
1.0
*Note : Operation at or above Absolute Maximum Ratings can adversely affect device reliability.
Recommended DC Operating Conditions (TA = 0 ~ 70C)
Symbol
VCC
Parameter
Supply Voltage
Typ
Max
3.6
0
Min
3.0
0
Unit
Notes
3.3
0
V
V
1,2
2
VSS
Supply Voltage
Vcc+0.3
0.8
VIH
VIL
Input High Voltage
Input Low Voltage
2.0
-
V
V
1
1
-0.3
-
TA
Ambient Temperature under Bias
70
C
0
-
Rev 0.1 / Apr’01
2
GM71V64403C
GM71VS64403CL
DC Electrical Characteristics: (VCC = 3.3V+/-10%, TA = 0 ~ 70C)
Symbol
Parameter
Min Max Unit Note
VOH
Output Level
Output Level Voltage (IOUT = -2mA)
2.4
0
VCC
V
V
VOL
ICC1
Output Level
Output Level Voltage (IOUT = 2mA)
0.4
Operating Current (tRC = tRC min)
50ns
60ns
-
-
120
110
1,2
mA
mA
Standby Current (TTL interface)
Power Supply Standby Current
(RAS, CAS= VIH, DOUT = High-Z)
ICC2
ICC3
-
2
50ns
60ns
-
-
120
110
RAS-Only Refresh Current
( tRC = tRC min)
mA
2
50ns
60ns
-
-
-
110
100
0.5
ICC4
ICC5
Extended Data Out page Mode Current
(RAS = VIL, CAS, Address Cycling: tHPC = tHPC min)
mA 1,3
mA
CMOS interface
(RAS, CAS>=VCC-0.2V, DOUT = High-Z)
4
Standby Current(L_Version)
-
300
uA
140
130
ICC6
CAS-before-RAS Refresh Current
(tRC = tRC min)
50ns
60ns
-
-
mA
Battery Back Up Operating Current(Standby with CBR)
(tRC=31.25us,tRAS=300ns,Dout=High-Z)
uA
ICC7
ICC8
-
500
4, 5
1
Standby Current (CMOS)
Power Supply Standby Current
RAS = VIH, CAS = VIL , DOUT = Enable
-
5
mA
ICC9
II(L)
Self Refresh Current
(RAS, CAS <=0.2V,Dout=High-Z)
-
400
5
uA
uA
uA
5
Input Leakage Current, Any Input
(0V<=VIN<=Vcc)
-5
-5
IO(L)
Output Leakage Current
(DOUT is Disabled, 0V<=VOUT<=Vcc)
5
Note: 1. ICC depends on output load condition when the device is selected. ICC(max) is specified at the
output open condition.
2. Address can be changed once or less while RAS = VIL.
3. Measured with one sequential address change per EDO cycle, tHPC.
4. VIH>=VCC-0.2V, 0V<=VIL<=0.2V
5. L-Version
Rev 0.1 / Apr’01
3
GM71V64403C
GM71VS64403CL
Capacitance (VCC = 3.3V+/-10%, TA = 25C)
Symbol
CI1
Parameter
Typ
Max
Unit
§ Ü
§ Ü
§ Ü
Note
1
-
Input Capacitance (Address)
Input Capacitance (Clocks)
5
7
7
CI2
-
-
1
CI/O
Output Capacitance (Data-in,Data-Out)
1, 2
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. RAS, CAS = VIH to disable DOUT.
AC Characteristics (VCC = 3.3V+/-10%, TA = 0 ~ 70C, Notes 1, 2,19)
Test Conditions
Input rise and fall times : 2ns
Input level : VIL/VIH = 0.0/3.0V
Input timing reference levels : VIL/VIH = 0.8/2.0V
Output timing reference levels : VOL/VOH = 0.8/2.0V
Output load : 1 TTL gate+CL (100pF)
(Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)
GM71V(S)64403C/CL-5 GM71V(S)64403C/CL-6
Symbol
Parameter
Notes
Unit
Min
84
Min
Max
Max
104
-
-
t
t
RC
RP
§ À
§ À
§ À
§ À
§ À
§ À
§ À
§ À
Random Read or Write Cycle Time
RAS Precharge Time
30
40
-
-
8
-
10000
10000
-
10
60
10
0
-
CAS Precharge Time
t
CP
50
10000
t
t
t
t
t
t
t
t
t
t
t
t
t
t
RAS
CAS
ASR
RAH
ASC
CAH
RCD
RAD
RSH
CSH
CRP
ODD
DZO
DZC
RAS Pulse Width
10000
8
0
CAS Pulse Width
-
-
Row Address Set-up Time
Row Address Hold Time
Column Address Set-up Time
Column Address Hold Time
RAS to CAS Delay Time
RAS to Column Address Delay Time
RAS Hold Time
10
0
8
-
-
0
-
10
8
-
-
§ À
§ À
3
4
14
12
15
12
10
13
35
5
37
25
-
45
30
-
§ À
§ À
§ À
§ À
40
5
-
-
-
-
CAS Hold Time
CAS to RAS Precharge Time
OE to DIN Delay Time
OE Delay Time from DIN
15
13
0
-
-
-
-
§ À
§ À
§ À
5
0
0
-
6
6
7
-
0
CAS Delay Time from DIN
TransitionTime (Rise and Fall)
Refresh Period
50
t
T
2
-
2
-
50
64
§ À
§ Â
§ Â
8192
cycles
8192
t
REF
64
-
-
Refresh Period ( L-Version )
128
128
cycles
Rev 0.1 / Apr’01
4
GM71V64403C
GM71VS64403CL
Read Cycles
GM71V(S)64403C/CL-6
GM71V(S)64403C/CL-5
Symbol
Parameter
Notes
Unit
Min
Max
50
Max
60
Min
-
-
-
-
§ À
§ À
Access Time from RAS
tRAC
CAC
8,9
13
15
Access Time from CAS
9,10,17
t
-
-
25
13
-
-
30
15
-
§ À
§ À
Access Time from Column Address
Access Time from OE
t
AA
9,11,17
9
t
OAC
RCS
0
0
0
Read Command Set-up Time
-
§ À
§ À
§ À
§ À
§ À
t
12
12
0
-
-
Read Command Hold Time to CAS
Read Command Hold Time to RAS
Column Address to RAS Lead Time
Column Address to CAS Lead Time
Output Buffer Turn-off Delay Time from
-
-
t
RCH
RRH
0
0
t
30
18
25
15
-
-
-
t
RAL
CAL
OFF
OEZ
CDD
-
t
-
-
13
13
-
-
-
15
15
§ À
§ À
§ À
t
13,21
13
CAS
Output Buffer Turn-off Delay Time from OE
t
13
-
-
5
15
15
CAS to DIN Delay Time
RAS to DIN Delay Time
t
-
13
§ À
t
RDD
15
-
§ À
§ À
-
-
WE to DIN Delay Time
13
-
t
WDD
13,21
13
Output Buffer Turn-off Delay Time from RAS
13
13
15
15
t
OFR
-
3
-
tWEZ
§ À
§ À
§ À
Output Buffer Turn-off Delay Time from WE
Output Data Hold Time
3
21
-
-
-
-
-
-
-
-
tOH
Output Data Hold Time from RAS
3
3
21
tOHR
50
3
Read Command Hold Time from RAS
Output data hold time from OE
CAS to Output in Low - Z
60
3
§ À
§ À
§ À
tRCHR
-
-
t
OHO
0
0
tCLZ
Rev 0.1 / Apr’01
5
GM71V64403C
GM71VS64403CL
Write Cycles
GM71V(S)64403C/CL-5 GM71V(S)64403C/CL-6
Notes
Symbol
Parameter
Unit
Min
Min
0
Max
Max
0
8
-
-
-
-
-
14
t
WCS
WCH
WP
RWL
CWL
Write Command Set-up Time
Write Command Hold Time
§ À
§ À
§ À
§ À
§ À
§ À
§ À
10
10
15
10
0
-
-
-
-
-
-
t
8
Write Command Pulse Width
t
13
8
Write Command to RAS Lead Time
t
-
-
t
Write Command to CAS Lead Time
Data-in Set-up Time
15
15
0
t
t
DS
10
8
-
Data-in Hold Time
DH
Read-Modify-Write Cycles
GM71V(S)64403C/CL-5
GM71V(S)64403C/CL-6
Notes
Symbol
Parameter
Unit
Min
116
67
Min
Max
Max
140
-
-
-
-
-
-
Read-Modify-Write Cycle Time
t
RWC
RWD
CWD
AWD
OEH
§ À
§ À
§ À
§ À
§ À
79
34
49
15
-
-
14
14
t
RAS to WE Delay Time
30
t
CAS to WE Delay Time
42
14
-
-
t
Column Address to WE Delay Time
OE Hold Time from WE
13
t
Refresh Cycles
GM71V(S)64403C/CL-5
GM71V(S)64403C/CL-6
Notes
Symbol
Unit
Parameter
Min
Min
Max
Max
CAS Set-up Time
(CAS-before-RAS Refresh Cycle)
-
-
5
§ À
t
CSR
5
CAS Hold Time
(CAS-before-RAS Refresh Cycle)
8
0
-
-
-
-
10
0
§ À
§ À
t
t
CHR
WRP
WE setup time
(CAS-before-RAS Refresh
Cycle)
WE hold time
(CAS-before-RAS Refresh
8
5
-
-
10
5
-
-
§ À
§ À
t
t
WRH
RPC
Cycle)
RAS Precharge to CAS Hold Time
6
Rev 0.1 / Apr’01
GM71V64403C
GM71VS64403CL
Extended Data Out Mode Cycles
GM71V(S)64403C/CL-5
GM71V(S)64403C/CL-6
Notes
Symbol
Parameter
Unit
Min
20
8
Min
Max
Max
25
-
-
EDO Page Mode Cycle Time
t
HPC
WPE
20
§ À
-
§ À
10
-
-
-
t
Write pulse width during CAS Precharge
EDO Mode RAS Pulse Width
100000
-
100000
t
t
RASP
ACP
16
§ À
§ À
§ À
§ À
§ À
§ À
Access Time from CAS Precharge
-
35
-
9,17
28
-
-
35
10
t
RHCP
28
8
RAS Hold Time from CAS Precharge
-
-
-
-
t
COL
COP
CAS Hold Time Referred OE
CAS to OE set-up Time
5
-
5
t
35
t
RCHP
28
-
Read Command Hold Time from CAS
Precharge
t
t
DOH
OEP
Output Data Hold Time from CAS Low
OE Precharge Time
3
8
-
-
-
-
3
§ À
§ À
9,22
10
EDO Page Mode Read-Modify-Write cycle
GM71V(S)64403C/CL-5
GM71V(S)64403C/CL-6
Notes
Symbol
Parameter
Unit
Min
57
Min
68
Max
Max
EDO Read-Modify-Write Cycle Time
-
-
-
-
t
t
HPRWC
CPW
§ À
§ À
45
54
14
EDO Page Mode Read-Modify-Write Cycle
CAS Precharge to WE Delay Time
Self Refresh Cycles (L_Version)
GM71V(S)64403C/CL-5
GM71V(S)64403C/CL-6
Symbol
Parameter
Notes
Unit
Min
100
90
Min
100
110
-50
Max
Max
us
-
-
-
-
-
-
t
RASS
26
26
RAS Pulse Width(Self-Refresh)
§ À
§ À
t
t
RPS
CHS
RAS Precharge Time(Self-Refresh)
CAS Hold Time(Self-Refresh)
-50
7
Rev 0.1 / Apr’01
GM71V64403C
GM71VS64403CL
Notes:
AC measurements assume tT = 2§ À.
AC initial pause of 200 § Áis required after power up followed by a minimum of eight
1.
2.
initialization cycles ( any combination of cycles containing RAS-only refresh or CAS-before-
RAS refresh)
Operation with the tRCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a
reference point only: if tRCD is greater than the specified tRCD(max) limit, then access time is
controlled exclusively by tCAC.
3.
4.
5.
Operation with the tRAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a
reference point only: if tRAD is greater than the specified tRAD(max) limit, then access time is
controlled exclusively by tAA.
Either tOED or tCDD must be satisfied.
6. Either tDZO or tDZC must be satisfied.
7. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Also,
transition times are measured between VIH(min) and VIL (max).
8. Assumes that tRCD¡ ÂtRCD(max) and tRAD¡ ÂtRAD(max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
10. Assumes that tRCD¡ ÃRCD
t
(max) and tRCD +tCAC(max) ¡ ÃtRAD +tAA(max).
11.
12.
Assumes that tRAD ¡ ÃtRAD (max) and tRCD + tCAC(max)¡ ÂtRAD +tAA(max).
Either tRCH or tRRH must be satisfied for a read cycles.
tOFF(max), tOEZ(max), tOFR(max) and tWEZ(max) define the time at which the outputs achieve the
open circuit condition and is not referenced to output voltage levels.
13.
14.
tWCS, tRWD, tCWD, tAWD, and tCPW are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only: if tWCS ¡ tÃWCS(min), the cycle is an early write cycle
and the data out pin will remain open circuit (high impedance) throughout the entire cycle: if
tRWD ¡ ÃtRWD(min), tCWD¡ tÃCWD(min), tAWD¡ ÃtAWD(min) and tCPW¡ ÃtCPW(min), the cycle is a read-
modify-write and the data output will contain data read from the selected cell: if neither of the
above sets of conditions is satisfied, the condition of the data out (at access time) is
indeterminate.
15.
tDS and tDH are referred to CAS leading edge in early write cycles and to WE leading edge in
delayed write or read-modify-write cycles.
16. tRASP defines RAS pulse width in extended data out mode cycles.
Access time is determined by the longest among tAA, tCAC and tCPA.
17.
18.
In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying
data to the device.
19.
When output buffers are enabled once, sustain the low impedance state until valid daa is
obtained. When output buffer is turned on and off within a very short time, generally it causes
large VCC/VSS line noise, which causes to degrade VIH min/VIL max level.
Rev 0.1 / Apr’01
8
GM71V64403C
GM71VS64403CL
HPC
t
(min) can be achieved during a series of EDO mode early write cycles or EDO mode read
20.
21.
cycles. If both write and read operation are mixed in a EDO mode, RAS cycle { EDO mode mix
cycle (1),(2) } minimum value of CAS cycle t
specified t (min) value.
EDO page mode mix cycle (1) and (2).
HPC CAS
CP
T
(t + t + 2t ) becomes greater than the
HPC
The value of CAS cycle time of mixed EDO page mode is shown in
Data output turns off and becomes high impedance from later rising edge of RAS and CAS.
Hold time and turn off time are specified by the timing specifications of later rising edge of RAS
and CAS between t and t , and between t and t
OHR
OH
OFR
OFF
.
DOH
OL
OH
t
defines the time at which the output level go cross.
V
=0.8V, V =2.0V of output timing
22.
23.
reference level.
Before and after self refresh mode, execute CBR refresh to all refresh addresses in or within 64
period on the condition a and b below.
§ Â
a. Enter self refresh mode within 15.6
after either burst refresh or distributed refresh at equal
us
interval to all refresh addresses are completed.
b. Start burst refresh or distributed refresh at equal interval to all refresh addressed within 15.6
after exiting from self refresh mode.
us
In case of entering from RAS-only-refresh, it is necessary to execute CBR refresh before and
after self refresh mode according as note 23.
24.
25.
26.
27.
For L_Version, it is available to apply each 128
note 23.
and 31.2
§ Â
instead of 64
and 15.6 at
§ Â us
us
RASS
RASS
At t
100
, self refresh mode is activated, and not active at t
10 . It is undefined
£ ¼ us
£ ¾ us
RASS
t
RASS
RPS
within the range of 10
100 . for t
10 , it is necessary to satisfy t
£ ¾ us
.
us £ ¼ £ ¼ us
IH
IN
IH
IH
IN
IH
XXX: H or L ( H : V (min)
V
V (max), L: V (min) V (max))
V
<= <= <= <=
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must
IH
IL.
be applied V or V
Rev 0.1 / Apr’01
9
GM71V64403C
GM71VS64403CL
Timing Waveforms
tRC
tRAS
tRP
RAS
tCSH
tCRP
tRCD
tRSH
tCAS
tT
CAS
t
RAD
t
tRCAALL
tASR
t
RAH
tASC
t
CA
H
ADDRESS
ROW
COLUMN
tRRH
tRCHR
tRCS
tRCH
WE
tCAC
tWEZ
tAA
tOFF
tCLZ
High-Z
DOUT
DOUT
tOFR
tRDD
tRAC
tOHR
tOH
tWDD
t
OEZ
OHO
CDD
t
tDZC
t
High-Z
DIN
OE
tDZO
tODD
tOAC
FIGURE 1. READ CYCLE
Rev 0.1 / Apr’01
10
GM71V64403C
GM71VS64403CL
tRC
tRAS
tRP
RAS
tRSH
tT
tRCD
tCAS
tCRP
tCSH
CAS
tASR
tRAH
tASC
tCAH
ADDRESS
ROW
COLUMN
tWCS
tWCH
WE
tDS
tDH
DIN
DIN
High-Z
DOUT
FIGURE 2. EARLY WRITE CYCLE
Rev 0.1 / Apr’01
11
GM71V64403C
GM71VS64403CL
tRC
tRAS
tRP
RAS
t
RSH
tT
tRCD
t
CAS
tCRP
tCSH
CAS
tASR
tRAH
tCAH
tASC
ADDRESS
ROW
COLUMN
tCWL
tRWL
tRCS
tWP
WE
tDZC
tDH
tDS
High-Z
DIN
DIN
tODD
tOEH
tDZO
tOEP
OE
tOEZ
tCLZ
High-Z
INVALID
OUTPUT
DOUT
FIGURE 3. DELAYED WRITE CYCLE*18
Rev 0.1 / Apr’01
12
GM71V64403C
GM71VS64403CL
tRWC
tRAS
tRP
RAS
CAS
tT
tRCD
tCAS
tCRP
tRAD
tRAH
tASR
tCAH
tASC
ADDRESS
ROW
COLUMN
t
CWL
t
CWD
tRCS
t
AWD
tRWL
tRWD
tWP
WE
tAA
tRAC
tDH
tDS
tDZC
tCAC
High-Z
DIN
DIN
tODD
tOEH
tCLZ
High-Z
DOUT
DOUT
tOAC
tOEZ
tOHO
tOEP
tDZO
OE
*18
FIGURE 4. READ MODIFY WRITE CYCLE
Rev 0.1 / Apr’01
13
GM71V64403C
GM71VS64403CL
tRC
tRAS
tRP
RAS
CAS
tT
tCRP
tRPC
tCRP
tASR
tRAH
ADDRESS
ROW
tOFR
tOFF
High-Z
DOUT
FIGURE 5. RAS ONLY REFRESH CYCLE
tRC
tRC
tRP
tRAS
tRP
tRAS
tRP
RAS
CAS
tT
t
RPC
t
RPC
tCRP
t
CP
tCSR
tCHR
t
CP
tCSR
tCHR
tWRP
tWRH
tWRP
tWRH
WE
ADDRESS
tOFR
tOFF
High-Z
DOUT
FIGURE 6. CAS BEFORE RAS REFRESH CYCLE
Rev 0.1 / Apr’01
14
GM71V64403C
GM71VS64403CL
tRC
tRC
tRC
tRAS
tRP
tRAS
tRP
tRAS
tRP
RAS
CAS
tT
tCHR
tRSH
tRCD
tCRP
tCAS
tRAD
tRAL
tASR
tRAH
tCAH
tASC
ADDRESS
ROW
COLUMN
t
RCH
tRCS
tRRH
WE
t
t
WDD
tDZC
CDD
tRDD
High-Z
DIN
tDZO
tOAC
tODD
OE
t
CAC
t
OEZ
WEZ
OHO
OFF
OH
t
AA
t
tRAC
t
tCLZ
t
t
DOUT
DOUT
tOFR
tOHR
FIGURE 7. HIDDEN REFRESH CYCLE
Rev 0.1 / Apr’01
15
GM71V64403C
GM71VS64403CL
tRASP
tRP
tHPC
RAS
tCRP
tRHCP
tHPC
tHPC
tT
tCSH
tCP
tCP
tCP
tRSH
CAS
tCAS
tCAS
tCAS
tCAS
tRCHR
tRCHP
t
RRH
tRCS
tRCH
tRCH
WE
tRAL
tWDD
t
WPE
tCAH
tCAH
tCAH
tRAH
tCAH
tASR
tASC
tASC
tASC
tASC
COLUMN
COLUMN
COLUMN
COLUMN
ADDRESS
ROW
tCAL
tCAL
tCAL
t
RDD
tCAL
tDZC
tCDD
High-Z
DIN
t
COL
tDZO
tCOP
tOEP
tODD
tOEP
OE
t
tOOFHRR
t
OEZ
t
ACP
AA
CAC
t
OAC
tOEZ
t
OHO
t
t
ACP
t
t
OHO
AA
t
CAC
tCAC
t
tCAC
tOFF
t
WEZ
AA
tAA
t
OEZ
tOH
t
OAC
tOAC
t
t
DOH
tRAC
t
OHO
t
ACP
High-Z
DOUT
DOUT 1
DOUT 2
DOUT 2
DOUT 3
DOUT 4
FIGURE 8. EXTENDED DATA OUT PAGE MODE READ CYCLE(1)
Rev 0.1 / Apr’01
16
GM71V64403C
GM71VS64403CL
tRASP
tRP
tHPC
RAS
tCRP
tRHCP
tHPC
tHPC
tT
tCSH
tCP
tCP
tCP
tRSH
CAS
tCAS
tCAS
tCAS
tCAS
tRCHP
t
RRH
tRCS
tRCH
WE
tRAL
tWDD
tCAH
tCAH
tCAH
tRAH
tCAH
tASR
tASC
tASC
tASC
tASC
COLUMN1
COLUMN2
COLUMN3
COLUMN4
ADDRESS
ROW
tCAL
tCAL
tCAL
t
RDD
tCAL
tDZC
tCDD
High-Z
DIN
t
COL
tDZO
tCOP
tOEP
tODD
tOEP
OE
t
tOOFHRR
t
OEZ
t
ACP
AA
CAC
t
OAC
tOEZ
t
OHO
t
t
ACP
t
t
OHO
AA
tCAC
t
CAC
t
tCAC
tOFF
tAA
tAA
t
OEZ
tOH
t
OAC
tOAC
t
DOH
tDOH
tRAC
t
ACP
t
OHO
High-Z
DOUT
DOUT 1
DOUT 2
DOUT 2
DOUT 3
DOUT 4
FIGURE 8. EXTENDED DATA OUT PAGE MODE READ CYCLE(2)
Rev 0.1 / Apr’01
17
GM71V64403C
GM71VS64403CL
tRP
tRASP
RAS
tT
tHPC
tCSH
tRSH
tCRP
tRCD
tCAS
tCP
tCAS
tCP
tCAS
CAS
tASR
tCAH
tASC
tASC
tASC
tRAH
tCAH
tCAH
ADDRESS
ROW
COLUMN 1
COLUMN 2
COLUMN N
tWCS
tWCS
tWCH
tWCH
tWCS
tWCH
WE
tDS
tDH
tDS
tDH
tDS
tDH
D
D
IN
D
IN 1
D
IN 2
DIN N
High-Z*
OUT
FIGURE 10. EXTENDED DATA OUT MODE EARLY WRITE CYCLE
Rev 0.1 / Apr’01
18
GM71V64403C
GM71VS64403CL
tRP
tRASP
RAS
CAS
tCP
tCP
tCRP
tT
tCSH
t
HPC
t
RSH
tRCD
tCAS
t
CAS
t
CAS
tASC
tASR
tASC
tASC
tRAD
tRAH
tCAH
tCAH
tCAH
ROW
COLUMN 1
COLUMN 2
COLUMN N
ADDRESS
tCWL
tCWL
tCWL
tRWL
tRCS
tRCS
tRCS
WE
tWP
tWP
tWP
tDZC
tDS
tDS
tDS
tDZC
tDZC
tDH
tDH
tDH
DIN
DIN 1
DIN 2
DIN N
tDZO
tDZO
tDZO
tODD
tODD
tODD
tOEH
tOEH
tOEH
OE
tOEP
tOEP
tCLZ
tCLZ
tCLZ
tOEZ
tOEZ
tOEZ
High-Z
INVALID
INVALID
INVALID
DOUT
DOUT
DOUT
DOUT
*18
FIGURE 11. EXTENDED DATA OUT MODE DELAYED WRITE CYCLE
Rev 0.1 / Apr’01
19
GM71V64403C
GM71VS64403CL
tRP
tRASP
RAS
t
HPRWC
tCRP
tT
t
RSH
tCP
tCP
tRCD
tCAS
tCAS
t
CAS
CAS
tRAD
tASR
tASC
tASC
tASC
tRAH
tCAH
tCAH
tCAH
ROW
COLUMN 1
COLUMN 2
COLUMN N
ADDRESS
t
CPW
AWD
CWD
t
CPW
t
RWD
AWD
CWD
tCWL
tCWL
t
CWL
t
t
t
AWD
t
t
t
CWD
t
RWL
tRCS
tRCS
tRCS
WE
tWP
tWP
tWP
tDZC
tDS
tDS
tDS
tDZC
tDZC
tDH
tDH
tDH
High-Z
DIN
OE
DIN 1
DIN 2
DIN N
tDZO
tDZO
t
OEP
t
OEP
t
OEP
t
DZO
tODD
tODD
tOEH
tOEH
tOEH
tODD
t
OEZ
t
OEZ
tOEZ
t
OHO
tOHO
t
OHO
t
t
OAC
CAC
AA
t
OAC
t
OAC
t
CAC
tCAC
t
AA
t
AA
t
tACP
t
ACP
tRAC
tCLZ
tCLZ
tCLZ
DOUT 1
DOUT 2
DOUT N
High-Z
DOUT
*18
FIGURE 12. EXTENDED DATA OUT MODE READ MODIFY WRITE CYCLE
Rev 0.1 / Apr’01
20
GM71V64403C
GM71VS64403CL
tRP
tRASP
RAS
CAS
tT
tCP
tCP
tCP
tCRP
tCAS
tCAS
tCAS
tCAS
tRCD
tCSH
tWP
tRSH
tWCS
tRRH
tWCH
tRCS
tRCH
tCPW
tRAL
WE
tAWD
tASC
tASC
tASC
tRAH
tASC
tCAH
tCAH
tCAH
tCAH
tASR
COLUMN
4
COLUMN
1
COLUMN
3
COLUMN
2
ROW
ADDRESS
t
RDD
tDS
tCAL
tCAL
tDH
tDS
t
CDD
tDH
High - Z
DIN 1
DIN 3
Din
tWDD
tODD
tOEP
OE
t
CAC
OAC
AA
ACP
t
t
CAC
AA
OAC
ACP
t
OFR
t
CAC
t
WEZ
t
DOH
t
OEZ
t
t
t
t
OEZ
t
OFF
t
tAA
t
OHO
tOH
t
tACP
High - Z
DOUT 2
DOUT
4
DOUT 3
Dout
*20
FIGURE 13. EXTENDED DATA OUT MODE MIX CYCLE (1)
Rev 0.1 / Apr’01
21
GM71V64403C
GM71VS64403CL
tRP
tRASP
RAS
CAS
tT
tCSH
tCRP
tCP
tCP
tCP
tCAS
tCAS
tCAS
tCAS
tRCD
t
RCHR
tRRH
tRSH
tWCH
tWP
tRCH
tRCS
tRCH
tWCS
tCPW
tRAL
WE
tASC
tASC
tASC
tASC
tRAH
tCAH
tCAH
tCAH
tCAH
tASR
COLUMN
3
COLUMN
4
COLUMN
2
COLUMN
1
ROW
ADDRESS
t
CAL
tCAL
t
CAL
tCAL
t
t
RDD
tDS
tDS
t
DH
t
DH
CDD
High - Z
Din
DIN 2
DIN 3
tODD
tWDD
tODD
tCOL
tOEP
tOEP
OE
t
COP
t
CAC
t
t
CAC
AA
OAC
OAC
t
t
CAC
AA
OAC
RAC
t
t
WEZ
t
t
t
AA
OAC
ACP
tOEZ
OEZ
t
OEZ
t
tOOFHF
t
t
t
t
tOHO
t
OFR
High - Z
DOUT 3
DOUT 1
DOUT 4
Dout
tOHO
FIGURE 14. EXTENDED DATA OUT MODE MIX CYCLE (2) *20
Rev 0.1 / Apr’01
22
GM71V64403C
GM71VS64403CL
tRP
tRASS
tRPS
RAS
tRPC
tT
tCHS
tCRP
tCSR
tCP
CAS
tWRP
tWRH
WE
tOFR
tOFF
High-Z
DOUT
*23, 24, 25, 26
FIGURE 15. SELF REFRESH CYCLE
Rev 0.1 / Apr’01
23
GM71V64403C
GM71VS64403CL
SOJ 32 pin PKG Dimension
Unit: mm
0.64 MIN
1.16 MAX
2.09 MIN
3.01 MAX
20.95 MIN
21.38 MAX
1.165 MAX
0.33 MIN
0.53 MAX
1.27
0.33 MIN
0.49 MAX
0.10
Rev 0.1 / Apr’01
24
GM71V64403C
GM71VS64403CL
TSOPII 32 PIN Package Dimension
0.40 MIN
Unit: mm
¡ £
20.95 MIN
21.35 MAX
0.60 MAX
0 ~ 5
NORMAL TYPE
0.145 0.05
0.125 0.04
0.80
1.15 MAX
0.42 0.08
0.40 0.06
1.27
0.08 MIN
0.18 MAX
0.10
Dimension including the plating thickness
Base material dimension
Rev 0.1 / Apr’01
25
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