GM71VS18160CLJ-7 [ETC]

x16 Fast Page Mode DRAM ; X16快速页模式DRAM\n


型号：	GM71VS18160CLJ-7
厂家：	ETC
描述：	x16 Fast Page Mode DRAM X16快速页模式DRAM\n 动态存储器
文件：	总10页 (文件大小：107K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

GM71V18160C

GM71VS18160CL

1,048,576 WORDS x 16 BIT

CMOS DYNAMIC RAM

Description

Features

The GM71V(S)18160C/CL is the new

generation dynamic RAM organized 1,048,576

x 16 bit. GM71V(S)18160C/CL has realized

higher density, higher performance and various

functions by utilizing advanced CMOS process

technology. The GM71V(S)18160C/CL offers

Fast Page Mode as a high speed access mode.

Multiplexed address inputs permit the

GM71V(S)18160C/CL to be packaged in

standard 400 mil 42pin plastic SOJ, and

standard 400mil 44(50)pin plastic TSOP II. The

package size provides high system bit densities

and is compatible with widely available

automated testing and insertion equipment.

* 1,048,576 Words x 16 Bit Organization

* Fast Page Mode Capability

* Single Power Supply (3V+/-0.3V)

* Fast Access Time & Cycle Time

(Unit: ns)

tRAC

tCAC

tPC

110

130

GM71V(S)18160C/CL-5

GM71V(S)18160C/CL-6

GM71V(S)18160C/CL-7

* Low Power

Active : 684/612/540/468mW (MAX)

Standby : 7.2mW (CMOS level : MAX)

0.54mW (L-version : MAX)

* RAS Only Refresh, CAS before RAS Refresh,

Hidden Refresh Capability

* All inputs and outputs TTL Compatible

* 1024 Refresh Cycles/16ms

* 1024 Refresh Cycles/128ms (L-version)

* Self Refresh Operation (L-version)

* Battery Back Up Operation (L-version)

* 2 CAS byte Control

Pin Configuration

42 SOJ

44(50) TSOP II

VSS

VCC

VSS

VCC

I/O0

I/O1

I/O2

I/O3

VCC

I/O0

I/O1

I/O2

I/O3

VCC

I/O4

I/O5

I/O6

I/O7

I/O15

⁴⁸I/O14

40 I/O14

39 I/O13

I/O13

⁴⁶I/O12

⁴⁵VSS

I/O12

VSS

I/O11

I/O4

I/O5

I/O6

I/O7

⁴³I/O10

⁴²I/O9

⁴¹I/O8

I/O10

I/O9

I/O8

LCAS

UCAS

RAS

NC 15

36 NC

LCAS

UCAS

RAS

A11

A10

26 A7

²⁸A5

²⁷A4

23 A4

VCC

VSS

VCC

VSS

(Top View)

Rev 0.1 / Apr’01

GM71V18160C

GM71VS18160CL

Pin Description

A0-A9

Function

Address Inputs

Read/Write Enable

A0-A9

Refresh Address Inputs

Data Input/ Data Output

Row Address Strobe

Output Enable

Power (+3.3V)

Ground

I/O0-I/O15

RAS

UCAS, LCAS

Column Address Strobe

No Connection

Ordering Information

Type No.

Access Time

Package

GM71V(S)18160CJ/CLJ -5

GM71V(S)18160CJ/CLJ -6

GM71V(S)18160CJ/CLJ -7

50ns

60ns

70ns

400 Mil

42 Pin

Plastic SOJ

GM71V(S)18160CT/CLT -5

GM71V(S)18160CT/CLT -6

GM71V(S)18160CT/CLT -7

50ns

60ns

70ns

400 Mil

44(50) Pin

Plastic TSOP II

Absolute Maximum Ratings*

Symbol

Parameter

Rating

0 ~ 70

Unit

Ambient Temperature under Bias

TSTG

Storage Temperature

-55 ~ 125

-0.5 ~ Vcc+0.5

(<=4.6V(MAX))

Voltage on any Pin Relative to VSS

VIN/OUT

VCC

IOUT

Supply Voltage Relative to VSS

Short Circuit Output Current

Power Dissipation

-0.5 ~ 4.6

1.0

Note: Operation at or above Absolute Maximum Ratings can adversely affect device reliability.

Rev 0.1 / Apr’01

GM71V18160C

GM71VS18160CL

Recommended DC Operating Conditions (TA = 0 ~ +70C)

Symbol

VCC

Parameter

Min

3.0

Typ

Max

3.6

Unit

Supply Voltage

3.3

Input High Voltage

Input Low Voltage

2.0

CC + 0.3

0.8

VIH

-0.3

VIL

Note: All voltage referred to Vss.

The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be

on the same level.

Truth Table

Output

Open

Operation

RAS

LCAS UCAS

Notes

1,3

Standby

Valid

Lower byte

1,3

Valid

Read cycle

Upper byte

Valid

Word

Open

Lower byte

Open

Early write cycle

Upper byte

1,2,3

1,3

Open

Word

Undefined

Lower byte

Upper byte

Delayed Write

cycle

Undefined

Valid

Word

Lower byte

H to L L to H

Read-modify

-write cycle

Upper byte

Valid

Open

Word

H to L

CBR Refresh

Self Refresh

(L-series)

Open

Word

1,3

RAS-only

Refresh cycle

Open

Word

1,3

Read cycle

(Output disabled)

Notes: 1. H: High (inactive) L: Low(active) D: H or L

2. tWCS >= 0ns Early write cycle

tWCS <= 0ns Delayed write cycle

3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by earliest of

UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However

write OPERATION and output High-Z control are done independently by each UCAS,LCAS.

ex) if RAS = H to L, UCAS = H, LCAS = L, then CAS-before-RAS refresh cycle is selected.

Rev 0.1 / Apr’01

GM71V18160C

GM71VS18160CL

DC Electrical Characteristics (VCC = 3.3V+/-0.3V, Vss = 0V, TA = 0 ~ 70C)

Symbol

Parameter

Min Max Unit Note

Output Level

Output "H" Level Voltage (IOUT = -2mA)

2.4

Output Level

Output "L" Level Voltage (IOUT = 2mA)

0.4

50ns

190

Operating Current

Average Power Supply Operating Current

(RAS, UCAS or LCAS Cycling: tRC = tRC min)

CC1

170

150

60ns

70ns

1, 2

CC2

CC3

Standby Current (TTL)

Power Supply Standby Current

(RAS, UCAS, LCAS = VIH, DOUT = High-Z)

50ns

60ns

70ns

50ns

190

170

RAS Only Refresh Current

Average Power Supply Current

RAS Only Refresh Mode

(tRC = tRC min)

150

185

165

CC4

Fast Page Mode Current

Average Power Supply Current

Fast Page Mode

1, 3

60ns

70ns

(tPC = tPC min)

145

Standby Current (CMOS)

Power Supply Standby Current

(RAS, UCAS or LCAS >= VCC - 0.2V, DOUT = High-Z)

CC5

CC6

150

CAS-before-RAS Refresh Current

(tRC = tRC min)

50ns

60ns

70ns

190

170

150

Battery Back Up Operating Current

(Standby with CBR Refresh)

(tRC=125us, tRAS<=0.3us, DOUT=High-Z)

CC7

400

4,5

Standby Current RAS = VIH

UCAS, LCAS = VIL

CC8

CC9

OUT = Enable

Self-Refresh Mode Current

(RAS, UCAS or LCAS<=0.2V, DOUT=High-Z)

250

L(I)

Input Leakage Current

Any Input (0V<=VIN<= 4.6V)

-10

Output Leakage Current

(DOUT is Disabled, 0V<=VOUT<= 4.6V)

L(O)

-10

Note: 1. ICC depends on output load condition when the device is selected.

CC(max) is specified at the output open condition.

2. Address can be changed once or less while RAS = VIL

3. Address can be changed once or less while LCAS and UCAS = VIH

4. UCAS = L (<=0.2) and LCAS = L (<=0.2) while RAS = L (<=0.2).

5. L-version.

Rev 0.1 / Apr’01

GM71V18160C

GM71VS18160CL

Capacitance (VCC = 3.3V+/-0.3V, TA = 25C)

Symbol

CI1

Parameter

Input Capacitance (Address)

Input Capacitance (Clocks)

Output Capacitance (Data-In/Out)

Min

Max

Unit

Note

CI2

CI/O

1, 2

Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.

2. UCAS and LCAS = VIH to disable DOUT

AC Characteristics (VCC = 3.3V+/-0.3V, TA = 0 ~ 70C, Note 1, 2, 18, 19, 20)

Test Conditions

Input rise and fall times : 5 ns

Input timing reference levels : 0.8V, 2.0V

Output timing reference levels : 0.8V, 2.0V

Output load : 1TTL gate + CL (100 pF)

(Including scope and jig)

Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)

GM71V(S)18160 GM71V(S)18160 GM71V(S)18160

C/CL-5

C/CL-6

C/CL-7

Unit Note

Symbol

Parameter

Min Max Min Max Min Max

Random Read or Write Cycle Time

RAS Precharge Time

110

130

tRP

CAS Precharge Time

RAS

CAS

ASR

RAH

ASC

CAH

RCD

RAD

RSH

CSH

CRP

ODD

DZO

DZC

RAS Pulse Width

50 10,000

10,000

CAS Pulse Width

13 10,000 15 10,000 18 10,000

Row Address Set up Time

Row Address Hold Time

Column Address Set-up Time

Column Address Hold Time

RAS to CAS Delay Time

RAS to Column Address Delay Time

RAS Hold Time

18 45

13 30

20 45

15 30

20 52

15 35

CAS Hold Time

CAS to RAS Precharge Time

OE to DIN Delay Time

OE Delay Time from DIN

CAS Delay Time from DIN

Transition Time (Rise and Fall)

Rev 0.1 / Apr’01

GM71V18160C

GM71VS18160CL

Read Cycle

GM71V(S)18160 GM71V(S)18160 GM71V(S)18160

C/CL-5 C/CL-6 C/CL-7

Unit Note

Symbol

Parameter

Min Max Min Max Min Max

RAC

CAC

OAC

RCS

RCH

Access Time from RAS

8,9

9,10,17

9,25

Access Time from CAS

Access Time from Address

Access Time from OE

Read Command Setup Time

Read Command Hold Time to CAS

12,22

Read Command Hold Time to RAS

Column Address to RAS Lead Time

RRH

RAL

CAL

CLZ

OHO

OFF

OEZ

CDD

Column Address to CAS Lead Time

CAS to Output in Low-Z

Output Data Hold Time

Output Data Hold Time from OE

Output Buffer Turn-off Time

Output Buffer Turn-off Time to OE

CAS to DIN Delay Time

Write Cycle

GM71V(S)18160 GM71V(S)18160 GM71V(S)18160

C/CL-5 C/CL-6 C/CL-7

Unit Note

Symbol

Parameter

Min Max Min Max Min Max

Write Command Setup Time

Write Command Hold Time

Write Command Pulse Width

Write Command to RAS Lead Time

Write Command to CAS Lead Time

Data-in Setup Time

14,21

WCS

tWCH

RWL

CWL

15,23

tDS

Data-in Hold Time

Rev 0.1 / Apr’01

GM71V18160C

GM71VS18160CL

Read- Modify-Write Cycle

GM71V(S)18160 GM71V(S)18160 GM71V(S)18160

C/CL-5 C/CL-6 C/CL-7

Unit Note

Symbol

Parameter

Min Max Min Max Min Max

RWC

RWD

CWD

AWD

OEH

Read-Modify-Write Cycle Time

RAS to WE Delay Time

131

155

181

CAS to WE Delay Time

Column Address to WE Delay Time

OE Hold Time from WE

Refresh Cycle

GM71V(S)18160 GM71V(S)18160 GM71V(S)18160

C/CL-5 C/CL-6 C/CL-7

Unit Note

Symbol

Parameter

Min Max Min Max Min Max

tCSR

CAS Setup Time

(CAS-before-RAS Refresh Cycle)

CHR

CAS Hold Time

(CAS-before-RAS Refresh Cycle)

RAS Precharge to CAS Hold Time

tRPC

Fast Page Mode Cycle

GM71V(S)18160 GM71V(S)18160 GM71V(S)18160

C/CL-5 C/CL-6 C/CL-7

Unit Note

Symbol

Parameter

Min Max Min Max Min Max

RASP

ACP

RHCP

Fast Page Mode Cycle Time

100,000

Fast Page Mode RAS Pulse Width

Access Time from CAS Precharge

RAS Hold Time from CAS Precharge

9,17,22

Fast Page Mode Read-Modify-Write Cycle

GM71V(S)18160 GM71V(S)18160 GM71V(S)18160

C/CL-5 C/CL-6 C/CL-7

Symbol

Parameter

Unit Note

Min Max Min Max Min Max

PRWC

Fast Page Mode Read-Modify-Write

Cycle Time

tCPW

14,22

WE Delay Time from CAS Precharge

Rev 0.1 / Apr’01

GM71V18160C

GM71VS18160CL

Self Refresh

Mode

Symbol

GM71VS18160

CL-5

GM71VS18160 GM71VS18160

CL-6 CL-7

Parameter

Unit

Note

Min Max Min Max Min Max

RASS

RAS Pulse Width(Self-Refresh)

100

110

-50

100

130

-50

tRPS

RAS Precharge Time(Self-Refresh)

CAS Hold Time(Self-Refresh)

-50

tCHS

Notes:

1. AC measurements assume tT = 5ns.

2. An initial pause of 200us is required after power up followed by a minimum of eight initialization

cycles(any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh).

If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are

required.

3. Operation with the tRCD(max)limit insures that tRAC(max)can be met, tRCD(max)is specified as a

reference point only; if tRCD >= tRAD(max) + tAA(max) - tCAC(max), then access time is controlled

exclusively by tCAC.

4. Operation with the tRAD(max) limit insures that tRAC(max)can be met, tRAD(max)is specified as a

reference point only; if tRAD is greater than the specified tRAD(max)limit, then access time is

controlled exclusively by tAA.

5. Either tODD or tCDD must be satisfied.

6. Either tDZO or tDZC must be satisfied.

7. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Also,

transition times are measured between VIH(min) and VIL(max).

8. Assumes that tRCD <= tRCD(max) and tRAD <= tRAD(max). If tRCD or tRAD is greater than the

maximum recommended value shown in this table, tRAC exceeds the value shown.

9. Measured with a load circuit equivalent to 2 TTL load and 100pF.

10. Assumes that tRCD >= tRCD(max) and tRCD + tCAC(max) >= tRAD + tAA(max).

11. Assumes that tRAD >= tRAD(max) and tRCD + tCAC(max) <= tRAD + tAA(max).

12. Either tRCH or tRRH must be satisfied for a read cycles.

13. tOFF(max) and tOEZ(max) define the time at which the outputs achieve the open circuit

condition and are not referred to output voltage levels.

14. tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in

the data sheet as electrical characteristics only; if tWCS >= tWCS(min), the cycle is an early write

cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle

; if tRWD >= tRWD(min), tCWD >=tCWD(min), and tAWD >= tAWD(min), or tCWD >= tCWD(min),tAWD

>= tAWD(min) and tCPW >= tCPW(min), the cycle is a read-modify-write and the data output will

contain data read from the selected cell; if neither of the above sets of conditions is satisfied,

the condition of data out (at access time)is indeterminate.

Rev 0.1 / Apr’01

GM71V18160C

GM71VS18160CL

15. These parameters are referred to UCAS and LCAS leading edge in early write cycles and to

WE leading edge in delayed write or read-modify-write cycles.

16. tRASP defines RAS pulse width in fast page mode cycles.

17. Access time is determined by the longest among tAA,tCAC,and tACP.

18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying

data to the device. After RAS is reset, if tOEH >= tCWL, the I/O pin will remain open circuit

(high impedance); if tOEH< tCWL, invalid data will be out at each I/O.

19. When both UCAS and LCAS go low at the same time, all 16-bit data are written into the device.

UCAS and LCAS cannot be staggered within the same write/read cycles.

20. All the VCC and VSS pins shall be supplied with the same voltages.

21. tASC, tCAH, tRCS, tWCS,tWCH,tCSR and tRPC are determined by the earlier falling edge of UCAS

or LCAS.

22. tCRP,tCHR, tRCH, tACP and tCPW are determined by the later rising edge of UCAS or LCAS.

23. tCWL, tDH,tDS and tCSH should be satisfied by both UCAS and LCAS.

24. tCP is determined by that time the both UCAS and LCAS are high.

25. When output buffers are enabled once, sustain the low impedance state until valid data is

obtained.

When output buffer is turned on and off within a very short time, generally it causes large

VCC/VSS line noise, which causes to degrade VIH min/VIL max level.

26. Please do not use tRASS timing, 10us <= tRASS <=100us. During this period, the device is in

transition state from normal operation mode to self refresh mode. If tRASS >=100us, then

RAS precharge time should use tRPS instead of tRP.

27. H or L (H: VIH(min) <= VIN <= VIH(max), L: VIL(min) <= VIN <= VIL(max))

Rev 0.1 / Apr’01

GM71V18160C

GM71VS18160CL

Unit: Inches (mm)

Package Dimension

42 SOJ

0.025(0.64)

MIN

0.093(2.38)

MIN

1.058(26.89) MAX

1.072(27.23) MAX

0.128(3.25) MIN

0.148(3.75) MAX

0.050(1.27)

TYP

0.026(0.66) MIN

0.032(0.81) MAX

0.015(0.38) MIN

0.020(0.50) MAX

44(50) TSOP I

0.016(0.40) MIN

0.024(0.60) MAX

_{0 ~ 5}¡ £

0.004(0.12) MIN

0.008(0.21) MAX

0.820(20.82) MIN

0.830(21.08) MAX

0.037(0.95) MIN

0.041(1.05) MAX

0.047(1.20)

MAX

0.012(0.30) MIN

0.017(0.45) MAX

0.031(0.80)

TYP

0.002(0.05) MIN

0.006(0.15) MAX

Rev 0.1 / Apr’01

GM71VS18160CLJ-7 [ETC]

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