GM71VS65403CLJ-5 [ETC]
x4 EDO Page Mode DRAM ; X4 EDO页模式DRAM\n
| 型号： | GM71VS65403CLJ-5 |
| 厂家： | 
ETC |
| 描述： | x4 EDO Page Mode DRAM
|
| 文件： | 总11页 (文件大小：107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GM71V65403C
GM71VS65403CL
16,777,216 WORDS x 4 BIT
CMOS DYNAMIC RAM
Description
Pin Configuration
32 SOJ / TSOP II
The GM71V(S)65403C/CL is the new generation
dynamic RAM organized 16,777,216 words by 4bits.
The GM71V(S)65403C/CL utilizes advanced CMOS
Silicon Gate Process Technology as well as
advanced circuit techniques for wide operating
margins, both internally and to the system user.
System oriented features include single power supply
of 3.3V+/-10% tolerance, direct interfacing
capability with high performance logic families such
as Schottky TTL.
1
2
3
32
31 IO3
VSS
VCC
IO0
IO1
NC
30
IO2
4
5
6
7
29
28
27
26
NC
NC
NC
NC
VSS
VCC
/CAS
The GM71V(S)65403C/CL offers Extended Data
Out(EDO) Mode as a high speed access mode.
25
8
9
/OE
/WE
/RAS
24 NC
23 A11
22 A10
Features
10
A0
* 16,777,216 Words x 4 Bit
* Extended Data Out (EDO) Mode Capability
* Fast Access Time & Cycle Time
11
12
A1
A2
A3
A9
21
A8
20
13
14
15
(Unit: ns)
A4
A5
19
18
A7
A6
tRAC
tAA
tCAC
tRC
tHPC
84
GM71V(S)65403C/CL-5
GM71V(S)65403C/CL-6
20
25
50
60
25
30
13
15
16
17 VSS
VCC
104
(Top View)
*Power dissipation
- Active : 504mW/468mW(MAX)
- Standby : 1.8 mW ( CMOS level : MAX )
0.54mW ( L-Version : MAX)
*EDO page mode capability
*Access time : 50ns/60ns (max)
*Refresh cycles
- RAS only Refresh
4096 cycles/64 ms (GM71V65403C)
4096 cycles/128ms (GM71VS65403CL)(L_Version)
*CBR & Hidden Refresh
4096 cycles/64 ms (GM71V65403C)
4096 cycles/128 ms (GM71VS65403CL)( L-Version )
*4 variations of refresh
-RAS-only refresh
-CAS-before-RAS refresh
-Hidden refresh
-Self refresh (L-Version)
*Single Power Supply of 3.3V+/-10 % with a built-in VBB generator
*Battery Back Up Operation ( L-Version )
Rev 0.1 / Apr’01
GM71V65403C
GM71VS65403CL
Pin Description
Pin
Function
Address Inputs
Pin
WE
Function
A0-A11
A0-A11
RAS
Write Enable
I/O0 - I/O3
VCC
Data Input / Output
Power (+3.3V)
Ground
Refresh Address Inputs
Row Address Strobe
Column Address Strobe
Output Enable
VSS
CAS
OE
NC
No Connection
Ordering Information
Type No.
Access Time
Package
400 Mil
32Pin
Plastic SOJ
GM71V(S)65403C/CLJ-5
GM71V(S)65403C/CLJ-66
50ns
60ns
400 Mil
32Pin
Plastic TSOP II
GM71V(S)65403C/CLT-5
GM71V(S)65403C/CLT-6
50ns
60ns
Absolute Maximum Ratings*
Symbol
Parameter
Storage Temperature (Plastic)
Rating
Unit
TSTG
-55 to 125
C
-0.5 to VCC + 0.5
(MAX ; 4.6V)
Voltage on any Pin Relative to VSS
VT
V
VCC
IOUT
PT
Voltage on VCC Relative to VSS
Short Circuit Output Current
Power Dissipation
-0.5 to 4.6
V
50
mA
W
1.0
*Note : Operation at or above Absolute Maximum Ratings can adversely affect device reliability.
Recommended DC Operating Conditions (TA = 0 ~ 70C)
Symbol
VCC
Parameter
Supply Voltage
Typ
Max
3.6
0
Min
3.0
0
Unit
Notes
3.3
0
V
V
1,2
2
VSS
Supply Voltage
Vcc+0.3
0.8
VIH
VIL
Input High Voltage
Input Low Voltage
2.0
-
V
V
1
1
-0.3
-
TA
Ambient Temperature under Bias
70
C
0
-
Rev 0.1 / Apr’01
GM71V65403C
GM71VS65403CL
DC Electrical Characteristics: (VCC = 3.3V+/-10%, TA = 0 ~ 70C)
Symbol
Parameter
Min Max Unit Note
VOH
Output Level
Output Level Voltage (IOUT = -2mA)
2.4
0
VCC
V
V
VOL
ICC1
Output Level
Output Level Voltage (IOUT = 2mA)
0.4
Operating Current (tRC = tRC min)
50ns
60ns
-
-
140
130
mA
mA
1,2
Standby Current (TTL interface)
Power Supply Standby Current
(RAS, CAS= VIH, DOUT = High-Z)
ICC2
ICC3
-
2
50ns
60ns
-
-
140
130
RAS-Only Refresh Current
( tRC = tRC min)
mA
2
50ns
60ns
-
-
-
110
100
0.5
ICC4
ICC5
Extended Data Out page Mode Current
(RAS = VIL, CAS, Address Cycling: tHPC = tHPC min)
mA 1,3
mA
CMOS interface
(RAS, CAS>=VCC-0.2V, DOUT = High-Z)
Standby Current(L_Version)
-
300
uA
4
140
130
ICC6
CAS-before-RAS Refresh Current
(tRC = tRC min)
50ns
60ns
-
-
mA
Battery Back Up Operating Current(Standby with CBR)
(tRC=31.25us,tRAS=300ns,Dout=High-Z)
uA
ICC7
ICC8
-
500
4, 5
Standby Current (CMOS)
Power Supply Standby Current
RAS = VIH, CAS = VIL , DOUT = Enable
-
5
mA
1
5
ICC9
II(L)
Self Refresh Current
(RAS, CAS <=0.2V,Dout=High-Z)
-
400
5
uA
uA
uA
Input Leakage Current, Any Input
(0V<=VIN<=Vcc)
-5
-5
IO(L)
Output Leakage Current
(DOUT is Disabled, 0V<=VOUT<=Vcc)
5
Note: 1. ICC depends on output load condition when the device is selected. ICC(max) is specified at the
output open condition.
2. Address can be changed once or less while RAS = VIL.
3. Measured with one sequential address change per EDO cycle, tHPC.
4. VIH>=VCC-0.2V, 0V<=VIL<=0.2V
5. L-Version
Rev 0.1 / Apr’01
GM71V65403C
GM71VS65403CL
Capacitance (VCC = 3.3V+/-10%, TA = 25C)
Symbol
CI1
Parameter
Typ
Max
Unit
pF
Note
1
-
Input Capacitance (Address)
Input Capacitance (Clocks)
5
7
7
CI2
-
-
pF
1
CI/O
Output Capacitance (Data-in,Data-Out)
pF
1, 2
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. RAS, CAS = VIH to disable DOUT.
AC Characteristics (VCC = 3.3V+/-10%, TA = 0 ~ 70C, Notes 1, 2,19)
Test Conditions
Input rise and fall times : 2ns
Input level : VIL/VIH = 0.0/3.0V
Input timing reference levels : VIL/VIH = 0.8/2.0V
Output timing reference levels : VOL/VOH = 0.8/2.0V
Output load : 1 TTL gate+CL (100pF)
(Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)
GM71V(S)65403C/CL-5 GM71V(S)65403C/CL-6
Symbol
Parameter
Notes
Unit
Min
84
Min
Max
Max
104
-
-
ns
ns
ns
ns
ns
ns
ns
ns
t
t
RC
RP
Random Read or Write Cycle Time
RAS Precharge Time
30
40
-
-
8
-
10000
10000
-
10
60
10
0
-
CAS Precharge Time
t
CP
50
10000
t
t
t
t
t
t
t
t
t
t
t
t
t
t
RAS
CAS
ASR
RAH
ASC
CAH
RCD
RAD
RSH
CSH
CRP
ODD
DZO
DZC
RAS Pulse Width
10000
8
0
CAS Pulse Width
-
-
Row Address Set-up Time
Row Address Hold Time
Column Address Set-up Time
Column Address Hold Time
RAS to CAS Delay Time
RAS to Column Address Delay Time
RAS Hold Time
10
0
8
-
-
0
-
10
8
-
-
ns
ns
3
4
14
12
15
12
10
13
35
5
37
25
-
45
30
-
ns
ns
ns
ns
40
5
-
-
-
-
CAS Hold Time
CAS to RAS Precharge Time
OE to DIN Delay Time
OE Delay Time from DIN
15
13
0
-
-
-
-
ns
ns
ns
5
0
0
-
6
6
7
-
0
CAS Delay Time from DIN
TransitionTime (Rise and Fall)
Refresh Period
50
t
T
2
-
2
-
50
64
ns
ms
ms
4096
cycles
4096
t
REF
64
-
-
Refresh Period ( L-Version )
128
128
cycles
Rev 0.1 / Apr’01
GM71V65403C
GM71VS65403CL
Read Cycles
GM71V(S)65403C/CL-6
GM71V(S)65403C/CL-5
Symbol
Parameter
Notes
Unit
Min
Max
50
Max
60
Min
-
-
-
-
Access Time from RAS
t
RAC
CAC
ns 8,9
13
15
Access Time from CAS
ns 9,10,17
ns 9,11,17
t
-
-
25
13
-
-
30
15
-
Access Time from Column Address
Access Time from OE
tAA
9
t
OAC
RCS
ns
0
0
0
Read Command Set-up Time
-
ns
t
12
ns
0
-
-
Read Command Hold Time to CAS
Read Command Hold Time to RAS
Column Address to RAS Lead Time
Column Address to CAS Lead Time
Output Buffer Turn-off Delay Time from CAS
Output Buffer Turn-off Delay Time from OE
-
-
t
RCH
RRH
12
ns
0
0
t
30
18
25
15
-
-
-
ns
t
RAL
CAL
OFF
OEZ
CDD
-
ns
t
-
-
13
13
-
-
-
15
15
t
ns 13,21
13
ns
t
13
-
-
5
ns
ns
15
15
CAS to DIN Delay Time
RAS to DIN Delay Time
t
-
13
tRDD
15
-
-
-
WE to DIN Delay Time
13
-
ns
ns
t
WDD
13,21
13
Output Buffer Turn-off Delay Time from RAS
13
13
15
15
t
OFR
-
3
-
tWEZ
Output Buffer Turn-off Delay Time from WE
Output Data Hold Time
ns
ns
ns
3
21
-
-
-
-
-
-
-
-
tOH
Output Data Hold Time from RAS
3
3
21
tOHR
50
3
Read Command Hold Time from RAS
Output data hold time from OE
CAS to Output in Low - Z
60
3
ns
ns
ns
tRCHR
-
-
t
OHO
0
0
tCLZ
Rev 0.1 / Apr’01
GM71V65403C
GM71VS65403CL
Write Cycles
GM71V(S)65403C/CL-5
GM71V(S)65403C/CL-6
Notes
Symbol
Parameter
Unit
Min
Min
0
Max
Max
0
8
-
-
-
-
-
14
ns
ns
ns
ns
ns
ns
ns
t
WCS
WCH
WP
RWL
CWL
Write Command Set-up Time
Write Command Hold Time
10
10
15
10
0
-
-
-
-
-
-
t
8
Write Command Pulse Width
t
13
8
Write Command to RAS Lead Time
t
-
-
t
Write Command to CAS Lead Time
Data-in Set-up Time
15
15
0
t
t
DS
10
8
-
Data-in Hold Time
DH
Read-Modify-Write Cycles
GM71V(S)65403C/CL-5
GM71V(S)65403C/CL-6
Notes
Symbol
Parameter
Unit
Min
116
67
Min
Max
Max
140
-
-
-
-
-
-
Read-Modify-Write Cycle Time
ns
ns
ns
ns
ns
t
RWC
RWD
CWD
AWD
OEH
79
34
49
15
-
-
14
14
t
RAS to WE Delay Time
30
t
CAS to WE Delay Time
42
14
-
-
t
Column Address to WE Delay Time
OE Hold Time from WE
13
t
Refresh Cycles
GM71V(S)65403C/CL-5 GM71V(S)65403C/CL-6
Notes
Symbol
Unit
Parameter
Min
Min
Max
Max
CAS Set-up Time
(CAS-before-RAS Refresh Cycle)
-
ns
-
5
t
CSR
5
CAS Hold Time
(CAS-before-RAS Refresh Cycle)
8
0
-
-
-
-
10
0
ns
ns
t
t
CHR
WRP
WE setup time
(CAS-before-RAS Refresh Cycle)
WE hold time
(CAS-before-RAS Refresh Cycle)
8
5
-
-
10
5
-
-
ns
ns
t
t
WRH
RPC
RAS Precharge to CAS Hold Time
Rev 0.1 / Apr’01
GM71V65403C
GM71VS65403CL
Extended Data Out Mode Cycles
GM71V(S)65403C/CL-5
GM71V(S)65403C/CL-6
Notes
Symbol
Parameter
Unit
Min
20
8
Min
Max
Max
25
-
-
EDO Page Mode Cycle Time
t
HPC
WPE
ns
-
ns
20
10
-
-
-
t
Write pulse width during CAS Precharge
EDO Mode RAS Pulse Width
100000
-
100000
t
t
RASP
ACP
16
ns
ns
ns
ns
ns
ns
Access Time from CAS Precharge
-
35
-
9,17
28
-
-
35
10
t
RHCP
28
8
RAS Hold Time from CAS Precharge
-
-
-
-
t
COL
COP
CAS Hold Time Referred OE
CAS to OE set-up Time
5
-
5
t
35
t
RCHP
28
-
Read Command Hold Time from CAS
Precharge
t
t
DOH
OEP
ns
ns
Output Data Hold Time from CAS Low
OE Precharge Time
3
8
-
-
-
-
3
9,22
10
EDO Page Mode Read-Modify-Write cycle
GM71V(S)65403C/CL-5
GM71V(S)65403C/CL-6
Notes
Symbol
Parameter
Unit
Min
57
Min
68
Max
Max
EDO Read-Modify-Write Cycle Time
-
-
-
-
ns
ns
t
t
HPRWC
CPW
45
54
14
EDO Page Mode Read-Modify-Write Cycle
CAS Precharge to WE Delay Time
Self Refresh Cycles (L_Version)
GM71V(S)65403C/CL-5
GM71V(S)65403C/CL-6
Symbol
Parameter
Notes
Unit
Min
100
90
Min
100
110
-50
Max
Max
us
-
-
-
-
-
-
t
RASS
26
26
RAS Pulse Width(Self-Refresh)
ns
ns
t
t
RPS
CHS
RAS Precharge Time(Self-Refresh)
CAS Hold Time(Self-Refresh)
-50
Rev 0.1 / Apr’01
GM71V65403C
GM71VS65403CL
Notes:
T
AC measurements assume t = 2
ns
.
1.
2.
AC initial pause of 200
is required after power up followed by a minimum of eight
us
initialization cycles ( any combination of cycles containing RAS-only refresh or CAS-before-
RAS refresh)
RCD
RAC
RCD
Operation with the t (max) limit insures that t (max) can be met, t (max) is specified as a
3.
4.
5.
RCD
RCD
reference point only: if t
controlled exclusively by t
is greater than the specified t
(max) limit, then access time is
CAC
.
RAD
RAC
RAD
Operation with the t (max) limit insures that t (max) can be met, t (max) is specified as a
RAD
RAD
reference point only: if t
controlled exclusively by t .
is greater than the specified t
(max) limit, then access time is
AA
OED
CDD
Either t or t must be satisfied.
DZO
DZC
6. Either t or t must be satisfied.
IH
IL
7. V (min) and V (max) are reference levels for measuring timing of input signals. Also,
IH
IL
transition times are measured between V (min) and V (max).
RCD
RCD
t
RAD
RAD
RCD
RAD
8. Assumes that t
(max) and t
t
£
(max). If t
or t is greater than the maximum
£
RAC
recommended value shown in this table, t exceeds the value shown.
9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
³
RCD
RAD
RCD
RCD
CAC
RAD
AA
10. Assumes that t
t
(max) and t + t (max)
t
+ t (max).
³
£
11.
RAD
t
RCD
CAC
RAD
t
AA
Assumes that t
(max) and t +t (max)
+t (max).
³
12.
RCH
RRH
Either t or t must be satisfied for a read cycles.
OFF
t
OEZ(
OFR
WEZ
13.
(max), t max), t (max) and t (max) define the time at which the outputs achieve the
open circuit condition and is not referenced to output voltage levels.
WCS
RWD
CWD, AWD,
CPW
14.
t
, t
data sheet as electrical characteristics only: if t
and the data out pin will remain open circuit (high impedance) throughout the entire cycle: if
, t
t
and t
are not restrictive operating parameters. They are included in the
WCS
WCS
t
(min), the cycle is an early write cycle
³
RWD
t
RWD
CWD
AWD
AWD
CPW CPW
t
³
t
(min), tCWD ³
t
(min), t
t
(min) and t
(min), the cycle is a read-
³
³
modify-write and the data output will contain data read from the selected cell: if neither of the
above sets of conditions is satisfied, the condition of the data out (at access time) is
indeterminate.
DS
DH
15.
t and t are referred to CAS leading edge in early write cycles and to WE leading edge in
delayed write or read-modify-write cycles.
RASP
16.
17.
18.
t
defines RAS pulse width in extended data out mode cycles.
AA, CAC
CPA
and t
Access time is determined by the longest among t
t
.
In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying
data to the device.
19.
When output buffers are enabled once, sustain the low impedance state until valid daa is
obtained. When output buffer is turned on and off within a very short time, generally it causes
CC
SS
IH
IL
large V /V line noise, which causes to degrade V min/V max level.
Rev 0.1 / Apr’01
GM71V65403C
GM71VS65403CL
HPC
t
(min) can be achieved during a series of EDO mode early write cycles or EDO mode read
20.
21.
cycles. If both write and read operation are mixed in a EDO mode, RAS cycle { EDO mode mix
cycle (1),(2) } minimum value of CAS cycle t
specified t (min) value.
EDO page mode mix cycle (1) and (2).
HPC CAS
CP
T
(t + t + 2t ) becomes greater than the
HPC
The value of CAS cycle time of mixed EDO page mode is shown in
Data output turns off and becomes high impedance from later rising edge of RAS and CAS.
Hold time and turn off time are specified by the timing specifications of later rising edge of RAS
and CAS between t and t , and between t and t
OHR
OH
OFR
OFF
.
DOH
OL
OH
t
defines the time at which the output level go cross.
V
=0.8V, V =2.0V of output timing
22.
23.
reference level.
Before and after self refresh mode, execute CBR refresh to all refresh addresses in or within 64
ms
period on the condition a and b below.
a. Enter self refresh mode within 15.6us after either burst refresh or distributed refresh at equal
interval to all refresh addresses are completed.
b. Start burst refresh or distributed refresh at equal interval to all refresh addressed within 15.6us
after exiting from self refresh mode.
In case of entering from RAS-only-refresh, it is necessary to execute CBR refresh before and
after self refresh mode according as note 23.
24.
25.
26.
27.
For L_Version, it is available to apply each 128 ms and 31.2 us instead of 64
note 23.
and 15.6us at
ms
tRASS
RASS
At t
100 us , self refresh mode is activated, and not active at
10us It is undefined
<
>
RASS
t
RPS
within the range of 10 us
100 us. for tRASS 10 us , it is necessary to satisfy t
>
.
<
<
IH
IN
IH
IH
IN
IH
XXX: H or L ( H : V (min)
V
V (max), L: V (min) V (max))
V
<= <= <= <=
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must
IH
IL.
be applied V or V
Rev 0.1 / Apr’01
GM71V65403C
GM71VS65403CL
SOJ 32 pin PKG Dimension
Unit: mm
0.64 MIN
1.16 MAX
2.09 MIN
3.01 MAX
20.95 MIN
21.38 MAX
1.165 MAX
0.33 MIN
0.53 MAX
1.27
0.33 MIN
0.49 MAX
0.10
Rev 0.1 / Apr’01
GM71V65403C
GM71VS65403CL
TSOPII 32 PIN Package Dimension
O
0.40 MIN
Unit: mm
20.95 MIN
21.35 MAX
0 ~ 5
0.60 MAX
NORMAL TYPE
0.145 0.05
0.125 0.04
0.80
1.15 MAX
0.42 0.08
0.40 0.06
1.27
0.08 MIN
0.18 MAX
0.10
Dimension including the plating thickness
Base material dimension
Rev 0.1 / Apr’01
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