GS71116AGU-8 [ETC]
1Mb Asynchronous SRAM; 1MB异步SRAM
| 型号： | GS71116AGU-8 |
| 厂家： | 
ETC |
| 描述： | 1Mb Asynchronous SRAM |
| 文件： | 总16页 (文件大小：385K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GS71116ATP/J/U
7, 8, 10, 12 ns
SOJ, TSOP, FP-BGA
Commercial Temp
Industrial Temp
64K x 16
1Mb Asynchronous SRAM
3.3 V V
DD
Center V and V
DD
SS
Features
• Fast access time: 7, 8, 10, 12 ns
• CMOS low power operation: 145/125/100/85 mA at
minimum cycle time
SOJ 64K x 16-Pin Configuration
• Single 3.3 V power supply
• All inputs and outputs are TTL-compatible
• Byte control
A4
A3
A5
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
A6
2
A2
A7
3
• Fully static operation
• Industrial Temperature Option: –40° to 85°C
• Package line up
A1
OE
4
Top view
A0
UB
5
CE
LB
6
DQ1
DQ2
DQ3
DQ4
VDD
DQ16
DQ15
DQ14
7
J:
400 mil, 44-pin SOJ package
8
TP: 400 mil, 44-pin TSOP Type II package
GP: Pb-Free 400 mil, 3244-pin TSOP Type II package
U: 6 mm x 8 mm Fine Pitch Ball Grid Array package
GU: Pb-Free 6 mm x 8 mm Fine Pitch Ball Grid Array
package
9
10
11
12
13
14
15
DQ13
VSS
VDD
DQ12
DQ11
DQ10
DQ9
NC
44-pin
SOJ
VSS
DQ5
DQ6
DQ7
DQ8
WE
• Pb-Free TSOP-II and FP-BGA packages available
Description
16
17
18
The GS71116A is a high speed CMOS static RAM organized
as 65,536-words by 16-bits. Static design eliminates the need
for external clocks or timing strobes. Operating on a single
3.3 V power supply and all inputs and outputs are TTL-
compatible. The GS71116A is available in a 6 mm x 8 mm
Fine Pitch BGA package, as well as in 400 mil SOJ and 400
mil TSOP Type-II packages.
A15
A14
A13
A12
NC
A8
A9
19
20
21
22
A10
A11
NC
Package J
Pin Descriptions
Symbol
A0–A15
DQ1–DQ16
CE
Description
Address input
Data input/output
Chip enable input
Lower byte enable input
(DQ1 to DQ8)
LB
Upper byte enable input
(DQ9 to DQ16)
UB
WE
OE
Write enable input
Output enable input
+3.3 V power supply
V
DD
V
Ground
SS
NC
No connect
Rev: 1.07 12/2004
1/16
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71116ATP/J/U
Fine Pitch BGA 64K x 16-Bump Configuration
1
2
3
4
5
6
A
B
C
LB
OE
A0
A3
A1
A4
A6
A2
NC
DQ16 UB
CE DQ1
DQ2 DQ3
DQ14 DQ15 A5
V
V
V
DD
D
E
DQ13 NC
DQ12 NC
A7
DQ4
SS
V
NC DQ5
DD
SS
F
G
H
DQ11 DQ10 A8
A9
DQ7 DQ6
WE DQ8
DQ9 NC
NC A12
A10
A13
A11
A14
A15
NC
6 mm x 8 mm, 0.75 mm Bump Pitch (Package U)
Top View
TSOP-II 64K x 16-Pin Configuration
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
A4
A3
A5
2
A6
3
A2
A7
4
A1
OE
Top view
5
A0
UB
6
CE
LB
7
DQ1
DQ2
DQ3
DQ4
VDD
DQ16
DQ15
DQ14
8
9
10
11
12
13
14
15
DQ13
VSS
VDD
DQ12
DQ11
DQ10
DQ9
NC
44-pin
VSS
DQ5
DQ6
DQ7
DQ8
WE
TSOP II
16
17
18
19
20
21
22
A15
A14
A13
A12
NC
A8
A9
A10
A11
NC
Package TP
Rev: 1.07 12/2004
2/16
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71116ATP/J/U
Block Diagram
A0
Row
Decoder
Memory Array
Address
Input
Buffer
Column
Decoder
A15
CE
WE
OE
I/O Buffer
Control
_____
UB
DQ16
DQ1
Truth Table
V
Current
CE
OE
WE
LB
UB
DQ1 to DQ8
DQ9 to DQ16
DD
H
X
X
X
L
X
L
Not Selected
Read
Not Selected
Read
ISB1, ISB2
L
L
L
H
L
L
H
L
Read
High Z
H
L
High Z
Read
L
Write
Write
IDD
X
L
H
L
Write
Not Write, High Z
Write
H
X
H
Not Write, High Z
High Z
L
L
H
X
H
X
X
H
High Z
High Z
High Z
Note:
X: “H” or “L”
Rev: 1.07 12/2004
3/16
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71116ATP/J/U
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Supply Voltage
VDD
–0.5 to +4.6
V
–0.5 to V +0.5
DD
Input Voltage
VIN
V
(≤ 4.6 V max.)
–0.5 to V +0.5
DD
Output Voltage
VOUT
V
(≤ 4.6 V max.)
Allowable power dissipation
Storage temperature
PD
0.7
W
o
TSTG
–55 to 150
C
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended
Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
Recommended Operating Conditions
Parameter
Supply Voltage for -7/-8/-10/-12
Input High Voltage
Symbol
Min
3.0
Typ
3.3
—
Max
Unit
V
3.6
V
V
V
DD
V
+0.3
VIH
VIL
2.0
DD
Input Low Voltage
–0.3
—
0.8
Ambient Temperature,
Commercial Range
o
TAc
TAI
0
—
—
70
85
C
Ambient Temperature,
Industrial Range
o
–40
C
Notes:
1. Input overshoot voltage should be less than V +2 V and not exceed 20 ns.
DD
2. Input undershoot voltage should be greater than –2 V and not exceed 20 ns.
Capacitance
Parameter
Input Capacitance
Output Capacitance
Symbol
CIN
Test Condition
VIN = 0 V
Max
Unit
pF
5
7
COUT
VOUT = 0 V
pF
Notes:
1. Tested at TA = 25°C, f = 1 MHz
2. These parameters are sampled and are not 100% tested.
Rev: 1.07 12/2004
4/16
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71116ATP/J/U
DC I/O Pin Characteristics
Parameter
Symbol
Test Conditions
Min
Max
VIN = 0 to V
DD
Input Leakage Current
IIL
–1 uA
1uA
Output High Z
Output Leakage
Current
ILO
–1 uA
2.4
1uA
VOUT = 0 to V
DD
Output High Voltage
Output Low Voltage
VOH
VOL
IOH = –4 mA
ILO = +4 mA
0.4V
Power Supply Currents
0 to 70°C
8 ns 10 ns 12 ns
–40 to 85°C
Parameter
Symbol
Test Conditions
7 ns
7 ns
8 ns
10 ns 12 ns
CE ≤ VIL
Operating
Supply
Current
All other inputs
≥ VIH or ≤ VIL
Min. cycle time
IOUT = 0 mA
IDD
145 mA 125 mA 100 mA 85 mA 150 mA 130 mA 105 mA 90 mA
CE ≥ VIH
Standby
Current
All other inputs
≥ VIH or ≤VIL
Min. cycle time
ISB1
25 mA 20 mA 20 mA 15 mA 30 mA
25 mA 25 mA 20 mA
CE ≥ VDD – 0.2 V
All other inputs
≥ VDD – 0.2 V or ≤ 0.2 V
Standby
Current
ISB2
2 mA
5 mA
Rev: 1.07 12/2004
5/16
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71116ATP/J/U
AC Test Conditions
Output Load 1
Parameter
Input high level
Input low level
Conditions
VIH = 2.4 V
VI L= 0.4 V
tr = 1V/ns
tf = 1 V/ns
1.4 V
DQ
1
30pF
50Ω
Input rise time
VT = 1.4 V
Input fall time
Input reference level
Output reference level
Output load
Output Load 2
1.4 V
3.3 V
Fig. 1& 2
589Ω
434Ω
DQ
Notes:
1
1. Include scope and jig capacitance.
5pF
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ
Rev: 1.07 12/2004
6/16
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71116ATP/J/U
AC Characteristics
Read Cycle
-7
-8
-10
-12
Parameter
Symbol
Unit
Min
7
Max
—
7
Min
8
Max
—
Min
10
—
—
—
—
3
Max
—
10
10
4
Min
12
—
—
—
—
3
Max
—
12
12
5
Read cycle time
tRC
tAA
tAC
tAB
tOE
tOH
ns
ns
ns
ns
ns
ns
ns
Address access time
—
—
—
—
3
—
—
—
—
3
8
Chip enable access time (CE)
Byte enable access time (UB, LB)
Output enable to output valid (OE)
Output hold from address change
Chip enable to output in low Z (CE)
7
8
3
3.5
3.5
—
3
4
5
—
—
—
—
—
—
*
3
3
—
3
3
tLZ
*
Output enable to output in low Z (OE)
Byte enable to output in low Z (UB, LB)
Chip disable to output in High Z (CE)
Output disable to output in High Z (OE)
Byte disable to output in High Z (UB, LB)
0
—
—
3.5
3
0
—
—
0
—
—
5
0
—
—
6
ns
ns
ns
ns
—
tOLZ
*
0
0
0
0
tBLZ
*
—
—
—
—
—
—
4
—
—
—
—
—
—
tHZ
*
3.5
3.5
4
5
tOHZ
*
3
3.5
3.5
tBHZ
* These parameters are sampled and are not 100% tested.
Read Cycle 1: CE = OE = V , WE = V , UB and, or LB = V
IL
IL
IH
tRC
Address
Data Out
tAA
tOH
Previous Data
Data valid
Rev: 1.07 12/2004
7/16
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71116ATP/J/U
Read Cycle 2: WE = V
IH
tRC
Address
CE
tAA
tAC
tHZ
tLZ
tAB
UB, LB
OE
tBHZ
tOHZ
tBLZ
tOE
tOLZ
Data valid
Data Out
High impedance
Write Cycle
-7
-8
-10
-12
Parameter
Symbol
Unit
Min
7
Max
—
—
—
—
—
—
—
—
—
—
—
Min
8
Max
—
—
—
—
—
—
—
—
—
—
—
Min
10
7
Max
—
—
—
—
—
—
—
—
—
—
—
Min
Max
—
—
—
—
—
—
—
—
—
—
—
Write cycle time
tWC
tAW
tCW
tBW
tDW
tDH
12
8
8
8
6
0
8
0
0
0
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address valid to end of write
Chip enable to end of write
Byte enable to end of write
Data set up time
5
5.5
5.5
5.5
4
5
7
5
7
3.5
0
5
Data hold time
0
0
Write pulse width
tWP
tAS
5
5.5
0
7
Address set up time
0
0
Write recovery time (WE)
Write recovery time (CE)
Output Low Z from end of write
tWR
tWR1
0
0
0
0
0
0
*
3
3
3
tWLZ
*
Write to output in High Z
—
3
—
3.5
—
4
—
5
ns
tWHZ
* These parameters are sampled and are not 100% tested.
Rev: 1.07 12/2004
8/16
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71116ATP/J/U
Write Cycle 1: WE control
tWC
Address
OE
tAW
tCW
tBW
tWR
CE
UB, LB
WE
tAS
tWP
tDW
tDH
Data valid
Data In
tWHZ
tWLZ
High impedance
Data Out
Write Cycle 2: CE control
tWC
Address
OE
tAW
tWR1
tAS
tCW
tBW
CE
UB, LB
WE
tWP
tDW
tDH
Data valid
Data In
Data Out
High impedance
Rev: 1.07 12/2004
9/16
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71116ATP/J/U
Write Cycle 3: UB, LB control
tWC
Address
OE
tAW
tWR1
tAS
tCW
tBW
CE
UB, LB
WE
tWP
tDW
tDH
Data valid
Data In
Data Out
High impedance
Rev: 1.07 12/2004
10/16
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71116ATP/J/U
44-Pin, 400 mil SOJ
Dimension in inch
min nom max
Dimension in mm
Symbol
min
—
nom
—
max
3.759
—
L
D
A
—
—
—
0.148
—
c
44
23
22
A1
0.025
0.635
—
A2
0.105 0.110 0.115 2.667
0.018
0.026 0.028 0.032 0.660
0.008
1.120 1.125 1.130 28.44
2.794
0.457
0.711
0.203
28.58
2.921
—
B
—
—
—
B1
0.813
—
c
—
—
—
1
D
28.70
e
A
E
0.395 0.400 0.405 10.033 10.160 10.287
0.05 1.27
0.435 0.440 0.445 11.049 11.176 11.303
e
—
—
—
—
HE
B
B1
y
GE
0.360 0.370 0.380 9.144
0.082 0.087 0.106 2.083
9.398
2.210
—
9.652
2.70
Q
L
Detail A
y
Q
—
—
—
0.004
—
0.102
o
o
o
o
—
0
7
0
7
Notes:
1. Dimension D& E do not include interlead flash.
2. Dimension B1 does not include dambar protrusion/intrusion.
3. Controlling dimension: inches
Rev: 1.07 12/2004
11/16
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71116ATP/J/U
44 Pin, 400 mil TSOP-II
Dimension in inch
Dimension in mm
Symbol
min
—
nom max
min
—
nom max
D
c
44
23
22
A
—
—
0.047
—
—
1.20
—
A1
0.002
0.05
—
A2
0.037 0.039 0.041 0.95
0.01 0.014 0.018 0.25
1.00
0.35
0.15
1.05
0.45
—
A
B
c
—
0.006
—
—
D
0.721 0.725 0.729 18.31 18.41 18.51
0.396 0.400 0.404 10.06 10.16 10.26
1
E
e
B
e
—
0.031
—
—
0.80
—
HE
0.455 0.463 0.471 11.56 11.76 11.96
L
0.016 0.020 0.024 0.40
0.50
0.80
—
0.60
—
y
L1
—
—
0.031
—
—
—
—
y
Q
0.004
0.10
o
o
o
o
—
—
0
5
0
5
Q
Detail A
Notes:
1. Dimension D& E do not include interlead flash.
2. Dimension B does not include dambar protrusion/intrusion.
3. Controlling dimension: mm
Rev: 1.07 12/2004
12/16
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71116ATP/J/U
6 mm x 8 mm Fine Pitch BGA
8 . 0 0 ± 0 . 1 0
0.10
5 . 2 5
Rev: 1.07 12/2004
13/16
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71116ATP/J/U
Ordering Information
*
Package
Access Time
Temp. Range
Status
Part Number
GS71116ATP-7
GS71116ATP-8
GS71116ATP-10
GS71116ATP-12
GS71116ATP-7I
GS71116ATP-8I
GS71116ATP-10I
GS71116ATP-12I
GS71116AGP-7
GS71116AGP-8
GS71116AGP-10
GS71116AGP-12
GS71116AGP-7I
GS71116AGP-8I
GS71116AGP-10I
GS71116AGP-12I
GS71116AJ-7
400 mil TSOP-II
400 mil TSOP-II
7 ns
8 ns
Commercial
Commercial
Commercial
Commercial
Industrial
400 mil TSOP-II
10 ns
12 ns
7 ns
400 mil TSOP-II
400 mil TSOP-II
400 mil TSOP-II
8 ns
Industrial
400 mil TSOP-II
10 ns
12 ns
7 ns
Industrial
400 mil TSOP-II
Industrial
Pb-free 400 mil TSOP-II
Pb-free 400 mil TSOP-II
Pb-free 400 mil TSOP-II
Pb-free 400 mil TSOP-II
Pb-free 400 mil TSOP-II
Pb-free 400 mil TSOP-II
Pb-free 400 mil TSOP-II
Pb-free 400 mil TSOP-II
400 mil SOJ
Commercial
Commercial
Commercial
Commercial
Industrial
8 ns
10 ns
12 ns
7 ns
8 ns
Industrial
10 ns
12 ns
7 ns
Industrial
Industrial
Commercial
Commercial
Commercial
Commercial
Industrial
GS71116AJ-8
400 mil SOJ
8 ns
GS71116AJ-10
GS71116AJ-12
GS71116AJ-7I
GS71116AJ-8I
GS71116AJ-10I
GS71116AJ-12I
GS71116AU-7
400 mil SOJ
10 ns
12 ns
7 ns
400 mil SOJ
400 mil SOJ
400 mil SOJ
8 ns
Industrial
400 mil SOJ
10 ns
12 ns
7 ns
Industrial
400 mil SOJ
Industrial
6 mm x 8 mm Fine Pitch BGA
6 mm x 8 mm Fine Pitch BGA
6 mm x 8 mm Fine Pitch BGA
6 mm x 8 mm Fine Pitch BGA
6 mm x 8 mm Fine Pitch BGA
6 mm x 8 mm Fine Pitch BGA
Commercial
Commercial
Commercial
Commercial
Industrial
GS71116AU-8
8 ns
GS71116AU-10
GS71116AU-12
GS71116AU-7I
GS71116AU-8I
10 ns
12 ns
7 ns
8 ns
Industrial
Rev: 1.07 12/2004
14/16
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71116ATP/J/U
Ordering Information
*
Package
Access Time
Temp. Range
Status
Part Number
GS71116AU-10I
GS71116AU-12I
GS71116AGU-7
GS71116AGU-8
GS71116AGU-10
GS71116AGU-12
GS71116AGU-7I
GS71116AGU-8I
GS71116AGU-10I
GS71116AGU-12I
6 mm x 8 mm Fine Pitch BGA
6 mm x 8 mm Fine Pitch BGA
10 ns
12 ns
7 ns
Industrial
Industrial
Pb-free 6 mm x 8 mm Fine Pitch BGA
Pb-free 6 mm x 8 mm Fine Pitch BGA
Pb-free 6 mm x 8 mm Fine Pitch BGA
Pb-free 6 mm x 8 mm Fine Pitch BGA
Pb-free 6 mm x 8 mm Fine Pitch BGA
Pb-free 6 mm x 8 mm Fine Pitch BGA
Pb-free 6 mm x 8 mm Fine Pitch BGA
Pb-free 6 mm x 8 mm Fine Pitch BGA
Commercial
Commercial
Commercial
Commercial
Industrial
8 ns
10 ns
12 ns
7 ns
8 ns
Industrial
10 ns
12 ns
Industrial
Industrial
*
Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. For example:
GS71116ATP-10T
Rev: 1.07 12/2004
15/16
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71116ATP/J/U
1Mb Asynchronous Datasheet Revision History
Rev. Code: Old;
New
Types of Changes
Format or Content
Page #/Revisions/Reason
• Creation of new datasheet
71116A_r1
• Added 6 ns speed bin to entire document
71116A_r1; 71116_r1_01
Content
Content
• Updated all power numbers
• Changed 6 mm x 10 mm FPBGA package designator from U to X
71116A_r1_01; 71116A
_r1_02
• Updated Recommended Operating Conditions table on page 4
• Changed FPBGA package from 6 x 10 to 6 x 8 (package U)
• Updated Read Cycle AC Characteristics table
71116A_r1_02; 71116A
_r1_03
Content
• Removed 6 ns speed bin from entire document
• Added 7 ns speed bin to entire document
71116A_r1_03; 71116A
_r1_04
Content
Content
• Updated timings for tBHZ (Read Cycle) for 10 ns and 12 ns
71116A_r1_04;
71116A _r1_05
• Updated format
71116A_r1_05;
71116A_r1_06
Content/Format
Content/Format
• Added Pb-free information for TSOP-II package
• Added Pb-free information for FP-BGA package
71116A_r1_06;
71116A_r1_07
Rev: 1.07 12/2004
16/16
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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