HB28B512IA2 [ETC]
HB28B1700IA2/HB28B1000IA2/HB28B512IA2 Datasheet ; HB28B1700IA2 / HB28B1000IA2 / HB28B512IA2数据表\n
| 型号： | HB28B512IA2 |
| 厂家： | 
ETC |
| 描述： | HB28B1700IA2/HB28B1000IA2/HB28B512IA2 Datasheet
|
| 文件： | 总48页 (文件大小：261K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
To all our customers
Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand
names are mentioned in the document, these names have in fact all been changed to Renesas
Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
Cautions
Keep safety first in your circuit designs!
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and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
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Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.
Notes regarding these materials
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8. Please contact Renesas Technology Corporation for further details on these materials or the products
contained therein.
HB28B1700IA2/HB28B1000IA2
HB28B512IA2
IDE Card
ADE-203-1370B (Z)
Rev. 1.0
Dec. 25, 2002
Description
HB28B1700IA2, HB28B1000IA2, HB28B512IA2 are IDE cards. These cards comply with ATA-5
specification standard, and are suitable for the usage of data storage memory medium for PC or any other
electric equipment. These cards are equipped with Hitachi 512 Mega bit Flash memory. By using these cards
it is possible to operate good performance for a system which has ATA interface.
Features
•
•
Conform to ANSI AT Attachment-5 (ATA-5) specification standard
Card density is 1.7 Giga bytes maximum
This card is equipped with Hitachi 512 Mega bit Flash memory
5 V power supplies are used
•
•
•
•
Data write is 300,000 cycle/block
High reliability based on internal ECC (Error Correcting Code) function
Data reliability is less than 1 error in 1014 bits read
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
Card Line Up*1
Total sectors/ Sectors/
Number of Number of
Type No.
Card density Capacity*4
card*3
1,794,465,792 byte 3,504,816
1,025,482,752 byte 2,002,896
track*2
63
head
cylinder
3,477
1,987
933
HB28B1700IA2 1.7 GB
HB28B1000IA2 1.0 GB
HB28B512IA2 512 MB
16
63
16
512,483,328 byte
1,000,944
63
16
Notes: 1. These data are written in ID.
2. Total tracks = number of head × number of cylinder.
3. Total sectors/card = sectors/track × number of head × number of cylinder.
4. It is the logical address capacity including the area which is used for file system.
Rev.1.0, Dec. 2002, page 2 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
Card Pin Assignment
Pin No.
1
Signal name
Pin No.
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Signal name
Pin No.
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Signal name
GND
D3
D4
D5
D6
D7
-CS0
2
3
4
A2
5
A1
VCC
6
A0
7
D0
8
D1
9
D2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
-IOIS16
GND
GND
*1
-CSEL
*1
-RESET
IORDY
DMARQ
-DMACK
-DASP
-PDIAG
D8
D11
D12
D13
D14
D15
-CS1
*1
INTRQ
VCC
D9
D10
*1
-IORD
-IOWR
GND
Note: 1. Host system should not connect these pin.
Rev.1.0, Dec. 2002, page 3 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
Card Pin Explanation
Host Interface Pin Explanation
Signal name
Direction Pin No.
Description
-RESET
I
58
This signal is active low host reset pin. Once the host asserts
-RESET, the host must keep -RESET asserting for at least 25
µs.
A2 to A0
I
27, 28, 29 Address bus of Host I/F is A2 to A0. A2 is MSB and A0 is
LSB.
D15 to D0
I/O
41, 40, 39 Data bus of Host I/F is D15 to D0. D0 is the LSB of the even
38, 37, 66 byte of the word. D8 is the LSB of the odd byte of the word.
65, 64, 6
5, 4, 3
2, 32, 31
30
-CS0
-CS1
I
I
7, 42
-CS1 is used for selecting the Alternate Status Register and
the Device Control Register. -CS0 is used for the other task
file registers.
-IOWR
45
-IOWR is used for control of write data in I/O task file area.
STOP
(Ultra DMA mode)
This signal must be negated prior to initiation of an Ultra DMA
burst. And this signal must be negated before data is
transferred in an Ultra DMA burst. Assertion during an Ultra
DMA burst flowing indicates the termination of the Ultra DMA
burst.
-IORD
I
44
-IORD is used for control of read data in I/O task file area.
-HDMARDY
(Ultra DMA data-in)
-HDMARDY is a data flow control signal. The host shall assert
this signal to indicate that the host is ready to receive Ultra
DMA data-in bursts. The host may negate this signal to
indicate that the host pauses an Ultra DMA data-in burst.
HSTROBE
(Ultra DMA data-out)
HSTROBE is a data strobe signal. Both the rising and falling
edges of HSTROBE latch the data of D15 to D0 into this card.
Stopping generating HSTROBE edges indicates that the host
pauses an Ultra DMA data-out burst.
-DMACK
-IOCS16
I
61
33
This signal is used for response to asserting DMARQ to initiate
DMA transfers.
O
This output signal is asserted low when the 16-bit wide data
register is addressed and the card is prepared to send or
receive a 16-bit wide data.
INTRQ
O
O
16
60
This signal is the active high Interrupt Request to the host.
DMARQ
This signal is asserted high when the card is ready to DMA
data transfers.
-PDIAG
I/O
63
-PDIAG is the Pass Diagnostic signal in Master/Slave
handshake protocol.
Rev.1.0, Dec. 2002, page 4 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
Signal name
Direction Pin No.
Description
IORDY
O
59
IORDY is used at PIO modes 3 and above. IORDY is negated
to extend the host transfer cycle of any host register access
(Read or Write) when the card is not ready to respond to a
data transfer request.
DSTROBE
(Ultra DMA data-in)
DSTROBE is a data strobe signal. The host latches the data
of D15 to D0 at both the rising and falling edge of DSTROBE.
Stopping generating DSTROBE edges indicates that the card
pauses an Ultra DMA data-in burst.
-DDMARDY
(Ultra DMA data-out)
-DDMARDY is a data flow control signal. The card asserts this
signal to indicate that the card is ready to receive Ultra DMA
data-out bursts. The card negates this signal to indicate that
the card pauses an Ultra DMA data-out burst.
-DASP
-CSEL
I/O
I
62
56
-DASP is the Device Active/Slave Present signal in the
Master/Slave handshake protocol.
This signal is used to configure this card as a Master or a
Slave. When this pin is grounded, this card is configured as a
Master. When the pin is open, this card is configured as a
Slave.
Rev.1.0, Dec. 2002, page 5 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
Card Block Diagram
SDRAM
(Data buffer)
16
16
Flash memory
Flash memory
16
Flash bus A
16
Controller
Flash bus B
Reset IC
X'tal
Rev.1.0, Dec. 2002, page 6 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
Card Function Explanation
Register Construction
•
Task File region
Data register
Error register
Feature register
Sector Count register
Sector Number register
Cylinder Low register
Cylinder High register
Device Head register
Status register
Alternate Status register
Command register
Device Control register
Rev.1.0, Dec. 2002, page 7 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
Host Access Specifications
Read I/O Function
Mode
-CS1
-CS0
A2 to A0
-IORD
-IOWR
D15 to D8
High-Z
D7 to D0
High-Z
Invalid mode
L
L
×
×
×
×
×
×
Standby
mode
H
H
High-Z
High-Z
Data register
access
H
L
L
H
L
0
L
L
L
H
H
H
odd byte
even byte
status out
data out
Alternate
status access
6H
1-7H
×
×
Other task file H
access
Note: ×: L or H
Write I/O Function
Mode
-CS1
-CS0
A2 to A0
-IORD
-IOWR
D15 to D8
don’t care
don’t care
D7 to D0
don’t care
don’t care
Invalid mode
L
L
×
×
×
×
×
×
Standby
mode
H
H
Data register
access
H
L
L
0
H
H
L
L
odd byte
even byte
control in
Device
control
register
access
H
6H
don’t care
Other task file H
access
L
1-7H
H
L
don’t care
data in
Note: ×: L or H
Rev.1.0, Dec. 2002, page 8 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
Task File Register Specification
These registers are used for reading and writing the storage data in this card. The decoded addresses are
shown as follows.
I/O map
-CS1
-CS0
A2
0
A1
0
A0
0
-IORD
-IOWR
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
Data register
Data register
0
0
1
Error register
Feature register
0
1
0
Sector count register
Sector number register
Cylinder low register
Cylinder high register
Device head register
Status register
Sector count register
Sector number register
Cylinder low register
Cylinder high register
Device head register
Command register
Device control register
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
1
1
0
Alt. status register
1. Data register: This register is a 16-bit register that has read/write ability, and it is used for transferring 1
sector data between the card and the host.
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
D15 to D0
2. Error register: This register is a read only register, and it is used for analyzing the error content at the
card accessing. This register is valid when the BSY bit in Status register and Alternate Status register are set
to "0" (Ready).
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ICRC
UNC
0
IDNF
0
ABRT
0
0
bit
Name
Function
7
ICRC (Interface CRC error)
This bit is set to one when an interface CRC error has occurred
during an Ultra DMA data transfer. The content of this bit is not
applicable for Multiword DMA data transfer.
6
UNC (Data ECC error)
This bit is set when Uncorrectable error is occurred at reading the
card.
4
2
IDNF (ID Not Found)
The requested sector cannot be found.
ABRT (ABoRTed command)
This bit is set if the command has been aborted because of the
card status condition. (Not ready, Write fault, Invalid command,
etc.)
Rev.1.0, Dec. 2002, page 9 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
3. Feature register: This register is write only register, and provides information regarding features of the
card which the host wishes to utilize.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Feature byte
4. Sector count register: This register contains the numbers of sectors of data requested to be transferred on
a read or write operation between the host and the card. If the value of this register is zero, a count of 256
sectors is specified. This register's initial value is "01H".
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Sector count byte
5. Sector number register: This register contains the starting sector number which is started by following
sector transfer command.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Sector number byte
6. Cylinder low register: This register contains the low 8-bit of the starting cylinder address which is
started by following sector transfer command.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Cylinder low byte
7. Cylinder high register: This register contains the high 8-bit of the starting cylinder address which is
started by following sector transfer command.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Cylinder high byte
8. Device head register: This register is used for selecting the Device number and Head number for the
following command.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
1
LBA
1
DEV
Head number
Rev.1.0, Dec. 2002, page 10 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
bit
7
Name
1
Function
This bit is set to "1".
6
LBA
LBA is a flag to select either Cylinder / Head / Sector (CHS) or
Logical Block Address (LBA) mode. When LBA=0, CHS mode is
selected. When LBA=1, LBA mode is selected. In LBA mode, the
Logical Block Address is interrupted as follows:
LBA07-LBA00: Sector number Register.
LBA15-LBA08: Cylinder low Register.
LBA23-LBA16: Cylinder high Register.
LBA27-LBA24: Head number in Device head register.
5
4
1
This bit is set to "1".
DEV (DEVice select)
This bit is used for selecting the Master (Device 0) and Slave
(Device 1) in Master/Slave organization.
3 to 0 Head number
This bit is used for selecting the Head number for the following
command. Bit 3 is MSB.
9. Status register: This register is read only register, and it indicates the card status of command and reset
execution. Other bits are invalid when BSY bit is "1". When this register is read, H_INTRQ is negated.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
BSY
DRDY
DWF
DSC
DRQ
CORR
IDX
ERR
bit
Name
BSY (BuSY)
Function
7
This bit is set when the card internal operation is executing. When
this bit is set to "1", other bits in this register are invalid.
6
DRDY (Device ReaDY)
If this bit and DSC bit are set to "1", the card is capable of receiving
the read or write or seek requests.
5
4
3
DWF (Device Write Fault)
DSC (Device Seek Complete)
DRQ (Data ReQuest)
This bit is set if this card indicates the write fault status.
This bit is set when the card seek complete.
This bit is set when the information can be transferred between the
host and Data register. This bit is cleared when the card receives
the other command.
2
CORR (CORRected data)
This bit is set when a correctable data error has been occurred and
the data has been corrected.
1
0
IDX (InDeX)
This bit is always set to "0".
ERR (ERRor)
This bit is set when the previous command has ended in some type
of error. The error information is set in Error register. This bit is
cleared by the next command.
Rev.1.0, Dec. 2002, page 11 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
10. Alternate status register: This register is the same as Status register physically, so the bit assignment
refers to previous item of Status register. But this register is different from Status register that INTRQ is not
negated when data read.
11. Command register: This register is write only register, and it is used for writing the command at
executing the card operation. The command code is written in the command register, after the parameter is
written in the Task File registers during the card is Ready state.
12. Device control register: This register is write only register, and it is used for controlling the card
interrupt request and issuing an ATA soft reset to the card.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
×
×
×
×
×
SRST
nIEN
0
bit
Name
Function
7 to 3 ×
don't care
2
SRST (Software ReSeT)
This bit is set to "1" in order to force the card to perform Task File
Reset operation. Once the host sets SRST bit to "1", SRST bit
must be kept to "1" for at least 5 µs. The card remains in Reset
until this bit is reset to "0". While BSY bit is set to "1" in Status
register as a result of executing either the power-on or hardware
reset protocol, the host must not set SRST bit to "1" in Device
Control register.
1
0
nIEN (Interrupt ENable)
0
This bit is used for enabling INTRQ. When this bit is set to "0",
INTRQ is enabled. When this bit is set to "1", INTRQ is disabled.
This bit is set to "0".
Rev.1.0, Dec. 2002, page 12 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
ATA Command specifications
This table summarizes the ATA command set with the paragraphs. Following shows the support commands
and command codes which are written in command registers.
ATA Command Set
No.
1
Command set
Code
98h,E5h
90h
FR
N
SC
N
N
N
Y
N
Y
N
Y
N
N
Y
Y
N
Y
Y
Y
N
N
Y
SN
N
N
N
Y
CY
N
N
N
Y
DR
Y
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
HD
N
N
N
Y
LBA
N
N
N
Y
CHECK POWER MODE
EXECUTE DEVICE DIAGNOSTIC
FLUSH CACHE
2
N
3
E7h
N
4
FORMAT TRACK
IDENTIFY DEVICE
IDLE
50h
N
5
ECh
N
N
N
N
N
N
N
Y
N
N
N
N
N
N
Y
N
N
N
Y
N
N
N
N
N
N
Y
6
97h,E3h
95h,E1h
91h
N
7
IDLE IMMEDIATE
INITIALIZE DEVICE PARAMETERS
NOP
N
8
N
9
00h
N
N
N
Y
10
11
12
13
14
15
16
17
18
19
READ BUFFER
E4h
N
READ DMA
C8h,C9h
C4h
N
READ MULTIPLE
READ NATIVE MAX ADDRESS
READ LONG SECTOR
READ SECTOR(S)
READ VERIFY SECTOR(S)
RECALIBRATE
N
Y
Y
Y
Y
F8h
N
N
Y
N
Y
N
Y
Y
22h,23h
20h,21h
40h,41h
1Xh
N
Y
N
Y
Y
Y
Y
N
Y
Y
Y
Y
N
N
Y
N
Y
N
Y
Y
SEEK
7Xh
N
Y
SET FEATURES SET TRANSFER
MODE
EFh
03h
N
N
N
N
Rev.1.0, Dec. 2002, page 13 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
No.
Command set
Code
FR
SC
SN
CY
DR
HD
LBA
20
SET FEATURES SET 4BYTES
APPENDED
EFh
BBh
N
N
N
Y
N
N
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
SET MAX ADDRESS
SET MAX SET PASSWORD
SET MAX LOCK
F9h
N
Y
N
N
N
N
Y
N
Y
N
N
N
Y
N
N
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
Y
Y
Y
Y
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
Y
F9h
01h
02h
03h
04h
N
F9h
SET MAX UNLOCK
SET MAX FREEZE LOCK
SET MULTIPLE
F9h
F9h
C6h
SLEEP
99h,E6h
N
SMART ENABLE/DISABLE AUTO SAVE B0h
D2h
D8h
D9h
DAh
N
SMART ENABLE OPERATION
SMART DISABLE OPERATION
SMART RETURN STATUS
STANDBY
B0h
B0h
B0h
96h,E2h
94h,E0h
E8h
STANDBY IMMEDIATE
WRITE BUFFER
N
N
Write DMA
CAh,CBh N
Write Multiple
C5h
N
N
Y
N
N
Write Long Sector
Write Same
32h,33h
E9h
Write Sector(s)
30h,31h
3Ch
Write Verify
Note: FR: Feature Register
SC: Sector Count register
SN: Sector Number register
CY: Cylinder Low/High register
DR: Device bit of Device/Head register
HD: Head No.(3 to 0) of Device/Head register
NH: No. of Heads
LBA: Logical Block Address
Y: Set up
N: Not set up
Rev.1.0, Dec. 2002, page 14 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
1. CHECK POWER MODE (code: E5h): This command checks the power mode.
2. EXECUTE DEVICE DIAGNOSTIC (code: 90h): This command performs the internal diagnostic tests
implemented by the card.
3. FLUSH CACHE (code: E7h): This command is used by the host request the card to flush the write
cache.
4. FORMAT TRACK (code: 50h): This command writes the desired head and cylinder of the selected
drive. But selected sector data is not exchange. This controller excepts a sector buffer of data from the host
to follow the command with same protocol as the WRITE SECTOR command.
5. IDENTIFY DEVICE (code: ECh): The IDENTIFY DEVICE command enables the host to receive
parameter information from the card.
Rev.1.0, Dec. 2002, page 15 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
Identify Device Information
Word bit
Description
Default value F / V
0
General configuration bit-significant information
15
0 = ATA device
0040h
F
14-8
Retired
7
1 = removable media device
6
1 = not removable controller and/or device
5-3
2
Retired
1 = Response incomplete
V
F
1
Retired
0
Reserved
1
Default number of logical cylinders
xxxxh
0000h
xxxxh
0000h
xxxxh
0000h
0000h
xxxxh
0000h
V
V
F
F
F
V
F
F
F
F
2
Specific configuration
3
Default number of logical heads
4-5
6
Retired
Default number of logical sectors per logical track
Reserved for assignment by CompactFlashTM Association
7-8
9
Retired
10-19
20-21
22
Serial Number
Retired
Number of vendor specific bytes available on READ/WRITE LONG 0004h
commands
23-26
27-46
47
Firmware revision (8 ASCII characters)
Model Number (40 ASCII characters)
READ/WRITE Multiple support
80h
xxxxh
xxxxh
F
F
15-8
7-0
8010h
0000h
X
F
Maximum number of sectors that shall be transferred per interrupt
on READ/WRITE MULTIPLE commands
48
Reserved
R
Rev.1.0, Dec. 2002, page 16 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
Word bit
Description
Capabilities
Reserved
Default value F / V
49
15-14
2F00h
R
F
13
1 = Standby timer values as specified in this standard are
supported
0 = Standby timer values shall be managed by the device
12
11
10
9
Reserved
R
F
1 = device supports IORDY operation
1 = device supports the disabling IORDY
1
R
X
F
8
1
7-0
Retired
50
51
Capabilities
15
14
13-1
0
0
4000h
0200h
1
Reserved
Shall be set to one to indicate a device specific Standby timer
value minimum
PIO data transfer mode number
00h = PIO mode-0 is supported
01h = PIO mode-1 is supported
02h = PIO mode-2 is supported
Obsolete
15-8
7-0
F
X
R
52
53
Obsolete
0000h
0007h
Field validity
15-3
Reserved
R
F
2
1
0
1 = Word88 is valid
1 = Words 64 through 70 are valid
1 = Words 54 through 58 are valid
Number of current logical cylinders
Number of current logical heads
Number of current logical sectors per track
Current capacity in sectors
Multiple sector setting
V
V
V
V
V
54
xxxxh
xxxxh
xxxxh
xxxxh
55
56
57-58
59
15-9
8
Reserved
0110h
R
V
1 = Multiple sector setting is valid
7-0
xxh = Current setting for number of sectors that shall be transferred
per interrupt on Read/Write Multiple command
Rev.1.0, Dec. 2002, page 17 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
Word bit
Description
Default value F / V
60-61
62
Total number of user addressable sectors (LBA mode only)
obsolete
xxxxh
0000h
F
F
63
Multiword DMA transfer
15-11
Reserved
0007h
R
V
10
9
1 = Multiword DMA mode-2 is selected
1 = Multiword DMA mode-1 is selected
1 = Multiword DMA mode-0 is selected
Reserved
8
7-3
2
R
F
1 = Multiword DMA mode-2 and below are supported
1 = Multiword DMA mode-1 and below are supported
1 = Multiword DMA mode-0 is supported
Advanced PIO transfer modes supported
Reserved
1
0
64
15-2
0003h
0078h
R
F
1
0
1 = PIO mode-4 is supported
1 = PIO mode-3 is supported
65
Minimum Multiword DMA transfer cycle time per word
F
F
F
F
R
F
F
66
Manufacturer’s recommended Multiword DMA transfer cycle time 0078h
67
Minimum PIO transfer cycle time without flow control
0078h
0078h
0000h
0030h
0000h
68
Minimum PIO transfer cycle time with IORDY flow control
69-79
80
Reserved
Major version number
Reserved
81
Rev.1.0, Dec. 2002, page 18 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
Word bit
Description
Default value F / V
82
15
14
13
12
11
10
9-5
4
Command sets supported
Obsolete
7409h
F
1 = NOP command supported
1 = READ BUFFER command supported
1 = WRITE BUFFER command supported
Obsolete
1 = Host Protect Area feature set supported
Reserved
0
3
1 = Power Management feature set supported
2-1
0
Reserved
1 = SMART feature set supported
83
15
14
Command sets supported
0
4100h
4000h
F
F
1
13-9
Reserved
8
1 = SET MAX security extension supported
7-0
15
Reserved
84
0
14
1
13-0
Reserved
Rev.1.0, Dec. 2002, page 19 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
Word bit
Description
Default value F / V
85
15
14
13
12
11
10
9-5
4
Command set/feature enabled
Obsolete
7408h
V
1 = NOP command enabled
1 = READ BUFFER command enabled
1 = WRITE BUFFER command enabled
Obsolete
1 = Host Protect Area feature set enabled
Reserved
0
3
1 = Power Management feature set enabled
Reserved
2-1
0
1 = SMART feature set enabled
Command set/feature enabled
Reserved
86
15-9
0000h
V
V
8
1 = SET MAX security extension enabled by SET MAX SET
PASSWORD
7-0
Reserved
87
88
Command set/feature default
0
15
4000h
101Fh
14
1
13-0
Reserved
Ultra DMA mode
15-13
12
11
10
9
Reserved
R
V
1 = Ultra DMA mode-4 is selected
1 = Ultra DMA mode-3 is selected
1 = Ultra DMA mode-2 is selected
1 = Ultra DMA mode-1 is selected
1 = Ultra DMA mode-0 is selected
Reserved
8
7-5
4
R
F
1= Ultra DMA mode-4 and below are supported
1= Ultra DMA mode-3 and below are supported
1= Ultra DMA mode-2 and below are supported
1= Ultra DMA mode-1 and below are supported
1= Ultra DMA mode-0 is supported
3
2
1
0
Rev.1.0, Dec. 2002, page 20 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
Word bit
Description
Default value F / V
89-92
93
Reserved
0000h
xxxxh
R
V
Hardware Reset result
15
0
1
14
13
1 = device detected CBLID_N above VIH
0 = device detected CBLID_N below VIL
12
11
Reserved
0 = Device 1 did not assert H_PDIAG_N
1 = Device 1 asserted H_PDIAG_N
10-9
These bit indicate how Device1 determined the device number
00 = Reserved
01 = a jumper was used
10 = H_CSEL_N signal was used
11 = some other method was used or the method is unknown
8
7
6
1
Reserved
0 = Device 0 does not respond when Device 1 is selected
1 = Device 0 responds when Device 1 is selected
5
0 = Device 0 did not detect the assertion of H_DASP_N
1 = Device 0 detected the assertion of H_DASP_N
4
0 = Device 0 did not detect the assertion of H_PDIAG-_N
1 = Device 0 detected the assertion of H_PDIAG_N
3
0 = Device 0 failed diagnostics
1 = Device 0 passed diagnostics
2-1
These bit indicate how Device 0 determined the device number.
00= Reserved
01 = a jumper was used
10 = H_CSEL_N signal was used
11 = some other method was used or the method was unknown
0
1
94-128
Reserved
0000h
R
Rev.1.0, Dec. 2002, page 21 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
Word
bit
Description
Vendor Specific
Reserved
Default value F / V
129-159
160-254
255
0000h
0000h
xxA5h
X
R
Integrity word
Checksum
15-8
7-0
V
F
Signature
Note: 1. F: the content of the word is fixed and does not change.
V: the content of the word is variable and may change depending on the state of the device or the
commands executed by the device.
X: the content of the word is Vendor Specific
R: the content of the word is reserved and set to zero
6. IDLE (code: 97h or E3h): This command allows the host to place the card in the Idle mode and also set
the Standby timer. H_INTRQ_P may be asserted even through the card may not have fully transitioned to
Idle mode. If the Sector Count register is non-zero then the Standby timer shall be enabled. The value in the
Sector Count register shall be used to determine the time programmed into the Standby timer. If the Sector
Count register is zero then the Standby timer is disabled.
Automatic Standby timer periods
Sector Count register contents
Corresponding timeout period
Timeout disabled
(Value × 5)s
0
(00h)
1-240
241-251
252
(01h-F0h)
(F1h-FBh)
(FCh)
((Value − 240) × 30) min
21 min
253
(FDh)
Period between 8 and 12 hrs
Reserved
254
(FEh)
255
(FFh)
21 min 15s
Note: 1. Times are approximate.
7. IDLE IMMEDIATE (code: 95h or E1h): This command causes the card to set BSY, enter the Idle
(Read) mode, clear BSY and generate an interrupt.
8. INITIALIZE DEVICE PARAMETERS (code: 91h): This command enables the host to set the number
of sectors per track and the number of heads per cylinder.
9. NOP (code: 00h): If this command is issued, the card respond with command aborted.
10. READ BUFFER(code: E4h): This command enables the host to read the current contents of the card's
sector buffer.
11. READ DMA (code: C8h,C9h): This command reads from 1 to 256 sectors as specified in the Sector
Count register using the DMA data transfer protocol. A sector count of 0 requests 256 sectors. The transfer
begins at the sector specified in the Sector Number register.
Rev.1.0, Dec. 2002, page 22 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
12. READ MULTIPLE (code: C4h): This command performs similarly to the READ SECTORS command.
Interrupts are not generated on each sector, but on the transfer of a block which contains the number of
sectors defined by a Set Multiple command.
13. READ NATIVE MAX ADDRESS (code: F8h): This command returns the native maximum address.
14. READ LONG SECTOR (code: 22h,23h): This command is provided for compatibility purposes and
nearly performs one sector READ SECTOR command except that it transfers the data and 4 bytes appended
to the sector. These appended 4 bytes are all 0 data.
15. READ SECTOR(S) (code: 20h, or 21h): This command reads from 1 to 256 sectors as specified in the
Sector Count register. A sector count of 0 requests 256 sectors. The transfer begins at the sector specified in
the Sector Number register.
16. READ VERIFY SECTOR(S) (code: 40h or 41h): This command is identical to the READ SECTORS
command, except that DRQ is never set and no data is transferred to the host .
17. RECALIBRATE (code: 1Xh): This command return value is select address mode by the host request.
Return address mode status
Request Addressing
Sector Number Reg.
0x01h
CHS
LBA
0x00h
18. SEEK (code: 7Xh): This command perform a range check.
19. SET FEATURES SET TRANSFER MODE (code: EFh): This command is a host can choose the
transfer mechanism by Set Transfer Mode.
20. SET FEATURES SET 4BYTES APPENDED ( code: EFh): This command allows the host to set the 4
byte data appended to the data transfer on Read Long and Write Long commands.
21. SET MAX ADDRESS (code: F9h): This command allows the host to redefine the maximum address of
the user-accessible address space.
22. SET MAX SET PASSWORD ( code: F9h): This command requests a transfer of a single sector of data
from the host. Password data table defines the content of this sector of information. The password is retained
by the card until the next power cycle. When the card accepts this command the card is in Set Max Unlocked
state.
Rev.1.0, Dec. 2002, page 23 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
SET MAX SET PASSWORD content
Word
0
Content
Reserved
1-16
17-255
Password (32 bytes)
Reserved
23. SET MAX LOCK ( code: F9h): This command sets the card into Set Max Locked state. After this
command is completed any other Set Max commands except Set Max Unlock and Set Max Freeze Lock are
rejected. The card remains in this state until a power cycle or the acceptance of a Set Max Unlock or Set Max
Freeze Lock command.
24. SET MAX UNLOCK (code: F9h): This command requests a transfer of a single sector of data from the
host. Password data Table defines the content of this sector of information. The password supplied in the
sector of data transferred shall be compared with the stored SET MAX password. If the password compare
fails, then the card returns command aborted and decrements the unlock counter. On the acceptance of the Set
Max Lock command, this counter is set to a value of five and shall be decremented for each password
mismatch when Set Max Unlock is issued and the card is locked. When this counter reaches zero, then the Set
Max Unlock command shall return command aborted until a power-cycle. If the password compare matches,
then the card shall make a transition to the Set Max Unlocked state and all SET MAX commands shall be
accepted.
SET MAX SET PASSWORD content
Word
0
Content
Reserved
1-16
17-255
Password (32 bytes)
Reserved
25. SET MAX FREEZE LOCK (code: F9h): The Set Max Freeze Lock command sets the card to Set Max
Frozen state. After command completion any subsequent Set Max commands are rejected.
Commands disabled by Set Max Freeze Lock
Set Max Address
Set Max Set Password
Set Max Lock
Set Max Unlock
Rev.1.0, Dec. 2002, page 24 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
26. SET MULTIPLE MODE (code: C6h): This command enables the card to perform READ and Write
Multiple operations and establishes the block count for these commands.
27. SLEEP ( code: 99h or E6h ): This command causes the card to set BSY, enter the Sleep mode, clear
BSY and generate an interrupt.
28. SMART ENABLE/DISABLE AUTO SAVE (code: B0h): This command enables and disables the
optional attribute auto save feature of the card.
29. SMART ENABLE OPERATIONS (code: B0h): This command enables access to all SMART
capabilities within the card.
30. SMART DISABLE OPERATIONS (code: B0h): This command disables all SMART capabilities
within the card.
31. SMART RETURN STATUS (code: B0h): This command causes the card return the reliability status of
the card to the host.
32. STANDBY (code: 96h or E2h): This command causes the card to set BSY, enter the Sleep mode (which
corresponds to the ATA "Standby" Mode), clear BSY and return the interrupt immediately.
33. STANDBY IMMEDIATE (code: 94h or E0h): This command causes the card to set BSY, enter the
Sleep mode (which corresponds to the ATA "Standby" Mode), clear BSY and return the interrupt
immediately.
34. WRITE BUFFER (code: E8h): This command enables the host to overwrite contents of the card's
sector buffer with any data pattern desired.
35. WRITE DMA (code: CAh or CBh): This command writes from 1 to 256 sectors as specified in the
Sector Count register using the DMA data transfer protocol. A sector count of 0 requests 256 sectors. The
transfer begins at the sector specified in the Sector Number register.
36. WRITE MULTIPLE (code: C5h): This command is similar to the WRITE SECTORS command.
Interrupts are not presented on each sector, but on the transfer of a block which contains the number of
sectors defined by Set Multiple command.
37. WRITE LONG SECTOR (code: 32h or 33h): This command is provided for compatibility purposes
and nearly performs one sector WRITE SECTOR command except that it transfers the data and 4 bytes
appended to the sector. These appended 4 bytes are not written on the flash memories.
38. WRITE SAME (code: E9h): This command nearly performs one sector WRITE SECTOR command
except that only one sector of data transferred. The Sector Counter Register value means one sector data write
counts. (ex: value is 5 to nearly fifth one sector write execute.)
39. WRITE SECTOR(S) (code: 30h or 31h): This command writes from 1 to 256 sectors as specified in
the Sector Count register. A sector count of zero requests 256 sectors. The transfer begins at the sector
specified in the Sector Number register.
Rev.1.0, Dec. 2002, page 25 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
40. WRITE VERIFY (code: 3Ch): This command is similar to the WRITE SECTOR(S) command, except
that each sector is verified before the command is completed.
Rev.1.0, Dec. 2002, page 26 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
Absolute Maximum Ratings
Parameter
Symbol
Vin, Vout
VCC
Value
Unit
V
Notes
All input/output voltages
VCC voltage
–0.3 to VCC + 0.3
–0.3 to +6.7
0 to +70
1
V
Operating temperature range
Storage temperature range
Topr
°C
°C
Tstg
–20 to +75
Notes: 1. Vin, Vout min = –2.0 V for pulse width ≤ 20 ns.
Recommended Operating Conditions
Parameter
Symbol
Ta
Min
0
Typ
25
Max
70
Unit
Operating temperature
VCC voltage
°C
VCC
4.5
5.0
5.5
V
Capacitance (Ta = 25°C, f = 1 MHz)
Parameter
Symbol
Cin
Min
—
Typ
—
Max
25
Unit
pF
Test conditions
Vin = 0 V
Note
Input capacitance
Output capacitance
1
1
Cout
—
—
25
pF
Vout = 0 V
Note: 1. This parameter is sampled and not 100% tested.
Rev.1.0, Dec. 2002, page 27 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
DC Characteristics-1 (Ta = 0 to +70°C, VCC = 5 V ꢀ0%)
Parameter
Symbol
Min
—
Typ
—
Max
1
Unit Test conditions
Note
Output leakage current ILO
µA
µA
V
Vout = high impedance
1
Pull-up current
Output voltage
–IPE
40
100
—
240
0.5
—
Vin = GND
IOL = 4 mA
VOL
VOH
VIL
—
2
2
2.4
—
—
V
IOH = –400 µA
Input voltage
—
0.8
—
V
VIH
2.2
—
V
Note: 1. Except pulled up input pin.
2. Output voltage is measured at static status.
Rev.1.0, Dec. 2002, page 28 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
DC Characteristics-2 (Ta = 0 to +70°C, VCC = 5 V ꢀ0%)
Parameter
Symbol
Min
Typ
Max
Unit Test conditions
Note
Sleep current
ISL
—
5
10
mA
mA
mA
mA
mA
mA
mA
CMOS level (Host control
signal = VCC − 0.2)
Standby current
Idle current
ISB
—
—
—
—
—
10
20
CMOS level (Host control
signal = VCC − 0.2)
IID
100
170
200
550
800
150
220
300
900
1300
CMOS level (Host control
signal = VCC − 0.2)
Sector read current
ICCR (DC)
ICCR (Peak)
ICCW (DC)
CMOS level (Host control
signal = VCC − 0.2)
1
1
2
2
CMOS level (Host control
signal = VCC − 0.2)
Sector write current
CMOS level (Host control
signal = VCC − 0.2)
ICCW (Peak) —
CMOS level (Host control
signal = VCC − 0.2)
Notes 1. Measured during sector read transfer.
2. Measured during sector write transfer.
Rev.1.0, Dec. 2002, page 29 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ꢀ0ꢁ%
Register Access AC Characteristics
Parameter
Symbol
(min) t0
Mode0 Mode1 Mode2 Mode3 Mode4 Unit
Cycle time
600
70
290
—
383
50
290
—
330
30
290
—
180
30
80
70
30
10
20
5
120
25
70
25
20
10
20
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address valid to -IORD/-IOWR setup (min) t1
-IORD/-IOWR pulse width 8bit
-IORD/-IOWR recovery time
-IOWR data setup
(min) t2
(min) t2i
(min) t3
(min) t4
(min) t5
(min) t6
(max) t6Z
(min) t9
(min) tRD
60
30
50
5
45
20
35
5
30
15
20
5
-IOWR data hold
-IORD data setup
-IORD data hold
-IORD data tristate
30
20
0
30
15
0
30
10
0
30
10
0
30
10
0
-IORD/-IOWR to address valid hold
Read data valid to IORDY active
(If IORDY initially low after tA)
IORDY setup time
IORDY pulse width
(min) tA
(max) tB
35
35
35
35
35
ns
ns
1250
1250
1250
1250
1250
PIO Mode Access AC Characteristics
Parameter
Symbol
(min) t0
Mode0 Mode1 Mode2 Mode3 Mode4 Unit
Cycle time
600
70
165
—
383
50
125
—
240
30
100
—
180
30
80
70
30
10
20
5
120
25
70
25
20
10
20
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address valid to -IORD/-IOWR setup (min) t1
-IORD/-IOWR pulse width 16bit
-IORD/-IOWR recovery time
-IOWR data setup
(min) t2
(min) t2i
(min) t3
(min) t4
(min) t5
(min) t6
(max) t6Z
(min) t9
(min) tRD
60
30
50
5
45
20
35
5
30
15
20
5
-IOWR data hold
-IORD data setup
-IORD data hold
-IORD data tristate
30
20
0
30
15
0
30
10
0
30
10
0
30
10
0
-IORD/-IOWR to address valid hold
Read data valid to IORDY active
(If IORDY initially low after tA)
IORDY setup time
IORDY pulse width
(min) tA
(max) tB
35
35
35
35
35
ns
ns
1250
1250
1250
1250
1250
Rev.1.0, Dec. 2002, page 30 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
Register Access/PIO Mode Access Timing
t0
ADDR valid*1
t2
t9
t1
t2i
-IORD/-IOWR
D15 to D0 (Write)
t3
t4
D15 to D0 (Read)
tA
t6
t5
tRD
t6Z
IORDY
tB
Note: 1. ADDR valid consists of signals -CS0, -CS1 and A2 to A0.
Rev.1.0, Dec. 2002, page 31 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
Multiword DMA Mode Access AC Characteristics
Parameter
Symbol
(min) t0
Mode0
480
215
150
5
Mode1
150
80
60
5
Mode2
120
70
50
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Cycle time
-IORD/-IOWR asserted pulse width
-IORD data access
(min) tD
(max) tE
(min) tF
(min) tG
(min) tH
(min) tI
(min) tJ
(min) tKR
(min) tKW
(max) tLR
(max) tLW
(min) tM
(min) tN
(max) tZ
-IORD data hold
-IORD/-IOWR data setup
-IOWR data hold
100
20
30
15
0
20
10
0
-DMACK to -IORD/-IOWR setup
-IORD/-IOWR to -DMACK hold
-IORD negated pulse width
-IOWR negated pulse width
-IORD to DMARQ delay
-IOWR to DMARQ delay
-CS0/-CS1 valid to -IORD/-IOWR
-CS0/-CS1 hold
0
20
5
5
50
50
50
40
40
30
10
25
25
25
35
35
25
10
25
215
120
40
50
15
-DMACK to read data released
20
Rev.1.0, Dec. 2002, page 32 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
Multiword DMA Mode Access Timing
-CS0/-CS1
tM
tN
DMARQ
-DMACK
tLR
tLW
t0
t KR
tKW
tJ
tI
tD
-IORD/-IOWR
D15 to D0 (Read)
D15 to D0 (Write)
tE
tZ
tG
tF
tG
tH
Rev.1.0, Dec. 2002, page 33 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
Ultra DMA Mode Access AC Characteristics
Mode0
Mode1
Mode2
Mode3
Mode4
Parameter
Symbol Min Max Min Max Min Max Min Max Min Max Unit
Cycle time allowing for asymmetry
and clock variations
tCYC
112 — 73
—
54
—
39
—
—
25
57
—
—
ns
ns
Two cycle time allowing for clock
variations
t2CYC
230 — 154 — 115 — 86
Data setup time at recipient
Data hold time at recipient
Data valid setup at sender
Data valid hold at sender
First STROBE time*2
tDS
tDH
tDVS
tDVH
tFS
tLI
15
5
—
—
—
—
10
5
—
—
—
—
7
—
—
—
—
7
—
—
—
—
5
5
6
6
—
—
—
—
ns
ns
ns
ns
5
5
70
6
48
6
30
6
20
6
0
230 0
150 0
200 0
150 0
170 0
150 0
130 0
100 0
120 ns
100 ns
Limited interlock time*3
0
Interlock time with minimum
Unlimited interlock time
tMLI
tUI
20
0
—
—
10
20
—
—
10
20
—
—
10
20
—
—
10
20
—
—
ns
ns
0
0
0
0
Maximum time allowed for output
drivers to release
tAZ
—
—
—
—
—
10 ns
Minimum delay time required for
output
tZAH
20
—
—
20
—
—
20
—
—
20
—
—
20
0
—
—
ns
ns
Drivers to assert or negate
Envelope time
tZAD
tENV
tSR
0
0
0
0
20 70 20 70 20 70 20 55 20 55 ns
STROBE–to–DMARDY time
Ready-to-final STROBE time
—
—
50
75
—
—
30
70
—
—
20
60
—
—
NA*1 —
NA*1 ns
tRFS
tRP
60
—
60 ns
Minimum time to assert STOP or
negate DMARQ
160 — 125 — 100 — 100 — 100 — ns
Setup and hold times for DMACK
tACK
20
50
—
—
20
50
—
—
20
50
—
—
20
50
—
—
20
50
—
—
ns
ns
Time from STROBE edge to negation tSS
of DMARQ or assertion of STOP
Note: 1. NA = Not Available
2. When Ultra DMA data-in burst termination is occured before command completion and then the
host resumes Ultra DMA data-in burst, the Fast STROBE time may be longer than tFS.
3. When Ultra DMA data-out burst termination is occurred before command completion and then the
host resumes Ultra DMA data-out burst, the STOP–to–DMARDY time may be longer than tLI.
4. All timing measurement switching points (low to high and high to low) is taken at 1.5 V.
Rev.1.0, Dec. 2002, page 34 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
Timing of Initializing an Ultra DMA data-in Burst
DMARQ
-DMACK
tUI
tFS
tACK
tENV
tZAD
STOP
tFS
tACK
tENV
tZAD
-HDMARDY
DSTROBE
tAZ
tDVS
tDVH
D15 to D0
tACK
-CS0/-CS1
A2 to A0
tACK
Timing of Sustained Ultra DMA data-in Burst
t2CYC
tCYC
tCYC
t2CYC
STROBE
D15 to D0
tDVH
tDVS
tDVH
tDVS
tDVH
Rev.1.0, Dec. 2002, page 35 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
Timing of Host pausing an Ultra DMA data-in Burst
DMARQ
-DMACK
tRP
STOP
-HDMARDY
-DSTROBE
tSR
1
*
tRFS
D15 to D0
Note: 1. If the tSR timing is not satisfied, the host may receive zero, one, or two more data words
from the card.
Rev.1.0, Dec. 2002, page 36 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
Timing of Card Terminating Ultra DMA data-in Burst
-DMARQ
-DMACK
tMLI
tLI
tLI
tACK
STOP
-HDMARDY
-DSTROBE
tLI
tACK
tSS
tZAH
tDS
tDH
tAZ
D15 to D0
-CS0/-CS1
CRC
tACK
tACK
A2 to A0
Rev.1.0, Dec. 2002, page 37 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
Timing of Host terminating an Ultra DMA data-in Burst
DMARQ
tLI
tMLI
tZAH
-DMACK
STOP
tAZ
tACK
tRP
tACK
-HDMARDY
-DSTROBE
tRFS
tLI
tMLI
tDS
tDH
D15 to D0
-CS0/-CS1
CRC
tACK
tACK
A2 to A0
Rev.1.0, Dec. 2002, page 38 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
Timing of Initializing an Ultra DMA data-out Burst
DMARQ
-DMACK
tUI
tACK
tENV
STOP
DDMARDY
HSTROBE
tLI
tUI
tACK
tDS
tDH
D15 to D0
-CS0/-CS1
A2 to A0
tACK
tACK
Timing of Sustained Ultra DMA data-out Burst
t2CYC
tCYC
tCYC
t2CYC
HSTROBE
D15 to D0
tDH
tDH
tDH
tDS
tDS
Rev.1.0, Dec. 2002, page 39 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
Timing of Card pausing an Ultra DMA data-out Burst
tRP
DMARQ
-DMACK
STOP
tSR
1
*
DDMARDY
tRFS
HSTROBE
D15 to D0
Note: 1. If the tSR timing is not satisfied, the card may receive zero, one,
or two more data words from the host.
Rev.1.0, Dec. 2002, page 40 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
Timing of Host terminating an Ultra DMA data-out Burst
tLI
DMARQ
-DMACK
tMLI
tLI
tACK
tSS
STOP
tLI
DDMARDY
HSTROBE
tACK
tDS
tDH
D15 to D0
-CS0/-CS1
CRC
tACK
tACK
A2 to A0
Rev.1.0, Dec. 2002, page 41 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
Timing of Card Terminating Ultra DMA data-out Burst
DMARQ
-DMACK
tLI
tACK
tMLI
STOP
tRP
-DDMARDY
HSTROBE
tRFS
tLI
tMLI
tACK
tDS
tDH
D15 to D0
-CS0/-CS1
CRC
tACK
tACK
A2 to A0
Rev.1.0, Dec. 2002, page 42 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
Attention for Card Use
•
•
In the reset or power off, all register informations are cleared.
After the card hard reset, soft reset, or power on reset, the host cannot access the card during BSY bit in
Status Register is set.
•
•
The card shall not have a pull-up resistor on D7. The host shall have a ꢀ0 kΩ pull-down resistor and not a
pull-up resistor on D7 to allow a host to recognize the absence of a card at power-up so that a host shall
detect BSY as being cleaned when attempting to read the status register of a card that is not present.
Power off should not be done during internal operation. When power off occurred during internal
operation, there is the possibility that data are lost.
•
•
•
•
•
All card status are cleared automatically when VCC voltage turns below about 2.5V.
Notice that the card insertion/removal should not be executed while host is kept power supply.
Before the card insertion VCC can not be supplied to the card.
We recommend that a circuit to detect the level of power supply voltage be added to the host.
When a read error occurs, rewriting of the sector is recommended. This may avoid the error.
Rev.1.0, Dec. 2002, page 43 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
Physical Outline
As of January, 2002
Surface A
Unit: mm
5.0 (max)
54.0 0.1
85.6 0.2
10.0 min
3.3 0.1
Surface A
34 pin
1 pin
1.27 0.1
68 pin
35 pin
1.27 0.1
41.91
(Reference value)
Surface B
Rev.1.0, Dec. 2002, page 44 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
Caution for Handling Cards
•
•
•
•
•
•
•
Confirm the direction of insertion before inserting the card.
Be careful not to damage the connector.
To avoid damaging the card, never insert it in the wrong direction.
Do not bend the card; do not drop the card or expose the card to mechanical shock of any other kind.
Never modify or disassemble the card.
Do not expose the card to static electricity or electrical noise.
Make regular backups of the data in the card.
Rev.1.0, Dec. 2002, page 45 of 46
HB28B1700IA2, HB28B1000IA2, HB28B512IA2
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual
property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of
bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,
safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions
and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the
guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or
failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the
equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage
due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: (03) 3270-2111 Fax: (03) 3270-5109
URL
http://www.hitachisemiconductor.com/
For further information write to:
Hitachi Semiconductor
(America) Inc.
Hitachi Europe Ltd.
Hitachi Asia Ltd.
Hitachi Asia (Hong Kong) Ltd.
Group III (Electronic Components)
7/F., North Tower
Electronic Components Group
Hitachi Tower
179 East Tasman Drive Whitebrook Park
16 Collyer Quay #20-00
Singapore 049318
Tel : <65>-6538-6533/6538-8577
Fax : <65>-6538-6933/6538-3877
URL : http://semiconductor.hitachi.com.sg
San Jose,CA 95134
Lower Cookham Road
World Finance Centre,
Tel: <1> (408) 433-1990 Maidenhead
Fax: <1>(408) 433-0223 Berkshire SL6 8YA, United Kingdom
Tel: <44> (1628) 585000
Harbour City, Canton Road
Tsim Sha Tsui, Kowloon Hong Kong
Tel : <852>-2735-9218
Fax : <852>-2730-0281
URL : http://semiconductor.hitachi.com.hk
Fax: <44> (1628) 778322
Hitachi Asia Ltd.
(Taipei Branch Office)
4/F, No. 167, Tun Hwa North Road
Hung-Kuo Building
Taipei (105), Taiwan
Hitachi Europe GmbH
Electronic Components Group
Dornacher Str 3
D-85622 Feldkirchen
Postfach 201, D-85619 Feldkirchen
Germany
Tel : <886>-(2)-2718-3666
Fax : <886>-(2)-2718-8180
Telex : 23222 HAS-TP
Tel: <49> (89) 9 9180-0
Fax: <49> (89) 9 29 30 00
URL : http://semiconductor.hitachi.com.tw
Copyright © Hitachi, Ltd., 2002. All rights reserved. Printed in Japan.
Colophon 7.0
Rev.1.0, Dec. 2002, page 46 of 46
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