HC05JB3GRS [ETC]
68HC05JB3 and 68HC705JB3 General Release Specification ; 68HC05JB3和68HC705JB3常规版本规格
| 型号： | HC05JB3GRS |
| 厂家： | 
ETC |
| 描述： | 68HC05JB3 and 68HC705JB3 General Release Specification
|
| 文件： | 总134页 (文件大小：1231K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
HC05JB3GRS/H
REV 1
68HC05JB3
68HC705JB3
SPECIFICATION
(General Release)
November 5, 1998
Semiconductor Products Sector
Motorola reserves the right to make changes without further notice to any products herein
to improve reliability, function or design. Motorola does not assume any liability arising out
of the application or use of any product or circuit described herein; neither does it convey
any license under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or other applications intended to support or sustain life, or for any
other application in which the failure of the Motorola product could create a situation
where personal injury or death may occur. Should Buyer purchase or use Motorola
products for any such unintended or unauthorized application, Buyer shall indemnify and
hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable attorney
fees arising out of, directly or indirectly, any claim of personal injury or death associated
with such unintended or unauthorized use, even if such claim alleges that Motorola was
negligent regarding the design or manufacture of the part.
Motorola, Inc., 1998
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November 5, 1998
GENERAL RELEASE SPECIFICATION
TABLE OF CONTENTS
Section
Page
SECTION 1
GENERAL DESCRIPTION
1.1
1.2
1.3
1.4
FEATURES...................................................................................................... 1-1
MASK OPTIONS.............................................................................................. 1-2
MCU STRUCTURE.......................................................................................... 1-2
FUNCTIONAL PIN DESCRIPTION.................................................................. 1-4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
1.4.8
1.4.9
V
and V ................................................................................................ 1-4
DD SS
OSC1, OSC2 ............................................................................................... 1-4
RESET......................................................................................................... 1-6
IRQ .............................................................................................................. 1-6
3.3V ............................................................................................................. 1-6
D+ and D– ................................................................................................... 1-6
PA0-PA7...................................................................................................... 1-6
PB0-PB2, PB3-PB7 ..................................................................................... 1-7
PC0-PC3...................................................................................................... 1-7
SECTION 2
MEMORY
2.1
2.2
2.3
2.4
I/O AND CONTROL REGISTERS ................................................................... 2-2
RAM ................................................................................................................. 2-2
ROM................................................................................................................. 2-2
I/O REGISTERS SUMMARY ........................................................................... 2-3
SECTION 3
CENTRAL PROCESSING UNIT
3.1
3.2
3.3
3.4
3.5
3.6
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
REGISTERS .................................................................................................... 3-1
ACCUMULATOR (A)........................................................................................ 3-2
INDEX REGISTER (X)..................................................................................... 3-2
STACK POINTER (SP).................................................................................... 3-2
PROGRAM COUNTER (PC) ........................................................................... 3-2
CONDITION CODE REGISTER (CCR)........................................................... 3-3
Half Carry Bit (H-Bit).................................................................................... 3-3
Interrupt Mask (I-Bit).................................................................................... 3-3
Negative Bit (N-Bit)...................................................................................... 3-3
Zero Bit (Z-Bit) ............................................................................................. 3-3
Carry/Borrow Bit (C-Bit)............................................................................... 3-4
SECTION 4
INTERRUPTS
4.1
4.2
4.3
4.4
INTERRUPT VECTORS .................................................................................. 4-1
INTERRUPT PROCESSING............................................................................ 4-2
RESET INTERRUPT SEQUENCE .................................................................. 4-4
SOFTWARE INTERRUPT (SWI)..................................................................... 4-4
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TABLE OF CONTENTS
Section
Page
4.5
HARDWARE INTERRUPTS ............................................................................ 4-4
External Interrupt IRQ.................................................................................. 4-4
IRQ Control/Status Register (ICSR) - $0A................................................... 4-5
Port A External Interrupts (PA0-PA3, by mask option)................................ 4-6
Timer1 Interrupt (TIMER1)........................................................................... 4-7
USB Interrupt (USB) .................................................................................... 4-7
MFT Interrupt (MFT) .................................................................................... 4-7
4.5.1
4.5.2
4.5.3
4.5.4
4.5.5
4.5.6
SECTION 5
RESETS
5.1
5.2
5.3
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
POWER-ON RESET........................................................................................ 5-2
EXTERNAL RESET ......................................................................................... 5-2
INTERNAL RESETS........................................................................................ 5-2
Power-On Reset (POR)............................................................................... 5-2
USB Reset................................................................................................... 5-3
Computer Operating Properly (COP) Reset ................................................ 5-3
Low Voltage Reset (LVR) ............................................................................ 5-3
Illegal Address Reset................................................................................... 5-4
SECTION 6
LOW POWER MODES
6.1
6.2
6.3
STOP MODE.................................................................................................... 6-3
WAIT MODE .................................................................................................... 6-3
DATA-RETENTION MODE.............................................................................. 6-3
SECTION 7
INPUT/OUTPUT PORTS
7.1
PORT-A............................................................................................................ 7-1
Port-A Data Register.................................................................................... 7-2
Port-A Data Direction Register .................................................................... 7-2
Port-A Pull-down/up Register ...................................................................... 7-2
PA0-PA3 Interrupts...................................................................................... 7-2
PA0-PA7 Optical Interface........................................................................... 7-3
PORT-B............................................................................................................ 7-3
Port-B Data Register.................................................................................... 7-3
Port-B Data Direction Register .................................................................... 7-3
Port-B Pull-down/up Register ...................................................................... 7-4
PB1, PB2 Slow Transition Output................................................................ 7-4
PORT-C ........................................................................................................... 7-5
Port-C Data Register ................................................................................... 7-5
Port-C Data Direction Register .................................................................... 7-5
Port-C Pull-down/up Register ...................................................................... 7-6
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.3
7.3.1
7.3.2
7.3.3
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GENERAL RELEASE SPECIFICATION
TABLE OF CONTENTS
Section
Page
SECTION 8
MULTI-FUNCTION TIMER
8.1
8.2
8.3
8.3.1
8.3.2
8.4
OVERVIEW...................................................................................................... 8-2
COMPUTER OPERATING PROPERLY (COP) WATCHDOG ........................ 8-2
MFT REGISTERS............................................................................................ 8-2
Timer Counter Register (TCNT) $09 ........................................................... 8-2
Timer Control/Status Register (TCSR) $08 ................................................. 8-3
OPERATION DURING STOP MODE .............................................................. 8-4
COP CONSIDERATION DURING STOP MODE............................................. 8-4
8.5
SECTION 9
16-BIT TIMER
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
TIMER REGISTERS (TMRH, TMRL)............................................................... 9-2
ALTERNATE COUNTER REGISTERS (ACRH, ACRL) .................................. 9-4
INPUT CAPTURE REGISTERS ...................................................................... 9-5
OUTPUT COMPARE REGISTERS ................................................................. 9-8
TIMER CONTROL REGISTER (TCR) ........................................................... 9-10
TIMER STATUS REGISTER (TSR)............................................................... 9-11
TIMER OPERATION DURING WAIT MODE................................................. 9-12
TIMER OPERATION DURING STOP MODE................................................ 9-12
SECTION 10
UNIVERSAL SERIAL BUS MODULE
10.1 FEATURES.................................................................................................... 10-1
10.2 OVERVIEW.................................................................................................... 10-2
10.2.1 USB Protocol ............................................................................................. 10-3
10.2.2 Reset Signaling.......................................................................................... 10-8
10.2.3 Suspend..................................................................................................... 10-9
10.2.4 Resume After Suspend.............................................................................. 10-9
10.2.5 Low Speed Device................................................................................... 10-10
10.3 CLOCK REQUIREMENTS........................................................................... 10-10
10.4 HARDWARE DESCRIPTION....................................................................... 10-10
10.4.1 Voltage Regulator.................................................................................... 10-11
10.4.2 USB Transceiver...................................................................................... 10-12
10.4.3 Receiver Characteristics.......................................................................... 10-12
10.4.4 USB Control Logic ................................................................................... 10-14
10.5 I/O REGISTER DESCRIPTION ................................................................... 10-18
10.5.1 USB Address Register (UADDR)............................................................. 10-19
10.5.2 USB Interrupt Register 0 (UIR0).............................................................. 10-19
10.5.3 USB Interrupt Register 1 (UIR1).............................................................. 10-21
10.5.4 USB Control Register 0 (UCR0) .............................................................. 10-22
10.5.5 USB Control Register 1 (UCR1) .............................................................. 10-23
10.5.6 USB Control Register 2 (UCR2) .............................................................. 10-24
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TABLE OF CONTENTS
Section
Page
10.5.7 USB Status Register (USR)..................................................................... 10-25
10.5.8 USB Endpoint 0 Data Registers (UE0D0-UE0D7)................................... 10-26
10.5.9 USB Endpoint 1/Endpoint 2 Data Registers (UE1D0-UE1D7) ................ 10-26
10.6 USB INTERRUPTS...................................................................................... 10-26
10.6.1 USB End of Transaction Interrupt............................................................ 10-27
10.6.2 Resume Interrupt..................................................................................... 10-27
10.6.3 End of Packet Interrupt............................................................................ 10-28
SECTION 11
OPTICAL INTERFACE
11.1 OVERVIEW.................................................................................................... 11-1
11.2 OPTICAL INTERFACE ENABLE REGISTER................................................ 11-3
SECTION 12
INSTRUCTION SET
12.1 ADDRESSING MODES ................................................................................. 12-1
12.1.1 Inherent...................................................................................................... 12-1
12.1.2 Immediate.................................................................................................. 12-1
12.1.3 Direct ......................................................................................................... 12-2
12.1.4 Extended.................................................................................................... 12-2
12.1.5 Indexed, No Offset..................................................................................... 12-2
12.1.6 Indexed, 8-Bit Offset.................................................................................. 12-2
12.1.7 Indexed, 16-Bit Offset................................................................................ 12-3
12.1.8 Relative...................................................................................................... 12-3
12.1.9 Instruction Types ....................................................................................... 12-3
12.1.10 Register/Memory Instructions.................................................................... 12-4
12.1.11 Read-Modify-Write Instructions ................................................................. 12-5
12.1.12 Jump/Branch Instructions .......................................................................... 12-5
12.1.13 Bit Manipulation Instructions...................................................................... 12-7
12.1.14 Control Instructions.................................................................................... 12-7
12.1.15 Instruction Set Summary ........................................................................... 12-8
SECTION 13
ELECTRICAL SPECIFICATIONS
13.1 MAXIMUM RATINGS..................................................................................... 13-1
13.2 THERMAL CHARACTERISTICS................................................................... 13-1
13.3 DC ELECTRICAL CHARACTERISTICS........................................................ 13-2
13.4 USB DC ELECTRICAL CHARACTERISTICS ............................................... 13-3
13.5 USB LOW SPEED SOURCE ELECTRICAL CHARACTERISTICS............... 13-4
13.6 CONTROL TIMING........................................................................................ 13-5
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GENERAL RELEASE SPECIFICATION
TABLE OF CONTENTS
Section
Page
SECTION 14
MECHANICAL SPECIFICATIONS
14.1 20-PIN PDIP (CASE 738) .............................................................................. 14-1
14.2 28-PIN PDIP (CASE 710) .............................................................................. 14-1
14.3 20-PIN SOIC (CASE 751D) ........................................................................... 14-2
14.4 28-PIN SOIC (CASE 751F)............................................................................ 14-2
APPENDIX A
MC68HC705JB3
A.1 INTRODUCTION..............................................................................................A-1
A.2 MEMORY.........................................................................................................A-1
A.3 MASK OPTION REGISTER (MOR).................................................................A-1
A.4 BOOTSTRAP MODE .......................................................................................A-3
A.5 EPROM PROGRAMMING...............................................................................A-3
A.5.1
A.5.2
EPROM Program Control Register (PCR)...................................................A-3
Programming Sequence..............................................................................A-4
A.6 EPROM PROGRAMMING SPECIFICATIONS................................................A-5
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TABLE OF CONTENTS
Section
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LIST OF FIGURES
Title
Figure
Page
1-1
1-2
1-3
2-1
2-2
2-3
2-4
2-5
2-6
3-1
4-1
4-2
4-3
4-4
5-1
5-2
6-1
7-1
8-1
8-2
8-3
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
MC68HC05JB3 Block Diagram........................................................................ 1-3
MC68HC05JB3 Pin Assignments .................................................................... 1-4
Oscillator Connections ..................................................................................... 1-5
MC68HC05JB3 Memory Map .......................................................................... 2-1
MC68HC05JB3 I/O Registers $0000-$000F.................................................... 2-3
MC68HC05JB3 I/O Registers $0010-$001F.................................................... 2-4
MC68HC05JB3 I/O Registers $0020-$002F.................................................... 2-5
MC68HC05JB3 I/O Registers $0030-$003F.................................................... 2-6
COP Register (COPR) ..................................................................................... 2-6
MC68HC05 Programming Model..................................................................... 3-1
Interrupt Stacking Order................................................................................... 4-2
Interrupt Flowchart ........................................................................................... 4-3
External Interrupt (IRQ) Logic .......................................................................... 4-5
IRQ Control and Status Register (ICSR).......................................................... 4-5
Reset Sources.................................................................................................. 5-1
COP Watchdog Register (COPR).................................................................... 5-3
STOP and WAIT Flowchart.............................................................................. 6-2
PB1 Slow Falling-edge Output......................................................................... 7-5
Multi-Function Timer Block Diagram................................................................ 8-1
Timer Counter Register.................................................................................... 8-3
Timer Control/Status Register (TCSR)............................................................. 8-3
Programmable Timer Block Diagram............................................................... 9-1
Programmable Timer Counter Block Diagram ................................................. 9-2
Programmable Timer Counter Registers (TMRH, TMRL)................................ 9-3
Alternate Counter Block Diagram..................................................................... 9-4
Alternate Counter Registers (ACRH, ACRL).................................................... 9-4
Timer Input Capture Block Diagram................................................................. 9-5
TCAP Input Signal Conditioning....................................................................... 9-6
TCAP Input Comparator Output....................................................................... 9-7
Input Capture Registers (ICRH, ICRL)............................................................. 9-7
9-10 Timer Output Compare Block Diagram............................................................ 9-9
9-11 Output Compare Registers (OCRH, OCRL) .................................................... 9-9
9-12 Timer Control Register (TCR) ........................................................................ 9-10
9-13 Timer Status Registers (TSR)........................................................................ 9-11
10-1 USB Block Diagram ....................................................................................... 10-2
10-2 Supported Transaction Types per Endpoint................................................... 10-3
10-3 Supported USB Packet Types ....................................................................... 10-4
10-4 Sync Pattern................................................................................................... 10-4
10-5 SOP, Sync Signaling and Voltage Levels...................................................... 10-5
10-6 CRC Block Diagram for Address and Endpoint Fields................................... 10-6
10-7 CRC Block Diagram for Data Packets ........................................................... 10-7
10-8 EOP Transaction Voltage Levels ................................................................... 10-8
10-9 EOP Width Timing.......................................................................................... 10-8
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LIST OF FIGURES
Title
Figure
Page
10-10 External Low Speed Device Configuration................................................... 10-10
10-11 Regulator Electrical Connections................................................................. 10-11
10-12 Low Speed Driver Signal Waveforms .......................................................... 10-12
10-13 Differential Input Sensitivity Over Entire Common Mode Range ................. 10-13
10-14 Data Jitter..................................................................................................... 10-14
10-15 Data Signal Rise and Fall Time.................................................................... 10-14
10-16 NRZI Data Encoding .................................................................................... 10-15
10-17 Flow Diagram for NRZI ................................................................................ 10-15
10-18 Bit Stuffing.................................................................................................... 10-16
10-19 Flow Diagram for Bit Stuffing ....................................................................... 10-17
10-20 USB Address Register (UADDR)................................................................. 10-19
10-21 USB Interrupt Register 0 (UIR0) .................................................................. 10-19
10-22 USB Interrupt Register 1(UIR1) ................................................................... 10-21
10-23 USB Control Register 0 (UCR0)................................................................... 10-22
10-24 USB Control Register 1 (UCR1)................................................................... 10-23
10-25 USB Control Register 2 (UCR2)................................................................... 10-24
10-26 USB Status Register (USR) ......................................................................... 10-25
10-27 USB Endpoint 0 Data Register (UE0D0-UE0D7)......................................... 10-26
10-28 USB Endpoint 1/Endpoint2 Data Registers (UE1D0-UE1D7)...................... 10-26
10-29 OUT Token Data Flow for Receive Endpoint 0............................................ 10-29
10-30 SETUP Token Data Flow for Receive Endpoint 0........................................ 10-30
10-31 IN Token Data Flow for Transmit Endpoint 0............................................... 10-31
10-32 IN Token Data Flow for Transmit Endpoint 1/2............................................ 10-32
11-1 A pair of Optical Coupler Interface................................................................. 11-2
11-2 Optical Interface Comparator......................................................................... 11-2
11-3 Optical Interface Enable Register (TCSR) ..................................................... 11-3
14-1 20-Pin PDIP Mechanical Dimensions ............................................................ 14-1
14-2 28-Pin PDIP Mechanical Dimensions ............................................................ 14-1
14-3 20-Pin SOIC Mechanical Dimensions............................................................ 14-2
14-4 28-Pin SOIC Mechanical Dimensions............................................................ 14-2
A-1 MC68HC705JB3 Memory Map ........................................................................A-2
A-2 EPROM Programming Sequence ....................................................................A-5
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LIST OF TABLES
Title
Table
Page
4-1
7-1
8-1
Reset/Interrupt Vector Addresses.................................................................... 4-1
Summary of Port Pin Functions ....................................................................... 7-1
RTI and COP Rates at f =3.0MHz................................................................ 8-3
OP
10-1 Supported Packet Identifiers.......................................................................... 10-5
10-2 Register Summary ....................................................................................... 10-18
11-1 Port-A Optical Interface Pairs......................................................................... 11-1
11-2 Optical Interface Reference Voltage Selection .............................................. 11-3
12-1 Register/Memory Instructions ........................................................................ 12-4
12-2 Read-Modify-Write Instructions ..................................................................... 12-5
12-3 Jump and Branch Instructions........................................................................ 12-6
12-4 Bit Manipulation Instructions .......................................................................... 12-7
12-5 Control Instructions ........................................................................................ 12-7
12-6 Instruction Set Summary ............................................................................... 12-8
12-7 Opcode Map................................................................................................. 12-14
13-1 DC Electrical Characteristics.......................................................................... 13-2
13-2 USB DC Electrical Characteristics ................................................................. 13-3
13-3 USB Low Speed Source Electrical Characteristics........................................ 13-4
13-4 Control Timing................................................................................................ 13-5
A-1 EPROM Programming Electrical Characteristics.............................................A-5
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LIST OF TABLES
Title
Table
Page
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SECTION 1
GENERAL DESCRIPTION
The MC68HC05JB3 is a member of the low-cost, high-performance M68HC05
Family of 8-bit microcontroller units (MCUs). The M68HC05 Family is based on
the customer-specified integrated circuit design strategy. All MCUs in the family
use the popular M68HC05 central processing unit (CPU) and are available with a
variety of subsystems, memory sizes and types, and package types.
The MC68HC05JB3 is specifically designed to be used in applications where a
low speed (1.5Mbps) Universal Serial Bus (USB) interface is required.
1.1
FEATURES
•
•
•
•
•
Industry standard M68HC05 CPU core
Memory-mapped input/output (I/O) registers
2560 Bytes of user ROM
144 Bytes of user RAM (includes 64 byte stack)
Fully compliant Low Speed USB with 3 Endpoints:
– 1 Control Endpoint (2×8-byte buffer)
– 2 Interrupt Endpoints (1×8-byte buffer shared)
3.3V dc output for USB pull-up resistors
•
•
19 Bidirectional I/O pins with the following features:
– 17 I/Os have software programmable pull-down capability
– 2 open-drain I/Os have software programmable pull-up, 25mA current
sink capability
– 4 I/Os with external interrupt capability
– 8 I/Os (in 4 pairs) with programmable optical interface
Multi-Function Timer (MFT)
•
•
•
•
•
16-bit Timer with 1 input capture and 1 output compare
Low Voltage Reset (LVR)
Computer Operating Properly (COP) Watchdog Reset
Illegal Address Reset
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GENERAL DESCRIPTION
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•
•
Power-Saving STOP and WAIT Modes
Available in 20-pin PDIP, 20-pin SOIC, 28-pin PDIP, and 28-pin SOIC
packages
1.2
MASK OPTIONS
The following mask options are available:
•
•
•
•
•
•
External interrupt pins (IRQ, PA0 to PA3):
[edge-triggered or edge-and-level-triggered]
Port A, port B, and port C pull-down/pull-up resistors:
[connected or disconnected]
PA0-PA3 external interrupt capability:
[enabled or disabled]
OSC, crystal/ceramic resonator startup delay:
[4064 or 224 internal bus cycles]
Low Voltage Reset (LVR):
[enabled or disabled]
COP function of MFT:
[enabled or disabled]
1.3
MCU STRUCTURE
Figure 1-1 shows the structure of MC68HC05JB3 MCU.
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VDD
PA0①
PA1①
PA2①
PA3①
PA4②
PA5②
PA6②
PA7②
PB0➂
PB1 ➃
PB2 ➃
LVR
VREF
POWER
SUPPLY
CPU CONTROL
68HC05 CPU
ALU
VSS
3.3V
RESET
and
IRQ
RESET
IRQ
ACCUM
CPU REGISTERS
INDEX REG.
OSC1
OSC2
Core
TImer
OSC
÷2
0 0 0 0 0 0 0 0 1 1
STK PNTR
TCAP➂
PROGRAM COUNTER
16-bit Timer
†
OCMP➄
PB4➄
PB5➄
PB6➄
PB7➄
COND CODE REG.
1 1 1 H I N Z C
D+
D–
Low Speed
USB
†
PC0➄
PC1➄
PC2➄
PC3➄
144 Bytes RAM
2560 Bytes EPROM
①: External edge interrupt capability,
with Schmitt trigger input and optical interface
②: 8mA current sink capability and optical interface
➂: PB0 is shared with TCAP
➃: 25mA current sink, open-drained
with internal pull-up, slow transition O/P
➄: Pins available in 28-pin package only
†
➄ : PC0 shared with OCMP
Figure 1-1. MC68HC05JB3 Block Diagram
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GENERAL DESCRIPTION
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1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RESET
PA0
VDD
RESET
PA0
VDD
OSC1
OSC2
VSS
2
OSC1
OSC2
VSS
3.3V
D+
3
PA1
PA1
4
PA2
PA2
5
PA3
PC2
PC0/OCMP
PC1
6
PA4
PA3
7
PB0/TCAP
PB1
PC3
D–
3.3V
D+
8
PA4
PA7
PA6
PA5
9
PB2
PB5
D–
10
11
12
13
14
IRQ
PB4
PB7
PB0/TCAP
PB1
PB6
20-pin package
PA7
PA6
PB2
PA5
IRQ
28-pin package
Figure 1-2. MC68HC05JB3 Pin Assignments
FUNCTIONAL PIN DESCRIPTION
1.4
The following paragraphs give a description of the general function of each pin
assigned in Figure 1-2.
1.4.1 V and V
DD
SS
Power is supplied to the MCU through V
and V . V
is the positive supply,
DD
SS DD
and V is ground. The MCU operates from a single power supply.
SS
Very fast signal transitions occur on the MCU pins. The short rise and fall times
place very high short-duration current demands on the power supply. To prevent
noise problems, special care should be taken to provide good power supply
bypassing at the MCU by using bypass capacitors with good high-frequency char-
acteristics that are positioned as close to the MCU as possible. Bypassing
requirements vary, depending on how heavily the MCU pins are loaded.
1.4.2 OSC1, OSC2
The OSC1 and OSC2 pins are the connections for the on-chip oscillator. The
OSC1 and OSC2 pins can accept the following sets of components:
1. A crystal as shown in Figure 1-3(a)
2. A ceramic resonator as shown in Figure 1-3(a)
3. An external clock signal as shown in Figure 1-3(b)
MOTOROLA
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GENERAL DESCRIPTION
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The frequency, f
, of the oscillator or external clock source is divided by two to
OSC
produce the internal operating frequency, f . If the internal operating frequency is
OP
3MHz, then the external oscillator frequency will be 6MHz. For LS USB 1.5MHz
frequency clock can be derived from a divided by 4 circuit. The type of oscillator is
selected by a mask option. An internal 2MΩ resistor may be selected between
OSC1 and OSC2 by a mask option (crystal/ceramic resonator mode only).
Crystal Oscillator
The circuit in Figure 1-3(a) shows a typical oscillator circuit for an AT-cut, parallel
resonant crystal. The crystal manufacturer’s recommendations should be fol-
lowed, as the crystal parameters determine the external component values
required to provide maximum stability and reliable start-up. The load capacitance
values used in the oscillator circuit design should include all stray capacitances.
The crystal and components should be mounted as close as possible to the pins
for start-up stabilization and to minimize output distortion. An internal start-up
resistor of approximately 2MΩ is provided between OSC1 and OSC2 for the crys-
tal type oscillator as a mask option.
MCU
MCU
OSC1
OSC2
OSC1
OSC2
2MΩ
Unconnected
External Clock
(b) External Clock Source Connection
(a) Crystal or Ceramic Resonator Connections
Figure 1-3. Oscillator Connections
Ceramic Resonator Oscillator
In cost-sensitive applications, a ceramic resonator can be used in place of the
crystal. The circuit in Figure 1-3(a) can be used for a ceramic resonator. The res-
onator manufacturer’s recommendations should be followed, as the resonator
parameters determine the external component values required for maximum sta-
bility and reliable starting. The load capacitance values used in the oscillator cir-
cuit design should include all stray capacitances. The ceramic resonator and
components should be mounted as close as possible to the pins for start-up stabi-
lization and to minimize output distortion. An internal start-up resistor of approxi-
mately 2 MΩ is provided between OSC1 and OSC2 for the ceramic resonator type
oscillator as a mask option.
MC68HC05JB3
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GENERAL DESCRIPTION
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External Clock
An external clock from another CMOS-compatible device can be connected to the
OSC1 input, with the OSC2 input not connected, as shown in Figure 1-3(b).This
configuration is possible ONLY when the crystal/ceramic resonator mask option is
selected.
1.4.3 RESET
This is an I/O pin. This pin can be used as an input to reset the MCU to a known
start-up state by pulling it to the low state. The RESET pin contains a steering
diode to discharge any voltage on the pin to V , when the power is removed. An
DD
internal pull-up is also connected between this pin and V . The RESET pin con-
DD
tains an internal Schmitt trigger to improve its noise immunity as an input. This pin
is an output pin if LVR triggers an internal reset.
1.4.4 IRQ
This input pin drives the asynchronous IRQ interrupt function of the CPU. The IRQ
interrupt function has a mask option to provide either only negative edge-sensitive
triggering or both negative edge-sensitive and low level-sensitive triggering. If the
option is selected to include level-sensitive triggering, the IRQ input requires an
external resistor to V for "wired-OR" operation, if desired. The IRQ pin contains
DD
an internal Schmitt trigger as part of its input to improve noise immunity.
NOTE
Each of the PA0 to PA3 I/O pins may be connected as an OR function with the IRQ
interrupt function by a mask option. This capability allows keyboard scan
applications where the transitions or levels on the I/O pins will behave the same
as the IRQ pin. The edge or level sensitivity selected by a separate mask option
for the IRQ pin also applies to the I/O pins OR’ed to create the IRQ signal.
1.4.5 3.3V
This is an output reference voltage nominally set at 3.3V dc.
1.4.6 D+ and D–
These two lines carry the USB differential data. For low speed device such as
MC68HC05JB3, a 1.5 kΩ resistor is required to be connected across D– and 3.3V
for proper signal termination.
1.4.7 PA0-PA7
These eight I/O lines comprise Port A. PA0 to PA7 are push-pull pins with pull-
down devices. The state of any pin is software programmable and all Port A lines
are configured as inputs during power-on or reset.
MOTOROLA
1-6
GENERAL DESCRIPTION
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PA0 to PA3 has external interrupt function (mask option) with schmitt trigger input
circuit, and PA4 to PA7 has 8mA current sink capability.
Port A can also be configured as the optical interface.
1.4.8 PB0-PB2, PB3-PB7
These seven I/O lines comprise Port B. The state of any pin is software program-
mable and is configured as an input during power-on or reset.
PB1 and PB2 are open-drain I/O lines with pull-up devices. PB0 (shared with
TCAP) is a push-pull I/O line with pull-down device.
PB1 and PB2 are also slow transition outputs, each has 25mA current sink capa-
bility at V =0.5V.
OL
PB4-PB7 I/O lines are push-pull pins with pull-down devices, and are only avail-
able in the 28-pin package.
1.4.9 PC0-PC3
These four I/O lines comprise Port C. The state of any pin is software programma-
ble and all Port C lines are configured as inputs during power-on or reset.
PC0 to PC3 are push-pull pins with pull-down devices. PC0 is also shared with the
OCMP pin from the output compare function of the 16-bit timer.
Port C is only available in the 28-pin package.
MC68HC05JB3
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MOTOROLA
1-8
GENERAL DESCRIPTION
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SECTION 2
MEMORY
The MC68HC05JB3 has 8k-bytes of addressable memory, with 64 bytes of I/O,
144 bytes of user RAM, and 2560 bytes of user ROM, as shown in Figure 2-1.
$0000
$0000
I/O Registers
64 Bytes
$003F
$0040
I/O Registers
64 Bytes
Unused
48 Bytes
$006F
$0070
$003F
$1FF0
User RAM
144 Bytes
Reserved
$00C0
Reserved
$1FF1
$1FF2
$1FF3
$1FF4
$1FF5
$1FF6
$1FF7
$1FF8
$1FF9
$1FFA
$1FFB
$1FFC
$1FFD
$1FFE
$1FFF
64 Byte Stack
$00FF
$0100
Reserved
Reserved
MFT Vector (High Byte)
MFT Vector (Low Byte)
Timer1 Vector (High Byte)
Timer1 Vector (Low Byte)
USB Vector (High Byte)
USB Vector (Low Byte)
IRQ Vector (High Byte)
IRQ Vector (Low Byte)
SWI Vector (High Byte)
SWI Vector (Low Byte)
Reset Vector (High Byte)
Reset Vector (Low Byte)
Unused
4864 Bytes
$13FF
$1400
User ROM
2560 Bytes
$1DFF
$1E00
Self-Check ROM
496 Bytes
$1FEF
$1FF0
User Vectors
16 Bytes
$1FFF
Figure 2-1. MC68HC05JB3 Memory Map
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2.1
2.2
2.3
I/O AND CONTROL REGISTERS
The I/O and Control Registers reside in locations $0000 to $003F. The bit assign-
ments for each register are shown in Figure 2-2, Figure 2-3, Figure 2-4, and
Figure 2-5. Reading from unused bits will return unknown states, and writing to
unused bits will be ignored.
RAM
The user RAM consists of 144 bytes (including the stack) at locations $0080 to
$012F. The stack begins at address $00FF and proceeds down to $00C0. Using
the stack area for data storage or temporary work locations requires care to pre-
vent it from being overwritten due to stacking from an interrupt or subroutine call.
ROM
There are a total of 3k-bytes of ROM on chip. This includes 2560 bytes of user
ROM with locations $1400 to $1DFF for user program storage and 16 bytes for
user vectors at locations $1FF0 to $1FFF. Also, 496 bytes of Self-check ROM on
chip at locations $1E00 to $1FEF.
MOTOROLA
2-2
MEMORY
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2.4
I/O REGISTERS SUMMARY
ADDR
REGISTER
Port A Data
PORTA
R/W BIT 7 BIT 6 BIT 5 BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
R
$0000
PA7
PB7
PA6
PB6
PA5
PB5
PA4
PB4
PA3
PA2
PA1
PA0
W
R
Port B Data
PORTB
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
PB2
PC2
PB1
PC1
PB0
PC0
W
R
Port C Data
PORTC
PC3
W
R
Unused
W
R
Port A Data Direction
DDRA
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
DDRB7 DDRB6 DDRB5 DDRB4 SLOWE DDRB2 DDRB1 DDRB0
W
R
Port B Data Direction
DDRB
W
R
Port C Data Direction
DDRC
OCMPO VROFF
DDRC3 DDRC2 DDRC1 DDRC0
W
R
Unused
W
R
MFT Ctrl/Status
TCSR
TOF
RTIF
TMR6
0
0
0
TOFE
TMR5
RTIE
RT1
RT0
W
R
TOFR
TMR3
RTIFR
TMR2
MFT Counter
TCNT
TMR7
TMR4
TMR1
TMR0
W
R
IRQ Control/Status
ICSR
0
0
IRQF
0
0
IRQE
IRQPU
W
R
IRQR
Unused
Unused
Unused
W
R
W
R
W
R
Optical Interface En.
OIER
TCMPE VREF2 VREF1 VREF0
OIE3
OIE2
OIE1
OIE0
W
R
Port C Pull-down/up
PDURC
W
PDRC3 PDRC2 PDRC1 PDRC0
reserved bits
unused bits
Figure 2-2. MC68HC05JB3 I/O Registers $0000-$000F
MC68HC05JB3
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ADDR
REGISTER
Port A Pull-down/up
PDURA
R/W BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
R
$0010
W
R
PDRA7 PDRA6 PDRA5 PDRA4 PDRA3 PDRA2 PDRA1 PDRA0
Port B Pull-down/up
PDURB
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
W
R
PDRB7 PDRB6 PDRB5 PDRB4
0
PURB2 PURB1 PDRB0
Timer1 Control
TCR
0
0
0
ICIE
OCIE
TOIE
IEDG
0
W
R
Timer1 Status
TSR
ICF
OCF
TOF
0
0
0
0
W
R
Input Capture MSB
ICH
ICH7
ICL7
ICH6
ICL6
ICH5
ICL5
ICH4
ICL4
ICH3
ICL3
ICH2
ICL2
ICH1
ICL1
ICH0
ICL0
W
R
Input Capture LSB
ICL
W
R
Output Compare MSB
OCH
OCH7
OCL7
OCH6
OCL6
OCH5
OCL5
OCH4
OCL4
OCH3
OCL3
OCH2
OCL2
OCH1
OCL1
OCH0
OCL0
W
R
Output Compare LSB
OCL
W
R
Timer1 Counter MSB
TCNTH
TCNTH7 TCNTH6 TCNTH5 TCNTH4 TCNTH3 TCNTH2 TCNTH1 TCNTH0
TCNTL7 TCNTL6 TCNTL5 TCNTL4 TCNTL3 TCNTL2 TCNTL1 TCNTL0
ACNTH7 ACNTH6 ACNTH5 ACNTH4 ACNTH3 ACNTH2 ACNTH1 ACNTH0
ACNTL7 ACNTL6 ACNTL5 ACNTL4 ACNTL3 ACNTL2 ACNTL1 ACNTL0
W
R
Timer1 Counter LSB
TCNTL
W
R
Alter. Counter MSB
ACNTH
W
R
Alter. Counter LSB
ACNTL
W
R
Unused
Unused
Unused
Unused
W
R
W
R
W
R
W
unused bits
reserved bits
Figure 2-3. MC68HC05JB3 I/O Registers $0010-$001F
MOTOROLA
2-4
MEMORY
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ADDR
REGISTER
USB Endpoint 0 Data 0
UD0R0
R/W BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
R
W
R
UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0
UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0
UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0
UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0
UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0
UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0
UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0
UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0
UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
$0020
USB Endpoint 0 Data 1
UD0R1
$0021
$0022
$0023
$0024
$0025
$0026
$0027
$0028
$0029
$002A
$002B
$002C
$002D
$002E
$002F
W
R
USB Endpoint 0 Data 2
UD0R2
W
R
USB Endpoint 0 Data 3
UD0R3
W
R
USB Endpoint 0 Data 4
UD0R4
W
R
USB Endpoint 0 Data 5
UD0R5
W
R
USB Endpoint 0 Data 6
UD0R6
W
R
USB Endpoint 0 Data 7
UD0R7
W
R
USB Endpoint 1 Data 0
UD1R0
W
R
UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
USB Endpoint 1 Data 1
UD1R1
W
R
USB Endpoint 1 Data 2
UD1R2
W
R
USB Endpoint 1 Data 3
UD1R3
W
R
USB Endpoint 1 Data 4
UD1R4
W
R
USB Endpoint 1 Data 5
UD1R5
W
R
USB Endpoint 1 Data 6
UD1R6
W
R
USB Endpoint 1 Data 7
UD1R7
W
unused bits
reserved bits
Figure 2-4. MC68HC05JB3 I/O Registers $0020-$002F
MC68HC05JB3
REV 1
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ADDR
REGISTER
R/W BIT 7 BIT 6 BIT 5 BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
R
W
R
$0030
Unused
$0031
$0032
$0033
$0034
$0035
$0036
$0037
$0038
$0039
$003A
$003B
$003C
$003D
$003E
$003F
Unused
Unused
Unused
Unused
Unused
Unused
W
R
W
R
W
R
W
R
W
R
W
USB Control 2
UCR2
R
W
R
0
TX1ST
0
ENABLE2 ENABLE1
STALL2 STALL1
TX1STR
USB Address
UADR
USBEN UADD6 UADD5 UADD4 UADD3 UADD2 UADD1 UADD0
W
R
USB Interrupt 0
UIR0
TXD0F RXD0F RSTF
0
0
SUSPND TXD0IE RXD0IE
W
R
0
0
0
TXD0FR RXD0FR
USB Interrupt 1
UIR1
TXD1F EOPF RESUMF
0
0
0
TXD1IE EOPIE
RESUMFR
W
R
0
0
0
TXD1FR EOPFR
USB Control 0
UCR0
T0SEQ STALL0 TX0E
T1SEQ ENDADD TX1E FRESUM TP1SIZ3 TP1SIZ2 TP1SIZ1 TP1SIZ0
RSEQ SETUP RPSIZ3 RPSIZ2 RPSIZ1 RPSIZ0
RX0E TP0SIZ3 TP0SIZ2 TP0SIZ1 TP0SIZ0
W
R
USB Control 1
UCR1
W
R
USB Status
USR
W
R
Reserved
Reserved
W
R
W
unused bits
reserved bits
Figure 2-5. MC68HC05JB3 I/O Registers $0030-$003F
ADDR
REGISTER
COP Register
COPR
R/W BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
R
0
0
0
0
0
0
0
$1FF0
W
COPR
Figure 2-6. COP Register (COPR)
MOTOROLA
2-6
MEMORY
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SECTION 3
CENTRAL PROCESSING UNIT
The MC68HC05JB3 has an 8k-bytes memory map. The stack has only 64 bytes.
Therefore, the stack pointer has been reduced to only 6 bits and will only
decrement down to $00C0 and then wrap-around to $00FF. All other instructions
and registers behave as described in this chapter.
3.1
REGISTERS
The MCU contains five registers which are hard-wired within the CPU and are not
part of the memory map. These five registers are shown in Figure 3-1 and are
described in the following paragraphs.
7
6
5
4
3
2
1
0
ACCUMULATOR
INDEX REGISTER
A
X
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
1
1
STACK POINTER
SP
PC
CC
PROGRAM COUNTER
CONDITION CODE REGISTER
1
1
1
H
I
N
Z
C
HALF-CARRY BIT (FROM BIT 3)
INTERRUPT MASK
NEGATIVE BIT
ZERO BIT
CARRY BIT
Figure 3-1. MC68HC05 Programming Model
MC68HC05JB3
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CENTRAL PROCESSING UNIT
MOTOROLA
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3.2
ACCUMULATOR (A)
The accumulator is a general purpose 8-bit register as shown in Figure 3-1. The
CPU uses the accumulator to hold operands and results of arithmetic calculations
or non-arithmetic operations. The accumulator is not affected by a reset of the
device.
3.3
INDEX REGISTER (X)
The index register shown in Figure 3-1 is an 8-bit register that can perform two
functions:
•
•
Indexed addressing
Temporary storage
In indexed addressing with no offset, the index register contains the low byte of
the operand address, and the high byte is assumed to be $00. In indexed
addressing with an 8-bit offset, the CPU finds the operand address by adding the
index register content to an 8-bit immediate value. In indexed addressing with a
16-bit offset, the CPU finds the operand address by adding the index register
content to a 16-bit immediate value.
The index register can also serve as an auxiliary accumulator for temporary
storage. The index register is not affected by a reset of the device.
3.4
STACK POINTER (SP)
The stack pointer shown in Figure 3-1 is a 16-bit register. In MCU devices with
memory space less than 64k-bytes the unimplemented upper address lines are
ignored. The stack pointer contains the address of the next free location on the
stack. During a reset or the reset stack pointer (RSP) instruction, the stack pointer
is set to $00FF. The stack pointer is then decremented as data is pushed onto the
stack and incremented as data is pulled off the stack.
When accessing memory, the ten most significant bits are permanently set to
0000000011. The six least significant register bits are appended to these ten fixed
bits to produce an address within the range of $00FF to $00C0. Subroutines and
interrupts may use up to 64($C0) locations. If 64 locations are exceeded, the
stack pointer wraps around and overwrites the previously stored information. A
subroutine call occupies two locations on the stack and an interrupt uses five
locations.
3.5
PROGRAM COUNTER (PC)
The program counter shown in Figure 3-1 is a 16-bit register. In MCU devices
with memory space less than 64k-bytes the unimplemented upper address lines
are ignored. The program counter contains the address of the next instruction or
operand to be fetched.
MOTOROLA
3-2
CENTRAL PROCESSING UNIT
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Normally, the address in the program counter increments to the next sequential
memory location every time an instruction or operand is fetched. Jump, branch,
and interrupt operations load the program counter with an address other than that
of the next sequential location.
3.6
CONDITION CODE REGISTER (CCR)
The CCR shown in Figure 3-1 is a 5-bit register in which four bits are used to
indicate the results of the instruction just executed. The fifth bit is the interrupt
mask. These bits can be individually tested by a program, and specific actions can
be taken as a result of their states. The condition code register should be thought
of as having three additional upper bits that are always ones. Only the interrupt
mask is affected by a reset of the device. The following paragraphs explain the
functions of the lower five bits of the condition code register.
3.6.1 Half Carry Bit (H-Bit)
When the half-carry bit is set, it means that a carry occurred between bits 3 and 4
of the accumulator during the last ADD or ADC (add with carry) operation. The
half-carry bit is required for binary-coded decimal (BCD) arithmetic operations.
3.6.2 Interrupt Mask (I-Bit)
When the interrupt mask is set, the internal and external interrupts are disabled.
Interrupts are enabled when the interrupt mask is cleared. When an interrupt
occurs, the interrupt mask is automatically set after the CPU registers are saved
on the stack, but before the interrupt vector is fetched. If an interrupt request
occurs while the interrupt mask is set, the interrupt request is latched. Normally,
the interrupt is processed as soon as the interrupt mask is cleared.
A return from interrupt (RTI) instruction pulls the CPU registers from the stack,
restoring the interrupt mask to its state before the interrupt was encountered. After
any reset, the interrupt mask is set and can only be cleared by the Clear I-Bit
(CLI), or WAIT instructions.
3.6.3 Negative Bit (N-Bit)
The negative bit is set when the result of the last arithmetic operation, logical
operation, or data manipulation was negative. (Bit 7 of the result was a logical
one.)
The negative bit can also be used to check an often tested flag by assigning the
flag to bit 7 of a register or memory location. Loading the accumulator with the
contents of that register or location then sets or clears the negative bit according
to the state of the flag.
3.6.4 Zero Bit (Z-Bit)
The zero bit is set when the result of the last arithmetic operation, logical
operation, data manipulation, or data load operation was zero.
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3.6.5 Carry/Borrow Bit (C-Bit)
The carry/borrow bit is set when a carry out of bit 7 of the accumulator occurred
during the last arithmetic operation, logical operation, or data manipulation. The
carry/borrow bit is also set or cleared during bit test and branch instructions and
during shifts and rotates.This bit is neither set by an INC nor by a DEC instruction.
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SECTION 4
INTERRUPTS
The MCU can be interrupted in six different ways:
•
•
•
•
•
•
Non-maskable Software Interrupt Instruction (SWI)
External Asynchronous Interrupt (IRQ)
External Interrupt via IRQ on PA0-PA3 (mask option)
USB Interrupt
Timer1 Interrupt (16-bit Timer)
Multi-Function Timer Interrupt
4.1
INTERRUPT VECTORS
Table 4-1. Reset/Interrupt Vector Addresses
Global
Hardware Software
Local
Control
Bit
Priority
(1 = Highest)
Vector
Address
Function
Source
Mask
Mask
Power-On Logic
RESET Pin
Low Voltage Reset
Illegal Address Reset
Reset
—
—
—
1
$1FFE–$1FFF
COP Watchdog
User Code
Software
Interrupt (SWI)
Same Priority
As Instruction
—
—
—
—
$1FFC–$1FFD
$1FFA–$1FFB
External
Interrupt (IRQ)
IRQ Pin
I Bit
IRQE Bit
2
3
TXD0F
TXD1F
RESUMP
TXD0IE
TXD1IE
—
USB
Interrupts
—
I Bit
$1FF8–$1FF9
ICF Bit
OCF Bit
TOF Bit
ICIE Bit
OCIE Bit
TOIE Bit
Timer1
Interrupts
—
—
I Bit
I Bit
4
5
$1FF6–$1FF7
$1FF4–$1FF5
MFT
Interrupts
CTOF Bit
RTIF Bit
CTOFE Bit
RTIE Bit
Reserved
Reserved
$1FF2–$1FF3
$1FF0–$1FF1
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NOTE
If more than one interrupt request is pending, the CPU fetches the vector of the
higher priority interrupt first. A higher priority interrupt does not actually interrupt a
lower priority interrupt service routine unless the lower priority interrupt service
routine clears the I bit.
4.2
INTERRUPT PROCESSING
The CPU does the following actions to begin servicing an interrupt:
•
•
•
Stores the CPU registers on the stack in the order shown in Figure 4-1.
Sets the I bit in the condition code register to prevent further interrupts.
Loads the program counter with the contents of the appropriate interrupt
vector locations as shown in Table 4-1.
The return from interrupt (RTI) instruction causes the CPU to recover its register
contents from the stack as shown in Figure 4-1. The sequence of events caused
by an interrupt are shown in the flow chart in Figure 4-2.
$0020
$0021
(BOTTOM OF RAM)
$00BE
$00BF
$00C0
$00C1
$00C2
(BOTTOM OF STACK)
UNSTACKING
ORDER
n
n+1
n+2
CONDITION CODE REGISTER
ACCUMULATOR
5
4
3
2
1
1
2
3
4
5
INDEX REGISTER
n+3 PROGRAM COUNTER (HIGH BYTE)
n+4
PROGRAM COUNTER (LOW BYTE)
STACKING
ORDER
$00FD
$00FE
$00FF
TOP OF STACK (RAM)
Figure 4-1. Interrupt Stacking Order
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FROM
RESET
YES
I BIT SET?
NO
EXTERNAL
INTERRUPT?
YES
CLEAR IRQ LATCH.
NO
YES
YES
YES
USB
INTERRUPT?
NO
TIMER1
INTERRUPT?
NO
MFT
INTERRUPT?
NO
STACK PCL, PCH, X, A, CCR.
SET I BIT.
LOAD PC WITH INTERRUPT VECTOR.
FETCH NEXT
INSTRUCTION.
SWI
YES
YES
INSTRUCTION?
NO
RTI
UNSTACK CCR, A, X, PCH, PCL.
EXECUTE INSTRUCTION.
INSTRUCTION?
NO
Figure 4-2. Interrupt Flowchart
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4.3
4.4
4.5
RESET INTERRUPT SEQUENCE
The RESET function is not in the strictest sense an interrupt; however, it is acted
upon in a similar manner as shown in Figure 4-2. A low level input on the RESET
pin or an internally generated RST signal causes the program to vector to its start-
ing address which is specified by the contents of memory locations $1FFE and
$1FFF. The I-bit in the condition code register is also set.
SOFTWARE INTERRUPT (SWI)
The SWI is an executable instruction and a non-maskable interrupt since it is exe-
cuted regardless of the state of the I-bit in the CCR. As with any instruction, inter-
rupts pending during the previous instruction will be serviced before the SWI
opcode is fetched. The interrupt service routine address is specified by the con-
tents of memory locations $1FFC and $1FFD.
HARDWARE INTERRUPTS
All hardware interrupts except RESET are maskable by the I-bit in the CCR. If the
I-bit is set, all hardware interrupts (internal and external) are disabled. Clearing
the I-bit enables the hardware interrupts. There are two types of hardware inter-
rupts which are explained in the following sections.
4.5.1 External Interrupt IRQ
The IRQ pin provides an asynchronous interrupt to the CPU. A block diagram of
the IRQ logic is shown in Figure 4-3.
The IRQ pin is one source of an IRQ interrupt and a mask option can also enable
the four lower Port-A pins (PA0 to PA3) to act as other IRQ interrupt sources.
Refer to Figure 4-3 for the following descriptions. IRQ interrupt source comes
from IRQ latch. The IRQ latch will be set on the falling edge of the IRQ pin or on
any falling edge of PA0-3 pins if PA0-3 interrupts have been enabled. If ‘edge-only’
sensitivity is chosen by a mask option, only the IRQ latch output can activate an
IRQF flag which creates a request to the CPU to generate the IRQ interrupt
sequence. This makes the IRQ interrupt sensitive to the following cases:
1. Falling edge on the IRQ pin.
2. Falling edge on any PA0-PA3 pin with IRQ enabled (via mask option).
If level sensitivity is chosen, the active high state of the signal to the clock input of
the IRQ latch can also activate an IRQF flag which creates an IRQ request to the
CPU to generate the IRQ interrupt sequence. This makes the IRQ interrupt sensi-
tive to the following cases:
1. Low level on the IRQ pin.
2. Falling edge on the IRQ pin.
3. Low level on any PA0-PA3 pin with IRQ enabled (via mask option).
4. Falling edge on any PA0-PA3 pin with IRQ enabled (via mask option).
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The IRQE enable bit controls whether an active IRQF flag can generate an IRQ
interrupt sequence. This interrupt is serviced by the interrupt service routine
located at the address specified by the contents of $1FFA and $1FFB.
If IRQF is set, the only way to clear this flag is by writing a logic one to the IRQR
acknowledge bit in the ICSR. As long as the output state of the IRQF flag bit is
active the CPU will continuously re-enter the IRQ interrupt sequence until the
active state is removed or the IRQE enable bit is cleared.
TO BIH & BIL
INSTRUCTION
PROCESSING
IRQ
V
DD
PA0
IRQ
LATCH
PA1
PA2
PA3
EXTERNAL
INTERRUPT
R
REQUEST
IRQ Level
(Mask Option)
Port A External Interrupt
(Mask Option)
RST
IRQ VECTOR FETCH
IRQ STATUS/CONTROL REGISTER
INTERNAL DATA BUS
Figure 4-3. External Interrupt (IRQ) Logic
4.5.2 IRQ Control/Status Register (ICSR) - $0A
The IRQ interrupt function is controlled by the ICSR located at $000A. All unused
bits in the ICSR will read as logic zeros. The IRQF bit is cleared and IRQE bit is
set by reset.
BIT 7
IRQE
1
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
IRQPU
0
ICSR
R
0
0
0
IRQF
0
0
$000A
W
IRQR
0
reset:
0
0
0
0
0
Figure 4-4. IRQ Control and Status Register (ICSR)
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IRQPU — IRQ pin PUll-up resistor enable
This bit enables/disables the internal pull-up resistor on the IRQ pin.
1 = Internal pull-up resistor in IRQ pin enabled.
0 = Internal pull-up resistor in IRQ pin disabled.
IRQR — IRQ Interrupt Acknowledge
This write-only bit clears an IRQ interrupt by clearing the IRQ latch, and hence
the IRQF bit. The IRQR bit will always read as a logic zero.
1 = Clears IRQ interrupt request (clears IRQF).
0 = No effect.
IRQF — IRQ Interrupt Request Flag
Writing to the IRQF flag bit will have no effect on it. If the additional setting of
IRQF flag bit is not cleared in the IRQ service routine and the IRQE enable bit
remains set the CPU will re-enter the IRQ interrupt sequence continuously until
either the IRQF flag bit or the IRQE enable bit is clear. The IRQF latch is
cleared by reset.
1 = Indicates that an IRQ request is pending.
0 = Indicates that no IRQ request triggered by pins PA0-3 or IRQ is
pending. The IRQF flag bit can be cleared by writing a logic one to
the IRQR acknowledge bit to clear the IRQ latch and also
conditioning the external IRQ sources to be inactive (if the level
sensitive interrupts are enabled via mask option). Doing so before
exiting the service routine will mask out additional occurrences of
the IRQF.
IRQE — IRQ Interrupt Enable
The IRQE bit enables/disables the IRQF flag bit to initiate an IRQ interrupt
sequence.
1 = Enables IRQ interrupt, that is, the IRQF flag bit can generate an
interrupt sequence. Reset sets the IRQE enable bit, thereby
enabling IRQ interrupts once the I-bit is cleared. Execution of the
STOP or WAIT instructions causes the IRQE bit to be set in order to
allow the external IRQ to exit these modes.
0 = The IRQF flag bit cannot generate an interrupt sequence.
4.5.3 Port A External Interrupts (PA0-PA3, by mask option)
The IRQ interrupt can also be triggered by the inputs on the PA0 to PA3 port pins
if enabled by a single mask option. If enabled, the lower four bits of Port A can
activate the IRQ interrupt function, and the interrupt operation will be the same as
for inputs to the IRQ pin. This mask option of PA0-3 interrupt allow all of these
input pins to be OR’ed with the input present on the IRQ pin. All PA0 to PA3 pins
must be selected as a group as an additional IRQ interrupt. All the PA0-3 interrupt
sources are also controlled by the IRQE enable bit.
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NOTE
The BIH and BIL instructions will only apply to the level on the IRQ pin itself, and
not to the output of the logic OR function with the PA0 to PA3 pins.The state of the
individual Port A pins can be checked by reading the appropriate Port A pins as
inputs.
NOTE
If enabled, the PA0 to PA3 pins will cause an IRQ interrupt only when the
corresponding pin is configured as input.
4.5.4 Timer1 Interrupt (TIMER1)
The TIMER1 interrupt is generated by the 16-bit timer when either an overflow or
an input capture or output compare has occurred as described in the section on
16-bit timer. The interrupt flags and enable bits for the Timer1 interrupts are
located in the Timer1 Control & Status Register (TSR) located at $0012, $0013.
The I-bit in the CCR must be clear in order for the TIMER1 interrupt to be enabled.
Either of these three interrupts will vector to the same interrupt service routine
located at the address specified by the contents of memory locations $1FF6 and
$1FF7.
4.5.5 USB Interrupt (USB)
The USB interrupt is generated by the USB module as described in the section on
Universal Serial Bus. The interrupt enable bits for the USB interrupt are located at
bit3-bit2 of UIR0 register and bit3-bit2 of UIR1 register. Also Once the device goes
into Suspend Mode, any bus activities will cause the USB to generate an interrupt
to CPU to come out from the Suspend mode. The I-bit in the CCR must be clear in
order for the USB interrupt to be enabled. Either of these two interrupts will vector
to the same interrupt service routine located at the address specified by the con-
tents of memory locations $1FF8 and $1FF9.
4.5.6 MFT Interrupt (MFT)
The MFT interrupt is generated by the MFT module as described in the section on
Multi-function Timer. These interrupts will vector to the same interrupt service rou-
tine located at the address specified by the contents of memory locations $1FF4
and $1FF5.
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SECTION 5
RESETS
This section describes the six reset sources and how they initialize the MCU. A
reset immediately stops the operation of the instruction being executed, initializes
certain control bits, and loads the program counter with a user defined reset vec-
tor address. The following conditions produce a reset:
•
•
•
•
•
Initial power up of device (power on reset).
A logic zero applied to the RESET pin (external reset).
Timeout of the COP watchdog (COP reset).
Low voltage applied to the device (LVR reset).
Fetch of an opcode from an address not in the memory map (illegal
address reset).
•
Detection of USB reset signal (USB reset).
Figure 5-1 shows a block diagram of the reset sources and their interaction.
USB RESET DETECTION
COP WATCHDOG
LOW VOLTAGE RESET
V
POWER-ON RESET
DD
ILLEGAL ADDRESS RESET
INTERNAL
ADDRESS BUS
S
TO CPU
RST
RESET
D
AND
RESET
LATCH
SUBSYSTEMS
R
INTERNAL
CLOCK
Figure 5-1. Reset Sources
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5.1
POWER-ON RESET
A positive transition on the V
pin generates a power-on reset. The power-on
DD
reset is strictly for conditions during powering up and cannot be used to detect
drops in power supply voltage.
A 224t
or 4064t
(internal clock cycle) delay after the oscillator becomes
CYC
CYC
active allows the clock generator to stabilize. If the RESET pin is at logic zero at
the end of the multiple t time, the MCU remains in the reset condition until the
CYC
signal on the RESET pin goes to a logic one.
5.2
EXTERNAL RESET
A logic zero applied to the RESET pin for 1.5t
generates an external reset.
CYC
This pin is connected to a Schmitt trigger input gate to provide and upper and
lower threshold voltage separated by a minimum amount of hysteresis. The exter-
nal reset occurs whenever the RESET pin is pulled below the lower threshold and
remains in reset until the RESET pin rises above the upper threshold. This active
low input will generate the internal RST signal that resets the CPU and peripher-
als.
The RESET pin can also act as an open drain output. It will be pulled to a low
state by an internal pulldown device that is activated by three internal reset
sources. This RESET pulldown device will only be asserted for 3 to 4 cycles of the
internal clock, f , or as long as the internal reset source is asserted. When the
OP
external RESET pin is asserted, the pulldown device will not be turned on.
NOTE
Do not connect the RESET pin directly to V , as this may overload some power
DD
supply designs when the internal pulldown on the RESET pin activates.
5.3
INTERNAL RESETS
The five internally generated resets are the initial power-on reset function, the
COP Watchdog timer reset, the low voltage reset, and the illegal address detector.
Only the COP Watchdog timer reset, low voltage reset and illegal address detec-
tor will also assert the pulldown device on the RESET pin for the duration of the
reset function or 3 to 4 internal clock cycles, whichever is longer.
5.3.1 Power-On Reset (POR)
The internal POR is generated on power-up to allow the clock oscillator to stabi-
lize. The POR is strictly for power turn-on conditions and is not able to detect a
drop in the power supply voltage (brown-out). There is an oscillator stabilization
delay of 224 or 4064 (224 or 4064 is selected by mask option) internal processor
bus clock cycles after the oscillator becomes active.
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The POR will generate the RST signal which will reset the CPU. If any other reset
function is active at the end of the 224 or 4064 cycle delay, the RST signal will
remain in the reset condition until the other reset condition(s) end.
POR will not activate the pulldown device on the RESET pin. V
must drop
DD
below V
in order for the internal POR circuit to detect the next rise of V .
POR
DD
5.3.2 USB Reset
The USB reset is generated by a detection on the USB bus reset signal. For
MC68HC05JB3, seeing a single-end zero on its upstream port for 4 to 8 bit times
will set RSTF bit in UIR0 register.The detections will also generate the RST signal
to reset the CPU and other peripherals in the MCU.
5.3.3 Computer Operating Properly (COP) Reset
The COP watchdog is enabled by a mask option.
A timeout of the COP watchdog generates a COP reset. The COP watchdog is
part of a software error detection system and must be cleared periodically to start
a new timeout period. To clear the COP watchdog and prevent a COP reset, write
a logic zero to the COPC bit of the COP register at location $1FF0.
BIT 7
0
BIT 6
0
BIT 5
0
BIT 4
0
BIT 3
0
BIT 2
0
BIT 1
0
BIT 0
COPR
$1FF0
R
0
COPC
0
W
reset:
U
U
U
U
U
U
U
U = UNAFFECTED BY RESET
Figure 5-2. COP Watchdog Register (COPR)
COPC — COP Clear
COPC is a write-only bit. Periodically writing a logic zero to COPC prevents the
COP watchdog from resetting the MCU. Reset clears the COPC bit.
1 = No effect on system.
0 = Reset COP watchdog timer.
The COP Watchdog reset will assert the pull-down device to pull the RESET pin
low for one cycle of the internal bus clock.
Refer to section on Multi-Function Timer for detail on COP watchdog timeout peri-
ods.
5.3.4 Low Voltage Reset (LVR)
The LVR activates the RST reset signal to reset the device when the voltage on
the V
pin falls below the LVR trip voltage. The LVR will assert the pulldown
DD
device to pull the RESET pin low one cycle of the internal bus clock. The Low Volt-
age Reset circuit is enabled by a mask option.
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5.3.5 Illegal Address Reset
An opcode fetch from an address that is not in the ROM or the RAM generates an
illegal address reset. The illegal address reset will assert the pull-down device to
pull the RESET pin low for 3 to 4 cycles of the internal bus clock.
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SECTION 6
LOW POWER MODES
There are three modes of operation that reduce power consumption:
•
•
•
Stop mode
Wait mode
Data retention mode
Figure 6-1 shows the sequence of events in Stop and Wait modes.
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STOP
WAIT
STOP EXTERNAL OSCILLATOR,
STOP INTERNAL TIMER CLOCK,
RESET START-UP DELAY
EXTERNAL OSCILLATOR ACTIVE,
INTERNAL TIMER CLOCK ACTIVE
STOP INTERNAL PROCESSOR CLOCK,
CLEAR I-BIT IN CCR,
STOP INTERNAL PROCESSOR CLOCK,
CLEAR I-BIT IN CCR,
SET IRQE IN ICSR
SET IRQE IN ICSR
YES
YES
EXTERNAL
RESET?
EXTERNAL
RESET?
NO
NO
IRQ
YES
IRQ
YES
EXTERNAL
EXTERNAL
INTERRUPT?
INTERRUPT?
NO
NO
USB
YES
USB
YES
RESET OR
INTERRUPT?
INTERRUPT
OR RESET?
NO
NO
TIMER1
YES
INTERNAL
INTERRUPT?
RESTART EXTERNAL OSCILLATOR,
START STABILIZATION DELAY
NO
MFT
YES
INTERNAL
INTERRUPT?
END OF
STABILIZATION
DELAY?
YES
NO
NO
RESTART INTERNAL PROCESSOR CLOCK
1. LOAD PC WITH RESET VECTOR
OR
2. SERVICE INTERRUPT.
a. SAVE CPU REGISTERS ON STACK.
b. SET I BIT IN CCR.
c. LOAD PC WITH INTERRUPT VECTOR.
Figure 6-1. STOP and WAIT Flowchart
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6.1
STOP MODE
STOP mode is entered by executing the STOP instruction. This is the lowest
power consumption mode of the MCU. In the STOP Mode the internal oscillator is
turned off, halting all internal processing.
Execution of the STOP instruction automatically clears the I-bit in the Condition
Code Register and sets the IRQE enable bit in the IRQ Control/Status Register so
that the IRQ external interrupt is enabled. All other registers, including the other
bits in the TCSR, and memory remain unaltered. All input/output lines remain
unchanged.
The MCU can be brought out of the STOP Mode by an IRQ external interrupt or a
USB coming out from Suspend Mode Interrupt (Bus activity detection) or an exter-
nally generated RESET, USB Reset or an LVR reset. When exiting the STOP
Mode the internal oscillator will resume after a 224 or 4064 internal processor
clock cycle oscillator stabilization delay.
6.2
WAIT MODE
WAIT mode is entered by executing the WAIT instruction. This places the MCU in
a low-power mode, which consumes more power than the STOP Mode. In the
WAIT Mode the internal processor clock is halted, suspending all processor and
internal bus activity. Execution of the WAIT instruction automatically clears the I-bit
in the Condition Code Register and sets the IRQE enable bit in the IRQ Control/
Status Register so that the IRQ external interrupt is enabled. All other registers,
memory, and input/output lines remain in their previous states.
The WAIT Mode may be exited when an external IRQ, USB, Timer1 or MFT inter-
rupt, an LVR reset, USB reset or an external RESET occurs.
6.3
DATA-RETENTION MODE
The Data-Retention mode is only available if the Low Voltage Reset function
(mask option) is not enabled.
In the data retention mode, the MCU retains RAM contents and CPU register con-
tents at V voltages as low as 2Vdc. The data retention feature allows the MCU
DD
to remain in a low power consumption state during which it retains data, but the
CPU cannot execute instructions. The RESET pin must be held low during data-
retention mode.
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6-4
LOW POWER MODES
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SECTION 7
INPUT/OUTPUT PORTS
In normal operating mode there are 19 usable bidirectional I/O lines arranged as
one 8-bit I/O port (Port-A), one 7-bit I/O port (Port-B), and one 4-bit I/O port
(Port C). The individual bits in these ports are programmable as either inputs or
outputs under software control by the data direction registers (DDRs).
The eight port pins, PB4-PB7 and PC0-PC3, are only available on the 28-pin
version of the device.
Table 7-1 shows a summary of Port-A, Port-B, and Port-C functions.
Table 7-1. Summary of Port Pin Functions
Internal Resistor
Configuration
Current
Drive/Sink
Port Pins
Additional Features
2
PA0-PA3
PA4-PA7
PB0
1.6mA sink
8mA sink
External Interrupt
Optical Interface
1
Pull-down
1.6mA sink
shared with TCAP
shared with OCMP
25mA sink,
open-drain
1
PB1, PB2
Pull-up
Slow Transition Output
PB4-PB7
PC0
Pins available only
in 28-pin device
1
Pull-down
1.6mA sink
PC1-PC3
Notes:
1. A pull-up/pull-down resistor is enabled by setting the corresponding register bit to “0” and the
port pull-up/down mask option is selected.
2. Selected by mask option.
7.1
PORT-A
Port-A is an 8-bit bi-directional port. The Port-A data register is at $0000 and the
data direction register (DDRA) is at $0004. Reset does not affect the data regis-
ters, but clears the data direction registers, thereby returning the port pins to
inputs. Writing a ‘1’ to a DDR bit sets the corresponding port bit to output mode.
All Port-A pins have programmable pull-down resistors. PA4 to PA7 each has 8mA
current sink capability.
The table below summarizes the pin configurations for Port-A.
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PDRAx
DDRAx
Pin Configuration
Input with pull-down
Output Push/Pull
Input
0
0
1
1
0
1
0
1
Output Push/Pull
7.1.1 Port-A Data Register
BIT 7
BIT 6
PA6
0
BIT 5
PA5
0
BIT 4
PA4
0
BIT 3
PA3
0
BIT 2
PA2
0
BIT 1
PA1
0
BIT 0
PA0
0
PORTA
$0000
R
PA7
0
W
reset:
7.1.2 Port-A Data Direction Register
BIT 7
DDRA7
0
BIT 6
DDRA6
0
BIT 5
DDRA5
0
BIT 4
DDRA4
0
BIT 3
DDRA3
0
BIT 2
DDRA2
0
BIT 1
DDRA1
0
BIT 0
DDRA0
0
DDRA
$0004
R
W
reset:
DDRAx — PAx Data Direction
1 = Port pin set as output.
0 = Port pin set as input.
7.1.3 Port-A Pull-down/up Register
With the pull-up/down mask option selected, each pin in Port-A has an internal
pull-down resistor which can be enabled by writing a ‘0’ to the corresponding bit in
the Port-A pull-down/up control register (PDURA) at location $0010.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PDURA
$0010
R
W
PDRA7
0
PDRA7
0
PDRA7
0
PDRA7
0
PDRA7
0
PDRA7
0
PDRA7
0
PDRA7
0
reset:
PDRAx — PAx Pin Pull-down enable
1 = Internal pull-down disabled.
0 = Internal pull-down enabled.
7.1.4 PA0-PA3 Interrupts
A mask option selects the capability for PA0-PA3 to be used as external IRQ inter-
rupt inputs. These four I/O pins also have schmitt trigger input circuits.
See INTERRUPTS section for detail.
MOTOROLA
7-2
INPUT/OUTPUT PORTS
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7.1.5 PA0-PA7 Optical Interface
Port-A is programmable to use as ports for the optical interface.
See OPTICAL INTERFACE section for details.
7.2
PORT-B
Port-B is a 7-bit bi-directional port. The Port-B data register is at $0001 and the
data direction register (DDRB) is at $0005. Reset does not affect the data regis-
ters, but clears the data direction registers, thereby returning the port pins to
inputs. Writing a ‘one’ to a DDR bit sets the corresponding port bit to output mode.
PB4-PB7 are only available on the 28-pin version of the device.
All Port-B pins have programmable pull-down or pull-up resistors. PB1 and PB2
each has 25mA current sink capability.
PB0 is also used as the 16-timer TCAP input pin. When configured as output, the
input to the input capture will be permanently tied “low” and no input capture can
be generated.
The table below summarizes the pin configurations for Port-B.
PDRBx/PURBx
DDRBx
Pin Configuration
PB0, PB4-PB7: Input with pull-down
PB1, PB2: Input with pull-up
0
0
PB0, PB4-PB7: Output Push-Pull
PB1, PB2: Output Open-drain with pull-up
0
1
1
1
0
1
Input
PB0, PB4-PB7: Output Push-Pull
PB1, PB2: Output Open-drain
7.2.1 Port-B Data Register
BIT 7
BIT 6
BIT 5
PB5
0
BIT 4
PB4
0
BIT 3
0
BIT 2
PB2
0
BIT 1
PB1
0
BIT 0
PB0
0
PORTB
$0001
R
PB7
0
PB6
0
W
reset:
0
7.2.2 Port-B Data Direction Register
BIT 7
DDRB7
0
BIT 6
DDRB6
0
BIT 5
DDRB5
0
BIT 4
DDRB4
0
BIT 3
SLOWE
0
BIT 2
DDRB2
0
BIT 1
DDRB1
0
BIT 0
DDRB0
0
DDRB
$0005
R
W
reset:
DDRBx — PBx Data Direction
1 = Port pin set as output.
0 = Port pin set as input.
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SLOWE — Slow Transition Enable
See Section 7.2.4 for details.
1 = Enable slow falling-edge output transition feature on PB1 and PB2.
0 = Disable slow falling-edge output transition feature on PB1 and PB2.
7.2.3 Port-B Pull-down/up Register
With the pull-up/down mask option selected, PB0 and PB4-PB7 each has an inter-
nal pull-down resistor, while PB1 and PB2 each has an internal pull-up resistor,
which can be enabled by writing a ‘0’ to the corresponding bit in the Port-B
pull-down/up control register (PDURB) at location $0011.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PDURB
$0011
R
W
PDRB7
0
PDRB6
0
PDRB5
0
PDRB4
0
PURB2
0
PURB1
0
PDRB0
0
reset:
0
PDRBx — PBx Pin Pull-down enable
1 = Internal pull-down disabled.
0 = Internal pull-down enabled.
PURBx — PBx Pin Pull-up enable
1 = Internal pull-up disabled.
0 = Internal pull-up enabled.
7.2.4 PB1, PB2 Slow Transition Output
The slow transition output feature is enabled by setting the SLOWE bit in DDRB at
$0005.
PB2 — a high-to-low output transition is a sharp falling edge transition delayed by
t
÷ 2.
CYC
PB1 — a high-to-low output transition is a slow falling edge (drops from 5.0V to
2.2V in 167ns typically at f =3MHz, with 50pF load) followed by a fast transition
OP
to V . The fast transition duration is depending on the strength of the output
SS
driver defined for each port. See Figure 7-1.
Both PB1 and PB2 have 25mA current sink capability.
MOTOROLA
7-4
INPUT/OUTPUT PORTS
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5.0V
2.2V
0V
Output Driver
50pF
165ns
330ns
Figure 7-1. PB1 Slow Falling-edge Output
7.3
PORT-C
Port-C is a 4-bit bi-directional port. The Port-C data register is at $0002 and the
data direction register (DDRC) is at $0006. Reset does not affect the data regis-
ters, but clears the data direction registers, thereby returning the port pins to
inputs. Writing a ‘one’ to a DDR bit sets the corresponding port bit to output mode.
All Port-C pins have programmable pull-down resistors, and are only available on
the 28-pin version of the device.
PC0 is also used as the 16-timer OCMP output pin.
The table below summarizes the pin configurations for Port-A.
PDRCx
DDRCx
Pin Configuration
Input with pull-down
Output Push-Pull
Input
0
0
1
1
0
1
0
1
Output Push-Pull
7.3.1 Port-C Data Register
BIT 7
BIT 6
BIT 5
0
BIT 4
0
BIT 3
PC3
0
BIT 2
PC2
0
BIT 1
PC1
0
BIT 0
PC0
0
PORTC
$0002
R
W
reset:
0
0
7.3.2 Port-C Data Direction Register
BIT 7
OCMPO
0
BIT 6
VROFF
0
BIT 5
BIT 4
0
BIT 3
DDRC3
0
BIT 2
DDRC2
0
BIT 1
DDRC1
0
BIT 0
DDRC0
0
DDRC
$0006
R
W
reset:
0
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DDRCx — PCx Data Direction
1 = Port pin set as output.
0 = Port pin set as input.
VROFF — USB 3.3V Voltage Reference
See USB section for details.
1 = Disable 3.3V regulator.
0 = Enables 3.3V regulator.
OCMPO — OCMP Output Enable
See 16-BIT TIMER section for details.
1 = PC0 is OCMP pin, OCF from 16-bit timer output compare.
0 = PC0 is standard I/O pin, from Port-C data register.
7.3.3 Port-C Pull-down/up Register
With the pull-up/down mask option selected, each pin in Port-C has an internal
pull-down resistor which can be enabled by writing a ‘0’ to the corresponding bit in
the Port-C pull-down/up control register (PDURC) at location $000F.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PDURC
$000F
R
W
PDRC3
0
PDRC2
0
PDRC1
0
PDRC0
0
reset:
0
0
0
0
PDRCx — PCx Pin Pull-down Enable
1 = Internal pull-down disabled.
0 = Internal pull-down enabled.
MOTOROLA
7-6
INPUT/OUTPUT PORTS
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GENERAL RELEASE SPECIFICATION
SECTION 8
MULTI-FUNCTION TIMER
The Multi-Function Timer (or Core Timer) module is a 15-stage ripple counter with
Timer Over Flow (CTOF), Real Time Interrupt (RTI), and COP Watchdog function.
MCU Internal Bus
8
8
Timer Counter Register ($09)
2
Internal
Timer Clock
(NTF1)
f
÷2
OP
÷4
10
÷2
7-bit counter
17
16
15
14
÷2
÷2
÷2
÷2
RTI Select Circuit
Overflow
Detect
Circuit
COP Watchdog
Resetable Timer
(÷8)
Timer Control & Status Register ($08)
CTOF RTIF CTOFE RTIE CTOFR RTIFR RT1
RT0
Interrupt Circuit
to CPU interrupt
Figure 8-1. Multi-Function Timer Block Diagram
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8.1
OVERVIEW
As shown in Figure 8-1, the Timer is driven by the timer clock, NTF1, divided by
four. NTF1 has the same phase and frequency as the processor bus clock, PH2,
but continues to run in WAIT mode. The NTF1 drives an 8-bit ripple counter. The
value of this 8-bit ripple counter can be read by the CPU at any time by accessing
the Timer Counter Register (TCNT) at address $09. A timer overflow function is
implemented on the last stage of this 8-bit counter, giving a possible interrupt rate
of f ÷1024.
OP
The last stage of the 8-bit counter also drives a further 7-bit counter. The final four
14 15 16
stages is used by the RTI circuit, giving possible RTI rates of f ÷2 , 2 , 2 or
OP
17
2 , selected by RT1 and RT0 (see Table 8-1). The RTI rate selector bits, and the
RTI and CTOF enable bits and flags are located in the Timer Control and Status
Register at location $08.
The power-on cycle clears the entire counter chain and begins clocking the
counter. After 224 or 4064 cycles, the power-on reset circuit is released which
again clears the counter chain and allows the device to come out of reset. At this
point, if RESET is not asserted, the timer will start counting up from zero and nor-
mal device operation will begin. If RESET is asserted at any time during operation
the counter chain will be cleared.
8.2
COMPUTER OPERATING PROPERLY (COP) WATCHDOG
The COP Watchdog is enabled by a mask option.
The COP Watchdog Timer function is implemented by using the output of the RTI
circuit and further dividing it by eight. The minimum COP reset rates are listed in
Table 8-1. If the COP circuit times out, an internal reset is generated and the nor-
mal reset vector is fetched.
Preventing a COP time-out is done by writing a “0” to bit-0 of address $1FF0.
When the COP is cleared, only the final divide by eight stage (output of the RTI) is
cleared.
8.3
MFT REGISTERS
8.3.1 Timer Counter Register (TCNT) $09
The Timer Counter Register is a read-only register which contains the current
value of the 8-bit ripple counter at the beginning of the timer chain. This counter is
clocked at f ÷4 and can be used for various functions including a software input
OP
capture. Extended time periods can be attained using the CTOF function to incre-
ment a temporary RAM storage location thereby simulating a 16-bit (or more)
counter. The value of each bit of the TCNT is shown in Figure 8-2. This register is
cleared by reset.
MOTOROLA
8-2
MULTI-FUNCTION TIMER
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BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TCNT
$0009
R
TMR7
TMR6
TMR5
TMR4
TMR3
TMR2
TMR1
TMR0
W
reset:
0
0
0
0
0
0
0
0
Figure 8-2. Timer Counter Register
8.3.2 Timer Control/Status Register (TCSR) $08
The TCSR contains the timer interrupt flag bits, the timer interrupt enable bits, and
the real time interrupt rate select bits. Bit 2 and bit 3 are write-only bits which will
read as logical zeros. Figure 8-3 shows the value of each bit in the TCSR follow-
ing reset.
BIT 7
BIT 6
RTIF
BIT 5
CTOFE
0
BIT 4
RTIE
0
BIT 3
BIT 2
BIT 1
RT1
1
BIT 0
RT0
1
TCSR
$0008
R
CTOF
0
CTOFR
0
0
RTIFR
0
W
reset:
0
0
Figure 8-3. Timer Control/Status Register (TCSR)
RT0, RT1 — Real-Time Interrupt period select bits
These two bits select the Real-Time Interrupt period and the COP Watchdog
reset period.
Table 8-1. RTI and COP Rates at f =3.0MHz
OP
Bus Frequency, f
=f =3.0 MHz
BUS OP
COP Reset Period
RT1
RT0
Divide Ratio
RTI Rate
(RTI × 8)
14
0
0
1
1
0
1
0
1
2
5.46ms
10.92ms
21.85ms
43.69ms
43.68ms
87.36ms
174.8ms
349.52ms
15
2
16
2
17
2
RTIFR — Real Time Interrupt Acknowledge
The RTIFR is an acknowledge bit that resets the RTIF flag bit. This bit is unaf-
fected by reset. Reading the RTIFR will always return a logical zero.
1 = Clears the RTIF flag bit.
0 = Does not clear the RTIF flag bit.
CTOFR — Timer Overflow Acknowledge
The CTOFR is an acknowledge bit that resets the CTOF flag bit. This bit is
unaffected by reset. Reading the CTOFR will always return a logical zero.
1 = Clears the CTOF flag bit.
0 = Does not clear the CTOF flag bit.
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RTIE — Real Time Interrupt Enable
The RTIE is an enable bit that allows generation of a TIMER Interrupt by the
RTIF bit.
1 = When set, the TIMER Interrupt is generated when the RTIF flag bit is
set.
0 = When cleared, no TIMER interrupt caused by RTIF bit set will be
generated. This bit is cleared by reset.
CTOFE — Timer Overflow Enable
The CTOFE is an enable bit that allows generation of a TIMER Interrupt upon
overflow of the Timer Counter Register.
1 = When set, the TIMER Interrupt is generated when the CTOF flag bit
is set.
0 = When cleared, no TIMER interrupt caused by CTOF bit set will be
generated. This bit is cleared by reset.
RTIF — Real Time Interrupt Flag
The RTIF is a read-only flag bit.
1 = Set when the output of the chosen (1 of 4 selections) Real Time
Interrupt stage goes active. A TIMER Interrupt request will be
generated if RTIE is also set.
0 = Reset by writing a logical one to the RTIF acknowledge bit, RTIFR.
Writing to the RTIF flag bit has no effect on its value. This bit is
cleared by reset.
CTOF — Timer Overflow Flag
The CTOF is a read-only flag bit.
1 = Set when the 8-bit ripple counter rolls over from $FF to $00. A
TIMER Interrupt request will be generated if CTOFE is also set.
0 = Reset by writing a logical one to the CTOF acknowledge bit,
CTOFR. Writing to the CTOF flag bit has no effect on its value. This
bit is cleared by reset.
8.4
8.5
OPERATION DURING STOP MODE
When STOP is exited by an external interrupt or an LVR reset or an external
RESET, the internal oscillator will resume, followed by a 224 or 4064 internal pro-
cessor oscillator stabilization delay.
COP CONSIDERATION DURING STOP MODE
In STOP mode, the clock to the Watchdog Timer is stopped and is therefore
impossible to generate COP reset when in STOP mode. The COP function will
resume 224 or 4064 cycles after exiting from STOP.
MOTOROLA
8-4
MULTI-FUNCTION TIMER
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GENERAL RELEASE SPECIFICATION
SECTION 9
16-BIT TIMER
This 16-bit Programmable Timer (Timer1) has an Input Capture function and an
Output Compare function. Figure 9-1 shows a block diagram of the 16-bit
programmable timer.
EDGE
SIGNAL
CONDITIONING
PB0/
TCAP
SELECT
ICRH ($0014) ICRL ($0015)
& DETECT
LOGIC
TMRH ($0018) TMRL ($0019)
ACRH ($001A) ACRL ($001B)
TCMPE
(bit7 at $0E)
INTERNAL
CLOCK
OSC
16-BIT COUNTER
16-BIT COMPARATOR
÷ 4
(f
÷ 2)
PORT-C LOGIC
OCRH ($0016) OCRL ($0017)
PC0/
OCMP
MUX
OCMPO
TIMER
INTERRUPT
REQUEST
RESET
TIMER CONTROL REGISTER
$0012
TIMER STATUS REGISTER
$0013
INTERNAL DATA BUS
Figure 9-1. Programmable Timer Block Diagram
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The basis of the 16-bit Timer is a 16-bit free-running counter which increases in
count with each internal bus clock cycle. The counter is the timing reference for
the input capture and output compare functions. The input capture and output
compare functions provide a means to latch the times at which external events
occur, to measure input waveforms, and to generate output waveforms and timing
delays. Software can read the value in the 16-bit free-running counter at any time
without affect the counter sequence.
Because of the 16-bit timer architecture, the I/O registers for the input capture and
output compare functions are pairs of 8-bit registers. Each register pair contains
the high and low byte of that function. Generally, accessing the low byte of a spe-
cific timer function allows full control of that function; however, an access of the
high byte inhibits that specific timer function until the low byte is also accessed.
Because the counter is 16 bits long and preceded by a fixed divide-by-four pres-
caler, the counter rolls over every 262,144 internal clock cycles. Timer resolution
with a 4MHz crystal oscillator is 2 microsecond/count.
The interrupt capability, the input capture edge, and the output compare state are
controlled by the timer control register (TCR) located at $0012 and the status of
the interrupt flags can be read from the timer status register (TSR) located at
$0013.
9.1
TIMER REGISTERS (TMRH,TMRL)
The functional block diagram of the 16-bit free-running timer counter and timer
registers is shown in Figure 9-2. The timer registers include a transparent buffer
latch on the LSB of the 16-bit timer counter.
READ
TMRL
LATCH
TMRL ($0019)
TMR LSB
READ
TMRH
READ
TMRH ($0018)
($FFFC)
INTERNAL
CLOCK
OSC
RESET
÷ 4
16-BIT COUNTER
(f
÷ 2)
OVERFLOW (TOF)
TIMER
INTERRUPT
REQUEST
TIMER CONTROL REG.
$0012
TIMER STATUS REG.
$0013
INTERNAL
DATA
BUS
Figure 9-2. Programmable Timer Counter Block Diagram
MOTOROLA
9-2
16-BIT TIMER
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The timer registers (TMRH, TMRL) shown in Figure 9-3 are read-only locations
which contain the current high and low bytes of the 16-bit free-running counter.
Writing to the timer registers has no effect. Reset of the device presets the timer
counter to $FFFC.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TMRH
$0018
R
TMRH7
TMRH6
TMRH5
TMRH4
TMRH3
TMRH2
TMRH1
TMRH0
W
reset:
1
TMRL7
1
1
TMRL6
1
1
TMRL5
1
1
TMRL4
1
1
TMRL3
1
1
TMRL2
1
1
TMRL1
0
1
TMRL0
0
TMRL
$0019
R
W
reset:
Figure 9-3. Programmable Timer Counter Registers (TMRH, TMRL)
The TMRL latch is a transparent read of the LSB until the a read of the TMRH
takes place. A read of the TMRH latches the LSB into the TMRL location until the
TMRL is again read. The latched value remains fixed even if multiple reads of the
TMRH take place before the next read of the TMRL. Therefore, when reading the
MSB of the timer at TMRH the LSB of the timer at TMRL must also be read to
complete the read sequence.
During power-on-reset (POR), the counter is initialized to $FFFC and begins
counting after the oscillator start-up delay. Because the counter is sixteen bits and
preceded by a fixed divide-by-four prescaler, the value in the counter repeats
every 262, 144 internal bus clock cycles (524, 288 oscillator cycles).
When the free-running counter rolls over from $FFFF to $0000, the timer overflow
flag bit (TOF) is set in the TSR. When the TOF is set, it can generate an interrupt if
the timer overflow interrupt enable bit (TOIE) is also set in the TCR. The TOF flag
bit can only be reset by reading the TMRL after reading the TSR.
Other than clearing any possible TOF flags, reading the TMRH and TMRL in any
order or any number of times does not have any effect on the 16-bit free-running
counter.
NOTE
To prevent interrupts from occurring between readings of the TMRH and TMRL,
set the I bit in the condition code register (CCR) before reading TMRH and clear
the I bit after reading TMRL.
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9.2
ALTERNATE COUNTER REGISTERS (ACRH, ACRL)
The functional block diagram of the 16-bit free-running timer counter and alternate
counter registers is shown in Figure 9-4. The alternate counter registers behave
the same as the timer registers, except that any reads of the alternate counter will
not have any effect on the TOF flag bit and Timer interrupts. The alternate counter
registers include a transparent buffer latch on the LSB of the 16-bit timer counter.
INTERNAL
DATA
BUS
READ
ACRL
LATCH
ACRL ($001B)
TMR LSB
READ
ACRH
READ
ACRH ($001A)
($FFFC)
INTERNAL
CLOCK
OSC
RESET
÷ 4
16-BIT COUNTER
(f
÷ 2)
Figure 9-4. Alternate Counter Block Diagram
The alternate counter registers (ACRH, ACRL) shown in Figure 9-5 are read-only
locations which contain the current high and low bytes of the 16-bit free-running
counter. Writing to the alternate counter registers has no effect. Reset of the
device presets the timer counter to $FFFC.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ACRH
$001A
R
ACRH7
ACRH6
ACRH5
ACRH4
ACRH3
ACRH2
ACRH1
ACRH0
W
reset:
1
ACRL7
1
1
ACRL6
1
1
ACRL5
1
1
ACRL4
1
1
ACRL3
1
1
ACRL2
1
1
ACRL1
0
1
ACRL0
0
ACRL
$001B
R
W
reset:
Figure 9-5. Alternate Counter Registers (ACRH, ACRL)
The ACRL latch is a transparent read of the LSB until the a read of the ACRH
takes place. A read of the ACRH latches the LSB into the ACRL location until the
ACRL is again read. The latched value remains fixed even if multiple reads of the
ACRH take place before the next read of the ACRL. Therefore, when reading the
MSB of the timer at ACRH the LSB of the timer at ACRL must also be read to
complete the read sequence.
During power-on-reset (POR), the counter is initialized to $FFFC and begins
counting after the oscillator start-up delay. Because the counter is sixteen bits and
preceded by a fixed divide-by-four prescaler, the value in the counter repeats
every 262,144 internal bus clock cycles (524,288 oscillator cycles).
Reading the ACRH and ACRL in any order or any number of times does not have
any effect on the 16-bit free-running counter or the TOF flag bit.
MOTOROLA
9-4
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NOTE
To prevent interrupts from occurring between readings of the ACRH and ACRL,
set the I bit in the condition code register (CCR) before reading ACRH and clear
the I bit after reading ACRL.
9.3
INPUT CAPTURE REGISTERS
INTERNAL
DATA
BUS
READ
ICRH
EDGE
SELECT
& DETECT
LOGIC
ICRH ($0014)
ICRL ($0015)
READ
LATCH
SIGNAL
CONDITIONING
PB0/
TCAP
ICRL
INTERNAL
CLOCK
÷ 4
16-BIT COUNTER
INPUT CAPTURE (ICF)
(f
÷ 2)
OSC
TIMER
INTERRUPT
REQUEST
TCMPE
(bit7 at $0E)
RESET
TIMER CONTROL REG.
$0012
TIMER STATUS REG.
$0013
INTERNAL
DATA
BUS
Figure 9-6. Timer Input Capture Block Diagram
The input capture function is a technique whereby an external signal (connected
to PB0/TCAP pin) is used to trigger the 16-bit timer counter. In this way it is possi-
ble to relate the timing of an external signal to the internal counter value, and
hence to elapsed time.
NOTE
Since the TCAP pin is shared with the PB0 I/O pin, changing the state of the PB0
DDR or Data Register can cause an unwanted TCAP interrupt. This can be
avoided by clearing the ICIE bit before changing the configuration of PB0, and
clearing any pending interrupts before enabling ICIE.
The signal on the TCAP pin is first directed to a schmitt trigger or a voltage
comparator as shown in Figure 9-7. Setting the TCMPE bit to “1” will enable the
comparator and the V /2 reference voltage.
DD
MC68HC05JB3
REV 1
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MOTOROLA
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BIT 7
TCMPE
0
BIT 6
VREF2
0
BIT 5
VREF1
0
BIT 4
VREF0
0
BIT 3
OIE3
0
BIT 2
OIE2
0
BIT 1
OIE1
0
BIT 0
OIE0
0
OIER
R
$000E
W
reset:
TCMPE — Timer Input Capture Comparator Enable
1 = Timer input capture comparator is selected.
0 = Timer input capture comparator schmitt trigger is selected.
NOTE
When the comparator and V /2 reference are enabled, PB0 pin will automatically
DD
becomes an input pin, irrespective of DDR setting. However, it is recommended to
set PB0 as an input first (via DDR), before enabling the comparator. A read of PB0
will reflect the TCAP pin status, not the PB0 register bit.
The comparator uses the V /2 reference as the compare voltage, resulting in a
DD
typical output as shown in Figure 9-8.
Switching off the V /2 voltage reference by clearing TCMPE=0 will further save
DD
power when the MCU is in a low power mode.
PB0 I/O
PORT LOGIC
PB0/
TCAP
Schmitt Trigger
Voltage
Reference
To edge select and
detect logic
MUX
Comparator
+
–
V
÷ 2
DD
V
REF
TCMPE bit
EN
Figure 9-7. TCAP Input Signal Conditioning
MOTOROLA
9-6
16-BIT TIMER
MC68HC05JB3
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V
DD
Output of Comparator
V
÷ 2
DD
Signal on TCAP pin
Time
Figure 9-8. TCAP Input Comparator Output
When the input capture circuitry detects an active edge on the TCAP pin, it
latches the contents of the free-running timer counter registers into the input cap-
ture registers as shown in Figure 9-6.
Latching values into the input capture registers at successive edges of the same
polarity measures the period of the selected input signal. Latching the counter val-
ues at successive edges of opposite polarity measures the pulse width of the sig-
nal.
The input capture registers are made up of two 8-bit read-only registers (ICRH,
ICRL) as shown in Figure 9-9.The input capture edge detector contains a Schmitt
trigger to improve noise immunity. The edge that triggers the counter transfer is
defined by the input edge bit (IEDG) in the TCR. Reset does not affect the con-
tents of the input capture registers.
The result obtained by an input capture will be one count higher than the value of
the free-running timer counter preceding the external transition. This delay is
required for internal synchronization. Resolution is affected by the prescaler,
allowing the free-running timer counter to increment once every four internal clock
cycles (eight oscillator clock cycles).
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ICRH
R
ICRH7
ICRH6
ICRH5
ICRH4
ICRH3
ICRH2
ICRH1
ICRH0
$0014
W
reset:
U
ICRL7
U
U
ICRL6
U
U
ICRL5
U
U
ICRL4
U
U
ICRL3
U
U
ICRL2
U
U
ICRL1
U
U
ICRL0
U
ICRL
R
$0015
W
reset:
U = UNAFFECTED BY RESET
Figure 9-9. Input Capture Registers (ICRH, ICRL)
MC68HC05JB3
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Reading the ICRH inhibits further captures until the ICRL is also read. Reading
the ICRL after reading the timer status register (TSR) clears the ICF flag bit. does
not inhibit transfer of the free-running counter. There is no conflict between read-
ing the ICRL and transfers from the free-running timer counters. The input capture
registers always contain the free-running timer counter value which corresponds
to the most recent input capture.
NOTE
To prevent interrupts from occurring between readings of the ICRH and ICRL, set
the I bit in the condition code register (CCR) before reading ICRH and clear the
I bit after reading ICRL.
9.4
OUTPUT COMPARE REGISTERS
The Output Compare function is a means of generating an interrupt when the 16-
bit timer counter reaches a selected value as shown in Figure 9-10. Software
writes the selected value into the output compare registers. On every fourth inter-
nal clock cycle (every eight oscillator clock cycle) the output compare circuitry
compares the value of the free-running timer counter to the value written in the
output compare registers. When a match occurs, the output compare interrupt
flag, OCF is set. A timer interrupt request to the CPU is generated if the output
compare interrupt enable is set, i.e. OCIE=1.
Port pin, PC0 is configured as the OCMP output pin when the OCMPO bit (bit7 at
$06) is set to “1”. The OCMP output reflects the logic of the output compare inter-
rupt flag, OCF, as shown in Figure 9-10.
BIT 7
OCMPO
0
BIT 6
VROFF
0
BIT 5
BIT 4
BIT 3
DDRC3
0
BIT 2
DDRC2
0
BIT 1
DDRC1
0
BIT 0
DDRC0
0
DDRC
$0006
R
W
reset:
0
0
OCMPO — OCMP Output Enable
1 = PC0 is OCMP pin, OCF from 16-bit timer output compare.
0 = PC0 is standard I/O pin, from Port-C data register.
Software can use the output compare register to measure time periods, to gener-
ate timing delays, or to generate a pulse of specific duration or a pulse train of
specific frequency and duty cycle.
Writing to the OCRH before writing to the OCRL inhibits timer compares until the
OCRL is written. Reading or writing to the OCRL after reading the TSR will clear
the output compare flag bit (OCF).
MOTOROLA
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PORT-C LOGIC
OCMPO (bit7 at $06)
R/W
OCRH
OCRH ($0016)
OCRL ($0017)
PC0/
OCMP
MUX
16-BIT COMPARATOR
($FFFC)
INTERNAL
CLOCK
OSC
÷ 4
16-BIT COUNTER
(f
÷ 2)
OUTPUT COMPARE
(OCF)
TIMER
INTERRUPT
REQUEST
R/W
OCRL
RESET
TIMER CONTROL REG.
$0012
TIMER STATUS REG.
$0013
INTERNAL
DATA
BUS
Figure 9-10. Timer Output Compare Block Diagram
BIT 7
OCRH7
U
BIT 6
OCRH6
U
BIT 5
OCRH5
U
BIT 4
OCRH4
U
BIT 3
OCRH3
U
BIT 2
OCRH2
U
BIT 1
OCRH1
U
BIT 0
OCRH0
U
OCRH
$0016
R
W
reset:
OCRL
$0017
R
OCRL7
U
OCRL6
U
OCRL5
U
OCRL4
U
OCRL3
U
OCRL2
U
OCRL1
U
OCRL0
U
W
reset:
U = UNAFFECTED BY RESET
Figure 9-11. Output Compare Registers (OCRH, OCRL)
To prevent OCF from being set between the time it is read and the time the output
compare registers are updated, use the following procedure:
1. Disable interrupts by setting the I bit in the condition code register.
2. Write to the OCRH. Compares are now inhibited until OCRL is written.
3. Read the TSR to arm the OCF for clearing.
4. Enable the output compare registers by writing to the OCRL. This also
clears the OCF flag bit in the TSR.
5. Enable interrupts by clearing the I bit in the condition code register.
A software example of this procedure is shown below.
MC68HC05JB3
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9B
SEI
...
...
STA
LDA
STX
...
...
CLI
DISABLE INTERRUPTS
.....
.....
INHIBIT OUTPUT COMPARE
ARM OCF FLAG FOR CLEARING
READY FOR NEXT COMPARE, OCF CLEARED
.....
.....
ENABLE INTERRUPTS
...
...
B7
B6
BF
...
...
9A
16
13
17
OCRH
TSR
OCRL
9.5
TIMER CONTROL REGISTER (TCR)
The timer control register is shown in Figure 9-12 performs the following func-
tions:
•
•
•
•
Enables input capture interrupts
Enables output compare interrupts
Enables timer overflow interrupts
Control the active edge polarity of the TCAP signal on pin PB0/TCAP
Reset clears all the bits in the TCR with the exception of the IEDG bit which is
unaffected.
BIT 7
ICIE
0
BIT 6
OCIE
0
BIT 5
TOIE
0
BIT 4
0
BIT 3
0
BIT 2
0
BIT 1
IEDG
BIT 0
0
TCR
R
$0012
W
reset:
0
0
0
Unaffected
0
Figure 9-12. Timer Control Register (TCR)
ICIE - INPUT CAPTURE INTERRUPT ENABLE
This read/write bit enables interrupts caused by an active signal on the PB0/
TCAP pin. Reset clears the ICIE bit.
1 = Input capture interrupts enabled.
0 = Input capture interrupts disabled.
OCIE - OUTPUT COMPARE INTERRUPT ENABLE
This read/write bit enables interrupts caused by a successful compare between
the timer counter and the output compare registers. Reset clears the OCIE bit.
1 = Output compare interrupts enabled.
0 = Output compare interrupts disabled.
TOIE - TIMER OVERFLOW INTERRUPT ENABLE
This read/write bit enables interrupts caused by a timer overflow. Reset clears
the TOIE bit.
1 = Timer overflow interrupts enabled.
0 = Timer overflow interrupts disabled.
MOTOROLA
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IEDG - INPUT CAPTURE EDGE SELECT
The state of this read/write bit determines whether a positive or negative transi-
tion on the TCAP pin triggers a transfer of the contents of the timer register to
the input capture register. Reset has no effect on the IEDG bit.
1 = Positive edge (low to high transition) triggers input capture.
0 = Negative edge (high to low transition) triggers input capture.
9.6
TIMER STATUS REGISTER (TSR)
The timer status register (TSR) shown in Figure 9-13 contains flags for the follow-
ing events:
•
An active signal on the PB0/TCAP pin, transferring the contents of the
timer registers to the input capture registers.
•
•
A match between the 16-bit counter and the output compare registers
An overflow of the timer registers from $FFFF to $0000.
Writing to any of the bits in the TSR has no effect. Reset does not change the
state of any of the flag bits in the TSR.
BIT 7
ICF
BIT 6
OCF
BIT 5
TOF
BIT 4
0
BIT 3
0
BIT 2
0
BIT 1
0
BIT 0
0
TSR
R
$0013
W
reset:
U
U
U
0
0
0
0
0
U = UNAFFECTED BY RESET
Figure 9-13. Timer Status Registers (TSR)
ICF - INPUT CAPTURE FLAG
The ICF bit is automatically set when an edge of the selected polarity occurs on
the PB0/TCAP pin. Clear the ICF bit by reading the timer status register with
the ICF set, and then reading the low byte (ICRL, $0015) of the input capture
registers. Reset has no effect on ICF.
OCF - OUTPUT COMPARE FLAG
The OCF bit is automatically set when the value of the timer registers matches
the contents of the output compare registers. Clear the OCF bit by reading the
timer status register with the OCF set, and then accessing the low byte (OCRL,
$0017) of the output compare registers. Reset has no effect on OCF.
OCF status will be latched to the output of OCMP (PC0 pin) if the OCMPO bit is
set to “1” (bit7 at $06).
TOF - TIMER OVERFLOW FLAG
The TOF bit is automatically set when the 16-bit timer counter rolls over from
$FFFF to $0000. Clear the TOF bit by reading the timer status register with the
TOF set, and then accessing the low byte (TMRL, $0019) of the timer registers.
Reset has no effect on TOF.
MC68HC05JB3
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9.7
9.8
TIMER OPERATION DURING WAIT MODE
During WAIT mode the 16-bit timer continues to operate normally and may gener-
ate an interrupt to trigger the MCU out of the WAIT mode.
TIMER OPERATION DURING STOP MODE
When the MCU enters the STOP mode the free-running counter stops counting
(the internal processor clock is stopped). It remains at that particular count value
until the STOP mode is exited by applying a low signal to the IRQ pin, at which
time the counter resumes from its stopped value as if nothing had happened. If
STOP mode is exited via an external reset (logic low applied to the RESET pin)
the counter is forced to $FFFC.
If a valid input capture edge occurs at the PB0/TCAP pin during the STOP mode
the input capture detect circuitry will be armed. This action does not set any flags
or “wake up” the MCU, but when the MCU does “wake up” there will be an active
input capture flag (and data) from the first valid edge. If the STOP mode is exited
by an external reset, no input capture flag or data will be present even if a valid
input capture edge was detected during the STOP mode.
MOTOROLA
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GENERAL RELEASE SPECIFICATION
SECTION 10
UNIVERSAL SERIAL BUS MODULE
This USB Module is designed for USB application in LS products. With minimized
software effort, it can fully comply with USB LS device specification. See USB
specification version 1.0 for the detail description of USB.
10.1 FEATURES
Integrated 3.3 Volt Regulator with 3.3V Output Pin
•
•
•
Integrated USB transceiver supporting Low Speed functions
USB Data Control Logic
– Packet decoding/generation
– CRC generation and checking
– NRZI encoding/decoding
– Bit-stuffing
•
•
•
•
•
•
•
•
•
•
•
USB reset support
Control Endpoint 0 and Interrupt Endpoints 1 and 2
Two 8-byte transmit buffers
One 8-byte receive buffer
Suspend and resume operations
Remote Wake-up support
USB generated interrupts
Transaction interrupt driven
Resume interrupt
End of Packet interrupt
STALL, NAK, and ACK handshake generation
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10.2 OVERVIEW
This section provides an overview of the Universal Serial Bus (USB) module in the
MC68HC05JB3. This USB module is designed to serve as a low-speed (LS) USB
device per the Universal Serial Bus Specification Rev 1.0. Three types of USB
data transfers are supported: control, interrupt, and bulk (transmit only).
Endpoint 0 functions as a receive/transmit control endpoint. Endpoints 1 and 2
can function as interrupt or bulk, but only in the transmit direction.
A block diagram of the USB module is shown Figure 10-1. The USB module
manages communications between the host and the USB function. The module is
partitioned into four functional blocks. These blocks consist of a 3.3 volt regulator,
a dual function transceiver, the USB control logic, and the endpoint registers. The
blocks are further detailed in Section 10.4.
RCV
D+
D–
VPIN
VMIN
USB
Upstream
Port
VPOUT
VMOUT
3.3V OUT
REGULATOR
CPU BUS
USB REGISTERS
Figure 10-1. USB Block Diagram
MOTOROLA
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10.2.1 USB Protocol
Figure 10-2 shows the various transaction types supported by the
MC68HC05JB3 USB module. The transactions are portrayed as error free. The
effect of errors in the data flow are discussed later.
ENDPOINT 0 TRANSACTIONS:
Control Write
SETUP
DATA0
OUT
ACK
OUT
DATA1
OUT
ACK
DATA0
ACK
DATA0/1
ACK
ACK
IN
DATA1
ACK
Control Read
SETUP
DATA0
IN
ACK
IN
DATA1
DATA0
ACK
IN
DATA0/1
ACK
ACK
OUT
DATA1
ACK
No-Data Control
SETUP
DATA0
ACK
IN
DATA1
ENDPOINTS 1 & 2 TRANSACTIONS:
KEY:
Interrupt
Unrelated Bus
Traffic
IN
DATA0/1
ACK
ACK
Host
Generated
Bulk Transmit
IN
Device
Generated
DATA0/1
Figure 10-2. Supported Transaction Types per Endpoint
Each USB transaction is comprised of a series of packets. The MC68HC05JB3
USB module supports the packet types shown in Figure 10-3. Token packets are
generated by the USB host and decoded by the USB device. Data and
Handshake packets are both decoded and generated by the USB device
depending on the type of transaction.
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Token Packet:
IN
OUT
SYNC
PID
PID
PID
ADDR ENDP CRC5
EOP
EOP
SETUP
Data Packet:
DATA0
SYNC
SYNC
PID
PID
DATA
CRC5
DATA1
0 - 8 bytes
Handshake Packet:
ACK
NAK
PID
EOP
STALL
Figure 10-3. Supported USB Packet Types
The following sections will give some detail on each segment used to form a
complete USB transaction.
10.2.1.1 Sync Pattern
The NRZI (See Section 10.4.4.1) bit pattern shown in Figure 10-4 is used as a
synchronization pattern and is prefixed to each packet. This pattern is equivalent
to a data pattern of seven 0’s followed by a 1 (0x80).
SYNC PATTERN
NRZI Data
Encoding
Idle
PID0 PID1
Figure 10-4. Sync Pattern
The start of a packet (SOP) is signaled by the originating port by driving the D+
and D– lines from the idle state (also referred to as the “J” state) to the opposite
logic level (also referred to as the “K” state). This switch in levels represents the
first bit of the Sync field. Figure 10-5 shows the data signaling and voltage levels
for the start of packet and the sync pattern.
MOTOROLA
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V
(min)
OH
V
(max)
SE
V
(min)
(min)
SE
OL
V
V
SS
FIRST BIT OF PACKET
SOP
END OF SYNC
BUS IDLE
Figure 10-5. SOP, Sync Signaling and Voltage Levels
10.2.1.2 Packet Identifier Field
The Packet Identifier field is an eight bit number comprised of the four bit packet
identification (PID) and its complement. The field follows the sync pattern and
determines the direction and type of transaction on the bus. Table 10-1 shows the
PID values for the supported packet types.
Table 10-1. Supported Packet Identifiers
PID Value
%1001
%0001
%1101
%0011
%1011
%0010
%1010
%1110
PID Type
IN Token
OUT Token
SETUP Token
DATA0 Packet
DATA1 Packet
ACK Handshake
NAK Handshake
STALL Handshake
10.2.1.3 Address Field (ADDR)
The Address field is a seven bit number that is used to select a particular USB
device. This field is compared to the lower seven bits of the UADDR register to
determine if a given transaction is targeting the MC68HC05JB3 USB device.
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10.2.1.4 Endpoint Field (ENDP)
The Endpoint field is a four bit number that is used to select a particular endpoint
within a USB device. For the MC68HC05JB3, this will be a binary number
between zero and two inclusive. Any other value will cause the transaction to be
ignored.
10.2.1.5 Cyclic Redundancy Check (CRC)
Cyclic Redundancy Checks are used to verify the address and data stream of a
USB transaction. This field is five bits wide for token packets and sixteen bits wide
for data packets. CRCs are generated in the transmitter and sent on the USB data
lines after both the endpoint field and the data field. Figure 10-6 shows how the
five bit CRC value is calculated from the data stream and verified for the address
and endpoint fields of a token packet. Figure 10-7 shows how the sixteen bit CRC
value is calculated and either transmitted or verified for the data packet of a given
transaction.
Update every bit time
Reset to ones at SOP
Generator Polynomial:
0 1
0
0 1
Data Stream
5
next bit
0
5
0
1
MUX
5
Expected Residual:
1 1
0
0 0
5
5
Equal?
Good CRC
Bad CRC
Y
N
Figure 10-6. CRC Block Diagram for Address and Endpoint Fields
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Update every bit time
Reset to ones at SOP
Generator Polynomial:
1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
Input / Output
Data Stream
16
next bit
0
16
1
0
MUX
Output
Data Stream
TRANSMIT
16
16
CRC16 Transmitted
MSB first after final
data byte.
Expected Residual:
RECEIVE
1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1
16
Equal?
Good CRC
Bad CRC
N
Y
Figure 10-7. CRC Block Diagram for Data Packets
10.2.1.6 End Of Packet (EOP)
The single-ended 0 (SE0) state is used to signal an end of packet (EOP). The
single-ended 0 state is indicated by both D+ and D– being below 0.8 V. EOP will
be signaled by driving D+ and D– to the single-ended 0 state for two bit times
followed by driving the lines to the idle state for one bit time. The transition from
the single-ended 0 to the idle state defines the end of the packet. The idle state is
asserted for one bit time and then both the D+ and D– output drivers are placed in
their high-impedance state. The bus termination resistors hold the bus in the idle
state. Figure 10-8 shows the data signaling and voltage levels for an end of
packet transaction.
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LAST BIT OF
PACKET
BUS DRIVEN TO
IDLE STATE
EOP
BUS FLOATS
STROBE
BUS IDLE
V
(min)
OH
V
(max)
SE
V
(min)
(min)
SE
OL
V
V
SS
Figure 10-8. EOP Transaction Voltage Levels
The width of the SE0 in the EOP is about two bit times. The EOP width is
measured with the same capacitive load used for maximum rise and fall times and
is measured at the same level as the differential signal crossover points of the
data lines.
t
Period
DATA
CROSSOVER
LEVEL
DIFFERENTIAL
DATA LINES
EOP
WIDTH
Figure 10-9. EOP Width Timing
10.2.2 Reset Signaling
A reset is signaled on the bus by the presence of an extended SE0 at the USB
data pins of a device. The reset signaling is specified to be present for a minimum
of 10 ms. An active device (powered and not in the suspend state) seeing a
single-ended zero on its USB data inputs for more than 2.5µs may treat that signal
as a reset, but must have interpreted the signaling as a reset within 5.5 µs. For a
Low speed device, an SE0 condition between 4 and 8 low speed bit times
represents a valid USB reset.
A USB sourced reset will hold the MC68HC05JB3 in reset for the duration of the
reset on the USB bus. The RSTF bit in the USB interrupt register 0 (UIR0) will be
set after the internal reset is removed (See Section 10.5.2 for more detail).
After a reset is removed, the device will be in the attached, but not yet addressed
or configured state (refer to Section 9.1 of the USB specification).The device must
be able to accept a device address via a SET_ADDRESS command (refer to
section 9.4 of the USB specification) no later than 10 ms after the reset is
removed.
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Reset can wake a device from the suspended mode. A device may take up to
10ms to wake up from the suspended state.
10.2.3 Suspend
The MC68HC05JB3 supports suspend mode for low power. Suspend mode
should be entered when the USB data lines are in the idle state for more than 3.0
ms. Entry into Suspend mode is controlled by the SUSPND bit in the USB
Interrupt Register. Any low speed bus activity should keep the device out of the
suspend state. Low speed devices are kept awake by periodic low speed EOP
signals from the host. This is referred to as Low speed keep alive (refer to Section
11.2.5.1 of the USB specification).
Firmware should monitor the EOPF flag and enter suspend mode by setting the
SUSPND bit if an EOP is not detected for 3 ms.
Per the USB specification, the MC68HC05JB3 is required to draw less than
500µA from the V supply when in the suspend state. This includes the current
DD
supplied by the voltage regulator to the 15 KΩ to ground termination resistors
placed at the host end of the USB bus. This low current requirement means that
firmware is responsible for entering STOP mode once the USB module has been
placed in the suspend state.
10.2.4 Resume After Suspend
The MC68HC05JB3 can be activated from the suspend state by normal bus
activity, a USB reset signal, or by a forced resume driven from the
MC68HC05JB3.
10.2.4.1 Host Initiated Resume
The host signals resume by initiating resume signalling (“K” state) for at least 20
ms followed by a standard low speed EOP signal. This 20 ms ensures that all
devices in the USB network are awakened.
After resuming the bus, the host must begin sending bus traffic within 3 ms to
prevent the device from re-entering suspend mode.
10.2.4.2 USB Reset Signalling
Reset can wake a device from the suspended mode. A device may take up to 10
ms to wake up from the suspended state.
10.2.4.3 Remote Wake-up
The MC68HC05JB3 also supports the remote wake-up feature. The firmware has
the ability to exit suspend mode by signaling a resume state to the upstream Host
or Hub. A non-idle state (“K” state) on the USB data lines is accomplished by
asserting the FRESUM bit in the UCR1 register.
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When using the remote wake-up capability, the firmware must wait for at least 5
ms after the bus is in the idle state before sending the remote wake-up resume
signaling. This allows the upstream devices to get into their suspend state and
prepare for propagating resume signaling. The FRESUM bit should be asserted to
cause the resume state on the USB data lines for at least 10ms, but not more than
15ms. Note that the resume signalling is controlled by the FRESUM bit and
meeting the timing specifications is dependent on the firmware. When FRESUM is
cleared by firmware, the data lines will return to their high impedance state. Refer
to Section 10.5.5 for more information about how the Force Resume (FRESUM)
bit can be used to initiate the remote wake-up feature.
10.2.5 Low Speed Device
Externally, low speed devices are configured by the position of a pull-up resistor
on the USB D– pin of the MC68HC05JB3. Low speed devices are terminated as
shown in Figure 10-10 with the pull-up on the D– line.
3.3V Regulator Out
1.5KΩ
MC68HC05JB3
D+
D–
USB Low Speed Cable
Figure 10-10. External Low Speed Device Configuration
For low speed transmissions, the transmitter’s EOP width must be between
1.25µs and 1.50µs. These ranges include timing variations due to differential
buffer delay and rise/fall time mismatches and to noise and other random effects.
A low speed receiver must accept a 670ns wide SE0 followed by a J transition as
a valid EOP. An SE0 narrower than 330ns or an SE0 not followed by a J transition
must be rejected as an EOP. An EOP between 330ns and 670ns may be rejected
or accepted as above. Any SE0 that is 2.5µs or wider is automatically a reset.
10.3 CLOCK REQUIREMENTS
The low speed data rate is nominally 1.5 Mbs. The OSCXCLK signal driven by the
oscillator circuits is the clock source for the USB module and requires that a 6
MHz oscillator circuit be connected to the OSC1 and OSC2 pins. The permitted
frequency tolerance for low speed functions is approximately ±1.5% (15000 ppm).
This tolerance includes inaccuracies from all sources: initial frequency accuracy,
crystal capacitive loading, supply voltage on the oscillator, temperature, and
aging. The jitter in the low speed data rate must be less than 10 ns. This tolerance
allows the use of resonators in low cost, low speed devices.
10.4 HARDWARE DESCRIPTION
The USB module as previously shown in Figure 10-1 contains four functional
blocks: a 3.3 volt regulator, a LS USB transceiver, the USB control logic, and the
USB registers. The following will detail the function of the regulator, transceiver
and control logic. See Section 10.5 for the register discussion.
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10.4.1 Voltage Regulator
The USB data lines are required by the USB Specification to have a maximum
output voltage between 2.8V and 3.6V. The data lines are also required to have an
external 1.5KΩ pullup resistor connected between a data line and a voltage
source between 3.0V and 3.6V. Since the power provided by the USB cable is
specified to be between 4.4V and 5.0V, an on-chip regulator is used to drop the
voltage to the appropriate level for sourcing the USB transceiver and external
pullup resistor. An output pin driven by the regulator voltage is provided to source
the 1.5KΩ external resistor. Figure 10-11 shows the worst case electrical
connection for the voltage regulator.
This regulator can be switched off by user program to save power when the device
is in suspend mode. Please note that if the regulator is off, the D– line should be
tied to another voltage source with an external pull-up resistor.
BIT 7
OCMPO
0
BIT 6
VROFF
0
BIT 5
BIT 4
BIT 3
DDRC3
0
BIT 2
DDRC2
0
BIT 1
DDRC1
0
BIT 0
DDRC0
0
DDRC
$0006
R
W
reset:
0
0
VROFF — USB 3.3V Voltage Reference
The 3.3V Voltage Regulator for the USB transmitter and external D– pull-up can
be switched off to reduce power consumption when device is in suspend mode.
1 = Disable 3.3V regulator.
0 = Enables 3.3V regulator.
4.4V
VROFF
3.3V
Regulator
USB Data Lines
USB Cable
R1
Host
or
Hub
LS
Transceiver
R2
R2
R1 = 1.5KΩ ±5%
R2 = 15KΩ ±5%
Figure 10-11. Regulator Electrical Connections
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10.4.2 USB Transceiver
The USB transceiver provides the physical interface to the USB D+ and D– data
lines. The transceiver is composed of two parts: an output drive circuit and a
differential receiver.
10.4.2.1 Output Driver Characteristics
The USB transceiver uses a differential output driver to drive the USB data signal
onto the USB cable. The static output swing of the driver in its low state is below
the V of 0.3 V with a 1.5 kΩ load to 3.6 V and in its high state is above the V
OL
OH
of 2.8 V with a 15 kΩ load to ground. The output swings between the differential
high and low state are well balanced to minimize signal skew. Slew rate control on
the driver is used to minimize the radiated noise and cross talk. The driver’s
outputs support three-state operation to achieve bi-directional half duplex
operation. The driver can tolerate a voltage on the signal pins of –0.5 V to 3.8 V
with respect to local ground reference without damage.
10.4.2.2 Low Speed (1.5 Mbs) Driver Characteristics
The rise and fall time of the signals on this cable are greater than 75 ns to keep
RFI emissions under FCC class B limits, and less than 300 ns to limit timing
delays and signaling skews and distortions. The driver reaches the specified static
signal levels with smooth rise and fall times, and minimal reflections and ringing
when driving the cable. This driver is used only on network segments between low
speed devices and the ports to which they are connected.
ONE BIT
TIME
(1.5 Mb/s)
SIGNAL PINS
V
(max)
(min)
SE
PASS OUTPUT SPEC
LEVELS WITH MINIMAL
REFLECTIONS AND RINGING
V
SE
V
SS
Figure 10-12. Low Speed Driver Signal Waveforms
10.4.3 Receiver Characteristics
USB data transmission is done with differential signals. A differential input receiver
is used to accept the USB data signal. A differential 1 on the bus is represented by
D+ being at least 200 mV more positive than D– as seen at the receiver, and a
differential 0 is represented by D– being at least 200 mV more positive than D+ as
seen at the receiver. The signal cross over point must be between 1.3V and 2.0V.
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The receiver features an input sensitivity of 200 mV when both differential data
inputs are in the range of 0.8 V to 2.5 V with respect to the local ground reference.
This is called the common mode input voltage range. Proper data reception is also
achieved when the differential data lines are outside the common mode range, as
shown in Figure 10-13. The receiver can tolerate static input voltages between
–0.5V to 3.8 V with respect to its local ground reference without damage. In
addition to the differential receiver, there is a single-ended receiver (schmitt
trigger) for each of the two data lines.
1.0
0.8
0.6
0.4
0.2
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2
COMMON MODE INPUT VOLTAGE (VOLTS)
Figure 10-13. Differential Input Sensitivity Over Entire Common Mode Range
10.4.3.1 Receiver Data Jitter
The data receivers for all types of devices must be able to properly decode the
differential data in the presence of jitter.The more of the bit cell that any data edge
can occupy and still be decoded, the more reliable the data transfer will be. Data
receivers are required to decode differential data transitions that occur in a
window plus and minus a nominal quarter bit cell from the nominal (centered) data
edge position.
Jitter will be caused by the delay mismatches and by mismatches in the source
and destination data rates (frequencies). The receive data jitter budget for low
speed is given in the electrical section of the this specification. The specification
includes the consecutive (next) and paired transition values for each source of
jitter.
10.4.3.2 Data Source Jitter
The source of data can have some variation (jitter) in the timing of edges of the
data transmitted. The time between any set of data transitions is
N x TPERIOD ± jitter time, where ‘N’ is the number of bits between the transitions
and T
is defined as the actual period of the data rate. The data jitter is
PERIOD
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measured with the same capacitive load used for maximum rise and fall times and
is measured at the crossover points of the data lines as shown in Figure 10-14.
t
Period
CROSSOVER
POINTS
DIFFERENTIAL
DATA LINES
CONSECUTIVE
TRANSITIONS
PAIRED
TRANSITIONS
Figure 10-14. Data Jitter
For low speed transmissions, the jitter time for any consecutive differential data
transitions must be within ±25 ns and within ±10 ns for any set of paired
differential data transitions. These jitter numbers include timing variations due to
differential buffer delay, rise/fall time mismatches, internal clock source jitter, and
to noise and other random effects.
10.4.3.3 Data Signal Rise and Fall Time
The output rise time and fall time are measured between 10% and 90% of the
signal. Edge transition time for the rising and falling edges of low speed signals is
75 ns (minimum) into a capacitive load (C ) of 50 pF and 300 ns (maximum) into a
L
capacitive load of 350 pF. The rising and falling edges should be smooth
transitional (monotonic) when driving the cable to avoid excessive EMI.
FALL TIME
90%
RISE TIME
90%
C
L
DIFFERENTIAL
DATA LINES
10%
10%
t
t
F
C
R
L
LOW SPEED: 75 ns at C = 50 pF, 300 ns at C = 350 pF
L
L
Figure 10-15. Data Signal Rise and Fall Time
10.4.4 USB Control Logic
The USB control logic manages data movement between the CPU and the
transceiver. The control logic handles both transmit and receive operations on the
USB. It contains the logic used to manipulate the transceiver and the endpoint
registers. The logic contains byte count buffers for transmit operations that load
the active transmit endpoints byte count and use this to determine the number of
bytes to transfer. This same buffer is used for receive transactions to count the
number of bytes received and, upon the end of the transaction, transfer that
number to the receive endpoints byte count register.
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When transmitting, the control logic handles parallel to serial conversion, CRC
generation, NRZI encoding, and bit stuffing.
When Receiving, the control logic handles Sync detection, packet identification,
end of packet detection, bit (un)stuffing, NRZI decoding, CRC validation, and
serial to parallel conversion. Errors detected by the control logic include bad CRC,
time-out while waiting for EOP, and bit stuffing violations.
10.4.4.1 Data Encoding/Decoding
The USB employs NRZI data encoding when transmitting packets. In NRZI
encoding, a 1 is represented by no change in level and a 0 is represented by a
change in level. Figure 10-16 shows a data stream and the NRZI equivalent and
Figure 10-17 is a flow diagram for NRZI. The high level represents the J state on
the data lines in this and subsequent figures showing NRZI encoding. A string of
zeros causes the NRZI data to toggle each bit time. A string of ones causes long
periods with no transitions in the data.
0
1
1
0
1
0
1
0
0
0
1
0
0
1
1
0
DATA
NRZI
IDLE
IDLE
Figure 10-16. NRZI Data Encoding
POWER UP
NO PACKET
TRANSMISSION
IDLE
BEGIN PACKET
TRANSMISSION
FETCH THE
DATA BIT
IS DATA
BIT = 0?
YES
NO
NO DATA
TRANSITION
TRANSITION
DATA
IS PACKAGE
TRANSFER
DONE?
NO
YES
Figure 10-17. Flow Diagram for NRZI
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10.4.4.2 Bit Stuffing
In order to ensure adequate signal transitions, bit stuffing is employed by the
transmitting device when sending a packet on the USB (see Figure 10-18 and
Figure 10-19). A 0 is inserted after every six consecutive 1’s in the data stream
before the data is NRZI encoded to force a transition in the NRZI data stream.
This gives the receiver logic a data transition at least once every seven bit times to
guarantee the data and clock lock. The receiver must decode the NRZI data,
recognize the stuffed bits, and discard them. Bit stuffing is enabled beginning with
the Sync Pattern and throughout the entire transmission. The data “one” that ends
the Sync Pattern is counted as the first one in a sequence. Bit stuffing is always
enforced, without exception. If required by the bit stuffing rules, a zero bit will be
inserted even if it is the last bit before the end-of-packet (EOP) signal.
RAW
DATA
SYNC PATTERN
SYNC PATTERN
PACKET DATA
PACKET DATA
STUFFED BIT
BIT
STUFFED
DATA
SIX ONES
NRZI
ENCODED
DATA
IDLE
PACKET DATA
SYNC PATTERN
Figure 10-18. Bit Stuffing
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POWER UP
NO PACKET
TRANSMISSION
IDLE
BEGIN PACKET
TRANSMISSION
RESET BIT
COUNTER TO 0
GET NEXT
BIT
= 0
= 1
BIT VALUE?
INCREMENT
THE COUNTER
NO
YES
COUNTER = 6?
INSERT A
ZERO BIT
RESET THE BIT
COUNTER TO 0
IS PACKAGE
TRANSFER
DONE?
NO
YES
Figure 10-19. Flow Diagram for Bit Stuffing
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10.5 I/O REGISTER DESCRIPTION
The USB Endpoint registers are comprised of a set of control/status registers and
twenty-four data registers that provide storage for the buffering of data between
the USB and the CPU. These registers are shown in Table 10-2.
Table 10-2. Register Summary
Register Name
Bit 7
6
5
4
3
2
1
Bit 0 Addr
0
TX1ST
0
USB Control Register 2
(UCR2)
ENABLE2 ENABLE1 STALL2 STALL1 $0037
TX1STR
USB Address Register
(UADDR)
USBEN
TXD0F
UADD6 UADD5
RXD0F RSTF
UADD4
UADD3
UADD2
UADD1 UADD0 $0038
0
0
USB Interrupt Register 0
(UIR0)
SUSPND TXD0IE RXD0IE
0
$0039
TXD0FR RXD0FR
TXD1F
T0SEQ
EOPF RESUMF
0
0
USB Interrupt Register 1
(UIR1)
TXD1IE
EOPIE
$003A
RESUMFR
RX0E
TXD1FR EOPFR
USB Control Register 0
(UCR0)
STALL0
TX0E
TP0SIZ3 TP0SIZ2 TP0SIZ1 TP0SIZ0 $003B
USB Control Register 1
(UCR1)
T1SEQ ENDADD TX1E
RSEQ SETUP
FRESUM TP1SIZ3 TP1SIZ2 TP1SIZ1 TP1SIZ0 $003C
0
0
RPSIZ3 RPSIZ2 RPSIZ1 RPSIZ0
USB Status Register
(USR)
$003D
UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0
UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
USB Endpoint 0 Data
Register 0 (UE0D0)
$0020
↓
↓
UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0
UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
USB Endpoint 0 Data
Register 7 (UE0D7)
$0027
USB Endpoint 1/2 Data
Register 0 (UE1D0)
$0028
↓
UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
↓
USB Endpoint 1/2 Data
Register 7 (UE1D7)
$002F
UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
= Unimplemented
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10.5.1 USB Address Register (UADDR)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
UADDR
$0038
R
USBEN UADD6 UADD5 UADD4 UADD3 UADD2 UADD1 UADD0
W
0
0
0
0
0
0
0
0
reset:
Figure 10-20. USB Address Register (UADDR)
USBEN — USB Module Enable
This read/write bit enables and disables the USB module and the USB pins.
When USBEN is clear, the USB module will not respond to any tokens. Reset
clears this bit.
1 = USB function enabled.
0 = USB function disabled.
UADD6-UADD0 — USB Function Address
These bits specify the USB address of the device. Reset clears these bits.
10.5.2 USB Interrupt Register 0 (UIR0)
BIT 7
BIT 6
BIT 5
RSTF
BIT 4
BIT 3
BIT 2
RXD0IE
0
BIT 1
0
BIT 0
0
UIR0
R
TXD0F
RXD0F
SUSPND TXD0IE
$0039
W
TXD0FR RXD0FR
0
0
0
0
0
0
0
reset:
= Unimplemented
Figure 10-21. USB Interrupt Register 0 (UIR0)
TXD0F — Endpoint 0 Data Transmit Flag
This read only bit is set after the data stored in Endpoint 0 transmit buffers has
been sent and an ACK handshake packet from the host is received. Once the
next set of data is ready in the transmit buffers, software must clear this flag by
writing a logic 1 to the TXD0FR bit. To enable the next data packet transmis-
sion, TX0E must also be set. If TXD0F bit is not cleared, a NAK handshake will
be returned in the next IN transaction.
Reset clears this bit. Writing a logic 0 to TXD0F has no effect.
1 = Transmit on Endpoint 0 has occurred.
0 = Transmit on Endpoint 0 has not occurred.
RXD0F — Endpoint 0 Data Receive Flag
This read only bit is set after the USB module has received a data packet and
responded with an ACK handshake packet. Software must clear this flag by
writing a logic 1 to the RXD0FR bit after all of the received data has been read.
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Software must also set RX0E bit to one to enable the next data packet recep-
tion. If RXD0F bit is not cleared, a NAK handshake will be returned in the next
OUT transaction.
Reset clears this bit. Writing a logic 0 to RXD0F has no effect.
1 = Receive on Endpoint 0 has occurred.
0 = Receive on Endpoint 0 has not occurred.
RSTF — USB Reset Flag
This read only bit is set when a valid reset signal state is detected on the D+
and D– lines. This reset detection will also generate an internal reset signal to
reset the CPU and other peripherals including the USB module. This bit is
cleared by writing a logic 1 to the RSTFR bit in the UCR2 register. This bit is
cleared by a POR reset.
SUSPND — USB Suspend Flag
To save power, this read/write bit should be set by the software if a 3ms con-
stant idle state is detected on USB bus. Setting this bit stops the clock to the
USB and causes the USB module to enter Suspend mode. Unnecessary ana-
log circuitry will be powered down. Software must clear this bit after the
Resume flag (RESUMF) is set while this Resume interrupt flag is serviced.
TXD0IE — Endpoint 0 Transmit Interrupt Enable
This read/write bit enables the Transmit Endpoint 0 to generate a USB interrupt
when the TXD0F bit becomes set.
1 = USB interrupts enabled for Transmit Endpoint 0.
0 = USB interrupts disabled for Transmit Endpoint 0.
RXD0IE — Endpoint 0 Receive Interrupt Enable
This read/write bit enables the Transmit Endpoint 0 to generate a USB interrupt
when the RXD0F bit becomes set.
1 = USB interrupts enabled for Receive Endpoint 0.
0 = USB interrupts disabled for Receive Endpoint 0.
TXD0FR — Endpoint 0 Transmit Flag Reset
Writing a logic 1 to this write only bit will clear the TXD0F bit if it is set.Writing a
logic 0 to TXD0FR has no effect. Reset clears this bit.
RXD0FR — Endpoint 0 Receive Flag Reset
Writing a logic 1 to this write only bit will clear the RXD0F bit if it is set.Writing a
logic 0 to RXD0FR has no effect. Reset clears this bit.
MOTOROLA
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10.5.3 USB Interrupt Register 1 (UIR1)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
TXD1IE
0
BIT 2
EOPIE
0
BIT 1
BIT 0
UIR1
R
TXD1F
EOPF
RESUMF
0
0
TXD1FR
0
0
EOPFR
0
$003A
W
RESUMFR
0
0
0
0
reset:
= Unimplemented
Figure 10-22. USB Interrupt Register 1(UIR1)
TXD1F — Endpoint 1/Endpoint 2 Data Transmit Flag
This read only bit is shared by Endpoint 1 and Endpoint 2. It is set after the data
stored in the shared Endpoint 1/Endpoint 2 transmit buffer has been sent and
an ACK handshake packet from the host is received. Once the next set of data
is ready in the transmit buffers, software must clear this flag by writing a logic 1
to the TXD1FR bit. To enable the next data packet transmission, TX1E must
also be set. If TXD1F bit is not cleared, a NAK handshake will be returned in
the next IN transaction.
Reset clears this bit. Writing a logic 0 to TXD1F has no effect.
1 = Transmit on Endpoint 1 or Endpoint 2 has occurred.
0 = Transmit on Endpoint 1 or Endpoint 2 has not occurred.
EOPF — End of Packet Detect Flag
This read only bit is set when a valid End-of-Packet sequence is detected on
the D+ and D– lines. Software must clear this flag by writing a logic 1 to the
EOPFR bit.
Reset clears this bit. Writing a logic 0 to EOPF has no effect.
1 = End-of-Packet sequence has been detected.
0 = End-of-Packet sequence has not been detected.
RESUMF — Resume Flag
This read only bit is set when USB bus activity is detected while the SUSPND
bit is set. Software must clear this flag by writing a logic 1 to the RESUMFR bit.
Reset clears this bit. Writing a logic 0 to RESUMF has no effect.
1 = USB bus activity has been detected.
0 = No USB bus activity has been detected.
RESUMFR — Resume Flag Reset
Writing a logic 1 to this write only bit will clear the RESUMF bit if it is set. Writ-
ing a logic 0 to RESUMFR has no effect. Reset clears this bit.
TXD1IE — Endpoint 1/Endpoint 2 Transmit Interrupt Enable
This read/write bit enables the USB to generate an interrupt when the shared
Transmit Endpoint 1/Endpoint 2 interrupt flag (TXD1F) bit becomes set. Reset
clears this bit.
1 = USB interrupts enabled for Transmit Endpoints 1 and 2.
0 = USB interrupts disabled for Transmit Endpoints 1 and 2.
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EOPIE — End of Packet Detect Interrupt Enable
This read/write bit enables the USB to generate an interrupt when the EOPF bit
becomes set. Reset clears this bit.
1 = USB interrupts enabled for Transmit Endpoints 1 and 2.
0 = USB interrupts disabled for Transmit Endpoint 1 and 2.
TXD1FR — Endpoint 1/Endpoint 2 Transmit Flag Reset
Writing a logic 1 to this write only bit will clear the TXD1F bit if it is set. Writing a
logic 0 to TXD1FR has no effect. Reset clears this bit.
EOPFR — End of Packet Flag Reset
Writing a logic 1 to this write only bit will clear the EOPF bit if it is set. Writing a
logic 0 to the EOPFR has no effect. Reset clears this bit.
10.5.4 USB Control Register 0 (UCR0)
BIT 7
BIT 6
BIT 5
TX0E
0
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
UCR0
$003B
R
T0SEQ STALL0
RX0E TP0SIZ3 TP0SIZ2 TP0SIZ1 TP0SIZ0
W
0
0
0
0
0
0
0
reset:
Figure 10-23. USB Control Register 0 (UCR0)
T0SEQ — Endpoint 0 Transmit Sequence Bit
This read/write bit determines which type of data packet (DATA0 or DATA1) will
be sent during the next IN transaction. Toggling of this bit must be controlled by
software. Reset clears this bit.
1 = DATA1 Token active for next Endpoint 0 transmit.
0 = DATA0 Token active for next Endpoint 0 transmit.
STALL0 — Endpoint 0 Force Stall Bit
This read/write bit causes Endpoint 0 to return a STALL handshake when
polled by either an IN or OUT token by the USB Host Controller. The USB hard-
ware clears this bit when a SETUP token is received. Reset clears this bit.
1 = Send STALL handshake.
0 = Default.
TX0E — Endpoint 0 Transmit Enable
This read/write bit enables a transmit to occur when the USB Host controller
sends an IN token to Endpoint 0. Software should set this bit when data is
ready to be transmitted. It must be cleared by software when no more Endpoint
0 data needs to be transmitted.
If this bit is 0 or the TXD0F is set, the USB will respond with a NAK handshake
to any Endpoint 0 IN tokens. Reset clears this bit.
1 = Data is ready to be sent.
0 = Data is not ready. Respond with NAK.
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RX0E — Endpoint 0 Receive Enable
This read/write bit enables a receive to occur when the USB Host controller
sends an OUT token to Endpoint 0. Software should set this bit when data is
ready to be received. It must be cleared by software when data cannot be
received.
If this bit is 0 or the RXD0F is set, the USB will respond with a NAK handshake
to any Endpoint 0 OUT tokens. Reset clears this bit.
1 = Data is ready to be received.
0 = Not ready for data. Respond with NAK.
TP0SIZ3-TP0SIZ0 — Endpoint 0 Transmit Data Packet Size
These read/write bits store the number of transmit data bytes for the next IN
token request for Endpoint 0. These bits are cleared by reset.
10.5.5 USB Control Register 1 (UCR1)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
UCR1
$003C
R
T1SEQ ENDADD TX1E FRESUM TP1SZ3 TP1SIZ2 TP1SIZ1 TP1SIZ0
W
0
0
0
0
0
0
0
0
reset:
Figure 10-24. USB Control Register 1 (UCR1)
T1SEQ — Endpoint1/Endpoint 2 Transmit Sequence Bit
This read/write bit determines which type of data packet (DATA0 or DATA1) will
be sent during the next IN transaction directed to Endpoint 1 or Endpoint 2.
Toggling of this bit must be controlled by software. Reset clears this bit.
1 = DATA1 Token active for next Endpoint 1/Endpoint 2 transmit.
0 = DATA0 Token active for next Endpoint 1/Endpoint 2 transmit.
ENDADD — Endpoint Address Select
This read/write bit specifies whether the data inside the registers
UE1D0-UE1D7 are used for Endpoint 1 or Endpoint 2. If all the conditions for a
successful Endpoint 2 USB response to a hosts IN token are satisfied
(TXD1F=0, TX1E=1, STALL2=0, and ENABLE2=1) except that the ENDADD bit
is configured for Endpoint 1, the USB responds with a NAK handshake packet.
1 = The data buffers are used for Endpoint 2.
0 = The data buffers are used for Endpoint 1.
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TX1E — Endpoint 1/Endpoint 2 Transmit Enable
This read/write bit enables a transmit to occur when the USB Host controller
sends an IN token to Endpoint 1 or Endpoint 2. The appropriate endpoint
enable bit, ENABLE1 or ENABLE2 bit in the UCR2 register, should also be set.
Software should set the TX1E bit when data is ready to be transmitted. It must
be cleared by software when no more data needs to be transmitted.
If this bit is 0 or the TXD1F is set, the USB will respond with a NAK handshake
to any Endpoint 1 or Endpoint 2 directed IN tokens. Reset clears this bit.
1 = Data is ready to be sent.
0 = Data is not ready. Respond with NAK.
FRESUM — Force Resume
This read/write bit forces a resume state (“K” or non-idle state) onto the USB
data lines to initiate a remote wake-up. Software should control the timing of the
forced resume to be between 10ms and 15 ms. Setting this bit will not cause
the RESUMF bit to set.
1 = Force data lines to “K” state.
0 = Default.
TP1SIZ3-TP1SIZ0 — Endpoint 1/Endpoint 2 Transmit Data Packet Size
These read/write bits store the number of transmit data bytes for the next IN
token request for Endpoint 1 or Endpoint 2. These bits are cleared by reset.
10.5.6 USB Control Register 2 (UCR2)
BIT 7
BIT 6
BIT 5
BIT 4
0
BIT 3
BIT 2
BIT 1
BIT 0
UCR2
$0037
R
0
TX1ST
ENABLE2 ENABLE1
STALL2 STALL1
W
TX1STR
-
-
0
-
0
0
0
0
reset:
= Unimplemented
Figure 10-25. USB Control Register 2 (UCR2)
TX1STR — Clear Transmit First Flag
Writing a logic 1 to this write-only bit will clear the TX1ST bit if it is set. Writing a
logic 0 to the TX1STR has no effect. Reset clears this bit.
TX1ST — Transmit First Flag
This read-only bit is set if the Endpoint 0 Data Transmit Flag (TXD0F) is set
when the USB control logic is setting the Endpoint 0 Data Receive Flag
(RXD0F). That is, this bit will be set if an Endpoint 0 Transmit Flag is still set at
the end of an Endpoint 0 reception. This bit lets the firmware know that the
Endpoint 0 transmission happened before the Endpoint 0 reception. Reset
clears this bit.
1 = IN transaction occurred before SETUP/OUT.
0 = IN transaction occurred after SETUP/OUT.
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ENABLE2 — Endpoint 2 Enable
This read/write bit enables Endpoint 2 and allows the USB to respond to IN
packets addressed to Endpoint 2. Reset clears this bit.
1 = Endpoint 2 is enabled and can respond to an IN token.
0 = Endpoint 2 is disabled.
ENABLE1 — Endpoint 1 Enable
This read/write bit enables Endpoint 1 and allows the USB to respond to IN
packets addressed to Endpoint 1. Reset clears this bit.
1 = Endpoint 1 is enabled and can respond to an IN token.
0 = Endpoint 1 is disabled.
STALL2 — Endpoint 2 Force Stall Bit
This read/write bit causes Endpoint 2 to return a STALL handshake when
polled by either an IN or OUT token by the USB Host Controller. Reset clears
this bit.
1 = Send STALL handshake.
0 = Default.
STALL1 — Endpoint 1 Force Stall Bit
This read/write bit causes Endpoint 1 to return a STALL handshake when
polled by either an IN or OUT token by the USB Host Controller. Reset clears
this bit.
1 = Send STALL handshake.
0 = Default.
10.5.7 USB Status Register (USR)
BIT 7
BIT 6
BIT 5
0
BIT 4
0
BIT 3
RPSIZ3
U
BIT 2
RPSIZ2
U
BIT 1
BIT 0
USR
R
RSEQ
SETUP
RPSIZ1 RPSIZ0
$003D
W
U
U
U
U
U
U
reset:
= Unimplemented
Figure 10-26. USB Status Register (USR)
RSEQ — Endpoint 0 Receive Sequence Bit
This read only bit indicates the type of data packet last received for Endpoint 0
(DATA0 or DATA1).
1 = DATA1 Token received in last Endpoint 0 receive.
0 = DATA0 Token received in last Endpoint 0 receive.
SETUP — SETUP Token Detect Bit
This read only bit indicates that a valid SETUP token has been received.
1 = Last token received for Endpoint 0 was a SETUP token.
0 = Last token received for Endpoint 0 was not a SETUP token.
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RPSIZ3-RPSIZ0 — Endpoint 0 Receive Data Packet Size
These read only bits store the number of data bytes received for the last OUT
or SETUP transaction for Endpoint 0. These bits are not affected by reset.
10.5.8 USB Endpoint 0 Data Registers (UE0D0-UE0D7)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
UE0D0
$0020
R
UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0
UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
W
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
to
UE0D7
$0027
R
UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0
UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0
W
X
X
X
X
X
X
X
X
reset:
Figure 10-27. USB Endpoint 0 Data Register (UE0D0-UE0D7)
UE0RD7 - UE0RD0 — Endpoint 0 Receive Data Buffer
These read only bits are serially loaded with OUT token or SETUP token data
received over the USB’s D+ and D– pins.
UE0TD7 - UE0TD0 — Endpoint 0 Transmit Data Buffer
These write only buffers are loaded by software with data to be sent on the
USB bus on the next IN token directed at Endpoint 0.
10.5.9 USB Endpoint 1/Endpoint 2 Data Registers (UE1D0-UE1D7)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
UE1D0
$0028
R
W
UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
to
UE1D7
$002F
R
W
UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0
X
X
X
X
X
X
X
X
reset:
Figure 10-28. USB Endpoint 1/Endpoint2 Data Registers (UE1D0-UE1D7)
UE1TD7 - UE1TD0 — Endpoint 1/ Endpoint 2 Transmit Data Buffer
These write only buffers are loaded by software with data to be sent on the
USB bus on the next IN token directed at Endpoint 1 or Endpoint 2. These buff-
ers are shared by Endpoints 1 and 2 and depend on proper configuration of the
ENDADD bit.
10.6 USB INTERRUPTS
The USB module is capable of generating interrupts and causing the CPU to
execute the USB interrupt service routine. There are three types of USB
interrupts:
MOTOROLA
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•
•
•
End of Transaction interrupts signify a completed transaction (receive or
transmit)
Resume interrupts signify that the USB bus is reactivated after having
been suspended
End of Packet interrupts signify that a low speed end of packet signal
was detected
All USB interrupts share the same interrupt vector. Firmware is responsible for
determining which interrupt is active.
10.6.1 USB End of Transaction Interrupt
There are three possible end of transaction interrupts: Endpoint 0 Receive,
Endpoint 0 Transmit, and a shared Endpoint 1 or Endpoint 2 Transmit. End of
transaction interrupts occur as detailed in the following sections.
10.6.1.1 Receive Control Endpoint 0
For a Control OUT transaction directed at Endpoint 0, the USB module will
generate an interrupt by setting the RXD0F flag in the UIR0 register. The
conditions necessary for the interrupt to occur are shown in the flowchart of
Figure 10-29.
SETUP transactions cannot be stalled by the USB function. A SETUP received by
a control endpoint will clear the STALL0 bit if it is set. The conditions for receiving
a SETUP interrupt are shown in Figure 10-30.
10.6.1.2 Transmit Control Endpoint 0
For a Control IN transaction directed at Endpoint 0, the USB module will generate
an interrupt by setting the TXD0F flag in the UIR0 register. The conditions
necessary for the interrupt to occur are shown in the flowchart of Figure 10-31.
10.6.1.3 Transmit Endpoint 1 and Transmit Endpoint 2
Transmit Endpoints 1 and 2 share their interrupt flag. For an IN transaction
directed at Endpoint 1 or 2, the USB module will generate an interrupt by setting
the TXD1F flag in the UIR1 register. The conditions necessary for the interrupt to
occur are shown in the flowchart of Figure 10-32.
10.6.2 Resume Interrupt
The USB module will generate a USB interrupt if low speed bus activity is
detected after entering the suspend state. A transition of the USB data lines to the
non-idle state (“K” state) while in the suspend mode will set the RESUMF flag in
the UIR1 register. There is no interrupt enable bit for this interrupt source and an
interrupt will be executed if the I bit in the CCR is cleared. A resume interrupt can
only occur while the MC68HC05JB3 is in the suspend mode.
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10.6.3 End of Packet Interrupt
The USB module can generate a USB interrupt upon detection of an end of
packet signal (a single ended 0) for low speed devices. Upon detection of an SE0
sequence, the USB module sets the EOPF bit and will generate an interrupt if the
EOPIE bit in the UIR1 register is set.
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Valid OUT token
received for Endpoint 0
Y
Time-out
No Response
from USB function
N
Valid DATA token
received for Endpoint 0?
Y
N
N
N
No Response
from USB function
Endpoint 0 Receive Enabled?
(USBEN = 1)
Y
Endpoint 0 Receive Not Stalled?
(STALL0 = 0)
Send STALL
Handshake
Y
Send NAK
Handshake
Endpoint 0 Receive Ready to Receive?
(RX0E = 1) && (RXD0F = 0)
Y
Accept Data
Set/clear RSEQ bit
N
Ignore transaction
No response from
USB function
Error free DATA packet?
Y
Set RXD0F to 1
Receive Control Endpoint
Interrupt Enabled?
(RXD0IE = 1)
N
Y
Valid transaction
Interrupt generated
No Interrupt
Figure 10-29. OUT Token Data Flow for Receive Endpoint 0
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Valid SETUP token
received for Endpoint 0
Y
N
Endpoint 0 Receive Enabled?
(USBEN = 1)
No Response
from USB function
Y
N
No Response
from USB function
Endpoint 0 Receive Ready to Receive?
(RX0E = 1) && (RXD0F = 0)
Y
N
STALL0 = 0?
Clear STALL0 bit
Accept Data
set/clear RSEQ bit
Set SETUP to 1
Y
Ignore transaction
No response from
USB function
N
Error free DATA packet?
Y
Set RXD0F to 1
Y
Receive Control Endpoint
Interrupt Enabled?
(RXD0IE = 1)
N
Y
No Interrupt
Valid transaction
Interrupt generated
Figure 10-30. SETUP Token Data Flow for Receive Endpoint 0
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Valid IN token
received for Endpoint 0
Y
N
Transmit Endpoint Enabled?
(USBEN = 1)
No Response
from USB function
Y
N
Send STALL
Handshake
Transmit Endpoint not Stalled by firmware?
(STALL0 = 0)
Y
N
Transmit Endpoint ready to Transfer?
(TX0E = 1) && (TXD0F = 0)
Send NAK
Handshake
Y
Send DATA
Data PID set by T0SEQ
N
No Response
ACK received and no
Time-out condition occur?
from USB function
Y
Set TXD0F to 1
Transmit Endpoint
Interrupt Enabled?
(TXD0IE = 1)
N
No Interrupt
Valid transaction
Interrupt generated
Figure 10-31. IN Token Data Flow for Transmit Endpoint 0
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Valid IN token
received for Endpoints 1 or 2
N
Transmit Endpoint Enabled?
(USBEN = 1)
No Response
from USB function
Y
N
Send STALL
Handshake
Transmit Endpoint not Stalled by firmware?
(STALL1 & ENDP1) + (STALL2 & ENDP2)
Y
Transmit Endpoint ready to Transfer?
(TX1E = 1) && (TXD1F = 0) &
((ENDP2 & ENDADD) + (ENDP1 & ENDADD))
N
Send NAK
Handshake
Y
Send DATA
Data PID set by T1SEQ
N
No Response
ACK received and no
from USB function
Time-out condition occurs?
Y
Set TXD1F to 1
Transmit Endpoint
Interrupt Enabled?
(TXD1IE = 1)
No Interrupt
Valid transaction
Interrupt generated
Note:
ENDP1 is Endpoint 1 directed traffic
ENDP2 is Endpoint 2 directed traffic
Figure 10-32. IN Token Data Flow for Transmit Endpoint 1/2
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SECTION 11
OPTICAL INTERFACE
The MC68HC05JB3 MCU has four pairs of Optical Interfaces, configured through
Port-A. This port has built-in optical coupler interface devices, which can be
directly connected to IR displacement encoders, such as in optical mouse and
optical joystick applications.
11.1 OVERVIEW
In practical designs, each axis requires two optical couplers to detect the displace-
ment. Hence, the eight optical interfaces on port-A are enabled in pairs, with each
pair enabled by a bit in the Optical Interface Enable Register ($0E). Figure 11-1
shows a one pair of the optical interface. Table 11-1 shows the port-A configura-
tion for the four pairs.
Table 11-1. Port-A Optical Interface Pairs
Optical Coupler
Pair 1
Port pin used
PA0 and PA1
PA2 and PA3
PA4 and PA5
PA6 and PA7
Enable bit in OIER
OIE0
OIE1
OIE2
OIE3
Pair 2
Pair 3
Pair 4
For optimal performance, the reference voltage used in the optical interface
module is selectable from eight predefined values, as shown in Figure 11-2. and
Table 11-2. This allows the optical interface to be easily configured by software to
match the IR displacement encoders. The reference voltage is selected using the
bits VREF0-VREF2 in the OIER.
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Output
Buffer
0
PAx
Port Logic
PAx
MUX
Optical
Interface
1
select
OPTI_EN
VREF
OIEn
select
1
Optical
Interface
PA(x+1)
Port Logic
PA(x+1)
MUX
0
Output
Buffer
Figure 11-1. A pair of Optical Coupler Interface
VREF2
VREF1
VREF0
VREF
Voltage Selector
enable
OIE2
OIE3
OIE1
OIE0
enable
Voltage Divider
OPTI_EN
–
+
To MUX
PAx
Dynamic
Input
Impedance
OPTICAL
INTERFACE
Figure 11-2. Optical Interface Comparator
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11.2 OPTICAL INTERFACE ENABLE REGISTER
The OIER register controls the operation of the optical interface devices on
Port-A. This register is located at address $0E.
BIT 7
TCMPE
0
BIT 6
VREF2
0
BIT 5
VREF1
0
BIT 4
VREF0
0
BIT 3
OIE3
0
BIT 2
OIE2
0
BIT 1
OIE1
0
BIT 0
OIE0
0
OIER
R
$000E
W
reset:
Figure 11-3. Optical Interface Enable Register (TCSR)
OIE0 — Optical Interface pair 0 Enable
1 = PA0 and PA1 optical interface are enabled.
0 = PA0 and PA1 optical interface are disabled.
OIE1 — Optical Interface pair 1 Enable
1 = PA2 and PA3 optical interface are enabled.
0 = PA2 and PA3 optical interface are disabled.
OIE2 — Optical Interface pair 2 Enable
1 = PA4 and PA5 optical interface are enabled.
0 = PA4 and PA5 optical interface are disabled.
OIE3 — Optical Interface pair 3 Enable
1 = PA6 and PA7 optical interface are enabled.
0 = PA6 and PA7 optical interface are disabled.
VREF[0:2] — Reference Voltage Selection
These 3 bits are used to select the optical interface reference voltage.
Table 11-2. Optical Interface Reference Voltage Selection
VREF2
VREF1
VREF0
Reference Voltage (mV), V = 5V
DD
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
300
430
560
690
820
950
1080
1210
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TCMPE — Timer Input Capture Comparator Enable
This bit is used to enable the comparator in the 16-bit timer input capture
circuit. Please refer to 16-BIT TIMER section.
1 = Timer input capture comparator is selected.
0 = Timer input capture comparator schmitt trigger is selected.
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SECTION 12
INSTRUCTION SET
This section describes the addressing modes and instruction types.
12.1 ADDRESSING MODES
The CPU uses eight addressing modes for flexibility in accessing data. The
addressing modes define the manner in which the CPU finds the data required to
execute an instruction. The eight addressing modes are the following:
•
•
•
•
•
•
•
•
Inherent
Immediate
Direct
Extended
Indexed, No Offset
Indexed, 8-Bit Offset
Indexed, 16-Bit Offset
Relative
12.1.1 Inherent
Inherent instructions are those that have no operand, such as return from interrupt
(RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU
registers, such as set carry flag (SEC) and increment accumulator (INCA).
Inherent instructions require no memory address and are one byte long.
12.1.2 Immediate
Immediate instructions are those that contain a value to be used in an operation
with the value in the accumulator or index register. Immediate instructions require
no memory address and are two bytes long. The opcode is the first byte, and the
immediate data value is the second byte.
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12.1.3 Direct
Direct instructions can access any of the first 256 memory addresses with two
bytes. The first byte is the opcode, and the second is the low byte of the operand
address. In direct addressing, the CPU automatically uses $00 as the high byte of
the operand address. BRSET and BRCLR are three-byte instructions that use
direct addressing to access the operand and relative addressing to specify a
branch destination.
12.1.4 Extended
Extended instructions use only three bytes to access any address in memory. The
first byte is the opcode; the second and third bytes are the high and low bytes of
the operand address.
When using the Motorola assembler, the programmer does not need to specify
whether an instruction is direct or extended. The assembler automatically selects
the shortest form of the instruction.
12.1.5 Indexed, No Offset
Indexed instructions with no offset are one-byte instructions that can access data
with variable addresses within the first 256 memory locations. The index register
contains the low byte of the conditional address of the operand. The CPU
automatically uses $00 as the high byte, so these instructions can address
locations $0000–$00FF.
Indexed, no offset instructions are often used to move a pointer through a table or
to hold the address of a frequently used RAM or I/O location.
12.1.6 Indexed, 8-Bit Offset
Indexed, 8-bit offset instructions are two-byte instructions that can access data
with variable addresses within the first 511 memory locations. The CPU adds the
unsigned byte in the index register to the unsigned byte following the opcode. The
sum is the conditional address of the operand. These instructions can access
locations $0000–$01FE.
Indexed 8-bit offset instructions are useful for selecting the kth element in an
n-element table. The table can begin anywhere within the first 256 memory
locations and could extend as far as location 510 ($01FE). The k value is typically
in the index register, and the address of the beginning of the table is in the byte
following the opcode.
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12.1.7 Indexed, 16-Bit Offset
Indexed, 16-bit offset instructions are three-byte instructions that can access data
with variable addresses at any location in memory. The CPU adds the unsigned
byte in the index register to the two unsigned bytes following the opcode. The sum
is the conditional address of the operand. The first byte after the opcode is the
high byte of the 16-bit offset; the second byte is the low byte of the offset. These
instructions can address any location in memory.
Indexed, 16-bit offset instructions are useful for selecting the kth element in an
n-element table anywhere in memory.
As with direct and extended addressing, the Motorola assembler determines the
shortest form of indexed addressing.
12.1.8 Relative
Relative addressing is only for branch instructions. If the branch condition is true,
the CPU finds the conditional branch destination by adding the signed byte
following the opcode to the contents of the program counter. If the branch
condition is not true, the CPU goes to the next instruction. The offset is a signed,
two’s complement byte that gives a branching range of –128 to +127 bytes from
the address of the next location after the branch instruction.
When using the Motorola assembler, the programmer does not need to calculate
the offset, because the assembler determines the proper offset and verifies that it
is within the span of the branch.
12.1.9 Instruction Types
The MCU instructions fall into the following five categories:
•
•
•
•
•
Register/Memory Instructions
Read-Modify-Write Instructions
Jump/Branch Instructions
Bit Manipulation Instructions
Control Instructions
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12.1.10 Register/Memory Instructions
Most of these instructions use two operands. One operand is in either the
accumulator or the index register. The CPU finds the other operand in memory.
Table 12-1 lists the register/memory instructions.
Table 12-1. Register/Memory Instructions
Instruction
Add Memory Byte and Carry Bit to Accumulator
Add Memory Byte to Accumulator
AND Memory Byte with Accumulator
Bit Test Accumulator
Mnemonic
ADC
ADD
AND
BIT
Compare Accumulator
CMP
CPX
EOR
LDA
Compare Index Register with Memory Byte
EXCLUSIVE OR Accumulator with Memory Byte
Load Accumulator with Memory Byte
Load Index Register with Memory Byte
Multiply
LDX
MUL
ORA
SBC
STA
OR Accumulator with Memory Byte
Subtract Memory Byte and Carry Bit from Accumulator
Store Accumulator in Memory
Store Index Register in Memory
STX
Subtract Memory Byte from Accumulator
SUB
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12.1.11 Read-Modify-Write Instructions
These instructions read a memory location or a register, modify its contents, and
write the modified value back to the memory location or to the register.The test for
negative or zero instruction (TST) is an exception to the read-modify-write
sequence because it does not write a replacement value. Table 12-2 lists the
read-modify-write instructions.
Table 12-2. Read-Modify-Write Instructions
Instruction
Mnemonic
ASL
Arithmetic Shift Left
Arithmetic Shift Right
Clear Bit in Memory
Set Bit in Memory
ASR
BCLR
BSET
CLR
Clear
Complement (One’s Complement)
Decrement
COM
DEC
Increment
INC
Logical Shift Left
LSL
Logical Shift Right
LSR
Negate (Two’s Complement)
Rotate Left through Carry Bit
Rotate Right through Carry Bit
Test for Negative or Zero
NEG
ROL
ROR
TST
12.1.12 Jump/Branch Instructions
Jump instructions allow the CPU to interrupt the normal sequence of the program
counter. The unconditional jump instruction (JMP) and the jump to subroutine
instruction (JSR) have no register operand. Branch instructions allow the CPU to
interrupt the normal sequence of the program counter when a test condition is
met. If the test condition is not met, the branch is not performed. All branch
instructions use relative addressing.
Bit test and branch instructions cause a branch based on the state of any
readable bit in the first 256 memory locations. These three-byte instructions use a
combination of direct addressing and relative addressing. The direct address of
the byte to be tested is in the byte following the opcode. The third byte is the
signed offset byte. The CPU finds the conditional branch destination by adding the
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third byte to the program counter if the specified bit tests true. The bit to be tested
and its condition (set or clear) is part of the opcode. The span of branching is from
–128 to +127 from the address of the next location after the branch instruction.
The CPU also transfers the tested bit to the carry/borrow bit of the condition code
register. Table 12-3 lists the jump and branch instructions.
Table 12-3. Jump and Branch Instructions
Instruction
Branch if Carry Bit Clear
Branch if Carry Bit Set
Branch if Equal
Mnemonic
BCC
BCS
BEQ
BHCC
BHCS
BHI
Branch if Half-Carry Bit Clear
Branch if Half-Carry Bit Set
Branch if Higher
Branch if Higher or Same
Branch if IRQ Pin High
Branch if IRQ Pin Low
Branch if Lower
BHS
BIH
BIL
BLO
Branch if Lower or Same
Branch if Interrupt Mask Clear
Branch if Minus
BLS
BMC
BMI
Branch if Interrupt Mask Set
Branch if Not Equal
Branch if Plus
BMS
BNE
BPL
Branch Always
BRA
Branch if Bit Clear
BRCLR
BRN
BRSET
BSR
Branch Never
Branch if Bit Set
Branch to Subroutine
Unconditional Jump
Jump to Subroutine
JMP
JSR
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12.1.13 Bit Manipulation Instructions
The CPU can set or clear any writable bit in the first 256 bytes of memory. Port
registers, port data direction registers, timer registers, and on-chip RAM locations
are in the first 256 bytes of memory. The CPU can also test and branch based on
the state of any bit in any of the first 256 memory locations. Bit manipulation
instructions use direct addressing. Table 12-4 lists these instructions.
Table 12-4. Bit Manipulation Instructions
Instruction
Mnemonic
BCLR
Clear Bit
Branch if Bit Clear
Branch if Bit Set
Set Bit
BRCLR
BRSET
BSET
12.1.14 Control Instructions
These register reference instructions control CPU operation during program
execution. Control instructions, listed in Table 12-5, use inherent addressing.
Table 12-5. Control Instructions
Instruction
Mnemonic
CLC
Clear Carry Bit
Clear Interrupt Mask
CLI
No Operation
NOP
RSP
RTI
Reset Stack Pointer
Return from Interrupt
Return from Subroutine
Set Carry Bit
RTS
SEC
SEI
Set Interrupt Mask
Stop Oscillator and Enable IRQ Pin
Software Interrupt
STOP
SWI
Transfer Accumulator to Index Register
Transfer Index Register to Accumulator
Stop CPU Clock and Enable Interrupts
TAX
TXA
WAIT
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12.1.15 Instruction Set Summary
Table 12-6 is an alphabetical list of all M68HC05 instructions and shows the effect
of each instruction on the condition code register.
Table 12-6. Instruction Set Summary
Effect on
Source
Form
CCR
Operation
Description
H I N Z C
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
IMM A9 ii
DIR B9 dd
EXT C9 hh ll
2
3
4
5
4
3
Add with Carry
A ← (A) + (M) + (C)
↕ —
↕
↕
↕
↕
↕
↕
IX2
IX1
IX
D9 ee ff
E9 ff
F9
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
IMM AB ii
DIR BB dd
EXT CB hh ll
2
3
4
5
4
3
Add without Carry
Logical AND
A ← (A) + (M)
↕ —
↕
IX2
IX1
IX
DB ee ff
EB ff
FB
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
IMM A4 ii
DIR B4 dd
EXT C4 hh ll
2
3
4
5
4
3
A ← (A) (M)
— —
↕ —
IX2
IX1
IX
D4 ee ff
E4 ff
F4
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
38 dd
48
58
68 ff
78
5
3
3
6
5
Arithmetic Shift Left
(Same as LSL)
— —
— —
↕
↕
↕
↕
↕
↕
↕
C
0
b7
b7
b0
b0
ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X
DIR
INH
INH
IX1
IX
37 dd
47
57
67 ff
77
5
3
3
6
5
C
Arithmetic Shift Right
Branch if Carry Bit
Clear
BCC rel
PC ← (PC) + 2 + rel ? C = 0
— — — — — REL
24 rr
3
DIR (b0) 11 dd
DIR (b1) 13 dd
DIR (b2) 15 dd
DIR (b3) 17 dd
DIR (b4) 19 dd
DIR (b5) 1B dd
DIR (b6) 1D dd
DIR (b7) 1F dd
5
5
5
5
5
5
5
5
BCLR n opr
Clear Bit n
Mn ← 0
— — — — —
Branch if Carry Bit
Set (Same as BLO)
BCS rel
BEQ rel
PC ← (PC) + 2 + rel ? C = 1
PC ← (PC) + 2 + rel ? Z = 1
— — — — — REL
— — — — — REL
25 rr
27 rr
3
3
Branch if Equal
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Table 12-6. Instruction Set Summary (Continued)
Effect on
CCR
Source
Form
Operation
Description
H I N Z C
Branch if Half-Carry
Bit Clear
BHCC rel
PC ← (PC) + 2 + rel ? H = 0
PC ← (PC) + 2 + rel ? H = 1
— — — — — REL
28 rr
3
Branch if Half-Carry
Bit Set
BHCS rel
BHI rel
— — — — — REL
29 rr
22 rr
24 rr
3
3
3
Branch if Higher
PC ← (PC) + 2 + rel ? C Z = 0 — — — — — REL
PC ← (PC) + 2 + rel ? C = 0 — — — — — REL
Branch if Higher or
Same
BHS rel
Branch if IRQ Pin
High
BIH rel
BIL rel
PC ← (PC) + 2 + rel ? IRQ = 1 — — — — — REL 2F rr
3
3
Branch if IRQ Pin
Low
PC ← (PC) + 2 + rel ? IRQ = 0 — — — — — REL 2E rr
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
IMM A5 ii
2
3
4
5
4
3
DIR
B5 dd
Bit Test
Accumulator with
Memory Byte
EXT C5 hh ll
(A) (M)
— — ↕ ↕ —
IX2
IX1
IX
D5 ee ff
E5 ff
F5
p
Branch if Lower
(Same as BCS)
BLO rel
BLS rel
PC ← (PC) + 2 + rel ? C = 1
— — — — — REL
25 rr
23 rr
3
3
Branch if Lower or
Same
PC ← (PC) + 2 + rel ? C Z = 1 — — — — — REL
Branch if Interrupt
Mask Clear
BMC rel
BMI rel
BMS rel
PC ← (PC) + 2 + rel ? I = 0
PC ← (PC) + 2 + rel ? N = 1
PC ← (PC) + 2 + rel ? I = 1
— — — — — REL 2C rr
— — — — — REL 2B rr
— — — — — REL 2D rr
3
3
3
Branch if Minus
Branch if Interrupt
Mask Set
BNE rel
BPL rel
BRA rel
Branch if Not Equal
Branch if Plus
PC ← (PC) + 2 + rel ? Z = 0
PC ← (PC) + 2 + rel ? N = 0
PC ← (PC) + 2 + rel ? 1 = 1
— — — — — REL
— — — — — REL 2A rr
— — — — — REL 20 rr
26 rr
3
3
3
Branch Always
DIR (b0) 01 dd rr
DIR (b1) 03 dd rr
DIR (b2) 05 dd rr
DIR (b3) 07 dd rr
DIR (b4) 09 dd rr
DIR (b5) 0B dd rr
DIR (b6) 0D dd rr
DIR (b7) 0F dd rr
5
5
5
5
5
5
5
5
BRCLR n opr rel Branch if bit n clear
PC ← (PC) + 2 + rel ? Mn = 0 — — — — ↕
DIR (b0) 00 dd rr
DIR (b1) 02 dd rr
DIR (b2) 04 dd rr
DIR (b3) 06 dd rr
DIR (b4) 08 dd rr
DIR (b5) 0A dd rr
DIR (b6) 0C dd rr
DIR (b7) 0E dd rr
5
5
5
5
5
5
5
5
BRSET n opr rel Branch if Bit n Set
PC ← (PC) + 2 + rel ? Mn = 1 — — — — ↕
BRN rel
Branch Never
PC ← (PC) + 2 + rel ? 1 = 0
— — — — — REL
21 rr
3
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Table 12-6. Instruction Set Summary (Continued)
Effect on
CCR
Source
Form
Operation
Description
H I N Z C
DIR (b0) 10 dd
DIR (b1) 12 dd
DIR (b2) 14 dd
DIR (b3) 16 dd
DIR (b4) 18 dd
DIR (b5) 1A dd
DIR (b6) 1C dd
DIR (b7) 1E dd
5
5
5
5
5
5
5
5
BSET n opr
Set Bit n
Mn ← 1
— — — — —
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
Branch to
Subroutine
BSR rel
— — — — — REL AD rr
6
PC ← (PC) + rel
CLC
CLI
Clear Carry Bit
C ← 0
I ← 0
— — — — 0
INH
98
9A
2
2
Clear Interrupt Mask
— 0 — — — INH
CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X
M ← $00
A ← $00
X ← $00
M ← $00
M ← $00
DIR
INH
3F dd
4F
5F
6F ff
7F
5
3
3
6
5
Clear Byte
— — 0 1 — INH
IX1
IX
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
IMM A1 ii
DIR B1 dd
EXT C1 hh ll
2
3
4
5
4
3
Compare
Accumulator with
Memory Byte
(A) – (M)
— —
— —
— —
— —
— —
↕
↕
↕
↕
↕
↕
↕
IX2
IX1
IX
D1 ee ff
E1 ff
F1
COM opr
COMA
COMX
COM opr,X
COM ,X
M ← ( ) = $FF – (M)
DIR
INH
INH
IX1
IX
33 dd
43
53
63 ff
73
5
3
3
6
5
M
A ← ( ) = $FF – (M)
A
Complement Byte
(One’s Complement)
X ← ( ) = $FF – (M)
↕ 1
X
M ← ( ) = $FF – (M)
M
M ← ( ) = $FF – (M)
M
CPX #opr
CPX opr
CPX opr
CPX opr,X
CPX opr,X
CPX ,X
IMM A3 ii
DIR B3 dd
EXT C3 hh ll
2
3
4
5
4
3
Compare Index
Register with
Memory Byte
(X) – (M)
↕
↕
IX2
IX1
IX
D3 ee ff
E3 ff
F3
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
DIR
INH
INH
IX1
IX
3A dd
4A
5A
6A ff
7A
5
3
3
6
5
Decrement Byte
↕ —
↕ —
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
IMM A8 ii
DIR B8 dd
EXT C8 hh ll
2
3
4
5
4
3
EXCLUSIVE OR
Accumulator with
Memory Byte
A ← (A) (M)
IX2
IX1
IX
D8 ee ff
E8 ff
F8
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Table 12-6. Instruction Set Summary (Continued)
Effect on
CCR
Source
Form
Operation
Description
H I N Z C
INC opr
INCA
INCX
INC opr,X
INC ,X
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
DIR
INH
INH
IX1
IX
3C dd
4C
5C
6C ff
7C
5
3
3
6
5
Increment Byte
— —
↕
↕ —
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
DIR BC dd
EXT CC hh ll
2
3
4
3
2
Unconditional Jump
Jump to Subroutine
PC ← Jump Address
— — — — —
— — — — —
IX2
IX1
IX
DC ee ff
EC ff
FC
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
DIR BD dd
EXT CD hh ll
5
6
7
6
5
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Conditional Address
IX2
IX1
IX
DD ee ff
ED ff
FD
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
IMM A6 ii
DIR B6 dd
EXT C6 hh ll
2
3
4
5
4
3
Load Accumulator
with Memory Byte
A ← (M)
X ← (M)
— —
↕
↕ —
IX2
IX1
IX
D6 ee ff
E6 ff
F6
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
IMM AE ii
DIR BE dd
EXT CE hh ll
2
3
4
5
4
3
Load Index Register
with Memory Byte
— —
— —
↕
↕
↕ —
IX2
IX1
IX
DE ee ff
EE ff
FE
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
DIR
INH
INH
IX1
IX
38 dd
48
58
68 ff
78
5
3
3
6
5
Logical Shift Left
(Same as ASL)
C
0
↕
↕
b7
b0
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
DIR
INH
INH
IX1
IX
34 dd
44
54
64 ff
74
5
3
3
6
5
0
C
Logical Shift Right
Unsigned Multiply
— — 0
↕
↕
b7
b0
MUL
X : A ← (X) × (A)
0 — — — 0
INH
42
11
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
DIR
INH
INH
IX1
IX
30 ii
40
50
60 ff
70
5
3
3
6
5
Negate Byte
(Two’s Complement)
— —
↕
↕
↕
NOP
No Operation
— — — — — INH
9D
2
MC68HC05JB3
REV 1
INSTRUCTION SET
MOTOROLA
12-11
For More Information On This Product,
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GENERAL RELEASE SPECIFICATION
November 5, 1998
Table 12-6. Instruction Set Summary (Continued)
Effect on
CCR
Source
Form
Operation
Description
H I N Z C
ORA #opr
IMM AA ii
DIR BA dd
EXT CA hh ll
2
3
4
5
4
3
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
Logical OR
Accumulator with
Memory
A ← (A) (M)
— —
↕
↕ —
IX2
IX1
IX
DA ee ff
EA ff
FA
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
DIR
INH
INH
IX1
IX
39 dd
49
59
69 ff
79
5
3
3
6
5
Rotate Byte Left
through Carry Bit
C
— —
— —
↕
↕
↕
↕
b7
b0
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
DIR
INH
INH
IX1
IX
36 dd
46
56
66 ff
76
5
3
3
6
5
Rotate Byte Right
through Carry Bit
C
↕
↕
b7
b0
RSP
RTI
Reset Stack Pointer
Return from Interrupt
SP ← $00FF
— — — — — INH
9C
80
2
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
↕
↕
↕
↕
↕
INH
9
Return from
Subroutine
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
RTS
— — — — — INH
81
6
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
IMM A2 ii
DIR B2 dd
EXT C2 hh ll
2
3
4
5
4
3
Subtract Memory
Byte and Carry Bit
from Accumulator
A ← (A) – (M) – (C)
— —
↕
↕
↕
IX2
IX1
IX
D2 ee ff
E2 ff
F2
SEC
SEI
Set Carry Bit
C ← 1
I ← 1
— — — — 1
INH
99
2
2
Set Interrupt Mask
— 1 — — — INH
9B
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
DIR
B7 dd
4
5
6
5
4
EXT C7 hh ll
Store Accumulator in
Memory
M ← (A)
— —
↕
↕ —
IX2
IX1
IX
D7 ee ff
E7 ff
F7
Stop Oscillator and
Enable IRQ Pin
STOP
— 0 — — — INH
DIR
8E
2
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
BF dd
4
5
6
5
4
EXT CF hh ll
Store Index
Register In Memory
M ← (X)
— —
↕
↕ —
IX2
IX1
IX
DF ee ff
EF ff
FF
MOTOROLA
12-12
INSTRUCTION SET
MC68HC05JB3
REV 1
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
November 5, 1998
GENERAL RELEASE SPECIFICATION
Table 12-6. Instruction Set Summary (Continued)
Effect on
CCR
Source
Form
Operation
Description
H I N Z C
SUB #opr
IMM A0 ii
DIR B0 dd
EXT C0 hh ll
2
3
4
5
4
3
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
Subtract Memory
Byte from
Accumulator
A ← (A) – (M)
— —
↕
↕
↕
IX2
IX1
IX
D0 ee ff
E0 ff
F0
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
SWI
TAX
Software Interrupt
— 1 — — — INH
83
97
10
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
Transfer
Accumulator to
Index Register
X ← (A)
(M) – $00
A ← (X)
— — — — — INH
2
TST opr
TSTA
TSTX
TST opr,X
TST ,X
DIR
INH
3D dd
4D
5D
6D ff
7D
4
3
3
5
4
Test Memory Byte
for Negative or Zero
— —
↕
↕ —
INH
IX1
IX
Transfer Index
Register to
Accumulator
TXA
— — — — — INH
— 0 — — — INH
9F
8F
2
2
Stop CPU Clock and
Enable
WAIT
Interrupts
A
C
Accumulator
Carry/borrow flag
opr
PC
Operand (one or two bytes)
Program counter
CCR
dd
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
PCH
PCL
REL
rel
rr
SP
X
Z
Program counter high byte
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer
dd rr
DIR
ee ff
EXT
ff
Offset byte in indexed, 8-bit offset addressing
Half-carry flag
Index register
Zero flag
H
hh ll
I
High and low bytes of operand address in extended addressing
Interrupt mask
#
Immediate value
Logical AND
ii
Immediate operand byte
Logical OR
IMM
INH
IX
IX1
IX2
M
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Loaded with
( )
–( )
←
?
:
↕
—
If
Concatenated with
Set or cleared
Not affected
N
n
Negative flag
Any bit
MC68HC05JB3
REV 1
INSTRUCTION SET
MOTOROLA
12-13
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Table 12-7. Opcode Map
Bit Manipulation Branch
Read-Modify-Write
Control
Register/Memory
DIR
DIR
REL
DIR
INH
INH
IX1
IX
INH
INH
IMM
DIR
EXT
IX2
IX1
IX
MSB
LSB
MSB
LSB
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
5
5
3
5
3
3
6
5
9
2
3
4
5
4
3
BRSET0
BSET0
BRA
NEG
NEGA
NEGX
NEG
NEG
RTI
SUB
SUB
SUB
SUB
SUB
SUB
CMP
SBC
CPX
AND
BIT
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
3
DIR
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
DIR
5
2
2
2
2
2
REL
3
2
DIR
1
INH
1
INH
2
IX1
1
IX
1
1
INH
6
2
2
2
2
2
2
2
IMM
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
DIR
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
EXT
4
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IX2
5
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IX1
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IX
3
5
BRCLR0
BCLR0
BRN
RTS
CMP
CMP
CMP
CMP
CMP
3
DIR
DIR
5
REL
3
INH
IMM
2
DIR
3
EXT
4
IX2
5
IX1
4
IX
3
5
11
BRSET1
BSET1
BHI
MUL
SBC
SBC
SBC
SBC
SBC
3
DIR
DIR
5
REL
3
1
1
1
INH
3
IMM
2
DIR
3
EXT
4
IX2
5
IX1
4
IX
3
5
5
3
6
5
10
BRCLR1
BCLR1
BLS
COM
COMA
COMX
COM
COM
LSR
SWI
CPX
CPX
CPX
CPX
CPX
3
DIR
DIR
5
REL
3
2
2
DIR
5
INH
3
1
1
INH
3
2
2
IX1
6
1
1
IX
5
1
INH
IMM
2
DIR
3
EXT
4
IX2
5
IX1
4
IX
3
5
BRSET2
BSET2
BCC
LSR
LSRA
LSRX
LSR
AND
AND
AND
AND
AND
3
DIR
DIR
5
REL
3
DIR
INH
INH
IX1
IX
IMM
2
DIR
3
EXT
4
IX2
5
IX1
4
IX
3
5
BRCLR2
BCLR2 BCS/BLO
BIT
BIT
BIT
BIT
LDA
STA
BIT
LDA
STA
3
DIR
DIR
5
2
2
2
2
2
2
2
2
2
2
2
REL
3
IMM
2
DIR
3
EXT
4
IX2
5
IX1
4
IX
3
5
5
3
3
6
5
BRSET3
BSET3
BNE
ROR
RORA
RORX
ROR
ROR
ASR
LDA
LDA
LDA
LDA
STA
EOR
ADC
ORA
ADD
JMP
JSR
LDX
STX
3
DIR
DIR
5
REL
3
2
2
DIR
5
1
1
INH
3
1
1
INH
3
2
2
IX1
6
1
1
IX
5
IMM
DIR
4
EXT
5
IX2
6
IX1
5
IX
4
5
2
RCLR3
BCLR3
BEQ
ASR
ASRA
ASRX
ASR
TAX
STA
STA
3
DIR
DIR
5
REL
3
DIR
5
INH
3
INH
3
IX1
6
IX
5
1
1
1
1
1
1
1
INH
2
DIR
3
EXT
4
IX2
5
IX1
4
IX
3
5
2
BRSET4
BSET4
BHCC
ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL
CLC
EOR
EOR
EOR
EOR
EOR
3
DIR
DIR
5
REL
3
2
2
2
DIR
5
1
1
1
INH
3
1
1
1
INH
3
2
2
2
IX1
6
1
1
1
IX
5
INH
2
2
2
2
2
IMM
2
DIR
3
EXT
4
IX2
5
IX1
4
IX
3
5
BRCLR4
BCLR4
BHCS
ROL
ROLA
ROLX
ROL
ROL
DEC
SEC
ADC
ADC
ADC
ADC
ADC
DIR
DIR
5
REL
3
DIR
5
INH
3
INH
3
IX1
6
IX
5
INH
2
IMM
2
DIR
3
EXT
4
IX2
5
IX1
4
IX
3
5
BRSET5
BSET5
BPL
DEC
DECA
DECX
DEC
CLI
ORA
ORA
ORA
ORA
ORA
3
DIR
DIR
5
REL
3
DIR
INH
INH
IX1
IX
INH
2
IMM
2
DIR
3
EXT
4
IX2
5
IX1
4
IX
3
5
BRCLR5
BCLR5
BMI
SEI
ADD
ADD
ADD
ADD
ADD
3
DIR
DIR
5
REL
3
INH
2
IMM
DIR
2
EXT
3
IX2
4
IX1
3
IX
2
5
5
3
3
6
5
BRSET6
BSET6
BMC
INC
INCA
INCX
INC
TST
INC
TST
RSP
JMP
JMP
JMP
JSR
LDX
STX
JMP
JSR
LDX
STX
3
DIR
DIR
5
REL
3
2
2
DIR
4
1
1
INH
3
1
1
INH
3
2
2
IX1
5
1
1
IX
4
INH
2
DIR
5
EXT
6
IX2
7
IX1
6
IX
5
5
6
BRCLR6
BCLR6
BMS
TST
TSTA
TSTX
NOP
BSR
JSR
JSR
DIR
DIR
5
REL
3
DIR
INH
INH
IX1
IX
INH
2
2
REL
2
DIR
3
EXT
4
IX2
5
IX1
4
IX
3
5
2
BRSET7
BSET7
BIL
STOP
LDX
LDX
LDX
3
DIR
DIR
5
REL
3
1
1
INH
2
IMM
DIR
4
EXT
5
IX2
6
IX1
5
IX
4
5
5
3
3
6
5
2
BRCLR7
BCLR7
BIH
CLR
CLRA
CLRX
CLR
CLR
WAIT
TXA
STX
STX
3
DIR
DIR
REL
2
DIR
1
INH
1
INH
2
IX1
1
IX
INH
1
INH
DIR
EXT
IX2
IX1
IX
INH = Inherent
IMM = Immediate
DIR = Direct
REL = Relative
IX = Indexed, No Offset
IX1 = Indexed, 8-Bit Offset
IX2 = Indexed, 16-Bit Offset
MSB
0
MSB of Opcode in Hexadecimal
LSB
5 Number of Cycles
LSB of Opcode in Hexadecimal
0
BRSET0 Opcode Mnemonic
3
DIR Number of Bytes/Addressing Mode
EXT = Extended
Freescale Semiconductor, Inc.
November 5, 1998
GENERAL RELEASE SPECIFICATION
SECTION 13
ELECTRICAL SPECIFICATIONS
This section provides the electrical and timing specifications for the
MC68HC05JB3.
13.1 MAXIMUM RATINGS
(Voltages referenced to V
)
SS
Rating
Symbol
Value
Unit
V
Supply Voltage
Bootloader Mode (IRQ/V Pin Only)
V
–0.3 to +7.0
DD
V
V
SS
– 0.3 to 17
25
V
PP
IN
Current Drain Per Pin Excluding V and V
I
mA
°C
DD
SS
Operating Junction Temperature
T
+150
J
Operating Temperature Range
MC68HC05JB3 (Standard)
MC68HC05JB3 (Extended)
T to T
L H
0 to +70
–40 to +85
T
T
°C
°C
A
A
Storage Temperature Range
T
–65 to +150
°C
stg
NOTE
Maximum ratings are the extreme limits the device can be exposed to without
causing permanent damage to the chip. The device is not intended to operate at
these conditions.
The MCU contains circuitry that protect the inputs against damage from high
static voltages; however, do not apply voltages higher than those shown in the
table below. Keep V and V
within the range from V ≤ (V or V
) ≤ V .
IN
OUT
SS
IN
OUT
DD
Connect unused inputs to the appropriate voltage level, either V or V .
SS
DD
13.2 THERMAL CHARACTERISTICS
Characteristic
Symbol
Value
Unit
Thermal Resistance
20-pin PDIP
θ
°C/W
°C/W
°C/W
°C/W
JA
θ
20-pin SOIC
28-pin PDIP
28-pin SOIC
JA
θ
JA
θ
JA
MC68HC05JB3
REV 1
ELECTRICAL SPECIFICATIONS
MOTOROLA
13-1
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
November 5, 1998
13.3 DC ELECTRICAL CHARACTERISTICS
Table 13-1. DC Electrical Characteristics
(V = 4.2V to 5.5V, V = 0 Vdc, T = 0°C to +70°C, unless otherwise noted)
DD
SS
A
Characteristic
Symbol
Min
Typ
Max
Unit
Output Voltage
V
—
—
—
0.1
—
OL
V
I
= 10.0 µA
V
V
V
– 0.1
Load
OH
DD
DD
Output High Voltage
(I
=–0.8 mA) PA0-7, PB0-2, PB4-7, PC0-3
V
– 0.8
—
—
V
V
Load
OH
Output Low Voltage
(I
(I
(I
= 1.6mA) PA0-3, PB0, PB4-7, PC0-3
= 8mA) PA4-7
= 25mA) PB1, PB2 (see note 8)
—
—
—
—
—
—
0.4
0.4
0.5
Load
Load
Load
V
OL
Input High Voltage
PA0-7, PB0-2, PB4-7, PC0-3, IRQ, RESET, OSC1
V
0.7×V
—
—
V
DD
V
V
IH
DD
Input Low Voltage
PA0-7, PB0-2, PB4-7, PC0-3, IRQ, RESET, OSC1
V
V
0.2×V
DD
IL
SS
Supply Current (see Notes)
Run (USB active)
8
7.5
3
10
9
5
mA
mA
mA
mA
Run (USB suspended)
Wait (USB active)
Wait (USB suspended)
Stop (USB suspended)
3.3V regulator on
I
DD
2.5
4
40
—
100
µA
I/O Ports Hi-Z Leakage Current
PA0-7, PB0-2, PB4-7, PC0-3
I
—
±10
µA
Z
(without individual pull-down/up activated)
Input Pull-down Current
PA0-7, PB0, PB4-7, PC0-3
(with individual pull-down activated)
I
50
—
100
—
200
5
µA
µA
IL
Input Current
RESET, IRQ, OSC1
I
in
Capacitance
Ports (as Input or Output)
RESET, IRQ, OSC1, OSC2
C
C
—
—
—
—
12
8
pF
pF
out
in
Crystal/Ceramic Resonator Oscillator Mode
Internal Resistor
R
1
3
2
MΩ
OSC1 to OSC2
OSC
MOTOROLA
13-2
ELECTRICAL SPECIFICATIONS
MC68HC05JB3
REV 1
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
November 5, 1998
GENERAL RELEASE SPECIFICATION
Table 13-1. DC Electrical Characteristics
(V = 4.2V to 5.5V, V = 0 Vdc, T = 0°C to +70°C, unless otherwise noted)
DD
SS
A
Characteristic
Symbol
Min
Typ
Max
Unit
Pullup Resistor
PB1, PB2
R
30
50
3.3
3.5
75
KΩ
V
PULLUP
LVR Inhibit (see note 9)
V
LVRI
LVR Recover (see note 9)
TCAP Input Threshold Voltage
V
V
LVRR
TCAP
V
V
/2
V
DD
NOTES:
1. All values shown reflect average measurements.
2. Typical values at midpoint of voltage range, 25°C only.
3. Wait I : Only MFT and Timer1 active.
DD
4. Run (Operating) I , Wait I : Measured using external square wave clock source to OSC1 (f = 6.0
OSC
DD
DD
MHz), all inputs 0.2 VDC from rail; no DC loads, less than 50pF on all outputs, C = 20 pF on OSC2.
L
5. Wait, Stop I : All ports configured as inputs, V = 0.2 VDC, V = V –0.2 VDC.
DD
IL
IH
DD
6. Stop I measured with OSC1 = V
.
DD
SS
7. Wait I is affected linearly by the OSC2 capacitance.
DD
8. T = 0°C to +40°C.
A
9. These are preliminary specifications.
13.4 USB DC ELECTRICAL CHARACTERISTICS
Table 13-2. USB DC Electrical Characteristics
(V = 4.2V to 5.5V, V = 0 Vdc, T = 0°C to +70°C, unless otherwise noted)
DD
SS
A
Characteristic
Symbol
Conditions
0V<Vin<3.3V
|(D+)–(D–)|
Min
–10
0.2
Typ
Max
Unit
µA
V
Hi-Z State Data Line Leakage
Differential Input Sensitivity
I
+10
LO
V
DI
Differential Common Mode
Range
Includes V
range
DI
V
0.8
0.8
2.5
2.0
0.3
V
V
V
CM
Single Ended Receiver
Threshold
V
V
SE
OL
OH
R of 1.5k to
L
Static Output Low
3.6V
R of 15k to
L
Static Output High
V
2.8
3.0
3.6
3.6
V
V
GND
3.3V External Reference Pin
V
I =200µA
3.3
3.3
L
MC68HC05JB3
REV 1
ELECTRICAL SPECIFICATIONS
MOTOROLA
13-3
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November 5, 1998
13.5 USB LOW SPEED SOURCE ELECTRICAL CHARACTERISTICS
Table 13-3. USB Low Speed Source Electrical Characteristics
Conditions
Parameter
Symbol
Min
Typ
Max
Unit
(Notes 1,2,3)
Transition time:
Notes 4, 5, 8
Rise Time
Fall Time
T
C =50pF
75
75
ns
ns
ns
ns
R
L
C =350pF
300
L
T
C =50pF
F
L
C =350pF
300
120
L
Rise/Fall Time Matching
T
T /T
F
80
%
V
RFM
R
Output Signal Crossover
Voltage
V
1.3
2.0
CRS
1.4775
676.8
1.500
666.0
1.5225
656.8
Mbs
ns
Low Speed Data Rate
T
1.5Mbs ±1.5%
DRATE
Source Differential Driver Jitter
To Next Transition
C =350pF
Notes 6 and 7
L
T
T
–25
–10
25
10
ns
ns
UDJ1
UDJ2
For Paired Transitions
Receiver Data Jitter Tolerance
To Next Transition
C =350pF
L
T
T
–75
–45
75
45
ns
ns
DJR1
DJR2
Notes 7
Note 7
Note 7
For Paired Transitions
Source EOP Width
TEOPT
TDEOP
1.25
–40
1.50
100
µs
Differential to EOP Transition
Skew
ns
Receiver EOP Width
Must Reject as EOP
Must Accept
T
T
Note 7
330
675
ns
ns
EOPR1
EOPR2
NOTES:
1. All voltages measured from local ground, unless otherwise specified.
2. All timings use a capacitive load of 50pF, unless otherwise specified.
3. Low speed timings have a 1.5k pull-up to 2.8V on the D– data line.
4. Measured from 10% to 90% of the data signal.
5. The rising and falling edges should be smooth transitions (monotonic).
6. Timing differences between the differential data signals.
7. Measured at crossover point of differential data signals.
8. Capacitive loading includes 50pF of tester capacitance.
MOTOROLA
13-4
ELECTRICAL SPECIFICATIONS
MC68HC05JB3
REV 1
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13.6 CONTROL TIMING
Table 13-4. Control Timing
(V = 4.2V to 5.5V, V = 0 Vdc, T = 0°C to +70°C, unless otherwise noted)
DD
SS
A
Characteristic
Symbol
Min
Max
Units
Frequency of Operation
Crystal Oscillator Option
External Clock Source
f
f
—
DC
6
6
MHz
MHz
OSC
OSC
Internal Operating Frequency
Crystal Oscillator (f
÷ 2)
÷ 2)
f
f
—
DC
3
3
MHz
MHz
OSC
OP
OP
External Clock (f
OSC
Cycle Time (1/f
)
t
330
1.5
—
—
—
—
ns
OP
CYC
RESET Pulse Width Low
t
t
t
t
RL
CYC
CYC
CYC
IRQ Interrupt Pulse Width Low (Edge-Triggered)
IRQ Interrupt Pulse Period
t
0.5
ILIH
t
note 1
ILIL
IHIL
IHIH
PA0 to PA3 Interrupt Pulse Width High
(Edge-Triggered)
—
t
0.5
t
CYC
PA0 to PA3 Interrupt Pulse Period
OSC1 Pulse Width
t
note 1
—
—
—
t
CYC
t
, t
ns
OH OL
Output High to Low Transition Period on
PA6, PA7, PB0-4
t
ns
SLOW
NOTES:
1. The minimum period t
or t
should not be less than the number of cycles it takes to execute the
CYC
ILIL
IHIH
interrupt service routine plus 19 t
.
2. Effects of processing, temperature, and supply voltage (excluding tolerances of external R and C)
3. is a parameter dependent on f and loading.Typical value of t is TENTATIVELY set at 170 ns
t
slow
OSC
slow
with minimal value of 130ns and maximal value of 185ns under the SIMULATION conditions that f
OSC
is 6.0 MHz and slow output transition feature is enabled. Actual transition time will be specified to
replace the TBDs when enough characterization has been done on various wafers from different lots.
The values listed here represent data off simulation runs under the specified conditions. Under no cir-
cumstances should they be treated as the final specification.
MC68HC05JB3
REV 1
ELECTRICAL SPECIFICATIONS
MOTOROLA
13-5
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MOTOROLA
13-6
ELECTRICAL SPECIFICATIONS
MC68HC05JB3
REV 1
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GENERAL RELEASE SPECIFICATION
SECTION 14
MECHANICAL SPECIFICATIONS
This section provides the mechanical dimensions for the 20-pin SDIP, and
28-pin SDIP, 20-pin SOIC, and 28-pin SOIC packages.
14.1 20-PIN PDIP (CASE 738)
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
20
1
11
10
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
L
C
INCHES
MILLIMETERS
DIM
A
B
C
D
MIN
MAX
1.070
0.260
0.180
0.022
MIN
25.66
6.10
3.81
0.39
MAX
27.17
6.60
4.57
0.55
1.010
0.240
0.150
0.015
–T–
SEATING
PLANE
K
E
0.050 BSC
1.27 BSC
M
0.050
0.070
1.27
1.77
F
G
J
K
L
N
E
0.100 BSC
2.54 BSC
0.008
0.110
0.015
0.140
0.21
2.80
0.38
3.55
G
F
J 20 PL
0.300 BSC
7.62 BSC
D 20 PL
0.25 (0.010)
M
M
0.25 (0.010)
T B
M
N
0
15
0
15
0.020
0.040
0.51
1.01
M
M
T
A
Figure 14-1. 20-Pin PDIP Mechanical Dimensions
14.2 28-PIN PDIP (CASE 710)
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25mm (0.010) AT
MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND
EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
28
1
15
14
B
MILLIMETERS
MIN MAX
INCHES
MIN MAX
DIM
A
B
C
D
F
36.45 37.21
13.72 14.22
1.435 1.465
0.540 0.560
0.155 0.200
0.014 0.022
0.040 0.060
L
A
C
3.94
0.36
1.02
5.08
0.56
1.52
N
G
H
J
2.54 BSC
0.100 BSC
1.65
0.20
2.92
2.16
0.38
3.43
0.065 0.085
0.008 0.015
0.115 0.135
J
H
G
K
L
M
K
SEATING
PLANE
15.24 BSC
0.600 BSC
F
D
0°
0.51
15°
1.02
0°
0.020 0.040
15°
M
N
Figure 14-2. 28-Pin PDIP Mechanical Dimensions
MC68HC05JB3
REV 1
MECHANICAL SPECIFICATIONS
MOTOROLA
14-1
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14.3 20-PIN SOIC (CASE 751D)
NOTES:
1. DIMENSIONING AND TOLERANCING PER
–A–
ANSI Y14.5M, 1982.
20
11
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
10X P
–B–
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
M
M
0.010 (0.25)
B
1
10
MILLIMETERS
INCHES
20X D
0.010 (0.25)
DIM
A
B
C
D
MIN
12.65
7.40
2.35
0.35
0.50
MAX
12.95
7.60
2.65
0.49
0.90
MIN
MAX
0.510
0.299
0.104
0.019
0.035
J
0.499
0.292
0.093
0.014
0.020
M
S
S
T
A
B
F
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
0.25
0.10
0
0.32
0.25
7
0.010
0.004
0
0.012
0.009
7
R X 45
10.05
0.25
10.55
0.75
0.395
0.010
0.415
0.029
C
SEATING
PLANE
–T–
M
18X G
K
Figure 14-3. 20-Pin SOIC Mechanical Dimensions
14.4 28-PIN SOIC (CASE 751F)
-A-
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
28
15
14X P
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
M
0.010 (0.25)
M
-B-
B
4. MAXIMUM MOLD PROTRUSION 0.15
(0.006) PER SIDE.
1
14
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
28X D
M
M
S
S
B
0.010 (0.25)
T
A
R X 45°
MILLIMETERS
MIN MAX
17.80 18.05
INCHES
MIN MAX
C
DIM
A
-T-
0.701 0.711
0.292 0.299
0.093 0.104
0.014 0.019
0.016 0.035
0.050 BSC
-T-
SEATING
PLANE
B
7.40
2.35
0.35
0.41
7.60
2.65
0.49
0.90
26X G
C
D
K
F
F
G
J
1.27 BSC
0.23
0.13
0°
0.32
0.29
8°
0.009 0.013
0.005 0.011
J
K
M
P
0° 8°
0.395 0.415
10.05 10.55
0.25 0.75
R
0.010 0.029
Figure 14-4. 28-Pin SOIC Mechanical Dimensions
MOTOROLA
14-2
MECHANICAL SPECIFICATIONS
MC68HC05JB3
REV 1
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GENERAL RELEASE SPECIFICATION
APPENDIX A
MC68HC705JB3
This appendix describes the MC68HC705JB3, the emulation part for
MC68HC05JB3. The entire MC68HC05JB3 data sheet applies to the
MC68HC705JB3, with exceptions outlined in this appendix.
A.1 INTRODUCTION
The MC68HC705JB3 is an EPROM version of the MC68HC05JB3, and is avail-
able for user system evaluation and debugging. The MC68HC705JB3 is function-
ally identical to the MC68HC05JB3 with the exception of the 2560 bytes user
ROM is replaced by 2560 bytes user EPROM. Also, the mask options available on
the MC68HC05JB3 are implemented using the Mask Option Register (MOR) in
the MC68HC705JB3.
The MC68HC705JB3 is not available in the 20-pin SOIC package.
A.2 MEMORY
The MC68HC705JB3 memory map is shown in Figure A-1.
A.3 MASK OPTION REGISTER (MOR)
The Mask Option Register (MOR) is a byte of EPROM used to select the features
controlled by mask options on the MC68HC05JB3. In order to program this regis-
ter the MORON bit in PCR need to be set to “1” before doing the EPROM pro-
gramming process.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
PULLREN
1
BIT 2
BIT 1
BIT 0
MOR
R
COPEN IRQTRIG
PAINTEN OSCDLY LVREN
$01FF
W
reset:
0
0
1
1
1
1
1
COPEN – COP Enable
1 = COP watchdog function disabled.
0 = COP watchdog function enabled.
IRQTRIG – IRQ, PA0-PA3 Interrupt Option
1 = Edge-triggered only.
0 = Edge-and-level-triggered.
MC68HC05JB3
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A-1
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PULLREN – Port A, B, and C Pull-up/down Option
1 = Connected.
0 = Disconnected
PAINTEN – PA0-PA3 External Interrupt Option
1 = External interrupt capability on PA0-PA3 disabled.
0 = External interrupt capability on PA0-PA3 enabled.
OSCDLY – Oscillator Delay Option
1 = 224 internal clock cycles.
0 = 4064 internal clock cycles.
LVREN – LVR Option
1 = Low Voltage Reset circuit enabled.
0 = Low Voltage Reset circuit disabled.
$0000
$0000
I/O Registers
64 Bytes
$003F
I/O Registers
$0040
64 Bytes
Unused
48 Bytes
$006F
$0070
$003E
$003F
EPROM Program Control Register
User RAM
144 Bytes
$1FF0
Reserved
$00C0
$00FF
Reserved
$1FF1
$1FF2
$1FF3
$1FF4
$1FF5
$1FF6
$1FF7
$1FF8
$1FF9
$1FFA
$1FFB
$1FFC
$1FFD
$1FFE
$1FFF
64 Byte Stack
Reserved
Unused: 256 Bytes
Mask Option Register
Reserved
$01FF
MFT Vector (High Byte)
MFT Vector (Low Byte)
Timer1 Vector (High Byte)
Timer1 Vector (Low Byte)
USB Vector (High Byte)
USB Vector (Low Byte)
IRQ Vector (High Byte)
IRQ Vector (Low Byte)
SWI Vector (High Byte)
SWI Vector (Low Byte)
Reset Vector (High Byte)
Reset Vector (Low Byte)
Unused
4608 Bytes
$13FF
$1400
User EPROM
2560 Bytes
$1DFF
$1E00
Bootloader ROM
496 Bytes
$1FEF
$1FF0
User Vectors
16 Bytes
$1FFF
Figure A-1. MC68HC705JB3 Memory Map
MOTOROLA
A-2
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A.4 BOOTSTRAP MODE
Bootloader mode is entered upon the rising edge of RESET if the IRQ/V pin is
PP
at V
and the PB0 pin is at logic zero. The Bootloader program is masked in the
TST
ROM area from $1E00 to $1FEF. This program handles copying of user code from
an external EPROM into the on-chip EPROM. The bootload function has to be
done from an external EPROM. The bootloader performs one programming pass
at 1ms per byte then does a verify pass.
The user code must be a one-to-one correspondence with the internal EPROM
addresses.
A.5 EPROM PROGRAMMING
Programming the on-chip EPROM is achieved by using the Program Control Reg-
ister located at address $3E.
Please contact Motorola for programming board availability.
A.5.1 EPROM Program Control Register (PCR)
This register is provided for programming the on-chip EPROM in the
MC68HC705JB3.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
MORON
0
BIT 1
ELAT
0
BIT 0
PGM
0
PCR
R
0
R
0
0
0
R
0
0
R
0
0
R
0
$003E
W
R
reset:
0
R
= Reserved
MORON – Mask Option Register ON
0 = Disable programming to Mask Option Register ($01FF)
1 = Enable programming to Mask Option Register ($01FF)
ELAT – EPROM LATch control
0 = EPROM address and data bus configured for normal reads
1 = EPROM address and data bus configured for programming (writes
to EPROM cause address and data to be latched). EPROM is in
programming mode and cannot be read if ELAT is 1. This bit should
not be set when no programming voltage is applied to the V pin.
pp
PGM – EPROM ProGraM command
0 = Programming power is switched OFF from EPROM array.
1 = Programming power is switched ON to EPROM array. If ELAT≠1,
then PGM=0.
Bits [7:3] – Reserved
These are reserved bits and should remain zero.
MC68HC05JB3
REV 1
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A.5.2 Programming Sequence
The EPROM programming sequence is:
1. Set the ELAT bit
2. Write the data to the address to be programmed
3. Set the PGM bit
4. Delay for a time t
PGMR
5. Clear the PGM bit
6. Clear the ELAT bit
The last two steps must be performed with separate CPU writes.
CAUTION
It is important to remember that an external programming voltage must be applied
to the V pin while programming, but it should be equal to V
during normal
PP
DD
operations.
Figure A-2 shows the flow required to successfully program the EPROM.
MOTOROLA
A-4
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GENERAL RELEASE SPECIFICATION
START
ELAT=1
Write EPROM byte
PGM=1
Wait 1ms
PGM=0
ELAT=0
Write
additional
byte?
Y
N
END
Figure A-2. EPROM Programming Sequence
A.6 EPROM PROGRAMMING SPECIFICATIONS
Table A-1. EPROM Programming Electrical Characteristics
(V = 4.2V to 5.5V, V = 0 Vdc, T = 0°C to +70°C, unless otherwise noted)
DD
SS
A
Characteristic
Symbol
Min
10
—
1
Typ
12
3
Max
15
Unit
V
Programming Voltage
V
IRQ/V
PP
PP
Programming Current
I
IRQ/V
—
mA
ms
PP
PP
Programming Time
per byte
t
4
—
EPGM
MC68HC05JB3
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A-5
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MOTOROLA
A-6
MC68HC05JB3
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disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for
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