HC908JB8AD [ETC]
Addendum to MC68HC908JB8 Technical Data Rev. 2.0 ; 增编MC68HC908JB8技术数据2.0版本\n
| 型号： | HC908JB8AD |
| 厂家： | 
ETC |
| 描述： | Addendum to MC68HC908JB8 Technical Data Rev. 2.0
|
| 文件： | 总8页 (文件大小：283K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
Addendum
HC908JB8AD/D
Rev. 0, 4/2002
Addendum to
MC68HC908JB8
Technical Data
This addendum provides additional information to the
MC68HC908JB8 Technical Data, Rev. 2
(Motorola document number MC68HC908JB8/D),
MC68HC08JB8A
The MC68HC08JB8A is the ROM part equivalent to the MC68HC908JB8. The
entire MC68HC908JB8 data book apply to this ROM device, with exceptions
outlined in this addendum.
Table 1. Summary of MC68HC08JB8A and MC68HC908JB8 Differences
MC68HC08JB8A
8,192 bytes ROM
MC68HC908JB8
8,192 bytes FLASH
16 bytes FLASH
Memory ($DC00–$FBFF)
User vectors ($FFF0–$FFFF)
16 bytes ROM
FLASH related registers.
$FE08 — FLCR
$FF09 — FLBPR
Not used;
locations are reserved.
Registers at $FE08 and $FF09
$FC00–$FDFF: Not used.
$FE10–$FFDF: Used for
testing purposes only.
Monitor ROM
($FC00–$FDFF and $FE10–$FFDF)
Used for testing and FLASH
programming/erasing.
OSC1 and OSC2 pins
VDD level (5V logic)
VREG level (3.3V logic)
MCU Block Diagram
Memory Map
Figure 1 shows the block diagram of the MC68HC08JB8A.
The MC68HC08JB8A has 8,192 bytes of user ROM from $DC00 to $FBFF, and
16 bytes of user ROM vectors from $FFF0 to $FFFF. On the MC68HC908JB8,
these memory locations are FLASH memory.
Figure 2 shows the memory map of the MC68HC08JB8A.
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HC908JB8AD/D
C P T
D P T
A P T
B P T
E P T
R C D D
R D D D
R A D D
R B D D
R E D D
E V R E I S C A N R T
U S L S
B
2
Addendum to MC68HC908JB8 Technical Data
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HC908JB8AD/D
MC68HC08JB8A
$0000
↓
$003F
I/O Registers
64 Bytes
$0040
↓
RAM
256 Bytes
$013F
$0140
↓
Unimplemented
56,000 Bytes
$DBFF
$DC00
↓
$FBFF
ROM
8,192 Bytes
$FC00
↓
$FDFF
Unimplemented
512 Bytes
$FE00
$FE01
$FE02
$FE03
$FE04
$FE05
$FE06
$FE07
$FE08
$FE09
$FE0A
$FE0B
$FE0C
$FE0D
$FE0E
$FE0F
Break Status Register (BSR)
Reset Status Register (RSR)
Reserved
Break Flag Control Register (BFCR)
Interrupt Status Register 1 (INT1)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Break Address High Register (BRKH)
Break Address Low Register (BRKL)
Break Status and Control Register (BRKSCR)
Reserved
$FE10
↓
$FFDF
Monitor ROM
464 Bytes
$FFE0
↓
$FFEF
Reserved
16 Bytes
$FFF0
↓
$FFFF
ROM Vectors
16 Bytes
Figure 2. MC68HC08JB8A Memory Map
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Addendum to MC68HC908JB8 Technical Data
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HC908JB8AD/D
Reserved Registers
The two registers at $FE08 and $FE09 are reserved locations on the
MC68HC08JB8A.
On the MC68HC908JB8, these two locations are the FLASH control register
and the FLASH block protect register respectively.
Monitor ROM
The monitor program (monitor ROM: $FE10–$FFDF) on the MC68HC08JB8A
is for device testing only. $FC00–$FDFF are unused.
Electrical
Specifications
Electrical specifications for the MC68HC908JB8 apply to the MC68HC08JB8A,
except for the parameters indicated below.
DC Electrical
Characteristics
Table 2. DC Electrical Characteristics
Characteristic(1)
Typ(2)
Symbol
Min
Max
Unit
VREG
Regulator output voltage
3.0
3.3
3.6
V
Output high voltage (ILoad = –2.0 mA)
VOH
VOL
VIH
VREG–0.8
—
—
V
V
V
PTA0–PTA7, PTB0–PTB7, PTC0–PTC7,
PTE0–PTE2
Output low voltage
(ILoad = 1.6 mA) All I/O pins
(ILoad = 25 mA) PTD0–PTD1 in ILDD mode
(ILoad = 10 mA) PTE3–PTE4 with USB disabled
—
—
—
—
—
—
0.4
0.5
0.4
Input high voltage
All ports, OSC1
IRQ, RST
0.7 × VREG
0.7 × VDD
VREG
VDD
—
—
Input low voltage
All ports, OSC1
IRQ, RST
VSS
VSS
0.3 × VREG
0.3 × VDD
VIL
—
—
V
Output low current (VOL = 2.0 V)
PTD2–PTD5 in LDD mode
IOL
12 (17)
17 (22)
22 (27)
mA
VDD supply current, VDD = 5.25V, fOP = 3MHz
Run, with low speed USB(3)
Run, with USB suspended(3)
Wait, with low speed USB(4)
Wait, with USB suspended(4)
—
—
—
—
6.0 (5.0)
5.5 (4.5)
4.0 (3.0)
3.0 (2.5)
7.5
6.5
5.0
4.0
mA
mA
mA
mA
IDD
Stop(5)
—
30
100
µA
0 °C to 70°C
4
Addendum to MC68HC908JB8 Technical Data
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HC908JB8AD/D
MC68HC08JB8A
Table 2. DC Electrical Characteristics
Characteristic(1)
I/O ports Hi-Z leakage current
Typ(2)
—
Symbol
Min
—
Max
Unit
µA
IIL
± ±10
± ±1
IIN
Input current
—
—
µA
COut
CIn
Capacitance
Ports (as input or output)
—
—
—
—
12
8
pF
POR re-arm voltage(6)
VPOR
RPOR
0
—
—
100
—
mV
V/ms
V
POR rise-time ramp rate(7)
Monitor mode entry voltage
0.035
VDD+V
1.4 × VDD
2 × VDD
HI
Pullup resistors
Port A, port B, port C, PTE0–PTE2, RST, IRQ
PTE3–PTE4 (with USB module disabled)
D– (with USB module enabled)
25
4
1.2
40
5
1.5
55
6
2.0
RPU
kΩ
3.8 (3.0)(8)
VLVR
LVI reset
2.8 (2.4)
3.3 (2.7)
V
1. VDD = 4.0 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) IDD measured using external square wave clock source (fXCLK = 6 MHz). All inputs 0.2 V from rail. No dc
loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
affects run IDD. Measured with all modules enabled.
4. Wait IDD measured using external square wave clock source (fXCLK = 6 MHz); all inputs 0.2 V from rail; no dc loads; less
than 100 pF on all outputs. CL = 20 pF on OSC2; 15 kΩ±± ±5% termination resistors on D+ and D– pins; all ports configured
as inputs; OSC2 capacitance linearly affects wait IDD
5. STOP IDD measured with USB in suspend mode; OSC1 grounded; transceiver pullup resistor of 1.5 kΩ±± ±5% between VREG
and D– pins and 15 kΩ±± ±5% termination resistor on D+ pin; no port pins sourcing current.
6. Maximum is highest voltage that POR is guaranteed.
7. If minimum VREG is not reached before the internal POR reset is released, RST must be driven low externally until minimum
VREG is reached.
8. The numbers in parenthesis are MC68HC08JB8 (non-A part) values.
Memory
Characteristics
Table 3. Memory Characteristics
Characteristic
RAM data retention voltage
Notes:
Symbol
Min
Max
Unit
VRDR
1.3
—
V
Since MC68HC08JB8A is a ROM device, FLASH memory electrical characteristics do not apply.
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Addendum to MC68HC908JB8 Technical Data
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HC908JB8AD/D
MC68HC08JB8A
Order Numbers
These part numbers are generic numbers only. To place an order, ROM code
must be submitted to the ROM Processing Center (RPC).
Table 4. MC68HC08JB8A Order Numbers
Operating
MC order number
Package
temperature range
0 °C to +70 °C
0 °C to +70 °C
0 °C to +70 °C
0 °C to +70 °C
MC68HC08JB8AJP
MC68HC08JB8AJDW
MC68HC08JB8AADW
MC68HC08JB8AFB
20-pin PDIP
20-pin SOIC
28-pin SOIC
44-pin QFP
MC68HC08JB8A and MC68HC08JB8 Differences
The MC68HC08JB8A and MC68HC08JB8 are identical devices, except for the
following:
Table 5. MC68HC08JB8A and MC68HC08JB8 Differences
MC68HC08JB8A
MC68HC08JB8
OSC1 and OSC2 pins
VDD level (5V logic)
VREG level (3.3V logic)
Output low current on PTD2–PTD5
in LDD mode
See Table 2 . DC Electrical Characteristics.
The numbers in parenthesis are MC68HC08JB8 values.
Operating IDD currents
LVI trip points
6
Addendum to MC68HC908JB8 Technical Data
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HC908JB8AD/D
NOTES
NOTES
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Addendum to MC68HC908JB8 Technical Data
7
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© Motorola, Inc. 2003
HC908JB8AD/D
Rev. 0
4/2003
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