HCF40108 [ETC]
4 X 4 MULTIPORT REGISTER ; 4× 4多端口寄存器\n
| 型号： | HCF40108 |
| 厂家： | 
ETC |
| 描述： | 4 X 4 MULTIPORT REGISTER
|
| 文件： | 总11页 (文件大小：1383K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HCF40108B
4 x 4 MULTIPORT REGISTER
■
■
ONE INPUT AND TWO OUTPUT BUSES
UNLIMITED EXPANSION IN BIT AND WORD
DIRECTION
■
■
■
DATA LINES HAVE LATCHED INPUTS
3-STATE OUTPUTS
SEPARATE CONTROL OF EACH BUS,
ALLOWING SIMULTANEOUS
SOP
INDEPENDENT READING AND ANY OF
FOUR REGISTERS ON BUS A AND BUS B
AND INDEPENDENT WRITING INTO ANY
OF THE FOUR REGISTERS
ORDER CODES
PACKAGE
TUBE
T & R
■
■
40108B IS PIN-COMPATIBLE WITH
INDUSTRY TYPE MC14580
STANDARDIZED, SYMMETRICAL OUTPUT
CHARACTERISTICS
QUIESCENT CURRENT SPECIF. UP TO 20V
5V, 10V AND 15V PARAMETRIC RATINGS
SOP
HCF40108BM1
HCF40108M013TR
four 4-bit registers, a write address decoder, two
separate read address decoders, and two 3-state
output buses. When the ENABLE input is low, the
■
■
■
corresponding
output
bus
is
switched,
INPUT LEAKAGE CURRENT
independently of the clock, to a high impedance
state. The high impedance third state provides the
outputs with the capability of being connected to
the bus lines in a bus organized system without
the need for interface or pull-up components.
When the WRITE ENABLE input is high, all data
input lines are latched on the positive transition of
the CLOCK and the data is entered into the word
selected by the write address lines. When WRITE
ENABLE is low, the CLOCK is inhibited and no
new data is entered. In either case, the contents of
any word may be accessed via the read address
lines independent of the state of the CLOCK input.
I = 100nA (MAX) AT V = 18V T = 25°C
100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC
JESD13B "STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
I
DD
A
■
■
DESCRIPTION
HCF40108B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in SOP packages.
HCF40108B is a 4 x 4 multiport register containing
PIN CONNECTION
September 2002
1/11
HCF40108B
IINPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
SYMBOL
NAME AND FUNCTION
4, 5, 6, 7
Q0A to Q3A Word A Output
22, 23, 2, 1 Q0B to Q3B Word B Output
20, 19, 18,
D0 to D3
Data Inputs
17
16
CLOCK
Clock Input
WRITE
ENABLE
15
Write Enable Input
21
3
3-STATE B 3 State Output
3-STATE A 3 State Output
WRITE 0,
8, 9
Write Address Inputs
WRITE 1
READ 0B,
READ 1B
10, 11
13, 14
Read Address Inputs
Read Address Inputs
READ 0A,
READ 1A
V
12
24
Negative Supply Voltage
Positive Supply Voltage
SS
V
DD
FUNCTIONAL DIAGRAM
2/11
HCF40108B
LOGIC DIAGRAM
3/11
HCF40108B
SCHEMATIC DIAGRAM
4/11
HCF40108B
TRUTH TABLE
Write
CLOCK
Read
1A
Read
0A
Read
1B
Read Enable Enable
Write 1 Write 2
Dn
DnA
QnB
Enable
0B
A
B
H
H
S1
S2
S1
S2
S1
S2
H
H
H
H
H
S1
X
S2
X
S1
X
S2
X
S1
X
S2
X
H
L
L
L
L
Z
L
Z
L
Z
X
X
X
H
Dn to Word 1 Word 2
word 0
L
L
L
H
H
L
H
H
Out
Out
Word 0
not
altered
Word 1 Word 2
Out Out
L
L
L
L
H
H
L
H
H
Word 2 Word 1
X
X
X
X
X
X
H
X
L
L
H
X
H
H
X
H
X
X
Out
Out
X
X
NC
NC
TIMING CHART
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
Supply Voltage
DC Input Voltage
DC Input Current
-0.5 to +22
V
V
DD
V
-0.5 to V + 0.5
I
DD
I
± 10
200
mA
mW
mW
°C
I
P
Power Dissipation per Package
D
Power Dissipation per Output Transistor
Operating Temperature
100
T
-55 to +125
op
T
Storage Temperature
-65 to +150
°C
stg
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to V pin voltage.
SS
5/11
HCF40108B
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
V
Supply Voltage
3 to 20
0 to V
V
V
DD
V
Input Voltage
I
DD
T
Operating Temperature
-55 to 125
°C
op
DC SPECIFICATIONS
Test Condition
Value
-40 to 85°C -55 to 125°C Unit
Min. Typ. Max. Min. Max. Min. Max.
T
= 25°C
Symbol
Parameter
A
V
V
|I |
V
DD
I
O
O
(V)
(V)
(µA) (V)
I
Quiescent Current
0/5
0/10
0/15
0/20
0/5
5
0.04
0.04
0.04
5
150
300
150
300
L
10
15
20
10
20
µA
600
600
0.08 100
3000
3000
V
High Level Output
Voltage
<1
<1
<1
<1
<1
<1
<1
<1
5
4.95
9.95
4.95
9.95
4.95
9.95
OH
0/10
0/15
5/0
10
V
V
V
V
15 14.95
14.95
14.95
V
Low Level Output
Voltage
5
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
OL
10/0
15/0
10
15
V
High Level Input
Voltage
0.5/4.5
1/9
5
3.5
7
3.5
7
3.5
7
IH
10
15
5
1.5/13.5 <1
11
11
11
V
Low Level Input
Voltage
4.5/0.5
9/1
<1
<1
1.5
3
1.5
3
1.5
3
IL
10
15
5
13.5/1.5 <1
4
4
4
I
Output Drive
Current
0/5
0/5
2.5
4.6
9.5
13.5
0.4
0.5
1.5
<1
<1
<1
<1
<1
<1
<1
-1.36 -3.2
-1.1
-0.36
-0.9
-2.4
0.36
0.9
-1.1
-0.36
-0.9
-2.4
0.36
0.9
OH
5
-0.44
-1.1
-3.0
0.44
1.1
-1
-2.6
-6.8
1
mA
0/10
0/15
0/5
10
15
5
I
Output Sink
Current
OL
0/10
0/15
10
15
2.6
6.8
mA
3.0
2.4
2.4
I
Input Leakage
Current
I
-5
0/18
0/18
Any Input
18
18
±0.1
±1
±1
µA
±10
I
3-State Output
Leakage Current
OZ
-4
Any Input
Any Input
±0.4
±12
±12
µA
±10
C
Input Capacitance
5
7.5
pF
I
The Noise Margin for both "1" and "0" level is: 1V min. with V =5V, 2V min. with V =10V, 2.5V min. with V =15V
DD
DD
DD
6/11
HCF40108B
DYNAMIC ELECTRICAL CHARACTERISTICS (T
= 25°C, C = 50pF, R = 200KΩ, t = t = 20 ns)
amb
L
L
r
f
Test Condition
Value (*)
Unit
Symbol
Parameter
V
(V)
Min. Typ. Max.
DD
t
t
Propagation Delay Time
Clock or Write Enable to Q
5
360
140
100
300
120
85
720
280
200
600
240
170
200
100
80
PHL PLH
10
15
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
Propagation Delay Time
Read or Write Address to
Q
10
15
5
t
t
3-State Disable Delay
Time
100
50
PZH PHZ
10
15
5
40
t
t
3-State Display Delay Time
Output Transition Time
130
60
260
120
100
200
100
80
PZL PLZ
10
15
5
50
t
t
100
50
THL TLH
10
15
5
40
t
Setup Time Data to Clock
0
-95
-35
-20
125
50
setup
t
s(D)
10
15
5
0
0
Setup Time Write Enable
to Clock t
250
100
70
s(WE)
10
15
5
35
Setup Time Write Address
to Clock t
250
100
70
125
50
s(WA)
10
15
5
35
t t
Clock Rise and Fall Time
15
5
r,
s
10
15
5
5
t
Hold Time Data to Clock
220
100
80
110
50
40
135
65
40
165
70
45
175
65
45
150
75
45
3
hold
t
s(D)
10
15
5
Hold Time Write Enable to
Clock t
270
130
80
s(WE)
10
15
5
Hold Time Write Address
to Clock t
330
140
90
s(WA)
10
15
5
t
t
Clock Pulse Width
350
130
90
W
10
15
5
Clock or Write Enable
t
W(CL)
Clock Pulse Width
300
150
90
W
10
15
5
Write Address t
W(WA)
f
Maximum Clock Input
Frequency
1.5
3.5
4.5
CL
10
15
7
9
7/11
HCF40108B
TEST CIRCUIT
TEST
SWITCH
t
t
t
, t
Open
PLH PHL
, t
V
V
PZL PLZ
DD
SS
, t
PZH PHZ
C
R
R
= 50pF or equivalent (includes jig and probe capacitance)
= 200KΩ
L
L
T
= Z
of pulse generator (typically 50Ω)
OUT
WAVEFORM : ENABLE AND DISABLE TIME
8/11
HCF40108B
SWITCHING WAVEFORM
9/11
HCF40108B
SO-24 MECHANICAL DATA
mm.
inch
TYP.
DIM.
MIN.
TYP
MAX.
2.65
0.2
MIN.
MAX.
0.104
0.008
0.096
0.019
0.012
A
a1
a2
b
0.1
0.004
2.45
0.49
0.32
0.35
0.23
0.014
0.009
b1
C
0.5
0.020
c1
D
45˚ (typ.)
15.20
10.00
15.60
10.65
0.598
0.393
0.614
0.419
E
e
1.27
0.050
0.550
e3
F
13.97
7.40
0.50
7.60
1.27
0.291
0.020
0.300
0.050
L
S
˚ (max.)
8
L
c1
b
e
s
e3
E
D
24
13
1
1
2
PO13T
10/11
HCF40108B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
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© 2002 STMicroelectronics - Printed in Italy - All Rights Reserved
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11/11
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