HFC-SP [ETC]
;
| 型号： | HFC-SP |
| 厂家： | 
ETC |
| 描述： |
|
| 文件： | 总83页 (文件大小：1114K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Cologne
Chip
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Copyright 1994-2001 Cologne Chip AG
All Rights Reserved
The information presented can not be considered as assured characteristics. Data can change without notice. Parts of the
information presented may be protected by patent or other rights. Cologne Chip products are not designed, intended, or
authorized for use in any application intended to support or sustain life, or for any other application in which the failure of
the Cologne Chip product could create a situation where personal injury or death may occur.
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Revision History
Date
Remarks
Jan. 2001
Oct. 2000
Aug. 2000
Feb. 2000
Nov. 1999
Aug. 1999
Information added to section: GCI/IOM2 timing.
Changes made on: PCMCIA card sample circuitry.
Changes made on: PCMCIA card sample circuitry.
Information added to section: DMA access in processor mode, GCI frame structure.
Information added to section: Power down considerations.
Section added: Configuring test loops.
Information added to section: Processor interface modes, processor mode, FIFO
channel operation: receive channels, STATES register bit description, ISA-PC bus
or processor access timing, S/T interface activation/deactivation layer 1 for finite
state matrix for NT.
Mar. 1999
Mar. 1999
Feb. 1999
Aug. 1998
Changes made on: PCMCIA card sample circuitry part list: R27 added.
Changes made on: S/T modules part numbers and manufacturers.
Changes made on: CLKDEL register bit description.
Changes made on: DMA access in processor mode, Register bit description of
GCI/IOM2 bus section: Auxiliary channel handling, B_MODE register bit
description.
July 1998
PCMCIA card part list: Values of D4, D5, D7 and D8 changed
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Cologne Chip AG
Eintrachtstrasse 113
D-50668 Köln
Germany
Tel.: +49 (0) 221 / 91 24-0
Fax: +49 (0) 221 / 91 24-100
http://www.CologneChip.com
http://www.CologneChip.de
info@CologneChip.com
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Contents
1
1.1
1.2
General description............................................................................................................................6
Applications.....................................................................................................................................7
Mode description .............................................................................................................................8
1.2.1
1.2.2
1.2.3
1.2.4
ISA-PC mode ..........................................................................................................................8
ISA Plug and Play mode .........................................................................................................8
Processor interface modes.......................................................................................................9
PCMCIA mode........................................................................................................................9
2
Pin description..................................................................................................................................10
ISA-PC bus and microprocessor interface..................................................................................... 10
S/T interface transmit signals ........................................................................................................12
S/T interface receive signals..........................................................................................................12
SRAM Interface.............................................................................................................................13
Oscillator........................................................................................................................................13
GCI/IOM2 bus interface ................................................................................................................14
GCI/IOM2 Timeslot enable signals...............................................................................................14
Interrupt outputs.............................................................................................................................15
Miscellaneous pins.........................................................................................................................15
Power supply .............................................................................................................................16
RESET characteristics...............................................................................................................16
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
3
3.1
3.2
Functional description .....................................................................................................................17
ISA-PC mode .................................................................................................................................17
ISA Plug and Play mode ................................................................................................................18
3.2.1
3.2.2
3.2.2.1
3.2.2.2
3.2.3
3.2.3.1
3.2.3.2
3.2.4
IRQ assignment.....................................................................................................................18
ISA Plug and Play control registers ......................................................................................19
Card level control regsisters .............................................................................................19
Logical device control registers........................................................................................ 21
ISA Plug and Play configuration registers............................................................................21
I/O port configuration registers ........................................................................................ 21
Interrupt configuration registers .......................................................................................22
Writing the Plug and Play configuration EEPROM .............................................................22
3.3
3.4
3.4.1
3.5
3.5.1
ISA-PC bus interface .....................................................................................................................23
Processor mode..............................................................................................................................24
DMA access in processor mode............................................................................................25
PCMCIA mode ..............................................................................................................................26
Internal HFC-SP register selection........................................................................................ 26
Attribute memory..................................................................................................................26
PCMCIA registers.................................................................................................................26
CIS programming..................................................................................................................27
Internal HFC-SP register description.............................................................................................28
FIFO control registers ...........................................................................................................28
FIFO select register...........................................................................................................28
FIFO registers ...................................................................................................................28
Registers of the S/T section ..................................................................................................30
Registers of the GCI/IOM2 bus section................................................................................31
Interrupt and status registers .................................................................................................32
Timer..............................................................................................................................................33
Watchdog.......................................................................................................................................33
3.5.2
3.5.3
3.5.4
3.6
3.6.1
3.6.1.1
3.6.1.2
3.6.2
3.6.3
3.6.4
3.7
3.8
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3.9
3.9.1
3.9.1.1
3.9.1.2
FIFOs .............................................................................................................................................34
FIFO channel operation.........................................................................................................35
Send channels (B1, B2 and D transmit)............................................................................36
Automatically D-channel frame repetition .......................................................................36
FIFO full condition in send channels................................................................................36
Receive Channels (B1, B2 and D receive) .......................................................................37
FIFO full condition in receive channels ...........................................................................38
FIFO reset .........................................................................................................................39
Transparent mode of HFC-SP...............................................................................................39
3.9.1.3
3.9.1.4
3.9.1.5
3.9.1.6
3.9.2
3.10
3.11
3.12
3.13
External SRAM .........................................................................................................................40
Connecting an external device to the HFC-SP..........................................................................41
Power down considerations.......................................................................................................41
Configuring test loops ...............................................................................................................42
4
Register bit description....................................................................................................................43
Register bit description of the FIFO select register.......................................................................43
Register bit description of S/T section ..........................................................................................43
Register bit description of GCI/IOM2 bus section........................................................................47
Register bit description of CONNECT register.............................................................................50
Register bit description of interrupt, status and control registers..................................................51
4.1
4.2
4.3
4.4
4.5
5
Electrical characteristics .................................................................................................................56
6
Timing characteristics .....................................................................................................................59
ISA-PC bus or processor access ....................................................................................................59
SRAM access.................................................................................................................................60
GCI/IOM2 bus clock and data alignment for Mitel STTM bus.......................................................61
GCI/IOM2 timing ..........................................................................................................................62
6.1
6.2
6.3
6.4
6.4.1
6.4.2
6.5
6.6
Master mode..........................................................................................................................62
Slave mode............................................................................................................................63
EEPROM access............................................................................................................................64
Access to an external device..........................................................................................................65
7
S/T interface circuitry......................................................................................................................66
External receiver circuitry .............................................................................................................66
External transmitter circuitry.........................................................................................................67
Oscillator circuitry.........................................................................................................................70
EEPROM circuitry.........................................................................................................................70
7.1
7.2
7.3
7.4
8
8.1
8.2
State matrices for NT and TE.........................................................................................................71
S/T interface activation/deactivation layer 1 for finite state matrix for NT..................................71
Activation/deactivation layer 1 for finite state matrix for TE .......................................................72
9
9.1
9.2
Binary organisation of the frames..................................................................................................73
S/T frame structure ........................................................................................................................73
GCI frame structure .......................................................................................................................74
10 Clock synchronisation......................................................................................................................75
10.1
10.2
Clock synchronisation in NT-mode........................................................................................... 75
Clock synchronisation in TE-mode........................................................................................... 76
11 HFC-SP package dimensions ..........................................................................................................77
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12 Sample circuitries with HFC-SP.....................................................................................................78
12.1
12.2
ISDN ISA PnP PC card .............................................................................................................78
ISDN PCMCIA card..................................................................................................................81
Figures
Figure 1: HFC-SP block diagram..................................................................................................................7
Figure 2: Pin Connection ............................................................................................................................10
Figure 3: FIFO Organisation (shown for B-channel, similar for D-channel).............................................35
Figure 4: FIFO Data Organisation ..............................................................................................................37
Figure 5: Connecting an external device to the HFC-SP............................................................................41
Figure 6: Function of the CONNECT register bits.....................................................................................50
Figure 7: GCI/IOM2 bus clock and data alignment....................................................................................61
Figure 8: External receiver circuitry...........................................................................................................66
Figure 9: External transmitter circuitry ......................................................................................................67
Figure 10: Oscillator Circuitry....................................................................................................................70
Figure 11: EEPROM circuitry ....................................................................................................................70
Figure 12: Frame structure at reference point S and T ...............................................................................73
Figure 13: Single channel GCI format........................................................................................................74
Figure 14: Clock synchronisation in NT-mode ..........................................................................................75
Figure 15: Clock synchronisation in TE-mode...........................................................................................76
Figure 16: HFC-SP package dimensions ....................................................................................................77
Tables
Table 1: Mode selection................................................................................................................................8
Table 2: Selected I/O address after reset ....................................................................................................17
Table 3: DMA access in processor mode ...................................................................................................25
Table 4: SRAM and FIFO size ...................................................................................................................40
Table 5: S/T module part numbers and manufacturer ................................................................................69
Table 6: Activation/deactivation layer 1 for finite state matrix for NT .....................................................71
Table 7: Activation/deactivation layer 1 for finite state matrix for TE......................................................72
Timing Diagrams
Timing diagram 1: ISA-PC bus or microprocessor access .........................................................................59
Timing diagram 2: SRAM access...............................................................................................................60
Timing diagram 3: GCI/IOM2 timing.........................................................................................................62
Timing diagram 4: EEPROM access ..........................................................................................................64
Timing diagram 5: Access to an external device........................................................................................65
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Chip
Features
One chip ISDN-S-controller with B- and D-channel HDLC support
Independent Read and Write HDLC-Channels for 2 ISDN B-channels and one ISDN D-channel
B1 and B2 transparent mode independently selectable
FIFO-size: 4x 7.5 KByte (B-channel) and 2x 512 Byte (D-channel)
max. 31 HDLC frames (B-channel) and 15 HDLC frames (D-channel) per channel and direction
in FIFO
56 kbit/s restricted mode for U.S. ISDN lines selectable
full I.430 ITU S/T ISDN support in TE and NT mode for 3.3V and 5V supply
B1+B2 HDLC mode
PCM30 interface configurable to interface MITEL STTM bus (MVIPTM), Siemens IOM2TM or
GCITM for interface to U-chip or external codecs
direct 8 bit ISA-PC bus interface with buffers for ISA-databus
integrated ISA Plug and Play (Windows 95 Spec.)
only 2 I/O addresses used on ISA-PC bus
one of 7 interrupt channels on ISA-PC bus selectable by software
integrated PCMCIA interface
microprocessor interface compatible to Motorala bus and Siemens/Intel bus
simple access to PCM30 interface for tone synthetisation
Timer with interrupt and watchdog capability in processor mode
3-5V supply voltage
rectangular QFP 100 case
1 General description
The HFC-SP is an ISDN S/T HDLC basic rate controller for so called „passive“ ISDN PC cards with
integrated S/T interface and PCM30 highway interface. It only needs an external SRAM to form a high
performance ISDN PC card. Most problems with passive ISDN PC cards as small FIFOs and massive
interrupt load for the host CPU are overcome by the HFC-SP. So we call ISDN cards with the HFC-SP
„semi-active“.
Additionally the HFC-SP can be used as a microprocessor peripheral in non-PC applications.
The ultra deep FIFOs of the HFC-SP are realized with an external SRAM. Also an industrial standard
serial interface for telecom peripheral ICs is implemented. Codecs are normally connected to this
interface.
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1.1
Applications
ISDN PC card
ISDN terminal adapter
ISDN smart NTs
ISDN PABX
ISDN modems
Figure 1: HFC-SP block diagram
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1.2
Mode description
The HFC-SP has 6 different bus modes, which can be selected by the lines MODE, ALE and IIOSEL0-
IIOSEL3. Depending on the selected mode the function of several pins is different (see: Pin description).
MODE
NC
ALE
GND
VDD
GND
pulse
GND
GND
IIOSEL0..3
Selected mode
ISA-PC mode (mode 1)
0
all 0
all 0
NC
NC
NC
GND
VDD
processor mode (mode 2)
processor mode (mode 3)
processor mode (mode 4)
ISA Plug and Play mode (mode 5)
PCMCIA mode (mode 6)
all 0
*)
*)
Table 1: Mode selection
NC = not connected (leave pin open)
*)
IIOSEL0: EE_SCL Clock of external EEPROM
IIOSEL1: EE_SDA Serial data of external EEPROM
IIOSEL2: SA10
IIOSEL3: SA11
ISA-bus address bit 10
ISA-bus address bit 11
1.2.1 ISA-PC mode
Mode 1: ALE = GND, IIOSEL3-0 0000, MODE = NC
In mode 1 the HFC-SP is addressed by two successive port addresses on the ISA-PC bus. The port
address is selected by the lines SA0 - SA9.
The address with SA0='1' is for register selection and the address with SA0='0' is used for data read/write
(see also: 3.1).
1.2.2 ISA Plug and Play mode
Mode 5:
ISA Plug and Play mode is selected by: ALE = GND and MODE = GND
In mode 5 the HFC-SP is addressed by two successive port addresses on the ISA-PC bus. The port
address is selected by the lines SA0 - SA11.
The address with SA0='1' is for register selection and the address with SA0='0' is used for data read/write
(see also: 3.2).
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1.2.3 Processor interface modes
The processor modes are selected by IIOSEL3-0 = '0000' and MODE left open.
In all processor modes line SA6 must be connected to GND.
Mode 2:
Mode 3:
Motorola bus with control signals /CS, R/W, /DS is selected by setting ALE to VDD.
Siemens/Intel bus with seperated address bus and databus and control signals /CS, /WR,
/RD is selected by setting ALE to GND.
Mode 4:
Intel bus with multiplexed address and databus with control signals /CS, /WR, /RD,
ALE.
ALE latches the address. The address lines SA0-SA7 must be connected to the data lines
BD0-BD7 (except SA6 which must be connected to GND).
The lines SA0-SA7 (except SA6) are used for direct addressing the internal registers of the HFC-SP (see
also 3.4).
1.2.4 PCMCIA mode
Mode 6:
PCMCIA mode is selected by: ALE = GND and MODE = VDD
In mode 6 the HFC-SP is addressed by two successive port addresses. The port address is selected by the
lines SA0 - SA11.
The address with SA0='1' is for register selection and the address with SA0='0' is used for data read/write
(see also: 3.5).
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2 Pin description
Figure 2: Pin Connection
2.1
ISA-PC bus and microprocessor interface
Pin No.
Pin Name
Input
Mode Function
Output
Mode/initial I/O address select
bit 0
1
2
3
4
IIOSEL0
I u)
O e)
I
1,2,3,4
5,6
1,2,3,4
5,6
1,2,3,4
5,6
1,2,3,4
5,6
EE_SCL
IIOSEL1
EE_SDA
IIOSEL2
SA10
Clock of external EEPROM
Mode/initial I/O address select bit 1
Serial data of external EEPROM
Mode/initial I/O address select bit 2
Address bit 10
I/O e)
I u)
IIOSEL3
SA11
I u)
Mode/initial I/O address select bit 3
Address bit 11
Register/ISA-PC address bus
Address bit 0
Address bit 1
Address bit 2
Address bit 3
5
6
7
8
9
SA0
SA1
SA2
SA3
SA4
I
I
I
I
I
all
all
all
all
all
Address bit 4
u)
e)
internal pull up
external pull up resistor required (see Figure 11 on page 70)
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Chip
Pin No.
Pin Name
SA5
Input
Output
Mode Function
10
11
I
I
all
Address bit 5
Address bit 6
SA6
all
(SA6 must be connected to GND in processor mode)
Address bit 7
Address bit 8
DMA acknowledge channel 0
Direct access to GCI/IOM2 bus AUX1 channel data
register (low active)
12
13
SA7
SA8
/DMAAK0
I
I
I
all
1,5,6
2,3,4
14
SA9
/DMAAK1
I
I
1,5,6
2,3,4
address bit 9
DMA acknowledge channel 1
direct access on GCI/IOM2 bus AUX2 channel
dataregister (low active)
* important!
If DMA acknowledge signals /DMAAK0 and /DMAAK1 are active, the function of the
read/write enables is inverted. This means a read command on the controller databus
writes the AUX-Channel register and a write command reads the register. The address on
the address bus (SA0-SA7) is ignored.
15
16
17
18
/AEN
/CE1
/CS
IOCHRDY
/WAIT
/WAIT
/IOR
/IORD
/DS
/IOW
/IOWR
R/W
BD0
BD1
BD2
BD3
BD4
BD5
BD6
BD7
I
I
I
1,5
6
2,3,4
1,5
2,3,4
6
1,3,4,5
6
2
1,3,4,5
6
2
all
all
all
all
all
all
all
all
PC bus address enable
Card enable (low active)
chipselect low active
I/O channel ready
low active wait signal for external processor
Extended bus cycle (low active)
I/O read enable
I/O read (low active)
I/O data strobe
I/O write enable
I/O write (low active)
Read/Write select (WR='0')
Databus bit 0 (LSB)
Databus bit 1
Databus bit 2
Databus bit 3
O 1)
O 1)
O 1)
I
I
I
I
I
I
21
22
23
24
25
26
27
28
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Databus bit 4
Databus bit 5
Databus bit 6
Databus bit 7 (MSB)
1)
open drain, external pull up resistor required
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Pin No.
Pin Name
BUSDIR
Input
Output
O
Mode Function
31
1,2,3,4,5 Databus direction signal for external busdriver
'0' BD0-BD7 are outputs
/INPACK
ALE
O
I
6
Input port acknowledge (low active)
Address latch enable
ALE is also used for mode selection of the HFC-SP.
See Mode selection on page 8 for detailed
information.
32
49
MODE
I
Mode selection
See Mode selection on page 8 for detailed
information.
2.2
S/T interface transmit signals
Pin No.
Pin Name
Input
Function
Output
34
35
36
37
38
TX2_HI
O
O
O
O
O
Transmit output 2
GND driver for transmitter 1
Transmit enable
GND driver for transmitter 2
Transmit output 1
/TX1_LO
/TX_EN
/TX2_LO
TX1_HI
See also: 7.2 External transmitter circuitry.
2.3
S/T interface receive signals
43
44
45
46
48
R2
I
I
I
I
O
Receive data 2
LEV_R2
LEV_R1
R1
Level detect for R2
Level detect for R1
Receive data 1
ADJ_LEV
Levelgenerator
See also: 7.1 External receiver circuitry.
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2.4
SRAM Interface
Pin Name
Pin No.
Input
Function
Output
SRAM data bus
53
54
55
56
57
58
59
60
SRD0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SRAM data bit 0 (LSB)
SRAM data bit 1
SRAM data bit 2
SRAM data bit 3
SRAM data bit 4
SRAM data bit 5
SRAM data bit 6
SRAM data bit 7 (MSB)
SRD1
SRD2
SRD3
SRD4
SRD5
SRD6
SRD7
SRAM address bus
63
64
65
66
67
68
69
70
71
72
74
75
76
77
78
SRA0
SRA1
SRA2
SRA3
SRA4
SRA5
SRA6
SRA7
SRA8
SRA9
SRA10
SRA11
SRA12
SRA13
SRA14
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
SRAM address bus bit 0 (LSB)
SRAM address bus bit 1
SRAM address bus bit 2
SRAM address bus bit 3
SRAM address bus bit 4
SRAM address bus bit 5
SRAM address bus bit 6
SRAM address bus bit 7
SRAM address bus bit 8
SRAM address bus bit 9
SRAM address bus bit 10
SRAM address bus bit 11
SRAM address bus bit 12
SRAM address bus bit 13
SRAM address bus bit 14 (MSB)
SRAM control signals
Read strobe to external device
SRAM chip select
50
79
80
/SRRD
/SRCS
/SRWR
O
O
O
SRAM write enable
2.5
Oscillator
OSC_IN
82
83
I
Oscillator input or quarz connection
12.288 MHz or 24.576 MHz
OSC_OUT
O
Oscillator output or quarz connection
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2.6
GCI/IOM2 bus interface
Pin No.
Pin Name
C4IO
Input
Output
I/O u)
Mode Function
85
86
all
all
4.096 Mhz clock
GCI/IOM2 bus clock master: output
GCI/IOM2 bus clock slave: input (reset default)
Frame synchronisation, 8kHz pulse for GCI/IOM2
bus frame synchronisation
F0IO
I/O u)
GCI/IOM2 bus master: output
GCI/IOM2 bus slave: input (reset default)
GCI/IOM2 bus databus I
Slotwise programmable as input or output
GCI/IOM2 bus databus II
87
88
STIO1
STIO2
I/O u)
I/O u)
all
all
Slotwise programmable as input or output
u)
internal pull up
2.7
GCI/IOM2 Timeslot enable signals
(e. g. for PCM codecs)
91
92
F1_A
F1_B
O
O
O
all
enable signal for external CODEC A
Programmable as positive (reset default) or negative
pulse.
1,2,3,4,6 enable signal for external CODEC B
Programmable as positive (reset default) or negative
pulse.
IRQ_G
5
PC bus interrupt request G
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2.8
Interrupt outputs
Pin Name
IRQ_A
Pin No.
Input
Output
I/O
Mode Function
94
95
1,5,6
PC bus interrupt request A or interrupt input from
external device (see: CIRM register bit description)
processor interrupt request low active
PC bus interrupt request B
/IRQ_P
IRQ_B
/IREQ
O 1)
O
2,3,4
1,5
O
6
Interrupt request (low active)
processor interrupt request high active
PC bus interrupt request C
Watchdog expired, external reset low active
PC bus interrupt request D
IRQ_P
IRQ_C
/WD_RES
IRQ_D
/OE
WD_RES
IRQ_E
/WE
O 2)
O
2,3,4
1,5,6
2,3,4
1,5
96
97
O 1)
O
I
6
Output enable (low active)
Watchdog expired, external reset high active
PC bus interrupt request E
Write enable (low active)
DMA request AUX1 channel register (high active)
PC bus interrupt request F
O 2)
O
2,3,4
1,5
6
2,3,4
1,5
6
98
99
I
O
O
I
DMARQ0
IRQ_F
/REG
Register select and I/O enable (low active)
DMA request AUX2 channel register (high active)
DMARQ1
O
2,3,4
1)
2)
open drain, external pull up resistor required
open source, external pull down resistor required
2.9
Miscellaneous pins
100
RESET
I
all
Reset for HFC-SP (high active)
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2.10 Power supply
Pin No.
Pin Name
VDD
GND
Function
VDD (+3V to +5V)
GND
19, 30, 41, 42, 51, 61, 84, 89
20, 29, 33, 39, 40, 47, 52, 62,
73, 81, 90, 93
* important!
All power supply pins VDD must be directly connected to each other. Also all pins GND must be
directly connected to each other.
To keep VDD and GND bounce to a minimum a bypass capacitor (10 nF to 100 nF) should be
placed between each pair of VDD/GND pins.
2.11 RESET characteristics
The reset signal (hardware reset or software reset) must be active for at least 4 clock cycles.
The GCI/IOM2 bus lines STIO1, STIO2 and the interrupt lines are in tristate mode after a reset.
The HFC-SP is in slave mode after reset. C4IO and F0IO are inputs.
In the processor modes DMARQ1 and DMARQ2 are inactive ('0').
The S/T state machine is stuck to '0' after reset. This means the HFC-SP does not react to any signal on
the S/T interface before the S/T state machine is initialised.
The registers' initial values are described in the Register bit description (section 4 of this data sheet).
After RESET the HFC-SP is in an initialisation cycle and is therefor busy for a maximum of 160 clock
cycles.
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3 Functional description
3.1
ISA-PC mode
ISA-PC mode is selected by MODE = NC, ALE = GND and IIOSEL0..3≠0.
The HFC-SP occupies two consecutive addresses in the I/O map of a PC if it is in ISA-PC mode. It
decodes only the 10 lower address lines as most slot cards do on the ISA-PC bus. The base I/O address is
2 byte aligned so the lower of both addresses is the one with SA0 = 0 and the higher address is the one
with SA0 = 1.
After every hardware reset (RESET = 1) the I/O address select circuit inside the HFC-SP is in hardware
mode. In this mode the HFC-SP can not be accessed until it is initialised to an I/O address.
At first one of 15 different I/O addresses must be selected by the 4 inputs IIOSEL0 .. IIOSEL3 as Table 2
shows:
IIOSEL
3 2 1 0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Selected I/O address
processor mode
2E0h
2D0h
210h
2C0h
200h
2F8h
2E8h
2B0h
3E0h
320h
278h
310h
330h
300h
3E8h
Table 2: Selected I/O address after reset
The hardware selected I/O address might have an address collision with another I/O device in the PC.
After a hardware reset (RESET = 1) you must first write an I/O address into the HFC-SP to set the I/O
address for every further access to the device.
The procedure is as follows:
First you must write the lower 8 bits of the new I/O address you want into the lower address (SA0 = 0) of
the hardware selected I/O address. The LSB of the new address is a don't care bit because the HFC-SP
always occupies two I/O addresses.
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Then the additional 2 bits of the new I/O address have to be written into the higher address (SA0 = 1) of
the hardware selected I/O address. The other 6 bits in the byte must have a special pattern to switch over
to the software selected address mode. This pattern must be 0101 01aa, whereby aa are the 2 higher
address bits.
e.g.: wanted I/O address: 3A4h / 3A5h
IIOSEL(3:0): 0001
then hardware selected I/O address is: 2E0h = 10 1110 0000 b
write the value A4h or A5h into 2E0h =
write the value 57h into 2E1h
=
pattern
address
x = don't care
All further accesses to the HFC-SP can only be done on the addresses 3A4h / 3A5h. Only a hardware
reset will switch back the HFC-SP into hardware selected address mode.
* hint:
It's useful to solve a possible address conflict by programming the I/O address as early as possible.
It is recommendable to set the address with a simple .SYS driver in a DOS environment.
3.2
ISA Plug and Play mode
To select ISA Plug and Play mode the pins MODE and ALE must both be connected to GND. The HFC-
SP needs two consecutive addresses in the I/O map of a PC for operation. Usually also one IRQ line is
used. The following section describes how to configure the HFC-SPs interrupts.
3.2.1 IRQ assignment
The IRQ lines are disabled after a hardware reset.
The IRQ assigned by the PnP BIOS can be read from register CHIP_ID (16h), bits [3:0]. Bits [2:0] of the
CIRM register have to be set according to the hardware wiring on the PCB and the IRQ number assigned
by the PnP BIOS.
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3.2.2 ISA Plug and Play control registers
3.2.2.1 Card level control regsisters
Plug and Play Read Accessable in state
control register Write
address
Description
00h
w
Isolation state
Set read data port address register. Bits[7:0]
become bits[9:2] of the port's I/O address. Bits[11:10]
are hardwired to 00b and bits[1:0] are hardwired to
11b.
Config state *)
01h
02h
r
Isolation state
Serial isolation register. Used to read the serial
identifier during the card isolation process.
Configuration control register. Bits[7:3] are
reserved and must be zero. The defined bits are:
w
Sleep state,
Isolation state,
Config state
0
Reset Bit. When set to one, resets all of the
card's configuration registers to their default
state. The CSN is not affected.
1
Return to wait for key state. When set to one,
all cards return to wait for key state.
Their CSNs and configuration registers are not
affected. This command is issued after all cards
have been configured and activated.
2
Reset CSN to zero. When set to one, all cards
reset their CSN to zero.
All bits are automatically cleared by the hardware.
Wake command register. Writing a CSN to this
register has the following effects:
03h
w
Sleep state,
Isolation state,
Config state
-
If the value written is 00h, all cards in the sleep
state with a CSN=00h go to the isolation state.
Any card in configure state (CSN not 00h) goes
to the sleep state.
-
If the value written is not 00h, any card in the
sleep state with a matching CSN goes to
configure state. Any card in the isolation state
goes to sleep state.
Any write to a card's wake command register with a
match on its CSN causes the pointer to the serial
identifier / resource data to be reset to the first byte of
the serial identifier.
*)
This is an extension to the Plug and Play Specification
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Plug and Play Read Accessable in state
control register Write
address
Description
04h
r
Config state
Resource data register. This register is used to read
the device's recource data. Each time that a read is
performed from this register a byte of the resource
data is returned and the resource data pointer is
incremented. Prior to reading each byte, the
programmer must read from the status register to
determine if the next byte is available for reading
from the resource data register.
The card's serial identifier and checksum must be read
prior to accessing the resource requirement list via
this register.
05h
06h
r
Config state
Status register. Prior to reading the next byte of the
device's resource data, the programmer must read
from this register and check bit 0 for a one. This is the
resource data byte available bit. Bits[7:1] are
reserved.
Card select number (CSN) register. The
configuration software uses the CSN register to assign
a unique ID to the card. The CSN is then used to wake
up the card's configuration logic whenever the
configuration program must access its configuration
registers.
Isolation state*),
Config state
r/w
07h
r
Config state
Logical device number register. The number in this
register points to the logical device the next
commands will operate on. The HFC-SP only
supports one logical device. This register is hardwired
to all zeros.
*)
only if the isolation process is finished; the last card remains in isolation state until a CSN is
assigned.
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3.2.2.2 Logical device control registers
Plug and Play Read Accessable in state
control register Write
address
Description
30h
r/w
Config state
Activate register. Setting bit 0 to a one activates the
card on the ISA bus. When cleared, the card cannot
respond to any ISA bus transactions (other than
accesses to its Plug and Play configuration ports).
Reset clears bit 0. Bits[7:1] are reserved and return
zeros when read.
The HFC-SP only supports one logical device, so it is
not necessary to write the logical device number into
the card's logical device number register prior to
writing to this register.
31h
r/w
Config state
I/O range check register.
Bit(s) Description
7:2
1
Reserved, return zero when read
When set to one, enables I/O range checking
and disables it when cleared to zero. When
enabled, bit 0 is used to select a pattern for the
logical device to return.
This bit is only valid if the logical device is
deactivated (see Activate register).
When set, the logical device returns 55h in
response to any read from the logical device's
assigned I/O space. When cleared, AAh is
returned.
0
3.2.3 ISA Plug and Play configuration registers
3.2.3.1 I/O port configuration registers
Plug and Play Read Accessable in state
configuration Write
Description
register address
60h
r/w
r/w
Config state
Config state
I/O decoder 0 base address upper byte.
I/O port base address bits[15:8]. *)
I/O decoder 0 base address lower byte.
I/O port base address bits[7:0]. *)
61h
*)
Only bits[11:0] are checked by the HFC-SP's internal address decoder in PnP mode.
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3.2.3.2 Interrupt configuration registers
Plug and Play Read Accessable in state
configuration Write
Description
register address
70h
r/w
r/w
Config state
Config state
IRQ select configuration register 0.
Bits[3:0] specify the sleceted IRQ number.
Bits[7:4] are reserved.
IRQ type configuration register 0.
Bits[1:0] are ignored.
71h
Bits[7:2] are reserved.
* important!
All registers not implemented return 00h when read except the DMA configuration registers 74h
and 75h. These two registers return 04h when read. This means no DMA channel has been
selected.
3.2.4 Writing the Plug and Play configuration EEPROM
The EEPROM Writing Spec. is only available on special request to avoid destruction of configuration
information by not authorized programs or software viruses.
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3.3
ISA-PC bus interface
The HFC-SP only uses 2 I/O addresses with SA0 switching between data or control information in ISA-
PC mode and ISA Plug and Play mode. As normal only 10 bits of the ISA-PC bus address are used for
I/O address selection in ISA-PC mode. In ISA Plug and Play mode 12 bits are decoded by the address
decoder.
SA0
X
X
0
/IOR
/IOW
/AEN
Operation
no access
X
1
0
1
0
1
X
1
1
0
1
0
1
X
0
no access
read data
0
0
write data
read status
write control
1
0
1
0
X = don't care
* important!
ALE must be connected to GND and at least one of the IIOSEL0-3 must be '1' or open!
The HFC-SP has no memory or DMA access to any component on the ISA-PC bus.
Because of its power drive characteristic it needs no external driver for the ISA-PC bus data lines.
If necessary an external bus driver can be added. In this case the output BUSDIR determines the driver
direction.
BUSDIR = 1 means that data is driven into the HFC-SP;
BUSDIR = 0 means that the HFC-SP is read and data is driven to the external bus.
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3.4
Processor mode
Processor mode is selected by MODE = NC and IIOSEL0..3=0.
In the microprocessor mode the HFC-SP uses 256 I/O addresses (SA0 - SA7).
/IOR
/IOW
/CS
ALE
Operation
Mode
/DS
X
1
0
0
0
1
0
1
R/W
X
1
1
0
1
0
1
0
1
X
0
0
0
0
0
0
X
X
1
1
0
no access
no access
read data
write data
read data
write data
read data
write data
all
all
2
2
3
3
4
4
0
0*)
0*)
X = don't care
*) 1-pulse latches I/O address.
All registers are directly accessable by their I/O address (see register description).
Except in mode 4 ALE is assumed to be stable after a RESET.
* important!
For write accesses to the HFC-SP the data lines must be stable and valid before /IOW or /DS get
low (see also: Timing diagram 1 on page 59). With Intel compatible processors it may be
neccessary to delay the /IOW or /DS signals.
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3.4.1 DMA access in processor mode
In processor mode a simple DMA access to the auxiliary channels of the GCI/IOM2 interface is possible.
This is useful for tone synthetisation or for voice recording. DMAREQ is asserted every 125µs.
DMAREQ is reset when /DMAAK is active.
* note
If DMA acknowledge signals /DMAAK0 and /DMAAK1 are active, the function of the read/write
enables is inverted. This means a read command on the controller databus writes the AUX-
Channel register and a write command reads the register. The address on the address bus (SA0-
SA7) is ignored.
Mode
/DMAAK0
/DMAAK1 /CS ALE /IOR /IOW Function
/DS R/W
2,3,4
1
0
1
0
1
0
1
1
1
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
0
X
1
1
1
1
1
1
no DMA
2
2
3
3
4
4
1
DMA write AUX1
DMA write AUX2
DMA write AUX1
DMA write AUX2
DMA write AUX1
DMA write AUX2
1
0
0
0
0*)
0*)
0
0
Table 3: DMA access in processor mode
*) 1-pulse latches I/O address.
* important!
If DMA is not used /DMAAK0 and /DMAAK1 must be connected to VDD.
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3.5
PCMCIA mode
3.5.1 Internal HFC-SP register selection
The HFC-SP occupies two consecutive addresses in the I/O map. The base I/O address must be 2 byte
aligned so the lower of both addresses is the one with SA0 = 0 and the higher address is the one with
SA0 = 1. The lines SA1 to SA11 are don't care. The registers of the HFC-SP are selected by writing the
registers' address to the higher I/O address (SA0=1). Registers are read/written by reading/writing the
base I/O address (SA0=0).
3.5.2 Attribute memory
After hardware reset the card's information structure (CIS) is copied from the EEPROM to even
numbered addresses of the SRAM starting with 0000h (288 byte are occupied for the CIS). To avoid
accesses in this phase the /WAIT signal is active.
3.5.3 PCMCIA registers
Configuration Option Register (COR):
Register address: 400h in Configuration Memory
D7
SRESET
D6
LevIREQ
1
D5
D4
D3
D2
D1
D0
Configuration Index
The fields are as follows:
SRESET
SRESET card. Setting this bit to one places the card in the reset state. This bit
must be cleared to zero by the user.
LevIREQ
This bit is not implemented and returns always 1 when read to indicate usage of
level mode interrupts.
Configuration Index
Configuration Index.
Bit 0 must be set to 1 to enable I/O accesses to the HFC-SP.
Bit 5 must be set to 1 to write data to the EEPROM.
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Card Configuration and Status Register (CSR): Register address: 402h in Configuration Memory
D7
Changed
0
D6
SigChg
0
D5
IOis8
1
D4
Rsvd
0
D3
Audio
0
D2
PwrDwn
0
D1
Intr
D0
Rsvd
0
The fields are as follows:
Changed
SigChg
Rsvd
Unimplemented and return 0 when read.
Audio
PwrDwn
IOis8
Unimplemented and return 1 when read to indicate an 8 bit data path.
Internal state of interrupt request (IREQ).
Intr
3.5.4 CIS programming
The EEPROM Programming Spec. is only available on special request to avoid destruction of
configuration information by not authorized programs or software viruses.
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3.6
Internal HFC-SP register description
In ISA-PC mode, ISA Plug and Play mode and PCMCIA mode all registers are selected by writing the
register address into the Control Internal Pointer (CIP) register. This is done by writing the HFC-SP on
the higher I/O address (SA0 = 1).
All consecutive read or write data accesses (SA0 = 0) are done with the selected register until the CIP
register is changed.
In processor mode all registers can be directly accessed. The registers are selected by SA0 - SA7.
3.6.1 FIFO control registers
The FIFO control registers are used to select and control the FIFOs of the HFC-SP. In processor mode
the value is the address which directly selects the corresponding register.
The FIFO register selection is independent of the B- or D-channel FIFO number.
The FIFO is selected by the FIFO select register.
3.6.1.1 FIFO select register
CIP / I/O-address Name
r/w
Function
00010000 10h
FIF_SEL
w
FIFO selection
3.6.1.2 FIFO registers
CIP / I/O-address Name
r/w
Function
100000xx 80h
100001xx 84h
100010xx 88h
100011xx 8Ch
101010xx A8h
101011xx ACh
101100xx B0h
101101xx B4h
101110xx B8h
101111xx BCh
FIF_Z1L
FIF_Z1H
FIF_Z2L
FIF_Z2H
FIF_INC_F1*)
FIF_DWR
FIF_F1
r
r
r
r
r
w
r
r
r
FIFO input counter (Z1) low byte
FIFO input counter (Z1) high byte
FIFO output counter (Z2) low byte
FIFO output counter (Z2) high byte
read this register to increment frame counter F1
data write into FIFO and increment Z1
FIFO input HDLC frame counter (F1)
FIFO output HDLC frame counter (F2)
read this register to increment frame counter F2
data read out of FIFO and increment Z2
FIF_F2
FIF_INC_F2*)
FIF_DRD
r
*)
only in HDLC mode; In transparent mode (see also: 3.9.2) the frame counters F1 and F2 must
not be incremented.
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* important!
FIFO change, FIFO reset and F1/F2 incrementation
Changing the FIFO, reseting the FIFO or incrementing the frame counters causes a short BUSY
period of the HFC-SP. This means an access to FIFO control registers is NOT allowed until BUSY
status is reset (bit 0 of STATUS register). This has a maximum duration of 25 clock cycles (2µs).
Status, interrupt and control registers can be read and written at any time.
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3.6.2 Registers of the S/T section
CIP / I/O-address Name
r/w
r/w
w
Function
00110000 30h
00110001 31h
00110010 32h
00110011 33h
00110100 34h
STATES
SCTRL
State of the TE/NT state machine
S/T control register
SCTRL_E
SCTRL_R
w
S/T control register (extended)
receive enable for B-channels
w
SQ_REC
r
w
receive register for S/Q bits
send register for S/Q bits
SQ_SEND
00110111 37h
CLKDEL
w
setup of the delay time between receive and
send direction (TE)
receive data sample time (NT)
00111100 3Ch
00111101 3Dh
00111110 3Eh
B1_REC*)
r
w
B1-channel receive register
B1-channel transmit register
B1_SEND*)
B2_REC*)
r
w
B2-channel receive register
B2-channel transmit register
B2_SEND*)
D_REC*)
r
w
D-channel receive register
D-channel transmit register
D_SEND*)
00111111 3Fh
E_REC*)
r
E-channel receive register
*)
These registers are read/written automatically by the HDLC FIFO controller (HFC) or
GCI/IOM2 bus controller and need not be accessed by the user. To read/write data the FIFO
registers should be used.
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3.6.3 Registers of the GCI/IOM2 bus section
GCI/IOM2 bus timeslot selection registers
CIP / I/O-address Name
r/w
Function
00000010 02h
00000011 03h
C/I
TRxR
r/w
r
C/I command/indication register
Monitor Tx ready handshake
00001010 0Ah
00001011 0Bh
MON1_D
MON2_D
r/w
r/w
first monitor byte
second monitor byte
GCI/IOM2 bus timeslot selection registers
CIP / I/O-address Name
r/w
Function
00100000 20h
00100001 21h
B1_SSL
B2_SSL
w
w
B1-channel transmit slot (0..31)
B2-channel transmit slot (0..31)
00100010 22h
00100011 23h
AUX1_SSL
AUX2_SSL
w
w
AUX1-channel transmit slot (0..31)
AUX2-channel transmit slot (0..31)
00100100 24h
00100101 25h
B1_RSL
B2_RSL
w
w
B1-channel receive slot (0..31)
B2-channel receive slot (0..31)
00100110 26h
00100111 27h
AUX1_RSL
AUX2_RSL
w
w
AUX1-channel receive slot (0..31)
AUX2-channel receive slot (0..31)
GCI/IOM2 bus data registers
CIP / I/O-address Name
r/w
Function
00101000 28h
00101001 29h
B1_D*)
B2_D*)
r/w
r/w
GCI/IOM2 bus B1-channel data register
GCI/IOM2 bus B2-channel data register
00101010 2Ah
00101011 2Bh
AUX1_D**)
AUX2_D**)
r/w
r/w
AUX1-channel data register
AUX2-channel data register
*)
These registers are read/written automatically by the HDLC FIFO controller (HFC) or by the
S/T controller and need not be accessed by the user.
**)
These registers can also be accessed by DMA
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GCI/IOM2 bus configuration registers
CIP / I/O-address Name
r/w
Function
00101101 2Dh
00101110 2Eh
00101111 2Fh
MST_EMOD w
MST_MODE w
CONNECT
extended mode register for GCI/IOM2 bus
mode register for GCI/IOM2 bus
w
connect functions for S/T, HFC, GCI/IOM2
3.6.4 Interrupt and status registers
CIP / I/O address Name r/w
Function
00010010 12h
00010011 13h
00010110 16h
00011000 18h
00011001 19h
TRM
w
w
r
transparent mode interrupt mode register
mode of B-channels
B_MODE
CHIP_ID
CIRM
register for chip and PnP interrupt identification
interrupt selection and softreset register
transparent mode and timer control register
w
w
CTMT
00011010 1Ah
00011011 1Bh
INT_M1
INT_M2
w
w
interrupt mask register 1
interrupt mask register 2
00011110 1Eh
00011111 1Fh
INT_S1
INT_S2
r
r
interrupt status register 1
interrupt status register 2
00011100 1Ch
STATUS
r
common status register
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3.7
Timer
The HFC-SP includes a timer with interrupt capability. The timer counts F0IO pulses. So the timer
counter is incremented every 125µs. It can be reset by bit 7 of of the CTMT register. Furthermore the
timer is reset at every HFC-SP access when bit 5 of the CTMT register is set. Seven different timer
values can be selected.
3.8
Watchdog
(only available in processor mode)
The watchdog outputs of the HFC-SP are activated if the timer interrupt bit is active (not reset by reading
INT_S1) and the timer elapses a second time.
The reset of the timer counter itself and the watchdog value can be programmed in the CTMT register. In
automatic reset mode the watchdog/timer is reset by every access to the HFC-SP.
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3.9
FIFOs
There are 6 FIFOs with 6 HDLC-Controllers in the HFC-SP. The HDLC circuits are located on the S/T
device side of the HFC-SP. So always plain data is stored in the FIFO. Zero insertion and deletion is
done in HDLC mode:
– if the data goes to the S/T or GCI/IOM device in send FIFOs and
– when the HDLC data comes from the S/T device or GCI/IOM2 bus in receive operation.
There are a send and a receive FIFO for each of the two B-channels and for the D-channel.
The FIFOs are realized as ring buffers in the external SRAM. To control them there are some counters.
B-channel D-channel
Z1: FIFO input counter
Z2: FIFO output counter 13 Bit
13 Bit
9 Bit
9 Bit
Each counter points to a byte position in the SRAM. On a FIFO input operation Z1 is incremented. On an
output operation Z2 is incremented.
After every pulse on the F0IO signal two HDLC-bytes are written into the S/T interface (FIFOs No. 0
and 2) and two HDLC-bytes are read from the S/T interface (FIFOs No. 1 and 3).
D-channel data is handled in a similar way but only 2 bits are processed.
* important!
Instead of the S/T interface also GCI/IOM2 bus is selectable for each B-channel (see CONNECT
register).
If Z1 = Z2 the FIFO is empty.
Additionally there are two counters F1 and F2 for every FIFO channel (5Bit for B-channel, 4Bit for D-
channel). They count the HDLC-frames in the FIFOs and form a ring buffer as Z1 and Z2 do, too.
F1 is incremented when a complete frame has been received and stored in the FIFO. F2 is incremented
when a complete frame has been read from the FIFO.
If F1 = F2 there is no complete frame in the FIFO.
When the RESET line is active or software reset is active Z1, Z2, F1 and F2 are all initialized to all 1s.
The access to a FIFO is selected by writing the FIFO number into the FIFO select register (FIF_SEL).
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* important!
FIFO change, FIFO reset and F1/F2 incrementation
Changing the FIFO, reseting the FIFO or incrementing the frame counters causes a short BUSY
period of the HFC-SP. This means an access to FIFO control registers is NOT allowed until BUSY
status is reset (bit 0 of STATUS register). This has a maximum duration of 25 clock cycles (2µs).
Status, interrupt and control registers can be read and written at any time.
* important!
The counter state 0200h of the Z-counters follows counter state 1FFFh in the B-channel FIFOs.
If 8k RAM mode is selected counter state 1A00h of the Z-counters follows counter state 1FFFh in
the B-channel FIFOs.
The counter state 000h of the Z-counters follows counter state 1FFh in the D-channel FIFOs.
The counter state 00h of the F-counters follows counter state 1Fh in the B-channel FIFOs.
The counter state 10h of the F-counters follows counter state 1Fh in the D-channel FIFOs.
3.9.1 FIFO channel operation
Figure 3: FIFO Organisation (shown for B-channel, similar for D-channel)
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3.9.1.1 Send channels (B1, B2 and D transmit)
The send channels send data from the host bus interface to the FIFO and the HFC-SP converts the data
into HDLC code and tranfers it from the FIFO into the S/T or/and the GCI/IOM2 bus interface write
registers.
The HFC-SP checks Z1 and Z2. If Z1=Z2 (FIFO empty) the HFC-SP generates a HDLC-Flag (01111110)
and sends it to the S/T device. In this case Z2 is not incremented. If also F1=F2 only HDLC flags are sent
to the S/T interface and all counters remain unchanged. If the frame counters are unequal F2 is
incremented and the HFC-SP tries to send the next frame to the output device. After the end of a frame
(Z2 reaches Z1) it automatically generates the 16 bit CRC checksum and adds the ending flag. If there is
another frame in the FIFO (F1≠F2) the F2 counter is incremented.
With every byte being sent from the host bus side to the FIFO Z1 is incremented automatically. If a
complete frame has been sent F1 must be incremented to send the next frame. If the frame counter F1 is
incremented also the Z-counters may change because Z1 and Z2 are functions of F1 and F2. So there are
Z1(F1), Z2(F1), Z1(F2) and Z2(F2) (see Figure 3).
Z1(F1) is used for the frame which is just written from the PC-bus side. Z2(F2) is used for the frame
which is just beeing transmitted to the S/T device side of the HFC-SP. Z1(F2) is the end of frame pointer
of the current output frame.
In the send channels F1 is only changed from the PC interface side if the software driver wants to say
„end of send frame“. Then the current value of Z1 is stored, F1 is incremented and Z1 is used as start
address of the next frame. Z1(F2) and Z2(F2) can not be accessed.
3.9.1.2 Automatically D-channel frame repetition
The D-channel send FIFO has a special feature. If the S/T interface signals a D-channel contention
before the CRC is sent the Z2 counter is set to the starting address of the current frame and the HFC-SP
tries to repeat the frame automatically.
important!
The HFC-SP begins to transmit the bytes from a FIFO at the moment the FIFO is changed or the
F1 counter is incremented. Also changing to the FIFO that is already selected starts the
transmission. So by selecting the same FIFO again transmission can be started.
3.9.1.3 FIFO full condition in send channels
Due to the limited number of registers in the HFC-SP the driver software must maintain a list of frame
start and end addresses to calculate actual FIFO size and check FIFO full condition. Because there are a
maximum of 32 frame counter values and the start address of a frame is the incremented value of the end
address of the last frame the memory table must have only 32 values of 16 bits (13 bits) instead of 64.
Remember that an increment of Z-value 1FFFh is 0200h in the B-channels!
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There are two different FIFO full conditions. The first one is met when the FIFO contents comes up to 31
frames (B-channel) or 15 frames (D-channel). There is no possibility for the HFC-SP to manage more
frames even if the frames are very small.
The second limitation is the size of the FIFO which is 512 byte for the D-channel and 7.5 KByte for the
B-channels.
3.9.1.4 Receive Channels (B1, B2 and D receive)
The receive channels receive data from the S/T or GCI/IOM2 bus interface read registers. The data is
converted from HDLC into plain data and sent to the FIFO. The data can then be read via the host bus
interface.
The HFC-SP checks the HDLC data coming in. If it finds a flag or more than 5 consecutive 1s it does not
generate any output data. In this case Z1 is not incremented. Proper HDLC data being received is
converted by the HFC-SP into plain data. After the ending flag of a frame the HFC-SP checks the HDLC
CRC checksum. If it is correct one byte with all 0s is inserted behind the CRC data in the FIFO named
STAT. This last byte of a frame in the FIFO is different from all 0s if there is no correct CRC field at the
end of the frame.
Figure 4: FIFO Data Organisation
The ending flag of a HDLC-frame can also be the starting flag of the next frame.
After a frame is received completely F1 is incremented by the HFC-SP automatically and the next frame
can be received.
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After reading a frame via the host bus interface F2 must be incremented. If the frame counter F2 is
incremented also the Z-counters may change because Z1 and Z2 are functions of F1 and F2. So there are
Z1(F1), Z2(F1), Z1(F2) and Z2(F2) (see Figure 3).
Z1(F1) is used for the frame which is just received from the S/T device side of the HFC. Z2(F2) is used
for the frame which is just beeing transmitted to the host bus interface. Z1(F2) is the end of frame pointer
of the current output frame.
To calculate the length of the current receive frame the software has to evaluate Z1-Z2+1. When Z2
reaches Z1 the complete frame has been read.
In the receive channels F2 must be incremented from the host interface side after the software detects an
end of receive frame (Z1=Z2) and F1 F2. Then the current value of Z2 is stored, F2 is incremented and
Z2 is copied as start address of the next frame. If Z1 = Z2 and F1 = F2 the FIFO is totally empty. Z1(F1)
can not be accessed.
important!
Before reading a FIFO a change FIFO operation (see also: FIF_SEL register) must be done even if
the desired FIFO is already selected. The change FIFO operation is required to update the internal
buffer of the HFC-SP. Otherwise the first byte of the FIFO will be taken from the internal buffer
and may be invalid.
3.9.1.5 FIFO full condition in receive channels
Because the ISDN-B-channels and the ISDN-D-channels have no hardware based flow control there is no
possibility to stop input data if a receive FIFO is full.
So there is no FIFO full condition implemented in the HFC-SP. The HFC-SP assumes that the FIFOs are
so deep that the host processor hard- and software is able to avoid any overflow of the receive FIFOs.
Overflow conditions are again more than 31 input frames (15 frames for D-channel) or a real overflow of
the FIFO because of excessive data.
Because HDLC procedures only know a window size of 7 frames no more than 7 frames are sent without
software intervention. Due to the great size of the FIFOs of the HFC-SP it is easy to poll the HFC-SP
even in large time intervalls without having to fear a FIFO overflow condition.
However to avoid any undetected FIFO overflows the software driver should check the number of frames
in the FIFO which is F1-F2. An overflow exists if the number (F1-F2) is less than the number in the last
reading even if there was no reading of a frame in between.
After a detected FIFO overflow condition this FIFO must be reset by setting the FIFO reset bit in the
CIRM register.
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3.9.1.6 FIFO reset
All counters Z1, Z2, F1 and F2 of all FIFOs are initialized to all 1s after a RESET.
Then the result is Z1 = Z2 = 1FFFh and F1 = F2 = 1Fh for the B-channels
and Z1 = Z2 = 1FFh and F1 = F2 = 1Fh for the D-channel.
Please mask bit 4 of D-channel from counter F1, F2.
The same initialisation is done if the bit 3 in the CIRM register is set (soft reset).
Individual FIFOs can be reset by bit 7 of CIRM register.
3.9.2 Transparent mode of HFC-SP
You can switch off HDLC operation for each B-channel independently. There is one bit for each B-
channel in the CTMT control register. If this bit is set data in the FIFO is sent directly to the S/T or
GCI/IOM2 bus interface and data from the S/T or GCI/IOM2 bus interface is sent directly to the FIFO.
Be sure to switch into transparent mode only if F1=F2. Being in transparent mode the Fx counters remain
unchanged. Z1 and Z2 are the input and output pointers respectively. Because F1=F2 both Z-counters are
always accessable and have valid data.
Because always one Z-counter is changed by the HFC-SP and only 8 bits of a counter can be read at a
time the counter should be read twice to check for a counter incrementation between low and high byte
accesses.
If a send FIFO channel changes to FIFO empty condition no CRC is generated and the last data byte
written into the FIFO is repeated until there is new data.
In receive channels there is no check on flags or correct CRCs and no status byte is added.
The byte bounderies are not arbitrary like in HDLC mode where byte synchronisation is achieved with
HDLC-flags. The data is just the same as it comes from the S/T or GCI/IOM2 bus interface or is sent to
this.
Send and receive transparent data can be handled in two ways. The usual way is tranporting B-channel
data with the LSB first as it is usual in HDLC mode. The second way is sending the bytes in reverse bit
order as it is usual for PWM data. So the first bit is the MSB. The bit order can be reversed by setting bit
7 of the FIF_SEL register when the FIFO is selected.
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3.10 External SRAM
For the FIFO data an 32K x 8 external SRAM is used. A 8K x 8 external SRAM is also possible but not
recommended.
The required access time is 80 ns or below. For the double clock mode (24.576 MHz) it is 40ns or below.
1024 Bytes of the external SRAM are reserved for internal HFC-SP use.
External SRAM
B-channel FIFO size
per channel and direction
1536 Bytes
D-channel FIFO size
per direction
512 Bytes
8K x 8
32K x 8
7680 Bytes
512 Bytes
Table 4: SRAM and FIFO size
To initialise the HFC-S for 8K x 8 SRAM use:
- write 18h to the CIRM register
- wait at least 4 clock cycles
- write 10h to the CIRM register
For all further accesses to the CIRM register bit 4 must be set.
hint!
If you connect the HFC-SP with the SRAM you can simplify PCB layout if you permutate address
lines and data lines. If you connect data lines of the SRAM with data lines of the HFC-SP and SR-
address lines of the HFC-SP with address lines of the SRAM you can do this in any order.
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3.11 Connecting an external device to the HFC-SP
It is possible to connect an external device parallel to the SRAM to the HFC-SP.
Figure 5: Connecting an external device to the HFC-SP
The external device is accessed when bit 6 in the CIP is set. Then bit[5:0] are the address select lines for
the external device.
3.12 Power down considerations
For very low power consumption the oscillator of the HFC-SP can be stopped. Furthermore the external
SRAM is disabled (/SR_CS=1). To avoid current generated by floating inputs the data bus of the SRAM
and all other inputs must be put to GND or VDD. So it is useful to connect the SRAM data bus to a
resistor array of about 1MΩ. If the HFC-SP is operated in processor mode the unused interrupt lines (and
watchdog lines) should not be left open. They should be connected to VDD or GND over a resistor to
reduce current.
If the oscillator is stopped and the awake option is disabled the supply current is reduced to less than
1mA.
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3.13 Configuring test loops
For electrical tests of layer 1 it is useful to create a S/T test loop for the B1/B2 channel. The test loop
described here transmits the data that has been received on the B1 or B2 channel to the same channel on
the S/T interface. To configure this loop the following must be done:
- write 0Fh to register CLKDEL (37h)
// Adjust the phase offset between receive and
// transmit direction (value depends on the external
// circuitry).
- write 43h to register SCTRL (31h)
// 03h is to enable B1, B2 at the S/T interface for
// transmission
// 40h is for TX_LO setup (capacitive line mode)
- write 00h to register STATES (30h)
- write 03h to register SCTRL_R (33h)
- write 36h to register CONNECT (2Fh)
- write 80h to register B1_SSL (20h)
- write C0h to register B1_RSL (24h)
- write 81h to register B2_SSL (21h)
- write C1h to register B2_RSL (25h)
// Release S/T state machine for activation over the
// S/T interface by incoming INFO 2 or INFO 4.
// Configure S/T B1 and B2 channel to normal
// receive operation.
// Configure CONNECT register for B1/B2 channel
// test loop.
// Enable transmit channel for GCI/IOM2 bus, pin
// STIO1 is used as output, use time slot #0.
// Enable receive channel for GCI/IOM2 bus, pin
// STIO1 is used as input, use time slot #0.
// Enable transmit channel for GCI/IOM2 bus, pin
// STIO1 is used as output, use transmission slot #1.
// Enable receive channel for GCI/IOM2 bus, pin
// STIO1 is used as input, use time slot #1.
- write 01h to register MST_MODE (2Eh) // Configure HFC-SP as GCI/IOM2 bus master.
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4 Register bit description
4.1
Register bit description of the FIFO select register
Name
Addr. Bits r/w Function
FIF_SEL
10h
2..0
w
select FIFO and operation
bit 2 bit 1 bit 0 selected operation
0
0
0
0
1
1
0
0
1
1
x
x
0
1
0
1
0
1
B1 transmit
B1 receive
B2 transmit
B2 receive
D transmit
D receive
6..3
7
unused, should be '0'
select data transmission bit order
w
'0'
'1'
normal read/write data operation
reverse bit order read/write data operation
4.2
Register bit description of S/T section
Addr. Bits r/w Function
Name
STATES
30h
3..0
r
r
r
binary value of actual state (NT: Gx, TE: Fx)
(read)
4
Frame-Sync ('1'=synchronized)
5
'1' timer T2 expired (NT mode only, see also 8.1 S/T interface
activation/deactivation layer 1 for finite state matrix for NT
on page 71)
6
7
r
r
'1' receiving INFO0
'0' no operation
'1' in NT mode allows transition from G2 to G3.
This bit is automatically cleared after the transition.
binary value of new state (NT: Gx, TE: Fx)
(bit 4 must also be set to load the state).
'1' loads the prepared state (bit 3..0) and stops the state
machine.This bit needs to be set for a minimum period of
5.21 s and must be cleared by software. (reset default)
'0' enables the state machine (bits 3..0 are ignored).
After writing an invalid state the state machine goes to
deactivated state (G1, F2)
STATES
(write)
30h
3..0
4
w
w
6..5
7
w
w
'00' no operation
'01' no operation
'10' start deactivation
'11' start activation
The bits are automatically cleared after activation/deactivation.
'0' no operation
'1' in NT mode allows transition from G2 to G3.
This bit is automatically cleared after the transition.
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* important!
The state machine is stuck to '0' after a reset. Writing a '0' to bit 4 of the STATES register restarts
the state machine.
In this state the HFC-SP sends no signal on the S/T-line and it is not possible to activate it by
incoming INFOx.
NT mode:
The NT state machine does not change automatically from G2 to G3 if the TE side sends INFO3
frames. This transition must be activated each time by bit 7 of the STATES register.
Fix the NT state machine to state G3 when activated (by writing 13h into STATES register). This
prevents deactivation of NT mode S/T interface due to sporadically errors on NT input data.
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Name
Addr. Bits r/w Function
SCTRL
31h
0
1
2
3
4
w
w
w
w
w
'0' B1 send data disabled (permanent 1 sent in activated states,
reset default)
'1' B1 data enabled
'0' B2 send data disabled (permanent 1 sent in activated states,
reset default)
'1' B2 data enabled
S/T interface mode
'0' TE mode (reset default)
'1' NT mode
D-channel priority
'0' high priority 8/9 (reset default)
'1' low priority 10/11
S/Q bit transmission
'0' S/Q bit disable (reset default)
'1' S/Q bit and multiframe enable
'0' normal operation (reset default)
'1' send 96kHz transmit test signal (alternating zeros)
TX_LO line setup
5
6
w
w
This bit must be configured depending on the used S/T module
and circuitry to match the 400Ω pulse mask test.
'0' capacitive line mode (reset default)
'1' non capacitive line mode
Power down
'0' power up, oscillator active (reset default)
'1' power down, oscillator stopped
This bit is not cleared by a soft reset.
Power down mode bit
7
0
w
w
SCTRL_E
32h
'0' S/T awake disable (reset default)
Power up can only be programmed by register access
(SCTRL bit 7).
'1' S/T awake enable. Oscillator starts on every non INFO0
S/T signal.
1
2
w
w
must be '0'
D reset
'0' normal operation (reset default)
'1' D bits are forced to '1'
3
4
w
w
D_U enable
'0' normal operation (reset default)
'1' D channel is always send enabled regardless of E receive
bit
force E=0 (NT mode)
'0' normal operation (reset default)
'1' E-bit send is forced to 0
must be '0'
6..5
7
w
w
'1' swap B1 and B2-channel in the S/T interface
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Name
Addr. Bits r/w Function
SCTRL_R
33h
0
1
w
w
B1-channel receive enable
B2-channel receive enable
'0' B-receive bits are forced to '1'
'1' normal operation
unused
TE mode: S bits (bit 3 = S1, bit 2 = S2, bit 1 = S3, bit 0 = S4)
NT mode: Q bits (bit 3 = Q1, bit 2 = Q2, bit 1 = Q3,
bit 0 = Q4)
7..2
3..0
w
r
SQ_REC
34h
4
r
'1' a complete S or Q multiframe has been received
Reading SQ_REC clears this bit.
6..5
7
r
r
not defined
'1' ready to send a new S or Q multiframe
Writing to SQ_SEND clears this bit.
TE mode: Q bits (bit 3 = Q1, bit 2 = Q2, bit 1 = Q3,
bit 0 = Q4)
SQ_SEND
CLKDEL
34h
37h
3..0
w
NT mode: S bits (bit 3 = S1, bit 2 = S2, bit 1 = S3, bit 0 = S4)
not defined
w TE: 4 bit delay value to adjust the 2 bit delay time between
receive and transmit direction. The delay of the external
S/T-interface circuit can be compensated. The lower the
value the smaller the delay between receive and transmit
direction (see also Figure 12)
7..4
3..0
w
NT: Data sample point. The lower the value the earlier the
input data is sampled.
The steps are 163ns.
6..4
w
w
NT mode only
early edge input data shaping
Low pass characteristic of extended bus configurations can be
compensated. The lower the value the earlier input data pulse is
sampled. No compensation means a value of 6 (110b). Step size
is the same as for bits 3-0.
7
unused
* note!
The register is not initialized with a '0' after reset. The register should be initialized as follows
before activating the TE/NT state machine:
TE mode: 0Dh .. 0Fh
NT mode: 6Ch
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4.3
Register bit description of GCI/IOM2 bus section
Timeslots for transmit direction
Name
Addr. Bits r/w Function
B1_SSL
B2_SSL
AUX1_SSL
AUX2_SSL
20h
21h
22h
23h
4..0
5
6
w
w
w
select GCI/IOM2 bus transmission slot (0..31)
unused
select GCI/IOM2 bus data lines
'0' STIO1 output
'1' STIO2 output
7
w
transmit channel enable for GCI/IOM2 bus
'0' disable (reset default)
'1' enable
* important!
Enabling more than one channel on the same slot causes undefined output data.
Timeslots for receive direction
Name
Addr. Bits r/w Function
B1_RSL
B2_RSL
AUX1_RSL
AUX2_RSL
24h
25h
26h
27h
4..0
5
6
w
w
w
select GCI/IOM2 bus receive slot (0..31)
unused
select GCI/IOM2 bus data lines
'0' STIO2 is input
'1' STIO1 is input
7
w
receive channel enable for GCI/IOM2 bus
'0' disable (reset default)
'1' enable
Data registers
Name
Addr. Bits r/w Function
B1_D
B2_D
AUX1_D
AUX2_D
28h
29h
2Ah
2Bh
0..7 r/w read/write data registers for selected timeslot data
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* note!
Auxiliary channel handling
If the data registers AUX1_D and AUX2_D are not overwritten, the transmisson slots AUX1_SSL
and AUX2_SSL mirror the data received in AUX1_RSL and AUX2_RSL slots. This is useful for
an internal connection between two CODECs. This mirroring is disabled by setting bit 1 in
MST_EMOD register.
In ISA, ISA-PnP and PCMCIA mode: To use the AUX1 channel the address pin SA8 must be '1'
at every access to the HFC-SP. To use the AUX2 channel the address pin SA9 must be '1' at every
access to the HFC-SP. The PnP information must be set accordingly.
Name
MST_MODE
Addr. Bits r/w Function
2Eh
0
w
w
w
w
w
GCI/IOM2 bus mode
'0' slave (reset default) (C4IO and F0IO are inputs)
'1' master (C4IO and F0IO are outputs)
polarity of C4- and C2O-clock
'0' F0IO is sampled on negative clock transition
'1' F0IO is sampled on positive clock transition
polarity of F0-signal
1
2
'0' F0 positive pulse
'1' F0 negative pulse
3
duration of F0-signal
'0' F0 active for one C4-clock (244ns) (reset default)
'1' F0 active for two C4-clocks (488ns)
time slot for codec-A signal F1_A
'00' B1 receive slot
5, 4
'01' B2 receive slot
'10' AUX1 receive slot
'11' signal C2O → pin F1_A (C2O is 2048 kHz clock)
time slot for codec-B signal F1_B
'00' B1 receive slot
7, 6
w
'01' B2 receive slot
'10' AUX1 receive slot
'11' AUX2 receive slot
The pulse shape and polarity of the codec signals F1_A and F1_B is the same as the pulseshape of the
F0IO signal. The polatity of C2O can be changed by bit 1.
RESET sets register MST_MODE to all '0's.
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Name
Addr. Bits r/w Function
MST_EMOD
2Dh
0
w
slow down C4IO clock adjustment (see Figure 15)
'0' C4IO clock is adjusted in the 31th time slot twice for one
half clock cycle (reset default)
'1' C4IO clock is adjusted in the 31th time slot once for one
half clock cycle
1
w
enable/disable AUX channel mirroring
'0' mirror AUX receive to AUX transmit (reset default)
'1' disable AUX channel data mirroring
unused
2
5..3
w
w
select D-channel data flow (see also: CONNECT register)
destination
bit 3: '0' D-HFC
source
← D-S/T
'1' D-HFC
bit 4: '0' D-S/T
'1' D-S/T
bit 5: '0' D-GCI/IOM2
'1' D-GCI/IOM2
unused
← D-GCI/IOM2
← D-HFC
← D-GCI/IOM2
← D-HFC
← D-S/T
6
7
w
w
enable GCI/IOM2 write slots
'0' disable GCI/IOM2 write slots; slot #2 and slot #3 may be
used for normal data
'1' enables slot #2 and slot #3 as master, D- and C/I-channel
C/I
02h
03h
3..0 r/w on read: indication
on write: command
7..4
0
unused
reserved
TRxR
r
r
1
'1' Monitor transmitter ready
Writing on MON2_D starts transmisssion and resets this bit.
5..2
6
7
r
r
r
reserved
STIO2 in
STIO1 in
RESET sets register MST_EMOD to all '0's.
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4.4
Register bit description of CONNECT register
Addr. Bits r/w Function
Name
CONNECT
2Fh
2..0
5..3
7..6
w
w
w
select B1-channel data flow
destination
bit 0: '0' B1-HFC
'1' B1-HFC
bit 1: '0' B1-S/T
'1' B1-S/T
bit 2: '0' B1-GCI/IOM2 ← B1-HFC
'1' B1-GCI/IOM2 ← B1-S/T
select B2-channel data flow
destination
bit 3: '0' B2-HFC
'1' B2-HFC
bit 4: '0' B2-S/T
'1' B2-S/T
bit 5: '0' B2-GCI/IOM2 ← B2-HFC
'1' B2-GCI/IOM2 ← B2-S/T
unused
source
← B1-S/T
← B1-GCI/IOM2
← B1-HFC
← B1-GCI/IOM2
source
← B2-S/T
← B2-GCI/IOM2
← B2-HFC
← B2-GCI/IOM2
RESET sets CONNECT register to all '0's.
The following figure shows the different options for switching the B-channels with the CONNECT
register (similar for D-channel; see MST_EMOD register).
Figure 6: Function of the CONNECT register bits
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4.5
Register bit description of interrupt, status and control registers
Addr. Bits r/w Function
Name
CIRM
18h
2..0
w
select IRQ channel in PC mode
'000' IRQ disable
'001' IRQ_A
'010' IRQ_B
'011' IRQ_C
'100' IRQ_D
'101' IRQ_E
'110' IRQ_F
'111' IRQ_G (only in ISA PnP mode)
3
w
soft reset, similar as hardware reset; the registers CIP, CIRM
and CTMT are not changed so selected I/O address is kept in
ISA-PC mode. The reset is active until the bit is cleared.
'0' deactivate reset (reset default)
'1' activate reset
4
5
w
w
select memory
'0' 32K x 8 external RAM (reset default)
'1' 8K x 8 external RAM
external interrupt enable
'0' ext. interrupt disable, IRQ_A is output (reset default)
'1' ext. interrupt enable IRQ_A is input and ored to IRQ
output
6
7
w
w
double clock mode (24.576 MHz external oscillator required)
when set, all RAM accesses are double speed
FIFO reset
The currently selected FIFO is initialised. This bit is
automatically cleared.
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Name
Addr. Bits r/w Function
CTMT
19h
0
w
w
w
HDLC/transparent mode for B1-channel
'0' HDLC mode (reset default)
'1' transparent mode
HDLC/transparent mode for B2-channel
'0' HDLC mode (reset default)
'1' transparent mode
1
4..2
select timer and watchdog (bit 4 = MSB)
timer
'000' off
watchdog
off
'001' 3.125ms 6.25ms
'010' 6.25ms
'011' 12.5ms
'100' 25ms
'101' 50ms
'110' 400ms
'111' 800ms
12.5ms
25ms
50ms
100ms
800ms
1600ms
5
w
timer/watchdog reset mode
'0' reset timer/WD by CTMT bit 7 (reset default)
'1' automatically reset timer/WD at each access to HFC-SP
ignored
reset timer/WD
6
7
w
w
'1' reset timer/WD
This bit is automatically cleared.
CHIP_ID
B_MODE
16h
13h
3..0
r
IRQ assigned by the PnP BIOS
Bits [2:0] of the CIRM register must be set to the value
corresponding to the hardware connected IRQ lines.
These bits are only valid in ISA Plug and Play mode.
Chip identification
7..4
r
1001b
HFC-SP
1..0
2
w
w
unused
in 64 kbit/s mode: bit is ignored
in 56 kbit/s mode: value of the LSB in 7-bit mode
unused
56 kbit/s mode selection bit for B1-channel
'0' 64 kbit/s mode (reset default)
'1' 56 kbit/s mode
3
4
w
w
5
w
56 kbit/s mode selection bit for B2-channel
'0' 64 kbit/s mode (reset default)
'1' 56 kbit/s mode
6
7
w
w
'0' Data not inverted for B1-channel (reset default)
'1' Data inverted for B1-channel
'0' Data not inverted for B2-channel (reset default)
'1' Data inverted for B2-channel
Cologne
Chip
Name
Addr. Bits r/w Function
INT_M1
1Ah
0
1
2
3
4
5
6
7
w
w
w
w
w
w
w
w
interrupt mask for channel B1 in transmit direction
interrupt mask for channel B2 in transmit direction
interrupt mask for channel D in transmit direction
interrupt mask for channel B1 in receive direction
interrupt mask for channel B2 in receive direction
interrupt mask for channel D in receive direction
interrupt mask for state change of TE/NT state machine
interrupt mask for timer
For mask bits a '1' enables and a '0' disables interrupt. RESET clears all bits to '0'.
Name
INT_M2
Addr. Bits r/w Function
1Bh
0
1
w
w
w
w
w
w
w
interrupt mask for processing/non processing phase transition
interrupt mask for GCI I-change
2
3
4
interrupt mask for GCI monitor receive
enable for interrupt output ('1' = enable)
interrupt output is reversed
5
7..6
interrupt from external device is reversed
unused
For mask bits a '1' enables and a '0' disables interrupt. RESET clears all bits to '0'.
Name
TRM
Addr. Bits r/w Function
12h
1..0
w
interrupt in transparent mode is generated if Z1 in receive
FIFOs or Z2 in transmit FIFOs change from:
00: x xxxx x011 1111 → x xxxx x100 0000
01: x xxxx 0111 1111 → x xxxx 1000 0000
10: x xxx0 1111 1111 → x xxx1 0000 0000
11: x 0111 1111 1111 → x 1000 0000 0000
must be '0'
4..2
5
w
w
E → B2 receive channel
When set the E receive channel of the S/T interface is
connected to the B2 receive channel.
B1+B2 mode
6
7
w
w
'0' normal operation (reset default)
'1' B1+B2 are combined to one HDLC or transparent channel.
All settings for data shape and connect are derived from
B1.
IOM test loop
When set MST output data is looped to the MST input.
Cologne
Chip
Name
Addr. Bits r/w Function
INT_S1
1Eh
0
1
r
r
B1-channel interrupt status in transmit direction
B2-channel interrupt status in transmit direction
in HDLC mode:
'1' a complete frame has been transmitted, the frame counter
F2 has been incremented
in transparent mode:
'1' interrupt as selected in TRM register bits 1..0
D-channel interrupt status in transmit direction
'1' a complete frame was transmitted, the frame counter
F2 was incremented
2
r
3
4
r
r
B1-channel interrupt status in receive direction
B2-channel interrupt status in receive direction
in HDLC mode:
'1' a complete frame has been transmitted, the frame counter
F1 has been incremented
in transparent mode:
'1' interrupt as selected in TRM register bits 1..0
D-channel interrupt status in receive direction
'1' a complete frame was received, the frame counter
F1 was incremented
5
r
6
7
0
r
r
r
TE/NT state machine interrupt status
'1' state of state machine changed
timer interrupt status
'1' timer is elapsed
INT_S2
1Fh
processing/non processing transition interrupt status
'1' The HFC-SP has changed from processing to non
processing state.
1
2
7
r
r
r
GCI I-change interrupt
'1' a different I-value on GCI was detected
receiver ready (RxR) of monitor channel
'1' 2 monitor bytes have been received
unused, '0'
* important!
Reading the INT_S1 or INT_S2 register resets all active read interrupts in the INT_S1 or INT_S2
register. New interrupts may occur during read. These interrupts are reported at the next read of
INT_S1 or INT_S2.
All interrupt bits are reported regardless of the mask registers settings (INT_M1 and INT_M2).
The mask register settings only influence the interrupt output condition.
The interrupt output goes inactive during the read of INT_S1 or INT_S2. If interrupts occur during
this read the interrupt line goes active immediately after the read is finished. So processors with
level or transition triggered interrupt inputs can be connected.
Cologne
Chip
Name
Addr. Bits r/w Function
STATUS
1Ch
0
r
BUSY/NOBUSY status
'1' the HFC-SP is BUSY after initialising Reset FIFO,
increment F or change FIFO
'0' the HFC-SP is not busy, all accesses are allowed
processing/non processing status
1
2
r
r
'1' the HFC-SP is in processing phase (every 125µs)
'0' the HFC-SP is not in processing phase
processing/non processing transition interrupt status
'1' The HFC-SP has finished internal processing phase (every
125µs)
3
4
r
r
unused, '0'
timer status
'0' timer not elapsed
'1' timer elapsed
5
6
7
r
r
r
TE/NT state machine interrupt state
'1' state of state machine has changed
FRAME interrupt has occured (any data channel interrupt)
all masked D-channel and B-channel interrupts are "ored"
ANY interrupt
all masked interrupts are "ored"
Reading the STATUS register clears no bit.
Cologne
Chip
5 Electrical characteristics
Absolute maximum ratings
Parameter
Symbol
Rating
Supply voltage
Input voltage
Output voltage
Operating temperature
Storage temperature
VDD
VI
VO
Topr
Tstg
-0.3V to +7.0V
-0.3V to VCC + 0.3V
-0.3V to VCC + 0.3V
-10°C to +85°C
-40°C to +125°C
Recommended operating conditions
Parameter
Supply voltage
Symbol
VDD
Condition
VDD=5V
VDD=3.3V
MIN. TYP. MAX.
4.75V 5.0V
3.15V 3.3V
0°C
5.25V
3.45V
+70°C
Operating temperature
Supply current
normal
Topr
IDD
fCLK=12.288MHz
DD = 5V, running oscillator:
V
V
25mA
8mA
< 1mA
DD = 3.3V, running oscillator:
power down
oscillator stopped*):
*)
see also: 3.12 Power down considerations
Electrical characteristics for 5V power supply
VDD = 4.75V to 5.25V, Topr = 0°C to +70°C
Parameter
Symbol
Condition
TTL level
CMOS level
MIN. TYP. MAX. MIN. TYP. MAX.
Input LOW voltage
Input HIGH voltage
Output LOW voltage
Output HIGH voltage
Output leakage current
Pull-up resistor input
current
VIL
VIH
VOL
VOH
| IOZ
| IIL |
0.8V
0.4V
10µA
1.0V
0.4V
10µA
2.0V
4.3V
3.5V
4.3V
|
High Z
VI = VSS
50µA
50µA
Electrical characteristics for 3.3V power supply
VDD = 3.15V to 3.45V, Topr = 0°C to +70°C
Parameter
Symbol
Condition
TTL level
CMOS level
MIN. TYP. MAX. MIN. TYP. MAX.
Input LOW voltage
Input HIGH voltage
Output LOW voltage
Output HIGH voltage
VIL
VIH
VOL
VOH
0.8V
1.0V
2.0V
2.4V
2.3V
2.4V
0.4V
0.4V
Cologne
Chip
I/O Characteristics
Input
IIOSEL0-3
SA0-9
/AEN
Interface Level
TTL, internal pull-up resistor
TTL
TTL
/IOR
TTL
/IOW
TTL
BD0-7
ALE
TTL
TTL
SRD0-7
C4IO
F0IO
STIO1-2
IRQ_A
/OE
/WE
/REG
RESET
TTL
TTL, internal pull-up resistor
TTL, internal pull-up resistor
TTL, internal pull-up resistor
TTL (as IRQ input)
TTL (only for PCMCIA)
TTL (only for PCMCIA)
TTL (only for PCMCIA)
CMOS Schmitt Trigger
Cologne
Chip
Driver Capability
Low
High
Output
EE_SCL
0.4V
1mA
1mA
6mA
18mA
4mA
4mA
12mA
4mA
12mA
4mA
1mA
4mA
2mA
4mA
4mA
4mA
6mA
6mA
6mA
6mA
6mA
0.6V
VDD - 0.8V
0.5mA
EE_SDA
IOCHRDY
BD0-7
0.5mA
24mA
8mA
2mA
2mA
BUSDIR
TX2_HI
/TX1_LO
/TX_EN
/TX2_LO
TX1_HI
ADJ_LEV
SRD0-7
SRA0-14
/SRRD
2mA
2mA
0.5mA
2mA
1mA
2mA
2mA
2mA
3mA
3mA
3mA
3mA
3mA
/SRCS
/SRWE
C4IO
F0IO
STIO1-2
F1_A-B
IRQA-F
Cologne
Chip
6 Timing characteristics
6.1
ISA-PC bus or processor access
Timing diagram 1: ISA-PC bus or microprocessor access
SYMBOL
CHARACTERISTICS
/IOR Low to Read Data Out Time
MIN.
3ns
MAX.
25ns
15ns
–
t
t
t
t
t
t
t
t
t
t
t
RDD
RDDH
SA
/IOR High to Data Buffer Turn Off Time
Address to /IOR or /IOW Low Setup Time
Address Hold Time after /IOR or /IOW High
Read Time
2ns
20ns
20ns
50ns
50ns
30ns
10ns
3ns
SAH
–
RD
WR
Write Time
WRDSU
WRDH
RDY
Write Data Setup Time to /IOW Low
Write Data Hold Time from /IOW High
Delay Time from /IOR or /IOW Low to IOCHRDY Low
Delay Time from /IOR Low or /IOW High to IOCHRDY High
Delay Time from /IOR Low to BUSDIR Low
–
30ns
30ns
25ns
RDYH
BUSRD
3ns
3ns
Cologne
Chip
SYMBOL
CHARACTERISTICS
Delay Time from /IOR High to BUSDIR High
Read/Write cycle
MIN.
2ns
MAX.
15ns
–
t
t
BUSRDH
CYCLE
6 x tCLK
* important!
For write accesses to the HFC-SP the data lines must be stable and valid before /IOW or /DS get
low. With Intel compatible processors it may be neccessary to delay the /IOW or /DS signals.
6.2
SRAM access
Timing diagram 2: SRAM access
SYMBOL CHARACTERISTICS
MIN.
12.288MHz
0
MAX.
24.576MHz *)
±10-4
f
CLK
OSC_IN frequency
f
CLK / fCLK
Relative OSC_IN frequency deviation
OSC_IN Cycle Time
t
t
t
t
t
CLK
1/ fCLK
**)
**)
LOW
OSC_IN Low Level Width
OSC_IN High Level Width
Address Stable after OSC_IN ↓
Address Stable Hold Time after OSC_IN ↓
t
CLK / 3
CLK / 3
2ns
HIGH
t
SRA
15ns
–
SRAH
1ns
Cologne
Chip
SYMBOL
CHARACTERISTICS
Data Out Stable after OSC_IN
MIN.
10ns
5ns
MAX.
t
t
t
t
t
t
t
t
SRD
30ns
SRDH
Data Out Stable Hold Time after OSC_IN
Data In Setup Time to OSC_IN ↓
Data In Hold Time after OSC_IN ↓
Delay Time OSC_IN to /SRWR Low
Delay Time OSC_IN to /SRWR High
Data Hold Time after /SRWR
–
–
SRDSU
SRDHR
SRWR
SRWRH
SRWRA
SRWRA
20ns
0ns
–
5ns
15ns
15ns
–
5ns
1ns
Address Hold Time after /SRWR
t
CLK / 3
–
*)
Double clock mode with 24.576MHz
OSC_IN should be symmetrical so tLOW = tHIGH
**)
6.3
GCI/IOM2 bus clock and data alignment for Mitel STTM bus
Figure 7: GCI/IOM2 bus clock and data alignment
Cologne
Chip
6.4
GCI/IOM2 timing
Timing diagram 3: GCI/IOM2 timing
*)
F0IO starts one C4IO clock earlier if bit 3 in MST_MODE register is set. If this bit is set
F0IO is also awaited one C4IO clock cycle earlier.
6.4.1 Master mode
To configure the HFC-SP as GCI/IOM2 bus master bit 0 of the MST_MODE register must be set. In this
case C4IO and F0IO are outputs.
SYMBOL
CHARACTERISTICS
Clock C4IO period (4.096 MHz)
Clock C4IO High Width
Clock C4IO Low Width
MIN.
TYP.
MAX.
t
180 ns *) 244.14 ns*) 308 ns*)
C4P
t
78 ns *)
78 ns *)
360 ns
180 ns
122 ns *)
122 ns *)
488.28 ns
244.14 ns
166 ns*)
166 ns *)
616 ns
C4H
C4L
t
C2P
t
Clock C2O Period
C2H
t
Clock C2O High Width
308 ns
Cologne
Chip
SYMBOL
CHARACTERISTICS
Clock C2O Low Width
F0IO Width
MIN.
180 ns
230 ns
460 ns
TYP.
244.14 ns
244 ns
488 ns
10 ns
MAX.
308 ns
260 ns
520 ns
25 ns
t
t
C2L
F0iW
Short F0IO
Long F0IO
t
t
SToD
STIO1/2 Delay fom C4IO ↓ Level 1 Output
F0iCYCLE
F0IO Cycle Time
1 half clock adjust
2 half clocks adjust
124.955 us 125.000 us 125.045 us
124.910 us 125.000 us 125.090 us
All specifications are for 2.048 Mb/s Streams and fCLK = 12.288 Mhz.
*)
Time depends on accuracy of OSC_IN frequency. Because of clock adjustment in the 31st time
slot these are the worst case timings when C4IO is adjusted.
6.4.2 Slave mode
To configure the HFC-SP as GCI/IOM2 bus slave bit 0 of the MST_MODE register must be cleared
(reset default). In this case C4IO and F0IO are inputs.
SYMBOL
CHARACTERISTICS
Clock C4IO period (4.096 MHz)
Clock C4IO High Width
Clock C4IO Low Width
Clock C2O Period
MIN.
TYP.
244.14 ns*)
MAX.
t
t
t
t
t
t
t
t
t
t
t
C4P
C4H
C4L
C2P
20 ns
20 ns
488.28 ns*)
C2H
C2L
F0iS
F0iH
F0iW
STiS
STiH
Clock C2O High Width
Clock C2O Low Width
F0IO Setup Time to C4IO ↓
F0IO Hold Time after C4IO ↓
F0IO Width
25 ns
25 ns
20 ns
20 ns
40 ns
20 ns
20 ns
STIO2 Setup Time
STIO2 Hold Time
All specifications are for 2.048 Mb/s Streams and fCLK = 12.288 Mhz.
*)
If the S/T interface is synchronized from C4IO (NT mode) the frequency must be stable to 10 -4.
Cologne
Chip
6.5
EEPROM access
Timing diagram 4: EEPROM access
SYMBOL
CHARACTERISTICS
TYP.
48 KHz *)
1 / fSCL
¾ tSCL
f
SCL
Serial Clock Frequency
Serial Clock Period
t
t
t
t
t
t
t
t
SCL
HD:STA
LOW
Start Condition Hold Time
Clock Low Period
½ tSCL
HIGH
SU:STA
HD:DAT
SU
Clock High Period
½ tSCL
Start Condition Setup Time
Output Data Change after Clock ↓
Data In Setup Time
¾ tSCL
10 ns
100 ns
100 ns
DH
Data In Hold Time
*)
with 12.288MHz
Cologne
Chip
6.6
Access to an external device
Timing diagram 5: Access to an external device
SYMBOL
CHARACTERISTICS
MIN.
1/ fCLK
4 x tCLK
MAX.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CLK
EXT
LOW
Clock Cycle Time
Access to External Device Cycle Time
Clock Low Level Width
**)
**)
t
t
CLK / 3
CLK / 3
2ns
HIGH
Clock High Level Width
SRA
Address Stable after Clock
15ns
–
SRAH
SRD
Address Stable Hold Time after Clock
Data Out Stable after Clock
1ns
10ns
5ns
30ns
–
SRDH
SRDSU
SRDHR
SRWR
SRWRH
SRWRA
SRWRA
Data Out Stable Hold Time after Clock
Data In Setup Time to Clock ↓
Data In Hold Time after Clock ↓
Delay Time Clock to /SRWR Low
Delay Time Clock to /SRWR High
Data Hold Time after /SRWR
Address Hold Time after /SRWR
20ns
0ns
–
–
5ns
15ns
15ns
–
5ns
1ns
t
CLK / 3
–
*)
Double clock mode with 24.576MHz
Clock should be symmetrical so tLOW = tHIGH
**)
Cologne
Chip
7 S/T interface circuitry
In order to comply to the physical requirements of ITU-T recommendation I.430 and considering the
national requirements concerning overvoltage protection and electromagnetic compatibility (EMC), the
HFC-SP needs some additional circuitry, which are shown in the following figures.
7.1
External receiver circuitry
VDD
R1
C3
R2
R7
R3
LEV_R1
R1
R5
R6
10
S/T module
5
RX
+
D1
D3
D2
D4
11
12
16
14
R1´
GND
VDD
S/T side
R5´
R6´
LEV_R2
RX -
R2´
R2
C3´
R4
ADJ_LEV
C1
GND
Figure 8: External receiver circuitry
Part list
C1
47 nF
22 pF
1N4148 or LL4148
1N4148 or LL4148
VDD
R1, R1'
R2, R2'
R3
5V
3.3V
C3, C3'
D1, D2
D3, D4
33 k
100 k
1 M
680k
S/T module
see Table 5 on page 69
R4
3.9 k
4.7 k
4.7 k
R5, R5'
R6, R6'
R7
1.8 M
1.2M
C3, C3' are for reduction of high frequency input noise and should be located as close as possible to the
HFC-SP.
Cologne
Chip
7.2
External transmitter circuitry
VDD
R6
C3
R4
R5
T3
TX_EN
TX1_HI
TX2_HI
R1
R1´
T1
T1´
R7
R2
R2´
T2
T2´
R8
TX2_LO
R3
R3´
TX1_LO
GND
S/T module
9
8
7
1
TX +
D2
D3
ZD1
3
S/T side
GND
D4
D5
18
TX -
Figure 9: External transmitter circuitry
Part List
C3
470 pF
VDD
R1
5V
2.2 k
3.0 k
3.3V
1% 560
1% 3.9 k
18
D2, D3
D4, D5
ZD1
1N4148 or LL4148
1N4148 or LL4148
Z-Diode 2.7 V
1%
1%
R2
R3, R3' *) 18
(e. g. BZV 55C 2V7)
R4
R5
R6
R7
R8
100
0
T1, T1'
T2, T2'
T3
BC550C, BC850C or similar
BC550C, BC850C or similar
BC560C, BC860C or similar
see Table 5 on page 69
5.6 k
3.3 k
3.3 k
2.2 k
3.3 k
2.2 k
1.8 k
2.2 k
S/T module
*)
value is depending on the used S/T module
Cologne
Chip
S/T module part number
manufacturer
Advanced Power Components
United Kingdom
S-Hybrid modules with receiver and transmitter Phone: +44 1634-290-588
APC 56624-1
circuitry included:
APC 5568-3V
Fax:
+44 1634-290-591
http://www.apcisdn.com
APC 5568-5V
APC 5568DS-3V
APC 5568DS-5V
FE 8131-55Z
FEE GmbH
Singapore
Phone: +65 741-5277
Fax:
+65 741-3013
Bangkok
Phone: +662 718-0726-30
Fax:
+662 718-0712
Germany
Phone: +49 6106-82980
Fax: +49 6106-829898
transformers:
PE-64995
PE-64999
PE-65795
PE-65799
PE-68995
PE-68999
T5006
Pulse Engineering, Inc.
United States
Phone: +1-619-674-8100
Fax:
+1-619-674-8262
http://www.pulseeng.com
T5007
S0-modules:
T5012
T5034
T5038
transformers:
SM TC-9001
SM ST-9002
SM ST-16311F
S0-modules:
SM TC-16311
SM TC-16311A
transformers
UT21023
Sun Myung
Korea
Phone: +82-348-943-8525
Fax:
+82-348-943-8527
http://www.sunmyung.com
UMEC GmbH
Germany
S0-modules:
UT 21624
UT 28624 A
Phone: +49 7131-7617-0
Fax:
+49 7131-7617-20
Taiwan
Phone: +886-4-359-009-6
Fax: +886-4-359-012-9
United States
Phone: +1-310-326-707-2
Fax:
+1-310-326-705-8
http://www.umec.de
Cologne
Chip
S/T module part number
manufacturer
T 6040...
transformers:
3-L4021-X066
VAC GmbH
Germany
Phone: +49 6181/ 38-0
3-L4025-X095
3-L5024-X028
3-L4096-X005
3-L5032-X040
Fax:
+49 6181/ 38-2645
http://www.vacuumschmelze.de
S0-modules:
7-L5051-X014
7-M5051-X032
7-L5052-X102
7-M5052-X110
7-M5052-X114
transformers:
Valor Electronics, Inc.
Asia
Phone: +852 2333-0127
ST5069
S0-modules:
PT5135
Fax:
+852 2363-6206
ST5201
North America
ST5202
Phone: +1 800 31VALOR
Fax:
+1 619 537-2525
Europe
Phone: +44 1727-824-875
Fax: +44 1727-824-898
http://www.valorinc.com
Vogt electronic AG
Germany
543 76 009 00
Phone: +49 8591/ 17-0
Fax:
+49 8591/ 17-240
http://www.vogt-electronic.com
Table 5: S/T module part numbers and manufacturer
Cologne
Chip
7.3
Oscillator circuitry
Part list:
OSC_IN
Q1
12.288 MHz quartz
C1
R1
R2
0..50
1 M
R2
Q1
C1, C2 47 pF
OSC_OUT
C2
R1
Figure 10: Oscillator Circuitry
The values of C1, C2 and R1 depend on the used quartz.
For a load-free check of the oscillator frequency the C4O clock of the GCI/IOM2 bus should be
measured (HFC-SP as master, S/T interface deactivated, 4.096 MHz frequency intented on the C4IO).
The input signal on OSC_IN should be as big as possible.
7.4
EEPROM circuitry
Figure 11: EEPROM circuitry
Cologne
Chip
8 State matrices for NT and TE
8.1
S/T interface activation/deactivation layer 1 for finite state matrix for NT
Pending
activation
Pending
deactivation
State name
Reset
G0
Deactive
G1
Active
G3
State number
G2
G4
INFO 0
|
INFO
sent
Event
INFO 0
G2
INFO 0
|
INFO 2
INFO 4
State machine release
(Note 3)
|
|
|
|
G2
(Note 1)
G2
(Note 1)
G2
(Note 1)
Activate request
Start timer T2
G4
Start timer T2
G4
Deactivate request
|
|
Expiry T2
(Note 2)
G1
G1
Receiving INFO 0
Receiving INFO 1
G2
/
G2
(Note 1)
G3
(Note 1)
Receiving INFO 3
/
Table 6: Activation/deactivation layer 1 for finite state matrix for NT
No state change
/
|
Impossible by the definition of peer-to-peer physical layer procedures or system internal reasons
Impossible by the definition of the physical layer service
Note 1: Timer 1 (T1) is not implemented in the HFC-SP and must be implemented in software.
Note 2: Timer 2 (T2) prevents unintentional reactivation. Its value is 32ms (256 x 125µs). This implies
that a TE has to recognize INFO 0 and to react on it within this time.
Note 3: After reset the state machine is fixed to G0.
* hint!
Fix the NT state machine to state G3 when activated (by writing 13h into STATES register). This
prevents deactivation of NT mode S/T interface due to sporadically errors on NT input data.
Cologne
Chip
8.2
Activation/deactivation layer 1 for finite state matrix for TE
Awaiting Identifying
Lost
framing
State name Reset
Sensing Deactivated
Synchronized Activated
signal
input
State number
F0
F2
F3
F4
F5
F6
F7
F8
Info
Event
INFO 0
INFO 0
INFO 0
INFO 1
/
INFO 0
/
INFO 3
INFO 3
INFO 0
/
sent
State machine release
(Note 1)
F2
/
/
/
/
Receiving any signal
Receiving INFO 0
Activate
Request
Expiry T3
(Note 5)
|
|
F5
F4
|
|
|
|
|
|
/
F3
F3
F3
F3
/
Receiving INFO 0
Receiving any signal
(Note 2)
Receiving INFO 2
(Note 3)
Receiving INFO 4
(Note 3)
Lost framing
(Note 4)
F3
F3
/
F3
F5
F6
F7
/
F6
F7
/
F6
F7
/
F6
F7
/
F6
F6
F7
F7
F8
F8
Table 7: Activation/deactivation layer 1 for finite state matrix for TE
No change, no action
|
/
Impossible by the definition of the layer 1 service
Impossible situation
Notes
Note 1: After reset the state machine is fixed to F0.
Note 2: This event reflects the case where a signal is received and the TE has not (yet) determined wether
it is INFO 2 or INFO 4.
Note 3: Bit- and frame-synchronisation achieved.
Note 4: Loss of Bit- or frame-synchronisation.
Note 5: Timer 3 (T3) is not implemented in the HFC-SP and must be implemented in software.
Cologne
Chip
9 Binary organisation of the frames
9.1
S/T frame structure
The frame structures on the S/T interface are different for each direction of transmission. Both structures
are illustrated in Figure 12.
Figure 12: Frame structure at reference point S and T
F
L
D
E
FA
M
Framing bit
D.C. balancing bit
D-channel bit
D-echo-channel bit
Auxiliary framing bit
Multiframing bit
N
Bit set to a binary value N = FA (NT to TE)
Bit within B-channel 1
Bit within B-channel 2
Bit used for activation
B1
B2
A
S
S-channel bit
note!
Lines demarcate those parts of the frame that are independently d.c.-balanced.
The FA bit in the direction TE to NT is used as Q bit in every fifth frame if S/Q bit transmission is
enabled (see SCTRL register).
The nominal 2-bit offset is as seen from the TE. The offset can be adjusted with the CLKDEL
register in TE mode. The corresponding offset at the NT may be greater due to delay in the
interface cable and varies by configuration.
HDLC-B-channel data start with the LSB, PCM-B-channel data start with the MSB.
Cologne
Chip
9.2
GCI frame structure
The binary organistation of a single GCI channel frame is described below. C4IO clock frequency is
4.096MHz.
C 4IO
F 0 IO
b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b 1 b 2 b 4 b 3 b 2 b 1
D IN
D O U T
B 1
B 2
M
D
C /I
M
R
M
X
B 1
B 1
Tim e S lo t
0
Tim e S lo t
1
Tim e S lo t
2
Tim e S lo t
3
Tim e S lo t
4
Tim e S lo t 3 2
G C I Fra m e
Figure 13: Single channel GCI format
B1
B2
M
B-channel 1 data
B-channel 2 data
Monitor channel data
D-channel data
D
C/I
Command/indication bits for controlling activation/deactivation and for additional control
functions
MR
MX
Handshake bit for monitor channel
Handshake bit for monitor channel
Cologne
Chip
10 Clock synchronisation
10.1 Clock synchronisation in NT-mode
Figure 14: Clock synchronisation in NT-mode
Cologne
Chip
10.2 Clock synchronisation in TE-mode
Figure 15: Clock synchronisation in TE-mode
The C4IO clock is adjusted in the 31th time slot at the GCI/IOM bus twice for one half clock cycle. This
can be reduced to one adjustment of a half clock cycle. This is useful if another HFC-S, HFC-S+ or HFC-
SP is connected as slave in NT mode to the GCI/IOM2 bus.
Cologne
Chip
11 HFC-SP package dimensions
Figure 16: HFC-SP package dimensions
Cologne
Chip
12 Sample circuitries with HFC-SP
12.1 ISDN ISA PnP PC card
Cologne
Chip
Cologne
Chip
Part List
Part
C1
C2
C3
C7
Value
47pF
47pF
47nF
none
1nF
470pF
none
47nF
47nF
47nF
47nF
47nF
47nF
47nF
33µF
33µF
Part
D9
D10
D11
Q1
Q2
Q3
Q29
Q30
Q34
R1
R2
R3
R4
R5
R5'
R6
R6'
R7
R7'
R8
R8'
R9
R10
Value
Part
R11
R12
R13
R14
R14'
R15
R15'
R16
R16'
R17
R18
R19
TR1
Value
100
5.6k
100k
2.2k
2.2k
3.0k
3.0k
18
LL4148
LL4148
2V7
12.288MHz
BC850C
BC850C
BC850C
BC860C
BC850C
50
1%
1%
1%
1%
C8
C9
C10
CB1
CB2
CB3
CB4
CB5
CB6
CB7
CB8
CB9
D1
D2
D3
D4
D6
D7
D8
18
15
1M
1M
2.2k
3.3k
S/T module
3.9k
4.7k
4.7k
4.7k
4.7k
100k
100k
33k
CON1 PINHD-2X4
CON2 WESTERN
CON3 ISA
U1
U2
U3
U4
LL4148
LL4148
LL4148
LL4148
2V7
HFC-SP
24C04
62256FP
74HC138
LL4148
LL4148
33k
1.8M
3.3k
Cologne
Chip
12.2 ISDN PCMCIA card
Cologne
Chip
Cologne
Chip
Part List
Resistors
R1
R2
R3
R4
R5
R5'
R6
R6'
R7
R7'
R8
0R
1M
1M
R8'
R9
33k
R19
R20
R21
R22
R23
R24
R25
R26
R27
R30
1k8
10k
10k
10k
10k
470R
560R
10k
6k8
10k
1M8
33R
18k
100R
2k2
2k2
10R
10R
10k
R11
R12
R13
R14
R14'
R16
R16'
R17
R18
1%
3k9
4k7
4k7
4k7
4k7
100k
100k
33k
1%
1%
2k2
Capacitors
C1
C2
C3
C5
C5'
C8
47pF
C9
C11
C12
CB1-1 33nF
CB1-2 33nF
CB1-3 33nF
150pF
10µF
33nF
CB1-4 33nF
CB1-5 33nF
CB1-6 33nF
CB7,1 22µF
CB7,2 22µF
47pF
47nF
22pF
22pF
100pF
cap
cap
cap
Transistors
T1
T2
BC560C
BC550C
T3
T4
BC550C
BC550C
T5
BC550C
Diodes
D1
D2
BAV 70
BAW 56
BAV 70
D4
D5
D6
BAW 56
BAV 70
BAR 43
D7
D8
BAV 99
ZMM002,7
D3
Chips
U1
U2
HFC-SP (A) ISDN
24C04
U3
U4
62256FP
TPS 7201 Q
others
Q1
TR1
MR03 1228
UT 21023
TR2
TR3
UT 21023
UT 28103-A
ANDA NC7S08
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