HI5640 [ETC]
3.3V Dual 8-Bit， 40 MSPS A/D Converter with Internal Voltage Reference (3 pages) FN4657 ; 3.3V双路，8位， 40 MSPS A / D转换器，内置参考电压（共3页） FN4657\n
| 型号： | HI5640 |
| 厂家： | 
ETC |
| 描述： | 3.3V Dual 8-Bit， 40 MSPS A/D Converter with Internal Voltage Reference (3 pages) FN4657
|
| 文件： | 总10页 (文件大小：76K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL5640
Data Sheet
June 2000
File Number 4657.3
ADVANCE INFORMATION
3V Dual 8-Bit, 20/40/60MSPS A/D
Features
Converter with Internal Voltage Reference
• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . .40MSPS
The ISL5640 is a monolithic, dual 8-bit analog-to-digital
converter fabricated in an advanced CMOS process. It is
designed for high speed applications where integration,
bandwidth and accuracy are essential. The ISL5640
features a 9-stage pipeline architecture. The fully pipelined
architecture and an innovative input stage enable the
ISL5640 to accept a variety of input configurations, single-
ended or fully differential. Only one external clock is
necessary to drive both converters and an internal band-gap
voltage reference is provided. This allows the system
designer to realize an increased level of system integration
resulting in decreased cost and power dissipation.
• 7.4 Bits at f = 1MHz
IN
• Low Power at 40MSPS. . . . . . . . . . . . . . . . . . . . . 100mW
• Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . <1mW
• Wide Full Power Input Bandwidth. . . . . . . . . . . . . 250MHz
• SFDR at f = 1MHz. . . . . . . . . . . . . . . . . . . . . . . . . .55dB
IN
• Excellent Channel-to-Channel Isolation . . . . . . . . . >75dB
• On-Chip Sample and Hold Amplifiers
• Internal Bandgap Voltage Reference . . . . . . . . . . . . 1.25V
• Single Supply Voltage Operation . . . . . . . . . . . . . . . +3.0V
• Offset Binary or Two’s Complement Output Format
• Dual 8-Bit A/D Converters on a Monolithic Chip
• Pin Compatible Upgrade to AD9288
The ISL5640 has excellent dynamic performance while
consuming less than 100mW power at 40MSPS. The A/D
only requires a single +3.0V power supply. Data output
latches are provided which present valid data to the output
bus with a latency of 5 clock cycles.
The ISL5640 is offered in 20MSPS, 30MSPS, 40MSPS and
60MSPS sampling rates.
Applications
• Wireless Local Loop
Ordering Information
• PSK and QAM I&Q Demodulators
• Medical Imaging
TEMP.
SAMPLING
RATE
(MSPS)
PART
NUMBER
RANGE
( C)
o
• High Speed Data Acquisition
PACKAGE PKG. NO.
ISL5640/2IN
ISL5640/3IN
ISL5640/4IN
ISL5640/6IN
ISL5640 EVAL
-40 to 85 48 Ld LQFP
-40 to 85 48 Ld LQFP
-40 to 85 48 Ld LQFP
-40 to 85 48 Ld LQFP
Q48.7x7
Q48.7x7
Q48.7x7
Q48.7x7
20
30
40
60
Pinout
48 LEAD LQFP
TOP VIEW
25
Evaluation Platform
48 47 46 45 44 43 42 41 40 39 38 37
N/C
N/C
GND
DV
36
35
34
33
32
31
30
29
28
27
26
25
1
GND
I
+
2
3
IN
I
-
IN
DFS
4
5
CC
GND
AV
IV
RIN
CC
V
ROUT
6
7
AV
QV
CC
RIN
S1
GND
DV
8
CC
S2
9
GND
N/C
N/C
Q
-
10
IN
Q
+
11
12
IN
GND
13 14 15 16 17 18 19 20 21 22 23 24
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
3-1
ISL5640
Functional Block Diagram
I/Q
-
IN
I/QCLK
CLOCK
I/Q
+
IN
S/H
STAGE 1
2-BIT
FLASH
2-BIT
DAC
+
-
∑
X2
I/QD7 (MSB)
I/QD6
DIGITAL DELAY
AND
STAGE 8
I/QD5
DIGITAL ERROR
CORRECTION
I/QD4
I/QD3
2-BIT
FLASH
2-BIT
DAC
I/QD2
I/QD1
+
I/QD0 (LSB)
∑
-
X2
STAGE 9
2-BIT
FLASH
I OR Q CHANNEL
V
ROUT
I/QV
MODE
DATA FORMAT
S1/S2
DFS
REFERENCE
RIN
AV
AGND
DV
CC
DGND
CC
3-2
ISL5640
Typical Application Schematic
ISL5640
(LSB) ID0 (37)
ID0
ID1
ID2
ID3
ID4
ID5
ID6
ID7
I
+
(2) I
(3) I
+
-
IN
IN
ID1 (38)
ID2 (39)
I
-
IN
IN
ID3 (40)
ID4 (31)
ID5 (42)
ID6 (43)
(MSB) ID7 (44)
(LSB) QD0 (24)
QD1 (23)
QD0
QD1
QD2
QD3
QD4
QD5
QD6
QD7
Q
+
-
(11) Q
(10) Q
+
-
IN
IN
QD2 (22)
Q
IN
IN
QD3 (21)
QD4 (20)
QD5 (19)
QD6 (18)
(MSB) QD7 (17)
(5) IV
RIN
(6) QV
RIN
(7) V
ROUT
0.1µF
ICLK (47)
CLOCK
QCLK (14)
S1 (8)
S2 (9)
S1
S2
DFS (4)
DFS
(13,30,31,48) AV
+3V
CC
DV
CC
(15, 28, 33, 46)
3V
+
+
0.1µF
10µF
10µF
0.1µF
(12,29,32) AGND
DGND (16, 27, 34, 45)
DGND
10µF AND 0.1µF CAPS
ARE PLACED AS CLOSE
TO PART AS POSSIBLE
AGND
BNC
3-3
ISL5640
Pin Descriptions (Continued)
Pin Descriptions
PIN NO.
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
NAME
QD0
N/C
DESCRIPTION
Q-Channel, Data Bit 0 Output (LSB)
No Connect
PIN NO.
NAME
DESCRIPTION
Analog Ground
1
2
3
4
A
GND
I
I-Channel Positive Analog Input
I-Channel Negative Analog Input
IN+
N/C
No Connect
I
IN-
D
Digital Ground
DFS
Data Format Select (Low for Offset
Binary and High for Twos Complement
Output Format)
GND
DV
Digital Supply
CC
A
Analog Ground
GND
5
6
IV
I-Channel Voltage Reference Input
RIN
AV
Analog Supply
CC
CC
V
+1.25V Reference Voltage Output
(Decouple with 0.1µF Capacitor)
ROUT
AV
Analog Supply
7
QV
Q-Channel Voltage Reference Input
Mode Select Pin 1 (See Table)
Mode Select Pin 2 (See Table)
Q-Channel Negative Analog Input
Q-Channel Positive Analog Input
Analog Ground
A
Analog Ground
RIN
S1
S2
GND
8
DV
Digital Supply
CC
9
D
Digital Ground
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Q
N/C
N/C
ID0
ID1
ID2
ID3
ID4
ID5
ID6
ID7
No Connect
IN-
Q
No Connect
IN+
A
I-Channel, Data Bit 0 Output
I-Channel, Data Bit 1 Output
I-Channel, Data Bit 2 Output
I-Channel, Data Bit 3 Output
I-Channel, Data Bit 4 Output
I-Channel, Data Bit 5 Output
I-Channel, Data Bit 6 Output
I-Channel, Data Bit 7 Output (MSB)
Digital Ground
GND
AV
Analog Supply
CC
QCLK
Q-Channel Clock Input
DV
Digital Supply
CC
D
Digital Ground
GND
QD7
QD6
QD5
QD4
QD3
QD2
QD1
Q-Channel, Data Bit 7 Output (MSB)
Q-Channel, Data Bit 6 Output
Q-Channel, Data Bit 5 Output
Q-Channel, Data Bit 4 Output
Q-Channel, Data Bit 3 Output
Q-Channel, Data Bit 2 Output
Q-Channel, Data Bit 1 Output
D
GND
DV
Digital Supply
CC
ICLK
I-Channel Clock Input
Analog Supply
AV
CC
3-4
ISL5640
o
Absolute Maximum Ratings T = 25 C
Thermal Information
A
o
Supply Voltage, AV
CC
or DV
to AGND or DGND . . . . . . . . . . .4V
Thermal Resistance (Typical, Note 1)
θJA ( C/W)
CC
DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V
ISL5640IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
o
Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to DV
Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AV
CC
CC
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150 C
o
o
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C
o
(Lead Tips Only)
Operating Conditions
Temperature Range
o
o
ISL5640IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
A
= D
= +3.3V; V = 1.50V; f = 40MSPS at 50% Duty Cycle;
IN
VDD
VDD
S
o
C = 10pF; T = 25 C; Unless Otherwise Specified
L
A
PARAMETER
ACCURACY
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Resolution
8
-
-
-
-
Bits
LSB
LSB
Integral Linearity Error, INL
f
f
= 1MHz
0.5
±0.2
IN
Differential Linearity Error, DNL
(Guaranteed No Missing Codes)
= 1MHz
-
±1.0
IN
Offset Error, V
OS
f
f
= DC
= DC
-10
-
-
+10
-
LSB
LSB
IN
Full Scale Error, FSE
1
IN
DYNAMIC CHARACTERISTICS
Minimum Conversion Rate
Maximum Conversion Rate
Effective Number of Bits, ENOB
No Missing Codes
No Missing Codes
-
40
-
-
-
-
-
-
-
MSPS
MSPS
Bits
f
f
= 1MHz
= 1MHz
7.5
46
IN
IN
Signal to Noise and Distortion Ratio, SINAD
-
dB
RMS Signal
= -------------------------------------------------------------
RMS Noise + Distortion
Signal to Noise Ratio, SNR
f
= 10MHz
-
47
-
dB
IN
RMS Signal
= -------------------------------
RMS Noise
Total Harmonic Distortion, THD
2nd Harmonic Distortion
3rd Harmonic Distortion
f
f
f
f
= 10MHz
= 10MHz
= 10MHz
= 10MHz
-
-
-
-
-
-
-
-
-
-
-53
-
-
-
-
-
-
-
-
-
-
dBc
dBc
IN
IN
IN
IN
-54
-70
dBc
Spurious Free Dynamic Range, SFDR
Intermodulation Distortion, IMD
I/Q Channel Crosstalk
54
-
dBc
f1 = 1MHz, f2 = 1.02MHz
dBc
-
dBc
I/Q Channel Offset Match
I/Q Channel Full Scale Error Match
Transient Response
-
LSB
LSB
Cycle
Cycle
-
(Note 2)
-
Over-Voltage Recovery
0.2V Overdrive (Note 2)
-
ANALOG INPUT
Maximum Peak-to-Peak Single-Ended
Analog Input Range
-
1.0
-
V
Analog Input Resistance, R
or R
INB
V
V
, V
INA INB
= V
, DC
-
-
-
-
-
-
MΩ
INA
REF
Analog Input Capacitance, C
or C
, V
INA INB
= 1.5V, DC
pF
INA
INB
3-5
ISL5640
Electrical Specifications
A
= D
= +3.3V; V = 1.50V; f = 40MSPS at 50% Duty Cycle;
VDD
VDD
IN
S
o
C = 10pF; T = 25 C; Unless Otherwise Specified (Continued)
L
A
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Analog Input Bias Current, I A or I B
V
/V
INA INB
= ART/BRT, ARB/BRB, DC
-
-
-
µA
B
B
(Notes 2, 3)
Full Power Input Bandwidth, FPBW
REFERENCE VOLTAGE INPUT
Reference Voltage Input Range
f
= 40MHz, (Note 2)
-
250
-
MHz
S
-
-
-
-
300
-
-
-
-
V
Ω
Total Reference Resistance, R
RIN
Reference Current, I
RIN
mA
SAMPLING CLOCK INPUT
Input Logic High Voltage, V
CLK
CLK
2.0
-
-
-
-
-
-
V
IH
Input Logic Low Voltage, V
-
-
-
-
0.8
V
IL
Input Logic High Current, I
CLK, V = 3.3V
IH
-
-
-
µA
µA
pF
IH
Input Logic Low Current, I
CLK, V = 0V
IL
IL
Input Capacitance, C
CLK
IN
DIGITAL OUTPUTS
Output Logic High Voltage, V
OH
I
I
I
I
= 100µA; D
= 3.3V
= 3.3V
= 3.0V
= 3.0V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
OH
OL
OH
OL
VDD
Output Logic Low Voltage, V
OL
= 1.5mA; D
= 100µA; D
VDD
Output Logic High Voltage, V
V
OH
OL
VDD
VDD
Output Logic Low Voltage, V
Output Capacitance, C
= 100µA; D
V
pF
OUT
TIMING CHARACTERISTICS
Aperture Delay, t
-
4
5
-
-
-
-
-
-
-
-
-
ns
AP
Aperture Jitter, t
AJ
-
ps
RMS
Data Output Hold, t
-
10.7
11.7
5
ns
ns
H
Data Output Delay, t
-
OD
Data Latency, t
For a Valid Sample (Note 2)
Data Invalid Time (Note 2)
(Note 2)
-
Cycles
Cycles
ns
LAT
Power-Up Initialization
-
-
Sample Clock Pulse Width (Low)
Sample Clock Pulse Width (High)
Sample Clock Duty Cycle Variation
POWER SUPPLY CHARACTERISTICS
11.25
11.25
-
12.5
12.5
±5
(Note 2)
ns
%
Analog Supply Voltage, A
(Note 2)
(Note 2)
3.0
3.3
3.3
3.6
3.6
-
V
VDD
Digital Supply Voltage, D
3.0
V
VDD
Supply Current, I
f
= 40MSPS
-
-
-
-
30.3
100
mA
mW
LSB
LSB
DD
Power Dissipation
Offset Error Sensitivity, ∆V
S
110
-
A
A
or D
or D
= 3.3V ±5%
= 3.3V ±5%
±0.125
±0.15
OS
VDD
VDD
VDD
Gain Error Sensitivity, ∆FSE
-
VDD
NOTES:
1. Parameter guaranteed by design or characterization and not production tested.
2. With the clock low and DC input.
3-6
ISL5640
Timing Waveforms
ANALOG
INPUT
CLOCK
INPUT
S
H
S
H
S
H
N + 1
S
S
H
S
H
S
H
S
H
N + 8
N - 1
N - 1
N
N
N + 1
N + 2
N + 5
N + 5
N + 6
N + 6
N + 7
N + 7
N + 8
INPUT
S/H
1ST
STAGE
B ,
B ,
B ,
B ,
B ,
B ,
B ,
1 N + 7
1
N - 1
1
N
1
N + 1
1
N + 4
1
N + 5
1
N + 6
2ND
STAGE
B ,
B ,
B ,
2 N + 6
B ,
B ,
B ,
2 N
2
N + 4
2
N + 5
2
N - 2
2
N - 1
9TH
STAGE
B ,
B ,
B ,
B ,
B ,
B ,
9 N + 3
9
N - 5
9
N - 4
9
N
9
N + 1
9
N + 2
DATA
OUTPUT
D
D
D
D
D
D
N + 2
N - 6
N - 5
N - 1
N
N + 1
t
LAT
NOTES:
3. S : N-th sampling period.
N
4. H : N-th holding period.
N
5. B
, : M-th stage digital output corresponding to N-th sampled input.
N
M
6. D : Final data output corresponding to N-th sampled input.
N
FIGURE 1. ISL5640 INTERNAL CIRCUIT TIMING
ANALOG
INPUT
t
AP
t
AJ
CLOCK
INPUT
1.5V
1.5V
t
OD
t
H
2.4V
0.5V
DATA
OUTPUT
DATA N-1
DATA N
FIGURE 2. ISL5640 INPUT TO OUTPUT TIMING
3-7
ISL5640
TABLE 1. A/D CODE TABLE
OFFSET BINARY OUTPUT CODE
DIFFERENTIAL INPUT
VOLTAGE
(I/Q + - I/Q -)
MSB
LSB
CODE CENTER
DESCRIPTION
I/QD9 I/QD8 I/QD7 I/QD6 I/QD5 I/QD4 I/QD3 I/QD2 I/QD1 I/QD0
IN IN
1
+Full Scale (+f ) - / LSB
0.499756V
0.498779V
732.422µV
-244.141µV
-0.498291V
-0.499268V
1
1
1
0
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
0
1
1
0
S
4
1
+f - 1 / LSB
S
4
3
+ / LSB
4
1
- / LSB
4
3
-f + 1 / LSB
S
4
3
-Full Scale (-f ) + / LSB
S
4
NOTE:
7. The voltages listed above represent the ideal center of each output code shown with V
= +1.25V.
REFIN
Detailed Description
Theory of Operation
Φ
Φ
C
1
1
H
The ISL5640 is a dual 8-bit fully differential sampling pipeline
Φ
1
C
C
S
I/Q
I/Q
IN+
A/D converter with digital error correction logic. Figure 3
depicts the circuit for the front end differential-in-differential-
out sample-and-hold (S/H) amplifiers. The switches are
controlled by an internal sampling clock which is a non-
overlapping two phase signal, Φ and Φ , derived from the
V
OUT+
+
-
Φ
2
V
+
-
OUT-
IN-
S
Φ
1
Φ
C
Φ
1
2
1
H
1
master sampling clock. During the sampling phase, Φ , the
1
input signal is applied to the sampling capacitors, C . At the
S
same time the holding capacitors, C , are discharged to
H
FIGURE 3. ANALOG INPUT SAMPLE-AND-HOLD
analog ground. At the falling edge of Φ the input signal is
1
sampled on the bottom plates of the sampling capacitors. In
As illustrated in the Functional Block Diagram and the timing
diagram in Figure 1, eight identical pipeline subconverter
stages, each containing a two-bit flash converter and a two-
bit multiplying digital-to-analog converter, follow the S/H
circuit with the ninth stage being a two bit flash converter.
Each converter stage in the pipeline will be sampling in one
phase and amplifying in the other clock phase. Each
individual subconverter clock signal is offset by 180 degrees
from the previous stage clock signal resulting in alternate
stages in the pipeline performing the same operation.
the next clock phase, Φ , the two bottom plates of the
2
sampling capacitors are connected together and the holding
capacitors are switched to the op amp output nodes. The
charge then redistributes between C and C completing one
S
H
sample-and-hold cycle. The front end sample-and-hold output
is a fully-differential, sampled-data representation of the
analog input. The circuit not only performs the sample-and-
hold function but will also convert a single-ended input to a
fully-differential output for the converter core. During the
sampling phase, the I/Q pins see only the on-resistance of a
switch and C . The relatively small values of these
S
components result in a typical full power input bandwidth of
400MHz for the converter.
IN
The output of each of the eight identical two-bit subconverter
stages is a two-bit digital word containing a supplementary bit
to be used by the digital error correction logic. The output of
each subconverter stage is input to a digital delay line which is
controlled by the internal sampling clock. The function of the
digital delay line is to time align the digital outputs of the eight
identical two-bit subconverter stages with the corresponding
output of the ninth stage flash converter before applying the
eighteen bit result to the digital error correction logic. The
digital error correction logic uses the supplementary bits to
correct any error that may exist before generating the final ten
bit digital data output of the converter.
Because of the pipeline nature of this converter, the digital
data representing an analog input sample is output to the
digital data bus following the 6th cycle of the clock after the
3-8
ISL5640
analog sample is taken (see the timing diagram in Figure 1).
This time delay is specified as the data latency. After the
data latency time, the digital data representing each
succeeding analog sample is output during the following
clock cycle. The digital output data is provided in offset
binary format (see Table 1, A/D Code Table).
For the AC coupled differential input (Figure 4) and with V
RIN
connected to V
, full scale is achieved when the V and
ROUT IN
-V input signals are 0.5V , with -V being 180 degrees
IN P-P IN
out of phase with V . The converter will be at positive full
IN
scale when the I/Q + input is at I/Q
+ 0.25V and the
IN VRIN
I/Q - input is at I/Q
- 0.25V (I/Q + - I/Q - = +0.5V).
IN VRIN IN IN
Conversely, the converter will be at negative full scale when
the I/Q + input is equal to I/Q - 0.25V and I/Q - is at
Internal Reference Voltage Output, V
ROUT
IN VRIN IN
The ISL5640 is equipped with an internal 1.25V bandgap
reference voltage generator, therefore, no external reference
I/Q
VRIN
+ 0.25V (I/Q + - I/Q - = -0.5V).
IN IN
The analog input can be DC coupled (Figure 5) as long as
the inputs are within the analog input common mode voltage
range (0.25V ≤ VDC ≤ 2.75V).
voltage is required. V
when using the internal reference voltage. An external, user-
supplied, 0.1µF capacitor may be connected from the V
should be connected to V
ROUT
RIN
ROUT
output pin to filter any stray board noise.
The resistors, R, in Figure 5 are not absolutely necessary
but may be used as load setting resistors. A capacitor, C,
Reference Voltage Inputs, I/Q V
REFIN
The ISL5640 is designed to accept a 1.25V reference
voltage source at the V input pins for the I and Q
connected from I/Q + to I/Q - will help filter any high
IN IN
frequency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on AC
coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.
RIN
channels. Typical operation of the converter requires V
to
RIN
connected
be set at 1.25V. The ISL5640 is tested with V
RIN
to V
yielding a fully differential analog input voltage
range of ±0.5V.
ROUT
The user does have the option of supplying an external 1.25V
reference voltage. As a result of the high input impedance
V
IN
I/Q
+
IN
V
V
DC
presented at the V
input pin, MΩ typically, the external
RIN
R
R
reference voltage being used is only required to source small
amount of reference input current.
ISL5640
I/QV
C
RIN
In order to minimize overall converter noise it is
recommended that adequate high frequency decoupling be
-V
IN
I/Q
-
IN
DC
provided at the reference voltage input pin, V
.
RIN
Analog Input, Differential Connection
FIGURE 5. DC COUPLED DIFFERENTIAL INPUT
The analog input of the ISL5640 is a differential input that
can be configured in various ways depending on the signal
source and the required level of performance. A fully
differential connection (Figure 4 and Figure 5) will deliver the
best performance from the converter.
Analog Input, Single-Ended Connection
The configuration shown in Figure 6 may be used with a
single ended AC coupled input.
V
I/Q +
IN
IN
I/Q
I/Q
+
V
IN
R
R
IN
ISL5640
I/QV
R
RIN
V
ISL5640
DC
-
IN
-V
I/Q -
IN
IN
FIGURE 6. AC COUPLED SINGLE ENDED INPUT
FIGURE 4. AC COUPLED DIFFERENTIAL INPUT
Since the ISL5640 is powered by a single +3V analog
supply, the analog input is limited to be between ground and
+3V. For the differential input connection this implies the
analog input common mode voltage can range from 0.25V to
2.75V. The performance of the ADC does not change
significantly with the value of the analog input common
mode voltage.
Again, with V
RIN
sinewave, then I/Q + is a 1.0V
positive voltage equal to V . The converter will be at
positive full scale when I/Q + is at V
IN
connected to V
, if V is a 1V
IN P-P
sinewave riding on a
ROUT
IN
P-P
DC
+ 0.5V (I/Q + -
IN
DC
I/Q - = +0.5V) and will be at negative full scale when I/Q
+
IN
IN
is equal to V
- 0.5V (I/Q + - I/Q - = -0.5V). Sufficient
DC
IN IN
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ISL5640
headroom must be provided such that the input voltage
never goes above +3V or below AGND. In this case, V
could range between 0.5V and 2.5V without a significant
OPERATIONAL MODES
MODE
DC
S1
0
S2
0
Standby I and Q Channels.
change in ADC performance. The simplest way to produce
VDC is to use the I/Q
the ISL5640.
bias source, I/QV , output of
DC
0
1
I channel operates normally with Q Channel in
standby mode.
VRIN
1
1
0
1
I and Q Channels operating with I/Q output data in
phase.
The single ended analog input can be DC coupled (Figure 7)
as long as the input is within the analog input common mode
voltage range.
I and Q Channels operating with Q data 180 degrees
out of phase.
V
IN
Sampling Clock Requirements
I/Q
+
IN
V
DC
The ISL5640 sampling clock input provides a standard high-
speed interface to external TTL/CMOS logic families.
R
ISL5640
C
In order to ensure rated performance of the ISL5640, the
duty cycle of the clock should be held at 50% ±5%. It must
also have low jitter and operate at standard TTL/CMOS
levels.
V
I/Q
-
IN
DC
Performance of the ISL5640 will only be guaranteed at
conversion rates above 1MSPS (Typ). This ensures proper
performance of the internal dynamic circuits. Similarly, when
power is first applied to the converter, a maximum of 20
cycles at a sample rate above 1MSPS must be performed
before valid data is available.
FIGURE 7. DC COUPLED SINGLE ENDED INPUT
The resistor, R, in Figure 7 is not absolutely necessary but
may be used as a load setting resistor. A capacitor, C,
connected from I/Q + to I/Q - will help filter any high
IN IN
Supply and Ground Considerations
frequency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on AC
coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.
The ISL5640 has separate analog and digital supply and
ground pins to keep digital noise out of the analog signal
path. The part should be mounted on a board that provides
separate low impedance connections for the analog and
digital supplies and grounds. For best performance, the
supplies to the ISL5640 should be driven by clean, linear
regulated supplies. The board should also have good high
frequency decoupling capacitors mounted as close as
possible to the converter. If the part is powered off a single
supply then the analog supply can be isolated by a ferrite
bead from the digital supply.
A single ended source may give better overall system
performance if it is first converted to differential before
driving the ISL5640.
Operational Mode
The ISL5640 contains several operational modes including a
normal two channel operation, placing one or both channels
in standby and delaying the Q channel data 1/2 clock cycle.
The operational mode is selected via the S1 and S2 pins and
is asynchronous to either clock. When either channel is
placed in standby, the output data is stalled and not high
impedance. When recovering from standby, valid data is
available after 20 clock cycles.
Refer to the application note “Using Intersil High Speed A/D
Converters” (AN9214) for additional considerations when
using high speed converters.
The delay mode can be used to set the Q channel 180
degrees out phase of the I channel if the same clock is
driving both channels. If separate, inverted clocks are used
for the I and Q channels, this feature can be used to align the
data.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
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