HM1-65642-9 [ETC]
SRAM|8KX8|CMOS|DIP|28PIN|CERAMIC ;
| 型号： | HM1-65642-9 |
| 厂家： | 
ETC |
| 描述： | SRAM|8KX8|CMOS|DIP|28PIN|CERAMIC 内存集成电路 静态存储器 |
| 文件： | 总8页 (文件大小：136K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM
HM-65642
8K x 8 Asynchronous
CMOS Static RAM
March 1997
Features
Description
• Full CMOS Design
The HM-65642 is a CMOS 8192 x 8-bit Static Random
Access Memory. The pinout is the JEDEC 28 pin, 8-bit wide
standard, which allows easy memory board layouts which
accommodate a variety of industry standard ROM, PROM,
EPROM, EEPROM and RAMs. The HM-65642 is ideally
suited for use in microprocessor based systems. In particu-
lar, interfacing with the Intersil 80C86 and 80C88 micropro-
cessors is simplified by the convenient output enable (G)
input.
• Six Transistor Memory Cell
• Low Standby Supply Current . . . . . . . . . . . . . . . .100µA
• Low Operating Supply Current. . . . . . . . . . . . . . . 20mA
• Fast Address Access Time . . . . . . . . . . . . . . . . . . 150ns
• Low Data Retention Supply Voltage . . . . . . . . . . . 2.0V
• CMOS/TTL Compatible Inputs/Outputs
• JEDEC Approved Pinout
The HM-65642 is a full CMOS RAM which utilizes an array
of six transistor (6T) memory cells for the most stable and
lowest possible standby supply current over the full military
temperature range. In addition to this, the high stability of the
6T RAM cell provides excellent protection against soft errors
due to noise and alpha particles. This stability also improves
the radiation tolerance of the RAM over that of four transistor
or MIX-MOS (4T) devices.
• Equal Cycle and Access Times
• No Clocks or Strobes Required
• Gated Inputs
• No Pull-Up or Pull-Down Resistors Required
• Easy Microprocessor Interfacing
• Dual Chip Enable Control
Ordering Information
TEMPERATURE
RANGE
(NOTE 1)
150ns/75µA
(NOTE 1)
150ns/150µA
(NOTE 1)
200ns/250µA
PACKAGE
CERDIP
PKG. NO.
F28.6
o
o
-40 C to +85 C
-
HM1-65642-9
-
-
o
o
JAN#
-55 C to +125 C
29205BXA
-
F28.6
NOTE:
1. Access Time/Data Retention Supply Current.
Pinout
HM-65642 (CERDIP)
TOP VIEW
1
2
28
27
26
25
24
23
22
21
20
19
18
NC
A12
A7
V
CC
PIN
A
DESCRIPTION
W
Address Input
3
E2
DQ
E1
E2
W
Data Input/Output
Chip Enable
Chip Enable
Write Enable
Output Enable
No Connections
Ground
4
A6
A8
5
A5
A9
6
A4
A11
G
7
A3
8
A2
A10
E1
G
9
A1
NC
GND
10
11
12
13
14
A0
DQ7
DQ6
DQ0
DQ1
DQ2
GND
V
Power
CC
17 DQ5
16
DQ4
15 DQ3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
File Number 3005.1
Copyright © Intersil Americas Inc. 2001. All Rights Reserved
1
HM-65642
Functional Diagram
A9
A
A8
A12
A7
8
256
256 x 256
MEMORY ARRAY
A6
A
8
A5
A4
A3
A2
256
A
A1
A0
5
COLUMN SELECT
(8 OF 256)
A
A10
A11
5
8
W
G
E1
8
E2
DQ
1 OF 8
TRUTH TABLE
MODE
Standby (CMOS)
Standby (TTL)
E1
E2
GND
X
W
X
G
X
X
X
X
V
X
IH
X
V
X
IL
IH
IH
IH
Enable (High Z)
Write
V
V
V
V
V
V
V
V
IH
IL
IL
IL
IH
V
X
IL
Read
V
V
IL
IH
2
HM-65642
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V
Input or Output Voltage Applied for All Grades . . . . . .GND -0.3V to
Thermal Resistance (Typical)
CERDIP Package . . . . . . . . . . . . . . . . 45 C/W
Maximum Storage Temperature Range . . . . . . . . .-65 C to +150 C
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +175 C
θ
θ
JC
8 C/W
JA
o
o
o
o
V
+0.3V
CC
o
Typical Derating Factor . . . . . . . . . . . 5mA/MHz Increase in ICCOP
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
o
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300 C
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101,000 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range
HM-65642-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to +85 C
Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +0.8V
Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . +2.2V to V +0.3V
CC
o
o
o
o
DC Electrical Specifications V = 5V ±10%; T = -40 C to +85 C (HM-65642-9)
CC
A
LIMITS
SYMBOL
ICCSB1
ICCSB2
ICCDR
PARAMETER
Standby Supply Current (CMOS)
Standby Supply Current (TTL)
Data Retention Supply Current
Enabled Supply Current
MIN
MAX
250
5
UNITS
µA
TEST CONDITIONS
E2 = GND, V = 5.5V
-
-
-
-
CC
E2 = 0.8V or E1 = 2.2V, V
mA
= 5.5V
CC
150
5
µA
E2 = GND, V
= 2.0V
CC
ICCEN
mA
E2 = 2.2V, E1 = 0.8V, V = 5.5V,
CC
IIO = 0mA
ICCOP
Operating Supply Current (Note 1)
-
20
mA
f = 1MHz, E1 = 0.8V, E2 = 2.2V,
= 5.5V, IIO = 0mA
V
CC
II
Input Leakage Current
-1.0
-1.0
+1.0
+1.0
µA
µA
VI = V
or GND, V
= 5.5V
CC
E2 = GND, VIO = V
= 5.5V
CC
IIOZ
Input/Output Leakage Current
or GND,
CC
V
CC
VCCDR
VOH1
VOH2
VOL
Data Retention Supply Voltage
Output High Voltage
2.0
2.4
-
-
V
V
V
V
IOH = -1.0mA, V
= 4.5V
= 4.5V
CC
Output High Voltage (Note 2)
Output Low Voltage
V
-0.4
-
IOH = -100µA, V
CC
CC
-
0.4
IOL = 4.0mA, V = 4.5V
CC
o
Capacitance T = +25 C
A
SYMBOL
PARAMETER
MAX
UNITS
TEST CONDITIONS
CI
Input Capacitance (Note 2)
12
14
pF
pF
f = 1MHz, All measurements are
referenced to device GND
CIO
Input/Output Capacitance (Note 2)
NOTES:
1. Typical derating 5mA/MHz increase in ICCOP.
2. Tested at initial design and after major design changes.
3
HM-65642
o
o
AC Electrical Specifications V = 5V ±10%; T = -40 C to +85 C (HM-65642-9)
CC
A
LIMITS
MAX
TEST
CONDITIONS
SYMBOL
READ CYCLE
(1) TAVAX
PARAMETER
MIN
UNITS
Read Cycle Time
Address Access Time
150
-
150
150
150
70
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Notes 1, 3)
(Notes 1, 3)
(Notes 2, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 2, 3)
(Notes 2, 3)
(Notes 2, 3)
(Notes 2, 3)
(Notes 2, 3)
(Notes 2, 3)
(Notes 2, 3)
(2) TAVQV
-
-
(3) TE1LQV
(4) TE2HQV
(5) TGLQV
Chip Enable Access Time
E1
E2
Chip Enable Access Time
-
Output Enable Access Time
-
(6) TE1LQX
(7) TE2HQX
(8) TGLQX
Chip Enable Valid to Output On
Chip Enable Valid to Output On
Output Enable Valid to Output On
Chip Enable Not Valid to Output Off
Chip Enable Not Valid to Output Off
Output Enable Not Valid to Output Off
Output Hold From Address Change
E1
E2
10
10
5
-
-
-
(9) TE1HQZ
(10) TE2LQZ
(11) TGHQZ
(12) TAXQX
WRITE CYCLE
(13) TAVAX
(14) TWLWH
(15) TE1LE1H
(16) TE2HE2L
(17) TAVWL
(18) TAVE1L
(19) TAVE2H
(20) TWHAX
(21) TE1HAX
(22) TE2LAX
(23) TDVWH
(24) TDVE1H
(25) TDVE2L
(26) TWHDX
(27) TE1HDX
(28) TE2LDX
(29) TWLQZ
(30) TWHQX
NOTES:
E1
E2
50
60
50
-
-
-
10
Write Cycle Time
150
90
90
90
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 2, 3)
(Notes 2, 3)
Write Pulse Width
Chip Enable to End of Write
Chip Enable to End of Write
E1
E2
-
-
Address Setup Time
Address Setup Time
Address Setup Time
Write Recovery Time
Write Recovery Time
Write Recovery Time
Data Setup Time
Late Write
-
Early Write
Early Write
Late Write
Early Write
Early Write
Late Write
Early Write
Early Write
Late Write
Early Write
Early Write
E1
E2
0
-
0
-
10
10
10
60
60
60
5
-
E1
E2
-
-
-
Data Setup Time
E1
E2
-
Data Setup Time
-
ns
ns
ns
ns
ns
ns
Data Hold Time
-
Data Hold Time
E1
E2
10
10
-
-
Data Hold Time
-
Write Enable Low to Output Off
Write Enable High to Output On
50
-
5
1. Input pulse levels: 0V to 3.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load:
1 TTL gate equivalent, C = 50pF (min) - for C greater than 50pF, access time is derated by 0.15ns per pF.
L
L
2. Tested at initial design and after major design changes.
3. V = 4.5V and 5.5V.
CC
4
HM-65642
Low Voltage Data Retention
1. The RAM must be kept disabled during data retention. This is ac-
complished by holding the E2 pin between -0.3V and GND.
Intersil CMOS RAMs are designed with battery backup in
mind. Data Retention voltage and supply current are guaran-
teed over the operating temperature range. The following
rules ensure data retention:
2. During power-up and power-down transitions, E2 must be held
between -0.3V and 10% of V
.
CC
3. The RAM can begin operating one TAVAX after V
minimum operating voltage of 4.5V.
reaches the
CC
DATA RETENTION MODE
V
CC
4.5V
V
IH
TAVAX
E2
VCCOR
GND
FIGURE 1. DATA RETENTION
Read Cycles
TAVAX (1)
ADDRESS 1
A
Q
ADDRESS 2
TAXQX (12)
DATA 1
TAVQV (2)
DATA 2
FIGURE 2. READ CYCLE I: W, E2 HIGH; G, E1 LOW
5
HM-65642
Read Cycles
TAVAX (1)
A
TAVQV (2)
TE1LQV (3)
E1
TE1HQZ (9)
TE2LQZ (10)
TGHQZ (11)
TE1LQX (6)
E2
G
TE2HQV (4)
TE2HQX (7)
TGLQV (5)
TGLQX (8)
Q
FIGURE 3. READ CYCLE II: W HIGH
Write Cycles
TAVAX (13)
TWLWH (14)
A
TAVWL (17)
TWHAX (20)
W
E1
E2
TWHQX (30)
TWHDX (26)
TDVWH (23)
D
Q
TWLQZ (29)
FIGURE 4. WRITE CYCLE I: LATE WRITE
6
HM-65642
Write Cycles
TAVAX (13)
A
TE1LE1H (15)
TAVE1L (18)
TE1HAX (21)
W
E1
E2
D
TE1HDX (27)
TDVE1H (24)
FIGURE 5. WRITE CYCLE II: EARLY WRITE - CONTROLLED BY E1
TAVAX (13)
A
TE2HE2L (16)
TAVE2H (19)
TE2LAX (22)
W
E1
E2
D
TE2LDX (28)
TDVE2L (25)
FIGURE 6. WRITE CYCLE III: EARLY WRITE - CONTROLLED BY E2
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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7
Typical Performance Curve
V
= 2.0V
CC
-3
-4
-5
-6
-7
-8
-9
-10
-11
-12
-55
-35
-15
5
25
45
65
85
105
125
o
T
( C)
A
FIGURE 7. TYPICAL ICCDR vs T
A
8
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