HM51W16160J-7 [ETC]
x16 Fast Page Mode DRAM ; X16快速页模式DRAM\n
| 型号： | HM51W16160J-7 |
| 厂家： | 
ETC |
| 描述： | x16 Fast Page Mode DRAM
|
| 文件： | 总33页 (文件大小：399K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM51W16160 Series
HM51W18160 Series
16 M FP DRAM (1-Mword × 16-bit)
4 k Refresh/1 k Refresh
ADE-203-635E (Z)
Rev. 5.0
Nov. 1997
Description
The Hitachi HM51W16160 Series, HM51W18160 Series are CMOS dynamic RAMs organized as
1,048,576-word × 16-bit. They employ the most advanced CMOS technology for high performance and
low power. The HM51W16160 Series, HM51W18160 Series offer Fast Page Mode as a high speed access
mode. They have package variations of 42-pin plastic SOJ and 50-pin plastic TSOP II
Features
•
•
•
Single 3.3 V (±0.3 V)
Access time: 60 ns/70 ns (max)
Power dissipation
Active mode
: 360 mW/324 mW (max) (HM51W16160 Series)
:612 mW/540 mW (max) (HM51W18160 Series)
Standby mode : 7.2 mW (max)
: 0.54 mW (max) (L-version)
•
•
Fast page mode capability
Refresh cycles
4096 refresh cycles : 64 ms (HM51W16160 Series)
: 128 ms (L-version)
1024 refresh cycles : 6 ms (HM51W18160 Series)
: 28 ms (L-version)
•
4 variations of refresh
RAS-only refresh
CAS-before-RAS refresh
Hidden refresh
Self refresh (L-version)
•
•
2 CAS-byte control
Battery backup operation (L-version)
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HM51W16160 Series, HM51W18160 Series
Ordering Information
Type No.
Access time
Package
HM51W16160J-6
HM51W16160J-7
60 ns
70 ns
400-mil 42-pin plastic SOJ (CP-42D)
HM51W16160LJ-6
HM51W16160LJ-7
60 ns
70 ns
HM51W18160J-6
HM51W18160J-7
60 ns
70 ns
HM51W18160LJ-6
HM51W18160LJ-7
60 ns
70 ns
HM51W16160TT-6
HM51W16160TT-7
60 ns
70 ns
400-mil 50-pin plastic TSOP II (TTP-50/44DC)
HM51W16160LTT-6
HM51W16160LTT-7
60 ns
70 ns
HM51W18160TT-6
HM51W18160TT-7
60 ns
70 ns
HM51W18160LTT-6
HM51W18160LTT-7
60 ns
70 ns
2
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HM51W16160 Series, HM51W18160 Series
Pin Arrangement
HM51W16160J/LJ Series
HM51W16160TT/LTT Series
1
2
3
4
5
6
7
8
50
49
48
47
46
45
44
43
42
41
40
V
SS
V
CC
1
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
V
V
SS
CC
I/O15
I/O14
I/O13
I/O12
I/O0
I/O1
I/O2
I/O3
2
I/O0
I/O1
I/O2
I/O3
I/O15
I/O14
I/O13
I/O12
3
4
5
V
V
SS
CC
6
V
V
I/O11
I/O10
I/O9
I/O8
NC
I/O4
I/O5
I/O6
I/O7
NC
CC
SS
7
I/O4
I/O5
I/O6
I/O7
NC
I/O11
I/O10
I/O9
I/O8
NC
9
10
11
8
9
10
11
12
13
14
15
16
17
18
19
20
21
NC
LCAS
UCAS
OE
15
16
17
18
19
20
21
22
23
24
25
36
35
34
33
32
31
30
29
28
27
26
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
NC
NC
WE
RAS
A11
A10
A0
A1
A2
A3
WE
RAS
A11
A10
A0
A9
A8
A7
A1
A6
A2
A5
A3
A4
A4
V
V
CC
SS
V
V
SS
CC
(Top view)
(Top view)
Pin Description
Pin name
Function
A0 to A11
Address input
A0 to A11
A0 to A7
•
•
Row/Refresh address
Column address
I/O0 to I/O15
Data input/Data output
Row address strobe
RAS
UCAS, LCAS Column address strobe
WE
OE
VCC
VSS
NC
Read/Write enable
Output enable
Power supply
Ground
No connection
3
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HM51W16160 Series, HM51W18160 Series
Pin Arrangement
HM51W18160J/LJ Series
HM51W18160TT/LTT Series
V
V
1
2
3
4
5
6
7
8
CC
50
49
48
47
46
45
44
43
42
41
40
SS
V
1
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
V
SS
CC
I/O0
I/O1
I/O2
I/O3
I/O15
I/O14
I/O13
I/O12
I/O0
I/O1
I/O2
I/O3
2
I/O15
I/O14
I/O13
I/O12
3
4
5
V
V
CC
SS
V
I/O4
I/O5
I/O6
I/O7
NC
6
V
I/O11
I/O10
I/O9
I/O8
NC
CC
SS
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
NC
A0
7
I/O11
I/O10
I/O9
I/O8
NC
8
9
10
11
9
10
11
12
13
14
15
16
17
18
19
20
21
LCAS
UCAS
OE
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
15
16
17
18
19
20
21
22
23
24
25
36
35
34
33
32
31
30
29
28
27
26
A9
A8
A7
A1
A6
A2
A5
A3
A4
A4
V
V
CC
SS
V
V
CC
SS
(Top view)
(Top view)
Pin Description
Pin name
Function
A0 to A9
Address input
A0 to A9
A0 to A9
•
•
Row/Refresh address
Column address
I/O0 to I/O15
Data input/Data output
Row address strobe
RAS
UCAS, LCAS Column address strobe
WE
OE
VCC
VSS
NC
Read/Write enable
Output enable
Power supply
Ground
No connection
4
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HM51W16160 Series, HM51W18160 Series
Block Diagram (HM51W16160 Series)
RAS UCAS LCAS
WE
OE
Timing and control
A0
A1
to
Column decoder
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
Column
address
buffers
•
•
•
A7
I/O0
to
•
•
•
I/O buffers
I/O15
Row
address
buffers
A8
A9
A10
A11
Block Diagram (HM51W18160 Series)
RAS UCAS LCAS
WE
OE
Timing and control
A0
A1
to
Column decoder
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
1M array
Column
address
buffers
•
•
•
A9
I/O0
I/O buffers
to
•
•
•
I/O15
Row
address
buffers
5
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HM51W16160 Series, HM51W18160 Series
Truth Table
RAS
LCAS
UCAS
WE
D
OE
Output
Open
Valid
Operation
Standby
H
D
L
D
H
L
D
L
H
L
Lower byte Read cycle
Upper byte
L
H
L
H
L
Valid
L
L
H
L
Valid
Word
L
L
H
L
L*2
L*2
L*2
L*2
L*2
L*2
H to L
H to L
H to L
D
D
Open
Open
Open
Lower byte Early write cycle
Upper byte
L
H
L
D
L
L
D
Word
L
L
H
L
H
Undefined Lower byte Delayed write cycle
Undefined Upper byte
L
H
L
H
L
L
H
Undefined Word
L
L
H
L
L to H
L to H
L to H
D
Valid
Valid
Valid
Open
Open
Open
Open
Open
Lower byte Read-modify-write cycle
L
H
L
Upper byte
Word
L
L
L
H
H
L
H
L
Word
Word
Word
Word
RAS-only refresh cycle
H to L
H to L
H to L
L
D
D
CAS-before-RAS refresh cycle or
Self refresh cycle (L-version)
H
L
D
D
L
D
D
L
L
H
H
Read cycle (Output disabled)
Notes: 1. H: High (inactive) L: Low (active) D: H or L
2. tWCS ≥ 0 ns Early write cycle
tWCS < 0 ns Delayed write cycle
3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by the earliest of
UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.)
However write OPERATION and output High-Z control are done independently by each UCAS,
LCAS.
ex. if RAS = H to L, UCAS = H, LCAS = L, then CAS-before-RAS refresh cycle is selected.
6
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HM51W16160 Series, HM51W18160 Series
Absolute Maximum Ratings
Parameter
Symbol
VT
Value
Unit
V
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
–0.5 to VCC + 0.5 (≤ +4.6 V (max))
VCC
–0.5 to +4.6
50
V
Iout
PT
mA
W
1.0
Operating temperature
Storage temperature
Topr
Tstg
0 to +70
–55 to +125
°C
°C
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
Symbol
VCC
Min
3.0
Typ
3.3
—
Max
Unit
V
Notes
Supply voltage
3.6
1, 2
1
Input high voltage
Input low voltage
VIH
2.0
VCC + 0.3
0.8
V
VIL
–0.3
—
V
1
Notes: 1. All voltage referred to VSS
2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS
pins must be on the same level.
7
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HM51W16160 Series, HM51W18160 Series
DC Characteristics
(Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) (HM51W16160 Series)
HM51W16160
-6
-7
Parameter
Symbol Min Max Min Max Unit
Test conditions
Operating current*1, *2
ICC1
ICC2
—
—
100
2
—
—
90
2
mA
mA
tRC = min
Standby current
TTL interface
RAS, UCAS, LCAS = VIH
Dout = High-Z
—
—
1
—
—
1
mA
CMOS interface
RAS, UCAS,
LCAS ≥ VCC – 0.2 V
Dout = High-Z
Standby current
(L-version)
ICC2
150
150 µA
CMOS interface
RAS, UCAS,
LCAS ≥ VCC – 0.2 V
Dout = High-Z
RAS-only refresh current*2
Standby current*1
ICC3
ICC5
—
—
100
5
—
—
90
5
mA
mA
tRC = min
RAS = VIH
UCAS, LCAS = VIL
Dout = enable
CAS-before-RAS refresh current ICC6
—
—
—
100
95
—
—
—
90
85
mA
mA
tRC = min
tPC = min
Fast page mode current*1, *3
ICC7
Battery backup current*4
(Standby with CBR refresh) (L-
version)
ICC10
400
400 µA
CMOS interface
Dout = High-Z
CBR refresh: tRC = 31.3 µs
t
RAS ≤ 0.3 µs
Self refresh mode current
(L-version)
ICC11
—
250
—
250 µA
CMOS interface
RAS, UCAS, LCAS ≤ 0.2 V
Dout = High-Z
Input leakage current
Output leakage current
ILI
–10 10
–10 10
–10 10
–10 10
µA
µA
0 V ≤ Vin ≤ 4.6 V
ILO
0 V ≤ Vout ≤ 4.6 V
Dout = disable
Output high voltage
Output low voltage
VOH
VOL
2.4
0
VCC
0.4
2.4
0
VCC
0.4
V
V
High Iout = –2 mA
Low Iout = 2 mA
Notes: 1. ICC depends on output load condition when the device is selected. ICC max is specified at the
output open condition.
2. Address can be changed once or less while RAS = VIL.
3. Address can be changed once or less while UCAS and LCAS = VIH.
4. VIH ≥ VCC – 0.2 V, 0 V ≤ VIL ≤ 0.2 V.
DC Characteristics
(Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) (HM51W18160 Series)
8
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HM51W16160 Series, HM51W18160 Series
HM51W18160
-6
-7
Parameter
Symbol Min Max Min Max Unit
Test conditions
Operating current*1, *2
ICC1
ICC2
—
—
170
2
—
—
150 mA
tRC = min
Standby current
2
mA
TTL interface
RAS, UCAS, LCAS = VIH
Dout = High-Z
—
—
1
—
—
1
mA
CMOS interface
RAS, UCAS,
LCAS ≥ VCC – 0.2 V
Dout = High-Z
Standby current
(L-version)
ICC2
150
150 µA
CMOS interface
RAS, UCAS,
LCAS ≥ VCC – 0.2 V
Dout = High-Z
RAS-only refresh current*2
Standby current*1
ICC3
ICC5
—
—
170
5
—
—
150 mA
tRC = min
5
mA
RAS = VIH
UCAS, LCAS = VIL
Dout = enable
CAS-before-RAS refresh current ICC6
—
—
—
170
165
400
—
—
—
150 mA
145 mA
400 µA
tRC = min
tPC = min
Fast page mode current*1, *3
ICC7
Battery backup current*4
(Standby with CBR refresh) (L-
version)
ICC10
CMOS interface
Dout = High-Z
CBR refresh: tRC = 125 µs
t
RAS ≤ 0.3 µs
Self refresh mode current
(L-version)
ICC11
—
250
—
250 µA
CMOS interface
RAS, UCAS, LCAS ≤ 0.2 V
Dout = High-Z
Input leakage current
Output leakage current
ILI
–10 10
–10 10
–10 10
–10 10
µA
µA
0 V ≤ Vin ≤ 4.6 V
ILO
0 V ≤ Vout ≤ 4.6 V
Dout = disable
Output high voltage
Output low voltage
VOH
VOL
2.4
0
VCC
0.4
2.4
0
VCC
0.4
V
V
High Iout = –2 mA
Low Iout = 2 mA
Notes: 1. ICC depends on output load condition when the device is selected. ICC max is specified at the
output open condition.
2. Address can be changed once or less while RAS = VIL.
3. Address can be changed once or less while UCAS and LCAS = VIH.
4. VIH ≥ VCC – 0.2 V, 0 V ≤ VIL ≤ 0.2 V.
9
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HM51W16160 Series, HM51W18160 Series
Capacitance (Ta = 25°C, VCC = 3.3 V ± 0.3 V)
Parameter
Symbol
CI1
Typ
—
Max
Unit
pF
Notes
Input capacitance (Address)
Input capacitance (Clocks)
Output capacitance (Data-in, Data-out)
5
7
7
1
CI2
—
pF
1
CI/O
—
pF
1, 2
Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. UCAS and LCAS = VIH to disable Dout.
10
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HM51W16160 Series, HM51W18160 Series
AC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) *1, *2, *18, *19, *20
Test Conditions
•
•
•
•
Input rise and fall time: 5 ns
Input timing reference levels: 0.8 V, 2.0 V
Output timing reference levels: 0.8 V, 2.0 V
Output load: 1 TTL gate + CL (100 pF) (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
HM51W16160/HM51W18160
-6
-7
Parameter
Symbol
tRC
Min
110
40
10
60
15
0
Max
—
Min
130
50
Max
—
Unit
ns
Notes
Random read or write cycle time
RAS precharge time
tRP
—
—
ns
CAS precharge time
tCP
—
10
—
ns
RAS pulse width
tRAS
tCAS
tASR
tRAH
tASC
tCAH
tRCD
tRAD
tRSH
tCSH
tCRP
tOED
tDZO
tDZC
tT
10000 70
10000 18
10000 ns
10000 ns
CAS pulse width
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time
RAS to column address delay time
RAS hold time
—
—
—
—
45
30
—
—
—
—
—
—
50
0
—
—
—
—
52
35
—
—
—
—
—
—
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
0
10
0
21
21
3
10
20
15
15
60
5
15
20
15
18
70
5
4
CAS hold time
CAS to RAS precharge time
OE to Din delay time
OE delay time from Din
CAS delay time from Din
Transition time (rise and fall)
22
5
15
0
18
0
6
0
0
6
3
3
7
11
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HM51W16160 Series, HM51W18160 Series
Read Cycle
HM51W16160/HM51W18160
-6
Min
—
—
—
—
0
-7
Min
—
—
—
—
0
Parameter
Symbol
tRAC
tCAC
tAA
Max
60
15
30
15
—
Max
70
18
35
18
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
8, 9
Access time from RAS
Access time from CAS
9, 10, 17,
9, 11, 17,
9, 25
Access time from address
Access time from OE
tOEA
tRCS
tRCH
tRRH
tRAL
Read command setup time
Read command hold time to CAS
Read command hold time to RAS
Column address to RAS lead time
Column address to CAS lead time
CAS to output in low-Z
0
—
0
—
12, 22
12
0
—
0
—
30
30
0
—
35
35
0
—
tCAL
—
—
tCLZ
—
—
Output data hold time
tOH
3
—
3
—
Output data hold time from OE
Output buffer turn-off time
Output buffer turn-off to OE
CAS to Din delay time
tOHO
tOFF
tOEZ
tCDD
3
—
3
—
—
—
15
15
15
—
—
—
18
15
15
—
13
13
5
Write Cycle
HM51W16160/HM51W18160
-6
-7
Parameter
Symbol
tWCS
tWCH
tWP
Min
0
Max
—
Min
0
Max
—
Unit
ns
Notes
14, 21
21
Write command setup time
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data-in setup time
10
10
15
15
0
—
15
10
18
18
0
—
ns
—
—
ns
tRWL
tCWL
tDS
—
—
ns
—
—
ns
23
—
—
ns
15, 23
15, 23
Data-in hold time
tDH
10
—
15
—
ns
12
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HM51W16160 Series, HM51W18160 Series
Read-Modify-Write Cycle
HM51W16160/HM51W18160
-6
-7
Parameter
Symbol
tRWC
Min
155
85
Max
—
Min
181
98
Max
—
Unit
ns
Notes
Read-modify-write cycle time
RAS to WE delay time
CAS to WE delay time
Column address to WE delay time
OE hold time from WE
tRWD
—
—
ns
14
14
14
tCWD
40
—
46
—
ns
tAWD
55
—
63
—
ns
tOEH
15
—
18
—
ns
Refresh Cycle
HM51W16160/HM51W18160
-6
Min
5
-7
Min
5
Parameter
Symbol
tCSR
Max
—
Max
—
Unit
ns
Notes
21
CAS setup time (CBR refresh cycle)
CAS hold time (CBR refresh cycle)
RAS precharge to CAS hold time
tCHR
10
5
—
10
5
—
ns
22
tRPC
—
—
ns
21
Fast Page Mode Cycle
HM51W16160/HM51W18160
-6
-7
Parameter
Symbol
tPC
Min
40
—
Max
Min
45
Max
Unit
Notes
Fast page mode cycle time
Fast page mode RAS pulse width
Access time from CAS precharge
RAS hold time from CAS precharge
—
—
ns
tRASP
tCPA
100000 —
100000 ns
16
—
35
—
—
40
—
ns
ns
9, 17, 22
tCPRH
35
40
13
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HM51W16160 Series, HM51W18160 Series
Fast Page Mode Read-Modify-Write Cycle
HM51W16160/HM51W18160
-6
-7
Parameter
Symbol
Min
85
Max
Min
96
Max
Unit
Notes
Fast page mode read-modify-write cycle tPRWC
time
—
—
ns
WE delay time from CAS precharge
tCPW
60
—
68
—
ns
14, 22
Refresh (HM51W16160 Series)
Parameter
Symbol
tREF
Max
Unit
Note
Refresh period
64
ms
ms
4096 cycles
4096 cycles
Refresh period (L-version)
tREF
128
Refresh (HM51W18160 Series)
Parameter
Symbol
tREF
Max
16
Unit
ms
Note
Refresh period
1024 cycles
1024 cycles
Refresh period (L-version)
tREF
128
ms
14
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HM51W16160 Series, HM51W18160 Series
Self Refresh Mode (L-version)
HM51W16160L/HM51W18160L
-6
-7
Parameter
Symbol Min
Max
Min
100
Max
Unit
Notes
RAS pulse width (self refresh)
tRASS
100
—
—
µs
26, 27, 28,
29
RAS precharge time (self refresh)
CAS hold time (self refresh)
tRPS
tCHS
110
–50
—
—
130
–50
—
—
ns
ns
Notes: 1. AC measurements assume tT = 5 ns.
2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization
cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). If
the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are
required.
3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a
reference point only; if tRCD is greater than the specified tRCD (max) limit, then access time is
controlled exclusively by tCAC
.
4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a
reference point only; if tRAD is greater than the specified tRAD (max) limit, then access time is
controlled exclusively by tAA.
5. Either tOED or tCDD must be satisfied.
6. Either tDZO or tDZC must be satisfied.
7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition
times are measured between VIH (min) and VIL (max).
8. Assumes that tRCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. (VOH = 2.0 V, VOL = 0.8 V)
10. Assumes that tRCD ≥ tRCD (max) and tRCD + tCAC (max) ≥ tRAD + tAA (max).
11. Assumes that tRAD ≥ tRAD (max) and tRCD + tCAC (max) ≤ tRAD + tAA (max).
12. Either tRCH or tRRH must be satisfied for a read cycles.
13. tOFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition
and are not referred to output voltage levels.
14. tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only; if tWCS ≥ tWCS (min), the cycle is an early write cycle
and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD
≥ tRWD (min), tCWD ≥ tCWD (min), and tAWD ≥ tAWD (min), or tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW
tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the
selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out
(at access time) is indeterminate.
≥
15. These parameters are referred to UCAS and LCAS leading edge in early write cycles and to WE
leading edge in delayed write or read-modify-write cycles.
16. tRASP defines RAS pulse width in fast page mode cycles.
17. Access time is determined by the longest among tAA, tCAC and tCPA
.
18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data
to the device.
19. When both UCAS and LCAS go low at the same time, all 16-bit data are written into the device.
UCAS and LCAS cannot be staggered within the same write/read cycles.
20. All the VCC and VSS pins shall be supplied with the same voltages.
21. tASC, tCAH, tRCS, tWCS, tWCH, tCSR and tRPC are determined by the earlier falling edge of UCAS or LCAS.
15
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HM51W16160 Series, HM51W18160 Series
22. tCRP, tCHR, tRCH, tCPA and tCPW are determined by the later rising edge of UCAS or LCAS.
23. tCWL, tDH and tDS should be satisfied by both UCAS and LCAS.
24. tCP is determined by the time that both UCAS and LCAS are high.
25. When output buffers are enabled once, sustain the low impedance state until valid data is
obtained. When output buffer is turned on and off within a very short time, generally it causes
large VCC/VSS line noise, which causes to degrade VIH min/VIL max level.
26. Please do not use tRASS timing, 10 µs ≤ tRASS ≤ 100 µs. During this period, the device is in
transition state from normal operation mode to self refresh mode. If tRASS ≥ 100 µs, then RAS
precharge time should use tRPS instead of tRP.
27. If you use distributed CBR refresh mode with 15.6 µs interval in normal read/write cycle, CBR
refresh should be executed within 15.6 µs immediately after exiting from and before entering
into self refresh mode.
28. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 4096 or 1024
cycles (4096 cycles: HM51W16160 Series, 1024 cycles: HM51W18160 Series) of distributed
CBR refresh with 15.6 µs interval should be executed within 64 or 16 ms (64 ms: HM51W16160,
16 ms: HM51W18160) immediately after exiting from and before entering into the self refresh
mode.
29. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from
self fresh mode, all memory cells need to be refreshed before re-entering the self refresh mode
again.
30. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ V ≤ VIL (max))
IN
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must
be applied VIH or VIL.
16
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HM51W16160 Series, HM51W18160 Series
Notes concerning 2CAS control
Please do not separate the UCAS/LCAS operation timing intentionally. However skew between
UCAS/LCAS are allowed under the following conditions.
1. Each of the UCAS/LCAS should satisfy the timing specifications individually.
2. Different operation mode for upper/lower byte is not allowed; such as following.
RAS
Delayed write
UCAS
Early write
LCAS
WE
3. Closely separated upper/lower byte control is not allowed. However when the condition (tCP ≤ tUL) is
satisfied, fast page mode can be performed.
RAS
UCAS
LCAS
t
UL
4. Byte control operation by remaining UCAS or LCAS high is guaranteed.
17
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HM51W16160 Series, HM51W18160 Series
Timing Waveforms*30
Read Cycle
t
t
RC
t
RAS
RP
RAS
t
t
CSH
CRP
t
t
t
RCD
RSH
CAS
t
T
UCAS
LCAS
t
t
t
RAD
RAL
CAL
t
t
t
CAH
ASR
ASC
t
RAH
Row
Column
Address
t
RRH
t
RCH
t
RCS
WE
t
t
CDD
DZC
High-Z
Din
t
t
t
OED
OEA
DZO
OE
t
t
OEZ
t
CAC
OHO
t
AA
t
OFF
t
RAC
t
t
OH
CLZ
Dout
Dout
18
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HM51W16160 Series, HM51W18160 Series
Early Write Cycle
tRC
tRAS
tRP
RAS
tCSH
tCRP
tRCD
tRSH
tCAS
tT
UCAS
LCAS
tASR tRAH
tASC
tCAH
Row
Column
Address
tWCS
tWCH
WE
tDS
tDH
Din
Din
High-Z*
Dout
t
t
(min)
WCS
WCS
*
19
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HM51W16160 Series, HM51W18160 Series
Delayed Write Cycle*18
t
t
RC
t
RAS
RP
RAS
t
t
CRP
CSH
t
t
t
RCD
RSH
CAS
t
T
UCAS
LCAS
t
t
t
t
CAH
ASR
RAH
ASC
Row
Column
Address
t
t
t
CWL
RWL
WP
t
RCS
WE
t
t
t
DH
DZC
DS
High-Z
Din
Din
t
t
OEH
DZO
t
OED
OE
t
OEZ
t
CLZ
High-Z
Dout
Invalid Dout
20
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HM51W16160 Series, HM51W18160 Series
Read-Modify-Write Cycle*18
t
t
RWC
RAS
t
RP
RAS
t
T
t
t
t
CRP
RCD
CAS
UCAS
LCAS
t
RAD
t
t
t
t
CAH
ASR
RAH
ASC
Address
Row
Column
t
t
t
t
t
CWD
CWL
t
RCS
AWD
RWD
RWL
t
WP
WE
Din
OE
t
t
DH
DZC
t
DS
High-Z
Din
t
OED
t
OEH
t
DZO
t
OEA
t
CAC
t
t
OEZ
t
t
AA
t
RAC
OHO
High-Z
Dout
Dout
CLZ
21
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HM51W16160 Series, HM51W18160 Series
RAS-Only Refresh Cycle
t
RC
t
t
RP
RAS
RAS
t
T
t
t
t
CRP
CRP
RPC
UCAS
LCAS
t
t
ASR
RAH
Row
Address
Dout
t
OFF
High-Z
22
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HM51W16160 Series, HM51W18160 Series
CAS-Before-RAS Refresh Cycle
t
t
RC
RC
t
t
t
t
t
RP
RP
RAS
RP
RAS
RAS
t
T
t
t
t
t
t
CRP
RPC
CP
RPC
CP
t
t
t
t
CHR
CSR
CHR
CSR
UCAS
LCAS
Address
Dout
t
OFF
High-Z
23
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HM51W16160 Series, HM51W18160 Series
Hidden Refresh Cycle
t
t
t
RC
RC
RC
t
t
t
t
t
t
RP
RAS
RP
RAS
RP
RAS
RAS
t
T
t
t
t
CRP
RSH
CHR
t
RCD
UCAS
LCAS
t
t
RAL
RAD
t
RAH
tASR
t
t
CAH
ASC
Address
Row
Column
t
RRH
t
RCS
WE
t
t
CDD
DZC
High-Z
Din
t
t
OED
DZO
t
OEA
OE
t
t
t
CAC
OEZ
t
AA
OHO
t
t
t
RAC
OFF
OH
t
CLZ
Dout
Dout
24
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HM51W16160 Series, HM51W18160 Series
Fast Page Mode Read Cycle
t
RASP
t
t
RP
CPRH
RAS
t
T
t
t
t
t
CSH
PC
RSH
t
CRP
t
t
t
t
t
RCD
CAS
CP
CAS
CAL
CP
CAS
UCAS
LCAS
t
t
RAL
CAL
t
t
t
RAD
CAL
t
t
t
t
t
t
t
t
ASR RAH
ASC CAH
ASC CAH
ASC CAH
Row
Address
Column 1
Column 2
Column N
t
t
t
t
RCS
RCS
RRH
RCH
t
t
t
t
t
t
RCS
DZC
RCH
CDD
RCH
CDD
WE
Din
OE
t
t
DZC
DZC
t
CDD
High-Z
High-Z
High-Z
t
t
t
t
t
t
OED
DZO
OED
DZO OED
DZO
t
t
t
CPA
RAC
CPA
t
t
t
t
t
t
OH
AA
OH
AA
OH
AA
t
OHO
t
t
OHO
OHO
t
t
t
OEA
OEA
OEA
t
t
CAC
t
t
t
t
t
CAC
CAC
CLZ
OFF
OFF
OEZ
OFF
OEZ
t
t
t
t
CLZ
t
OEZ
CLZ
Dout 1
Dout 2
Dout N
Dout
25
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HM51W16160 Series, HM51W18160 Series
Fast Page Mode Early Write Cycle
t
t
RP
RASP
RAS
t
T
t
t
t
RSH
CSH
PC
t
t
t
t
t
t
t
CRP
RCD
CAS
CP
CAS
CP
CAS
UCAS
LCAS
t
t
t
t
t
t
t
t
ASR RAH
ASC CAH
ASC CAH
ASC CAH
Row
Column 1
Column 2
Column N
Address
t
t
t
t
t
t
WCH
WCS
WCH
WCS
WCH
WCS
WE
t
t
t
t
t
t
DH
DS
DH
DS
DH
DS
Din 1
Din 2
Din N
Din
High-Z*
Dout
t
t
(min)
WCS
*
WCS
26
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HM51W16160 Series, HM51W18160 Series
Fast Page Mode Delayed Write Cycle*18
t
RASP
t
RP
RAS
t
t
t
t
CP
CRP
T
CP
t
t
t
t
CSH
PC
RSH
CAS
t
t
t
CAS
RCD
CAS
UCAS
LCAS
t
RAD
t
t
t
t
ASR
ASC
t
ASC
t
ASC
t
t
RAH
CAH
CAH
CAH
Row
Column 1
Column 2
Column N
Address
t
t
t
CWL
CWL
t
CWL
t
RWL
t
t
RCS
RCS
RCS
WE
t
t
t
WP
WP
WP
t
t
t
t
t
t
t
DZC DS
DZC DS
DZC DS
t
t
t
DH
DH
DH
Din
1
Din
2
Din
N
Din
t
t
t
DZO
DZO
DZO
OED
t
t
OED
OED
t
t
t
OEH
OEH
OEH
OE
t
t
t
CLZ
CLZ
CLZ
t
t
t
OEZ
OEZ
OEZ
High-Z
Dout
Invalid Dout
Invalid Dout
Invalid Dout
27
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HM51W16160 Series, HM51W18160 Series
Fast Page Mode Read-Modify-Write Cycle*18
t
RASP
t
RP
RAS
t
t
T
PRWC
t
t
t
t
RSH
CAS
t
CRP
CP
CP
t
t
t
CAS
RCD
CAS
UCAS
LCAS
t
RAD
t
t
t
t
ASC
t
CAH
ASR
ASC
RAH
ASC
t
t
t
CAH
CAH
Row
Column 1
Column 2
Column N
Address
t
t
t
t
t
t
t
t
t
RWD
AWD
CWL
CPW
AWD
CWL
t
CPW
AWD
CWL
t
RCS
RWL
t
t
t
t
CWD
CWD
RCS
CWD
WE
t
t
t
t
t
WP
t
DS
RCS
DZO
WP
DS
WP
t
t
t
DS
t
DZC
DZC
DZC
t
t
t
DH
DH
DH
Din
1
Din
2
Din
N
Din
t
t
t
OED
OED
OED
t
t
t
DZO
DZO
t
t
t
OEH
OEH
OEH
OE
t
t
t
OHO
OHO
OHO
t
t
t
t
t
t
OEA
CAC
OEA
CAC
OEA
CAC
t
t
t
AA
AA
AA
t
t
CPA
CPA
t
t
RAC
t
t
t
OEZ
t
t
OEZ
OEZ
CLZ
CLZ
CLZ
High-Z
Dout
Dout 1
Dout 2
Dout N
28
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HM51W16160 Series, HM51W18160 Series
Self Refresh Cycle (L-version)*26, 27, 28, 29
t
t
RPS
t
RASS
RP
RAS
t
T
t
t
t
CRP
RPC
CP
t
CSR
t
CHS
UCAS
LCAS
t
OFF
High-Z
Dout
29
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HM51W16160 Series, HM51W18160 Series
Package Dimensions
HM51W16160J/LJ Series
HM51W18160J/LJ Series (CP-42D)
Unit: mm
27.06
27.43 Max
22
42
21
1
0.74
1.30 Max
1.27
0.10
9.40 ± 0.25
CP-42D
Conforms
—
Weight (reference value) 1.75 g
0.43 ± 0.10
0.41 ± 0.08
Hitachi Code
JEDEC
EIAJ
Dimension including the plating thickness
Base material dimension
30
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HM51W16160 Series, HM51W18160 Series
HM51W16160TT/LTT Series
HM51W18160TT/LTT Series (TTP-50/44DC)
Unit: mm
20.95
21.35 Max
50
40 36
26
25
11 15
0.80
1
0.80
0.27 ± 0.07
0.25 ± 0.05
M
0.13
11.76 ± 0.20
1.15 Max
0° – 5°
0.50 ± 0.10
3.20
0.10
Hitachi Code
TTP-50/44DC
JEDEC
EIAJ
Conforms
—
Dimension including the plating thickness
Base material dimension
Weight (reference value) 0.50 g
31
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HM51W16160 Series, HM51W18160 Series
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of
this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any
other reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual
property claims or other problems that may result from applications based on the examples described
herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party or
Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company.
Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are
requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan
Tel: Tokyo (03) 3270-2111
Fax: (03) 3270-5109
For further information write to:
Hitachi Semiconductor
(America) Inc.
2000 Sierra Point Parkway
Brisbane, CA. 94005-1897
U S A
Hitachi Europe GmbH
Continental Europe
Dornacher Straße 3
D-85622 Feldkirchen
München
Hitachi Europe Ltd.
Electronic Components Div.
Northern Europe Headquarters
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA
United Kingdom
Tel: 01628-585000
Fax: 01628-585160
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 049318
Tel: 535-2100
Tel: 800-285-1601
Fax:303-297-0447
Tel: 089-9 91 80-0
Fax: 089-9 29 30-00
Fax: 535-1533
Hitachi Asia (Hong Kong) Ltd.
Unit 706, North Tower,
World Finance Centre,
Harbour City, Canton Road
Tsim Sha Tsui, Kowloon
Hong Kong
Tel: 27359218
Fax: 27306071
Copyright © Hitachi, Ltd., 1997. All rights reserved. Printed in Japan.
32
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HM51W16160 Series, HM51W18160 Series
Revision Record
Rev. Date
Contents of Modification
Drawn by Approved by
Y. Kasama M. Mishima
Y. Kasama M. Mishima
1.0
2.0
Sep. 30, 1996
Dec. 5, 1996
Initial issue
Addition of HM51W16160/HM51W18160-5 Series
DC Characteristics (HM51W16160 Series)
ICC7 max: 105/95 mA to 105/95/85 mA
DC Characteristics (HM51W18160 Series)
ICC7 max: 170/150 mA to 185/165/145 mA
AC Characteristics
tRRH min: 0/0 ns to 5/5/5 ns
tRPC min: 0/0 ns to 5/5/5 ns
3.0
Feb. 21, 1997
AC Characteristics
Y. Kasama Y. Matsuno
Y. Kasama Y. Matsuno
t
RRH min: 5/5/5 ns to 0/0/0 ns
4.0
5.0
Jun. 26, 1997
Nov. 1997
Deletion of HM51W16160/HM51W18160-5 Series
Change of Subtitle
33
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SI9137LG
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SI9122E
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