HM5221605TT-15_技术文档

HM5221605 Series

2 M LVTTL interface SDRAM (64-kword × 16-bit × 2-bank)

66 MHz / 58 MHz / 50 MHz

ADE-203-199C (Z)

Rev. 3.0

Nov. 1997

Description

All inputs and outputs are referred to the rising edge of the clock input. The HM5221605 is offered in 2

banks for improved performance.

Features

•

3.3V Power supply

Clock frequency: 50 MHz/58 MHz/66 MHz (max)

LVTTL interface

Single pulsed RAS

2 Banks can operates simultaneously and independently

Burst read/write operation and burst read/single write operation capability

Programmable burst length: 1/2/4/8/full page (256)

Programmable burst sequence:

Sequential

Interleave

•

Full page burst length capability

Sequential burst

Burst stop capability

•

Programmable CAS latency: 1/2/3

Byte control by DQMU and DQML

512 refresh cycles: 8 ms

2 variations of refresh

Auto refresh

Self refresh

HM5221605 Series

Ordering Information

Type No.

Frequency

Package

HM5221605TT-15

HM5221605TT-17

HM5221605TT-20

66 MHz

57 MHz

50 MHz

400-mil 50-pin plastic TSOP II (TTP-50DA)

Pin Arrangement

HM5221605TT Series

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

V_SS

V_CC

I/O0

I/O1

1

I/O15

I/O14

2

3

V_SS

Q

V_SS

Q

I/O2

I/O3

4

I/O13

I/O12

5

6

V_CC

Q

V_CC

Q

I/O4

I/O5

7

I/O11

I/O10

8

9

V_SS

Q

V_SS

Q

I/O6

I/O7

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

I/O9

I/O8

V_CC

Q

V_CC

Q

DQML

WE

CAS

RAS

CS

NC

DQMU

CLK

CKE

NC

A9

NC

A8

A7

A0

A6

A1

A5

A2

A4

A3

V_SS

V_CC

(Top View)

2

HM5221605 Series

Pin Description

Pin name

Function

A0 to A9

Address input

•

Row address

A0 to A6, A8

A0 to A7

Column address

Bank select address A9

I/O0 to I/O15

CS

Data-input/output

Chip select

RAS

Row address strobe command

Column address strobe command

Write enable command

CAS

WE

DQMU

DQML

Upper byte input/output mask

Lower byte input/output mask

CLK

CKE

V_CC

Clock input

Clock enable

Power for internal circuit

Ground for internal circuit

Power for I/O circuit

Ground for I/O circuit

No connection

V_SS

V_CCQ

V_SSQ

NC

3

HM5221605 Series

Block Diagram

A0 – A9

A0 – A7

A0 – A6, A8, A9

Refresh

counter

Column address

counter

Column address

buffer

Row address

buffer

Row decoder

Memory array

Bank 0

Bank 1

256 row X 256 column X 16 bit

Input

buffer

Output

buffer

Control logic &

timing generator

I/O0 – I/O15

4

HM5221605 Series

Pin Functions

CLK (input pin): CLK is the master clock input to this pin. The other input signals are referred at CLK

rising edge.

CS (input pin): When CS is Low, the command input cycle becomes valid. When CS is High, all inputs

are ignored. However, internal operations (bank active, burst operations, etc.) are held.

RAS, CAS, and WE (input pins): Although these pin names are the same as those of conventional

DRAMs, they function in a different way. These pins define operation commands (read, write, etc.)

depending on the combination of their voltage levels. For details, refer to the command operation section.

A0 to A8 (input pins): Row address (AX0 to AX6, AX8) is determined by A0 to AX6, A8 level at the

bank active command cycle CLK rising edge. Column address (AY0 to AY7) is determined by A0 to A7

level at the read or write command cycle CLK rising edge. And this column address becomes burst access

start address. A8 defines the precharge mode. When A8 = High at the precharge command cycle, both

banks are precharged. But when A8 = Low at the precharge command cycle, only the bank that is selected

by A9 (BS) is precharged.

A9 (input pin): A9 is a bank select signal (BS). The memory array of the HM5221605 is divided into

bank 0 and bank 1, both which contain 256 row × 256 column × 16 bits. If A9 is Low, bank 0 is selected,

and if A9 is High, bank 1 is selected.

CKE (input pin): This pin determines whether or not the next CLK is valid. If CKE is High, the next

CLK rising edge is valid. If CKE is Low, the next CLK rising edge is invalid. This pin is used for power-

down and clock suspend modes.

DQMU/DQML (input pins): DQMU controls upper byte and DQML controls lower byte input/output

buffers.

Read operation: If DQMU/DQML is High, the output buffer becomes High-Z. If the DQMU/DQML is

Low, the output buffer becomes Low-Z.

Write operation: If DQMU/DQML is High, the previous data is held (the new data is not written). If

DQMU/DQML is Low, the data is written.

I/O0 to I/O15 (I/O pins): Data is input to and output from these pins. These pins are the same as those of

a conventional DRAM.

V_CCand V_CCQ (power supply pins): 3.3 V is applied. (V_CCis for the internal circuit and V_CCQ is for the

output buffer.)

V_SSand V_SSQ (power supply pins): Ground is connected. (V_SSis for the internal circuit and V_SSQ is for

the output buffer.)

5

HM5221605 Series

Command Operation

Command Truth Table

The synchronous DRAM recognizes the following commands specified by the CS, RAS, CAS, WE and

address pins.

CKE

A0

Function

Symbol

DESL

NOP

n - 1 n

CS

H

L

RAS CAS WE A9

A8 to A7

Ignore command

No operation

H

×

V

×

L

×

V

×

V

H

L

H

L

H

L

×

Burst stop in full page

BST

L

×

Column address and read command READ

L

H

L

V

×

Read with auto-precharge

READ A

L

H

L

Column address and write command WRIT

L

Write with auto-precharge

WRIT A

L

H

V

L

Row address strobe and bank active ACTV

L

H

L

H

L

Precharge select bank

Precharge all bank

Refresh

PRE

L

PALL

L

H

×

V

REF/SELF

MRS

L

H

L

×

Mode register set

L

V

Note: H: V_IH. L: V_IL. ×: V_IHor V_IL. V: Valid address input

Ignore command [DESL]: When this command is set (CS is High), the synchronous DRAM ignore

command input at the clock. However, the internal status is held.

No operation [NOP]: This command is not an execution command. However, the internal operations

continue.

Burst stop in full-page [BST]: This command stops a full-page burst operation (burst length = full-page

(256)), and is illegal otherwise. Full page burst continues until this command is input. When data

input/output is completed for a full-page of data (256), it automatically returns to the start address, and

input/output is performed repeatedly.

Column address strobe and read command [READ]: This command starts a read operation. In

addition, the start address of burst read is determined by the column address (AY0 to AY7) and the bank

select address (BS). After the read operation, the output buffer becomes High-Z.

Read with auto precharge [READ A]: This command automatically performs a precharge operation after

a burst read with a burst length of 1, 2, 4 or 8. When the burst length is full-page (256), this command is

illegal.

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HM5221605 Series

Column address strobe and write command [WRIT]: This command starts a write operation. When the

burst write mode is selected, the column address (AY0 to AY7) and the bank select address (A9) become

the burst write start address. When the single write mode is selected, data is only written to the location

specified by the column address (AY0 to AY7) and the bank select address (A9).

Write with auto precharge [WRIT A]: This command automatically performs a precharge operation

after a burst write with a length of 1, 2, 4 or 8, or after a single write operation. When the burst length is

full-page (256), this command is illegal.

Row address strobe and bank activate [ACTV]: This command activates the bank that is selected by A9

(BS) and determines the row address (AX0 to AX6, AX8). When A9 is Low, bank 0 is activated. When

A9 is High, bank 1 is activated.

Precharge selected bank [PRE]: This command starts precharge operation for the bank selected by A9.

If A9 is Low, bank 0 is selected. If A9 is High, bank 1 is selected.

Precharge all banks [PALL]: This command starts a precharge operation for all banks.

Refresh [REF/SELF]: This command starts the refresh operation. There are two types of refresh

operation, the one is auto refresh, and the other is self refresh. For details, refer to the CKE truth table

section.

Mode register set [MRS]: Synchronous DRAM has a mode register that defines how it operates. The

mode register is specified by the address pins (A0 to A9) at the mode register set cycle. For details, refer to

the mode register configuration. After power on, the contents of the mode register are undefined, execute

the mode register set command to set up the mode register.

DQM Truth Table

CKE

Function

Symbol

ENBU

n - 1

n

×

DQMU

DQML

Upper byte write enable/output enable

Lower byte write enable/output enable

Upper byte write inhibit/output disable

Lower byte write inhibit/output disable

Note: H: V_IH. L: V_IL. ×: V_IHor V_IL.

H

L

×

H

×

L

×

H

ENBL

H

MASKU

MASKL

H

The HM5221605 series can mask input/output data by means of DQMU and DQML. DQMU masks the

upper byte and DQML masks the lower byte.

During reading, the output buffer is set to Low-Z by setting DQMU/DQML to Low, enabling data output.

On the other hand, when DQMU/DQML is set to High, the output buffer becomes High-Z, disabling data

output.

During writing, data is written by setting DQMU/DQML to Low. When DQMU/DQML is set to High, the

previous data is held (the new data is not written). Desired data can be masked during burst read or burst

7

HM5221605 Series

write by setting DQMU/DQML. For details, refer to the DQM control section of the HM5221605

operating instructions.

CKE Truth Table

CKE

Current state Function

n - 1

H

L

n

L

CS

H

×

RAS CAS WE

Address

Active

Any

Clock suspend mode entry

Clock suspend

×

H

×

L

×

H

×

L

×

L

×

Clock suspend Clock suspend mode exit

L

H

L

H

×

L

H

L

Idle

Auto-refresh command

Self-refresh entry

REF

H

L

H

×

SELF

L

Power down entry

L

H

×

H

×

H

×

H

×

H

×

H

×

L

H

L

Self refresh

Power down

Self refresh exit

Power down exit

SELFX

H

×

L

H

L

H

×

L

H

Note: H: V_IH. L: V_IL. ×: V_IHor V_IL.

Clock suspend mode entry: The synchronous DRAM enters clock suspend mode from active mode by

setting CKE to Low. The clock suspend mode changes depending on the current status (1 clock before) as

shown below.

ACTIVE clock suspend: This suspend mode ignores inputs after the next clock by internally maintaining

the bank active status.

READ suspend and READ A suspend: The data being output is held (and continues to be output).

WRITE suspend and WRIT A suspend: In this mode, external signals are not accepted. However, the

internal state is held.

Clock suspend: During clock suspend mode, keep the CKL to Low.

Clock suspend mode exit: The synchronous DRAM exits from clock suspend mode by setting CKE to

High during the clock suspend state.

IDLE: In this state, all banks are not selected, and completed precharge operation.

Auto refresh command [REF]: When this command is input from the IDLE state, the synchronous

DRAM starts auto-refresh operation. (The auto-refresh is the same as the CBR refresh of conventional

DRAMs.) During the auto-refresh operation, refresh address and bank select address are generated inside

the synchronous DRAM. For every auto-refresh cycle, the internal address counter is updated.

Accordingly, 512 times are required to refresh the entire memory. Before executing the auto-refresh

8

HM5221605 Series

command, all the banks must be in the IDLE state. In addition, since the precharge for all banks is

automatically performed after auto-refresh, no precharge command is required after auto refresh.

Self refresh entry [SELF]: When this command is input during the IDLE state, the synchronous DRAM

starts self refresh operation. After the execution of this command, self refresh continues while CKE is

Low. Since self refresh is performed internally and automatically, external refresh operations are

unnecessary.

Power down mode entry: When this command is executed during the IDLE state, the synchronous

DRAM enters power down mode. In power down mode, power consumption is suppressed by cutting off

the initial input circuit.

Self refresh exit: When this command is executed during self refresh mode, the synchronous DRAM can

exit from self refresh mode. After exiting from self refresh mode, the synchronous DRAM enters the IDLE

state.

Power down exit: When this command is executed at the power down mode, the synchronous DRAM can

exit from power down mode. After exiting from power down mode, the synchronous DRAM enters the

IDLE state.

9

HM5221605 Series

Function Truth Table

The following table shows the operations that are performed when each command is issued in each mode of

the synchronous DRAM.

Current state CS

Precharge

RAS CAS WE Address

Command

DESL

Operation

H

L

H

L

×

Enter IDLE after t_RP

ILLEGAL

H

L

H

L

H

L

NOP

BST

H

L

BA, CA, A8 READ/READ A ILLEGAL

BA, CA, A8 WRIT/WRIT A ILLEGAL

L

H

L

H

L

BA, RA

ACTV

ILLEGAL

NOP

L

BA, A8

PRE, PALL

REF, SELF

MRS

L

H

L

×

L

MODE

Idle

×

DESL

H

L

H

L

H

L

NOP

BST

NOP

H

L

BA, CA, A8 READ/READ A ILLEGAL

BA, CA, A8 WRIT/WRIT A ILLEGAL

L

H

L

H

L

BA, RA

BA, A8

×

ACTV

Bank and row active

NOP

L

PRE, PALL

REF, SELF

MRS

L

H

L

Refresh

L

MODE

Mode register set

10

HM5221605 Series

Current state CS

RAS CAS WE Address

Command

DESL

Operation

Row active

H

L

×

NOP

H

L

H

L

H

L

NOP

BST

H

L

BA, CA, A8 READ/READ A Begin read

BA, CA, A8 WRIT/WRIT A Begin write

L

H

BA, RA

ACTV

Other bank active ILLEGAL on same

bank*³

L

H

L

H

L

BA, A8

PRE, PALL

REF, SELF

MRS

Precharge

L

H

L

×

ILLEGAL

L

MODE

ILLEGAL

Read

×

DESL

Continue burst to end

Burst stop to full page

H

L

H

L

NOP

BST

H

BA, CA, A8 READ/READ A Continue burst read to CAS latency

and New read

L

H

L

BA, CA, A8 WRIT/WRIT A Term burst read/start write

H

BA, RA

ACTV

Other bank active ILLEGAL on same

bank*³

L

H

L

BA, A8

PRE, PALL

REF, SELF

MRS

Term burst read and Precharge

ILLEGAL

L

H

L

×

L

MODE

ILLEGAL

Read with auto H

X

H

L

×

DESL

Continue burst to end and precharge

ILLEGAL

precharge

L

H

L

H

L

NOP

BST

H

L

BA, CA, A8 READ/READ A ILLEGAL

BA, CA, A8 WRIT/WRIT A ILLEGAL

L

H

BA, RA

ACTV

Other bank active ILLEGAL on same

bank*³

L

H

L

H

L

BA, A8

×

PRE, PALL

REF, SELF

MRS

ILLEGAL

MODE

11

HM5221605 Series

Current state CS

RAS CAS WE Address

Command

DESL

Operation

Write

H

L

×

Continue burst to end

Burst stop on full page

H

L

H

L

H

L

NOP

BST

H

L

BA, CA, A8 READ/READ A Term burst and New read

BA, CA, A8 WRIT/WRIT A Term burst and New write

L

H

BA, RA

ACTV

Other bank active ILLEGAL on same

bank*³

L

H

L

BA, A8

PRE, PALL

REF, SELF

MRS

Term burst write and Precharge*²

L

H

L

×

ILLEGAL

L

MODE

ILLEGAL

Write with auto H

×

DESL

Continue burst to end and precharge

ILLEGAL

precharge

L

H

L

H

L

H

L

NOP

BST

H

L

BA, CA, A8 READ/READ A ILLEGAL

BA, CA, A8 WRIT/WRIT A ILLEGAL

L

H

BA, RA

ACTV

Other bank active ILLEGAL on same

bank*³

L

H

L

H

L

BA, A8

PRE, PALL

REF, SELF

MRS

ILLEGAL

L

H

L

×

ILLEGAL

L

MODE

ILLEGAL

Refresh

×

H

L

×

DESL

Enter IDLE after t_RC

(auto refresh)

H

L

H

L

NOP

BST

H

L

BA, CA, A8 READ/READ A ILLEGAL

BA, CA, A8 WRIT/WRIT A ILLEGAL

L

H

L

H

L

BA, RA

BA, A8

×

ACTV

ILLEGAL

L

PRE, PALL

REF, SELF

MRS

L

H

L

MODE

Notes 1. H: V_IH. L: V_IL. ×: V_IHor V_IL.

The other combinations are inhibit.

2. An interval of t_RWLis required between the final valid data input and the precharge command.

3. If t_RRDis not satisfied, this operation is illegal.

12

HM5221605 Series

From [PRECHARGE]

To [DESL], [NOP] or [BST]: When these commands are executed, the synchronous DRAM enters the

IDLE state after t_RPhas elapsed from the completion of precharge.

From [IDLE]

To [DESL], [NOP], [BST], [PRE] or [PALL]: These commands result in no operation.

To [ACTV]: The bank specified by the address pins and the ROW address is activated.

To [REF], [SELF]: The synchronous DRAM enters refresh mode (auto refresh or self refresh).

To [MRS]: The synchronous DRAM enters the mode register set cycle.

From [ROW ACTIVE]

To [DESL], [NOP] or [BST]: These commands result in no operation.

To [READ], [READ A]: A read operation starts. (However, an interval of t_RCDis required.)

To [WRIT], [WRIT A]: A write operation starts. (However, an interval of t_RCDis required.)

To [ACTV]: This command makes the other bank active. (However, an interval of t_RRDis required.)

Attempting to make the currently active bank active results in an illegal command.

To [PRE], [PALL]: These commands set the synchronous DRAM to precharge mode. (However, an

interval of t_RASis required.)

From [READ]

To [DESL], [NOP]: These commands continue read operations until the burst operation is completed.

To [BST]: This command stops a full-page burst.

To [READ], [READ A]: Data output by the previous read command continues to be output. After CAS

latency, the data output resulting from the next command will start.

To [WRIT], [WRIT A]: These commands stop a burst read, and start a write cycle.

To [ACTV]: This command makes other banks bank active. (However, an interval of t_RRDis required.)

Attempting to make the currently active bank active results in an illegal command.

To [PRE], [PALL]: These commands stop a burst read, and the synchronous DRAM enters precharge

mode.

13

HM5221605 Series

From [READ with AUTO-PRECHARGE]

To [DESL], [NOP]: These commands continue read operations until the burst operation is completed, and

the synchronous DRAM then enters precharge mode.

To [ACTV]: This command makes other banks bank active. (However, an interval of t_RRDis required.)

Attempting to make the currently active bank active results in an illegal command.

From [WRITE]

To [DESL], [NOP]: These commands continue write operations until the burst operation is completed.

To [BST]: This command stops a full-page burst.

To [READ], [READ A]: These commands stop a burst and start a read cycle.

To [WRIT], [WRIT A]: These commands stop a burst and start the next write cycle.

To [ACTV]: This command makes the other bank active. (However, an interval of t_RRDis required.)

Attempting to make the currently active bank active results in an illegal command.

To [PRE], [PALL]: These commands stop burst write and the synchronous DRAM then enters precharge

mode.

From [WRITE with AUTO PRECHARGE]

To [DESL], [NOP]: These commands continue write operations until the burst is completed, and the

synchronous DRAM enters precharge mode.

To [ACTV]: This command makes the other bank active. (However, an interval of t_RRDis required.)

Attempting to make the currently active bank active results in an illegal command.

From [REFRESH]

To [DESL], [NOP], [BST]: After an auto refresh cycle (after t_RC), the synchronous DRAM automatically

enters the IDLE state.

14

HM5221605 Series

Simplified State Diagram

SELF

REFRESH

SR ENTRY

SR EXIT

*1

MRS

REFRESH

MODE

REGISTER

SET

AUTO

IDLE

REFRESH

CKE

CKE_

IDLE

POWER

DOWN

ACTIVE

CLOCK

SUSPEND

CKE_

CKE

ROW

ACTIVE

BST

(on full page)

BST

(on full page)

WRITE

READ

Write

WRITE

WITH

AP

READ

WITH

AP

Read

CKE_

WRITE

SUSPEND

READ

SUSPEND

WRITE

READ

WRITE

CKE

READ

WITH AP

WRITE

WITH AP

WRITE

WITH AP

READ

WITH AP

PRECHARGE

CKE_

WRITEA

SUSPEND

READA

SUSPEND

WRITEA

READA

CKE

PRECHARGE PRECHARGE

POWER

APPLIED

POWER

ON

PRECHARGE

Automatic transition after completion of command.

Transition resulting from command input.

Note: 1. After the auto-refresh operation, precharge operation is performed automatically and

enter the IDLE state.

15

HM5221605 Series

Mode Register Configuration

The mode register is set by the input to the address pins (A0 to A9) during mode register set cycles. The

mode register consists of five sections, each of which is assigned to address pins.

A9 and A8: (OPCODE): The synchronous DRAM has two types of write modes. One is the burst write

mode, and the other is the single write mode. These bits specify write mode.

Burst read and BURST WRITE: Burst write is performed for the specified burst length starting from the

column address specified in the write cycle.

Burst read and SINGLE WRITE: Data is only written to the column address specified during the write

cycle, regardless of the burst length.

A7: Keep this bit Low at the mode register set cycle.

A6, A5, A4: (LMODE): These pins specify the CAS latency.

A3: (BT): A burst type is specified. When full-page burst is performed, only "sequential" can be selected.

A2, A1, A0: (BL): These pins specify the burst length.

16

HM5221605 Series

A9

A8

A7

0

A6

A5

A4

A3

BT

A2

A1

BL

A0

OPCODE

LMODE

A6 A5 A4 CAS Latency

A3 Burst Type

Burst Length

A2 A1 A0

R

1

0

1

0

1

×

0

1

0

1

×

0

1

Sequential

Interleave

BT = 0 BT = 1

1

2

1

0

1

0

1

0

1

0

1

0

1

0

1

2

0

1

3

4

R

8

R

A9 A8 Write mode

R

0

1

0

1

0

1

Burst read and burst write

F.P.

R

Burst read and SINGLE WRITE

R

F.P. = Full Page (256)

R is Reserved (inhibit)

× = 0 or 1

Burst Sequence

Burst length = 2

Starting Ad. Addressing(decimal)

Burst length = 4

Starting Ad. Addressing(decimal)

A0

0

Sequence Interleave

A1

0

A0 Sequence

Interleave

0, 1,

1, 0,

0, 1,

1, 0,

0

1

0

1

0, 1, 2, 3,

1, 0, 3, 2,

2, 3, 0, 1,

3, 2, 1, 0,

1

0

1, 2, 3, 0,

2, 3, 0, 1,

1

3,

0, 1, 2,

Burst length = 8

Starting Ad.

Addressing(decimal)

A2 A1 A0 Sequence

Interleave

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0, 1, 2, 3, 4, 5, 6, 7,

1, 2, 3, 4, 5, 6, 7, 0,

2, 3, 4, 5, 6, 7, 0, 1,

3, 4, 5, 6, 7, 0, 1, 2,

4, 5, 6, 7, 0, 1, 2, 3,

5, 6, 7, 0, 1, 2, 3, 4,

6, 7, 0, 1, 2, 3, 4, 5,

7, 0, 1, 2, 3, 4, 5, 6,

0, 1, 2, 3, 4, 5, 6, 7,

1, 0, 3, 2, 5, 4, 7, 6,

2, 3, 0, 1, 6, 7, 4, 5,

3, 2, 1, 0, 7, 6, 5, 4,

4, 5, 6, 7, 0, 1, 2, 3,

5, 4, 7, 6, 1, 0, 3, 2,

6, 7, 4, 5, 2, 3, 0, 1,

7, 6, 5, 4, 3, 2, 1, 0,

17

HM5221605 Series

Operation of HM5221605 Series

Read/Write Operations

Bank active: Before executing a read or write operation, the corresponding bank and the row address must

be activated by the bank active (ACTV) command. Either bank 0 or bank 1 is activated according to the

status of the A9 pin, and the row address (AX0 to AX6, AX8) is activated by the A0 to A8 pins at the bank

active command cycle. An interval of t_RCDis required between the bank active command input and the

following read/write command input.

Read operation: A read operation starts when a read command is input. Output buffer becomes Low-Z in

the (CAS Latency - 1) cycle after read command set. HM5221605 series can perform a burst read

operation. The burst length can be set to 1,2,4,8 or full-page (256). The start address for a burst read is

specified by the column address (AY0 to AY7) and the bank select address (A9) at the read command set

cycle. In a read operation, data output starts after the number of cycles specified by the CAS Latency. The

CAS Latency can be set to 1, 2, 3. When the burst length is 1, 2, 4 or 8, the Dout buffer automatically

becomes High-Z at the next cycle after the successive burst-length data has been output. When the burst

length is full-page (256), data is repeatedly output until the burst stop command is input. The CAS latency

and burst length must be specified at the mode register.

CAS Latency

CLK

t

RCD

Command

Address

READ

ACTV

Row

Column

out 3

out 1 out 2

out 0 out 1 out 2

out 1 out 2

out 0

CL = 1

CL = 2

Dout

out 3

out 0

out 3

CL = 3

CL: CAS latency

Burst length = 4

18

HM5221605 Series

Burst Length

CLK

t

RCD

Command

Address

ACTV

Row

READ

Column

out 0

BL = 1

out 0 out 1

BL = 2

BL = 4

BL = 8

out 3

out 0 out 1 out 2

Dout

out 5 out 6 out 7

out 4

out 255

out 0 out 1

out 0 out 1 out 2 out 3 out 4

out 6 out 7 out 8

out 5

BL = full page (256)

BL: Burst length

CAS latency = 2

Write operation: Burst write or single write mode is selected by the OPCODE (A9, A8) of the mode

register.

1. Burst write: A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write

starts in the same cycle as a write command set. (The latency of data input is 0.) The burst length can be

set to 1, 2, 4, 8, and full-page, like burst read operations. The write start address is specified by the column

address (AY0 to AY7) and the bank select address (A9) at the write command set cycle.

Burst Write

CLK

t

RCD

Command

Address

ACTV

Row

WRIT

Column

in 0

BL = 1

in 1

BL = 2

BL = 4

BL = 8

in 3

in 2

in 0

Din

in 5

in 6 in 7

in 3 in 4

in 255

in 4

in 3

in 8

in 0

in 1

in 0 in 1 in 2

BL = full page (256)

CAS latency = 1, 2, 3

19

HM5221605 Series

2. Single write: A single write operation is enabled by setting OPCODE (A9, A8) to (1, 0). In a single

write operation, data is only written to the column address (AY0 to AY7) and the bank select address (A9)

specified by the write command set cycle without regard to the burst length setting. (The latency of data

input is 0).

Single Write

CLK

t

RCD

Command

Write

Active

Row

Column

in 0

Address

Din

CAS latency = 1, 2, 3

Burst length = 1, 2, 4, 8, full page

20

HM5221605 Series

Auto Precharge

Read with auto precharge: In this operation, since precharge is automatically performed after completing

a read operation, a precharge command need not be executed after each read operation. The command

executed for the same bank after the execution of this command must be the bank active (ACTV)

command. In addition, an interval defined by l_APRis required before execution of the next command.

CAS latency

Precharge start cycle

3

2

1

2 cycle before the final data is output

1 cycle before the final data is output

same cycle as the final data is output

CLK

CL=1 Command

READ

ACTV

out0

out1

out0

out2

out1

out3

Dout

l

APR

CL=2 Command

Dout

ACTV

out2

out3

l

APR

CL=3 Command

Dout

READ

ACTV

out0

out1

out2

out3

l

APR

Note: Internal auto-precharge starts at the timing indicated by " ".

At CLK = 33 MHz (I changes depending on the operating frequency.

APR

21

HM5221605 Series

Write with auto precharge: In this operation, since precharge is automatically performed after

completing a burst write or single write operation, a precharge command need not be executed after each

write operation. The command executed for the same bank after the execution of this command must be

the bank active (ACTV) command. In addition, an interval of l_APWis required between the final valid data

input and input of the next command.

Burst Write (Burst Length = 4)

CLK

WRIT

in0

ACTV

Command

I/O (input)

in1

in2

in3

l

APW

Single Write

CLK

Command

I/O (input)

WRIT

in

ACTV

l

APW

Full-page Burst Stop

Burst stop command during burst read: The burst stop (BST) command is used to stop data output

during a full-page burst. The BST command sets the output buffer to High-Z and stops the full-page burst

read. The timing from command input to the last data changes depending on the CAS latency setting.

When the CAS latency is 3, the data becomes invalid two cycles after the BST command. In addition, the

BST command is valid only during full-page burst mode, and is invalid with burst lengths of 1, 2, 4 and 8.

CAS latency

BST to valid data

BST to High impedance

1

2

3

0

1

2

1

2

3

22

HM5221605 Series

CAS Latency = 1, Burst Length = full page

CLK

BST

Command

I/O (output)

out

l

BSR

0 cycle

BSH

1 cycle

CAS Latency = 2, Burst Length = full page

CLK

BST

Command

I/O (output)

out

l

= 2 cycle

BSH

l

= 1 cycle

BSR

CAS Latency = 3, Burst Length = full page

CLK

BST

Command

I/O (output)

out

l

out

l

= 3 cycle

BSH

= 2 cycle

BSR

23

HM5221605 Series

Burst stop command at burst write: The burst stop command (BST command) is used to stop data input

during a full-page burst write. Data is still written in the same cycle as the BST command, but no data is

written in subsequent cycles. In addition, the BST command is only valid during full-page burst mode, and

is invalid with burst lengths of 1, 2, 4 and 8. And an interval of t_RWLis required between the BST command

and the next precharge command.

Burst Length = full page

CLK

BST

in

PRE/PALL

Command

I/O (input)

in

l

= 1 cycle

BSW

t

RWL

24

HM5221605 Series

Command Intervals

Read command to Read command interval

1. Same bank, same ROW address: When another read command is executed at the same ROW address

of the same bank as the preceding read command execution, the second read can be performed after an

interval of no less than 1 cycle. Even when the first command is a burst read that is not yet finished, the

data read by the second command will be valid.

READ to READ Command Interval (same ROW address in same bank)

CLK

Command

READ

ACTV

Row

READ

Address

(A0-A8)

Column B

Column A

BS(A9)

Dout

out A0

out B2 out B3

out B0 out B1

Column =B

Dout

Bank0

Active

Column =A Column =B Column =A

Read Read Dout

CAS latency = 3

Burst length = 4

Bank0

2. Same bank, different ROW address: When the ROW address changes on same bank, consecutive

read commands cannot be executed; it is necessary to separate the two read commands with a precharge

command and a bank-active command.

25

HM5221605 Series

3. Different bank: When the bank changes, the second read can be performed after an interval of no less

than 1 cycle, provided that the other bank is in the bank-active state. Even when the first command is a

burst read that is not yet finished, the data read by the second command will be valid.

READ to READ Command Interval (different bank)

CLK

Command

ACTV

Row 1

READ

Address

(A0-A8)

Column A

Column B

Row 0

BS(A9)

Dout

out A0

out B2 out B3

out B0 out B1

Bank1

Dout

CAS latency = 3

Burst length = 4

Bank0

Dout

Bank0

Active

Bank1 Bank0 Bank1

Active Read Read

Write command to Write command interval

1. Same bank, same ROW address: When another write command is executed at the same ROW

address of the same bank as the preceding write command, the second write can be performed after an

interval of no less than 1 cycle. In the case of burst writes, the second write command has priority.

WRITE to WRITE Command Interval (same ROW address in same bank)

CLK

Command

WRIT

ACTV

Row

WRIT

Address

(A0-A8)

Column B

Column A

BS(A9)

Din

in A0

in B2 in B3

in B0 in B1

Burst write mode

Burst length = 4

Bank0

Active

Column =A Column =B

Write Write

2. Same bank, different ROW address: When the ROW address changes, consecutive write commands

cannot be executed; it is necessary to separate the two write commands with a precharge command and a

bank-active command.

3. Different bank: When the bank changes, the second write can be performed after an interval of no less

than 1 cycle, provided that the other bank is in the bank-active state. In the case of burst write, the second

write command has priority.

26

HM5221605 Series

WRITE to WRITE Command Interval (different bank)

CLK

Command

ACTV

Row 1

WRIT

ACTV

Address

(A0-A8)

Column A

Column B

Row 0

BS(A9)

Din

in A0

in B2 in B3

in B0 in B1

Burst write mode

Burst length = 4

Bank0

Active

Bank1 Bank0 Bank1

Active Write Write

Read command to Write command interval

1. Same bank, same ROW address: When the write command is executed at the same ROW address of

the same bank as the preceding read command, the write command can be performed after an interval of no

less than 1 cycle. However, DQMU/DQML must be set High so that the output buffer becomes High-Z

before data input.

READ to Write Command Interval (1)

CLK

Command

WRIT

READ

CL=1

CL=2

CL=3

DQMU

/DQML

in B0

in B3

in B1 in B2

Din

Burst Length = 4

Burst write

High-Z

Dout

27

HM5221605 Series

READ to Write Command Interval (2)

CLK

Command

WRIT

READ

DQMU

/DQML

2 clock

High-Z

CL=1

Dout

CL=2

CL=3

High-Z

Din

2. Same bank, different ROW address: When the ROW address changes, consecutive write commands

cannot be executed; it is necessary to separate the two write commands with a precharge command or a

bank-active command.

3. Different bank: When the bank changes, the write command can be performed after an interval of no

less than 1 cycle, provided that the other bank is in the bank-active state. However, DQML/DQMU must

be set High so that the output buffer becomes High-Z before data input.

28

HM5221605 Series

Write command to Read command interval

1. Same bank, same ROW address: When the read command is executed at the same ROW address of

the same bank as the preceding write command, the write command can be performed after an interval of

no less than 1 cycle. However, in the case of a burst write, data will continue to be written until one cycle

before the read command is executed.

WRITE to READ Command Interval (1)

CLK

WRIT

READ

Command

DQMU/DQML

Din

in A0

Dout

out B0

out B1

out B2

out B3

Burst Write Mode

CAS Latency = 1

Burst Length = 4

Bank0

Column=A

Write

CAS Latency

Column=B

Read

Column=B

Dout

WRITE to READ Command Interval (2)

CLK

WRIT

READ

Command

DQMU/DQML

Din

in A0

in A1

Dout

out B0

CAS Latency

out B1

out B2

out B3

Burst Write Mode

CAS Latency = 1

Burst Length = 4

Bank0

Column=A

Write

Column=B

Read

Column=B

Dout

29

HM5221605 Series

2. Same bank, different ROW address: When the ROW address changes, consecutive write commands

cannot be executed; it is necessary to separate the two write commands with a precharge command and a

bank-active command.

3. Different bank: When the bank changes, the read command can be performed after an interval of no

less than 1 cycle, provided that the other bank is in the bank-active state. However, in the case of a burst

write, data will continue to be written until one cycle before the read command is executed (as in the case

of the same bank and the same address).

Read command to Precharge command interval (same bank): When the precharge command is

executed for the same bank as the read command that preceded it, the minimum interval between the two

commands is one cycle. However, since the output buffer then becomes High-Z after the cycles defined by

l_HZP, there is a possibility that burst read data output will be interrupted, if the precharge command is input

during burst read. To read all data by burst read, the cycles defined by l_EPmust be assured as an interval

from the final data output to precharge command execution.

READ to PRECHARGE Command Interval (same bank): To output all data

CAS Latency = 1, Burst Length = 4

CLK

PRE/PALL

out A3

READ

Command

Dout

out A0

out A1

out A2

l

= 0 cycle

EP

CL=1

CAS Latency = 2, Burst Length = 4

CLK

PRE/PALL

out A2

READ

Command

Dout

out A0

out A1

out A3

CL=2

l

= -1 cycle

EP

30

HM5221605 Series

CAS Latency = 3, Burst Length = 4

CLK

PRE/PALL

out A1

READ

Command

Dout

out A0

out A2

out A3

CL=3

l

= -2 cycle

EP

READ to PRECHARGE Command Interval (same bank): To stop output data

CAS Latency = 1, Burst Length = 2, 4, 8

CLK

PRE/PALL

out A0

READ

Command

Dout

High-Z

l

=1

HZP

CAS Latency = 2, Burst Length = 2, 4, 8

CLK

READ

PRE/PALL

Command

Dout

High-Z

out A0

=2

l

HZP

CAS Latency = 3, Burst Length = 2, 4, 8

CLK

PRE/PALL

READ

Command

Dout

High-Z

out A0

l

=3

HZP

31

HM5221605 Series

Write command to Precharge command interval (same bank): When the precharge command is

executed for the same bank as the write command that preceded it, the minimum interval between the two

commands is 1 cycle. However, if the burst write operation is unfinished, the input data must be masked

by means of DQMU and DQML for assurance of the cycle defined by t_RWL

WRITE to PRECHARGE Command Interval (same bank)

Burst Length = 4 (To stop write operation)

.

CLK

WRIT

PRE/PALL

Command

DQMU/DQML

Din

t

RWL

CLK

WRIT

PRE/PALL

Command

DQMU/DQML

Din

in A0

in A1

t

RWL

Burst Length = 4 (To write all data)

CLK

WRIT

PRE/PALL

Command

DQMU/DQML

Din

in A0

in A1

in A2

in A3

t

RWL

32

HM5221605 Series

Bank active command interval

1. Same bank: The interval between the two bank-active commands must be no less than t_RC.

Bank active to bank active for same bank

CLK

ACTV

ROW

ACTV

ROW

Command

Address

(A0-A8)

BS (A9)

t

RC

Bank 0

Active

Bank 0

Active

2. In the case of different bank-active commands: The interval between the two bank-active commands

must be no less than t_RRD

.

Bank active to bank active for different bank

CLK

ACTV

Command

Address

(A0-A8)

ROW:0

ROW:1

BS (A9)

t

RRD

Bank 0

Active

Bank 1

Active

33

HM5221605 Series

Mode register set to Bank-active command interval: The interval between setting the mode register and

executing a bank-active command must be no less than t_RSA

.

CLK

Command

MRS

ACTV

Address

(A0-A9)

CODE

BS & ROW

t

RSA

Mode

Register Set

Bank

Active

34

HM5221605 Series

DQM Control

The DQMU and DQML mask the lower and upper bytes of the I/O data, respectively. The timing of

DQMU/DQML is different during reading and writing.

Reading: When data is read, the output buffer can be controlled by DQMU/DQML. By setting

DQMU/DQML to Low, the output buffer becomes Low-Z, enabling data output. By setting

DQMU/DQML to High, the output buffer becomes High-Z, and the corresponding data is not output.

However, internal reading operations continue. The latency of DQMU/DQML during reading is 2.

CLK

DQMU

/DQML

High-Z

I/O (output)

out 0

l

out 1

out 3

= 2 Latency

DOD

Writing: Input data can be masked by DQMU/DQML. By setting DQMU/DQML to Low, data can be

written. In addition, when DQMU/DQML is set to High, the corresponding data is not written, and the

previous data is held. The latency of DQMU/DQML during writing is 0.

CLK

DQMU

/DQML

I/O (input)

in 3

in 0

in 1

l

= 0 Latency

DID

35

HM5221605 Series

Refresh

Auto refresh: All the banks must be precharged before executing an auto refresh command. Since the

auto refresh command updates the interval counter every time it is executed and determines the banks and

the ROW addresses to be refreshed, external address specification is not required. The refresh cycle is 512

cycles/8 ms. (512 cycles are required to refresh all the ROW addresses.) The output buffer becomes High-

Z after auto refresh start. In addition, since a precharge has been completed by an internal operation after

the auto refresh, an additional precharge operation by the precharge command is not required.

Self refresh: After executing a self refresh command, the self refresh operation continues while CKE is

held Low. During self refresh operation, all ROW addresses are refreshed by the internal refresh timer. A

self refresh is terminated by a self refresh exit command. After the self refresh, since it is impossible to

determine the address of the last ROW to be refreshed, an auto refresh should immediately be performed

for all addresses (512 cycles).

Others

Power down mode: The synchronous DRAM enters power down mode when CKE goes Low in the IDLE

state. In power down mode, power consumption is suppressed by deactivating the input initial circuit.

Power down mode continues while CKE is held Low. In addition, by setting CKE to High, the

synchronous DRAM exits from the power down mode, and command input is enabled from the next cycle.

In this mode, internal refresh is not performed.

Clock suspend mode: By driving CKE to Low during a bank-active or read/write operation, the

synchronous DRAM enters clock suspend mode. During clock suspend mode, external input signals are

ignored and the internal state is maintained. When CKE is driven High, the synchronous DRAM

terminates clock suspend mode, and command input is enabled from the next cycle. For details, refer to the

"CKE Truth Table".

Power up sequence: HM5221605 series has two types of power up sequence. Hitachi recommends that

the DQMU/DQML and the CKE are set to High to ensure output to be in the high impedance and to

prevent from bus contention.

1. During power up sequence, the DQMU/DQML and the CKE must be set to High. When 100 µs has

past after power on, all banks must be precharged using the precharge command. After t delay, set the

RP

mode register. And after t_RSAdelay, execute two or more cycles of auto refresh operation as dummy, an

interval of t_RCis required between two auto refresh commands.

2. During power up sequence, the DQMU/DQML and the CKE must be set to High. When 200 µs has

past after power on, all banks must be precharged using the precharge command. After t_RPdelay, set 8 or

more auto refresh commands. And set the mode register set command to initialize the mode register.

36

HM5221605 Series

Absolute Maximum Ratings

Parameter

Symbol

V_T

Value

Unit

V

Notes

1, 2

2

Voltage on any pin relative to V_SS

Supply voltage relative to V_SS

Short circuit output current

Power dissipation

–1.0 to +5.5

–1.0 to +4.6

50

V_CC

V

Iout

P_T

mA

W

1.0

Operating temperature

Storage temperature

Topr

Tstg

0 to +70

–55 to +125

°C

Notes: 1. V_IH(max) = 5.75 V for pulse width ≤ 5 ns.

2. Respect to V_SS.

Recommended DC Operating Conditions (Ta = 0 to +70°C)

Parameter

Symbol

V_CC, V_CCQ

V_SS, V_SSQ

V_IH

Min

3.0

0

Max

3.6

0

Unit

V

Notes

Supply voltage

1

V

Input high voltage

2.0

–0.3

5.5

0.8

V

1, 2

1, 3

Input low voltage

V_IL

V

Notes: 1. All voltage referred to V_SS

2. V_IH(max) = 5.75 V for pulse width ≤ 5 ns

3. V_IL(min) = –1.0 V for pulse width ≤ 5 ns

37

HM5221605 Series

DC Characteristics (Ta = 0 to 70°C, V_CC, V_CCQ = 3.3 V ± 0.3 V, V_SS, V_SSQ = 0 V)

HM5221605

-15

-17

-20

Parameter

Symbol Min Max Min Max Min Max Unit Test conditions

Notes

Operating current

I_CC1

I_CC2

—

85

—

75

—

70

mA Burst length = 1

_RC= min

1, 2, 4

t

Standby current

(Bank Disable)

—

3

2

—

3

2

—

3

2

mA CKE = V_IL, t_CK= min

5

6

mA CKE = V_IL

CLK = V_ILor V_IHFixed

—

33

—

30

—

26

mA CKE = V_IH,

NOP command,

3

t

_CK= min

Active standby current I_CC3

(Bank active)

—

7

—

7

—

7

mA CKE = V_IL, t_CK= min,

I/O = High-Z

1, 2

34

31

26

mA CKE = V_IH,

NOP command

1, 2, 3

t

_CK= min, I/O = High-Z

Burst operating

current

(CL = 1)

I_CC4

—

65

—

60

—

50

mA t_CK= min, BL = 4

1, 2, 4

(CL = 2)

I_CC4

I_CC5

I_CC6

—

100

105

70

—

95

65

2

—

80

85

60

2

mA

(CL = 3)

mA

Refresh current

Self refresh current

mA t_RC= min

2

mA V_IH≥ V_CC– 0.2

V_IL≤ 0.2 V

7

Input leakage current I_LI

–10 10

µA

0 ≤ Vin ≤ V_CC

Output leakage

current

I_LO

0 ≤ Vout ≤ V_CC

I/O = disable

Output high voltage

Output low voltage

V_OH

V_OL

2.4

—

2.4

—

2.4

—

V

I_OH= –2 mA

I_OL= 2 mA

0.4

Notes: 1. I_CCdepends on output load condition when the device is selected. I_CC(max) is specified at the

output open condition.

2. One bank operation.

3. Input signal transition is once per two CLK cycles.

4. Input signal transition is once per one CLK cycle.

5. After power down mode set, CLK operating current.

6. After power down mode set, no CLK operating current.

7. After self refresh mode set, self refresh current.

38

HM5221605 Series

Capacitance (Ta = 25°C, V_CC, V_CCQ = 3.3 V ± 0.3 V)

Parameter

Symbol

C_I1

Typ

—

Max

Unit

pF

Notes

1, 3

Input capacitance (Address)

Input capacitance (Signals)

Output capacitance (I/O)

5

7

C_I2

—

pF

1, 3

C_O

—

pF

1, 2, 3

Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.

2. DQMU/DQML = V_IHto disable Dout.

3. This parameter is sampled and not 100% tested.

AC Characteristics (Ta = 0 to 70°C, V_CC, V_CCQ = 3.3 V ± 0.3 V, V_SS, V_SSQ = 0 V)

HM5221605

-15

-17

-20

Parameter

Symbol Min Max

Min Max

Unit Notes

System clock cycle time

(CL = 1)

t_CK

30

—

34

17

7

—

40

20

8

—

ns

1

(CL = 2,3)

t_CK

15

CLK high pulse width

CLK low pulse width

t_CKH

t_CKL

4.5

1

7

8

Access time from CLK

(CL = 1)

t_AC

—

30

15

13

—

34

—

38

18

ns

1, 2

(CL = 2)

(CL = 3)

16.5

15.5

Read command to data valid time

(CL = 1)

t_ACK

—

30

43

—

34

—

38

58

ns

(CL = 2)

(CL = 3)

33.5

49.5

Data-out hold time

(CL = 1)

t_OH

t_LZ

4

2

0

—

4

2

0

—

4

2

0

—

ns

(CL = 2, 3)

CLK to Data-out low impedance

1, 2

1, 3

CLK to Data-out high impedance

(CL = 1)

t_HZ

4

2

15

10

4

2

17

12

4

2

19

14

ns

(CL = 2, 3)

39

HM5221605 Series

AC Characteristics (Ta = 0 to 70°C, V_CC, V_CCQ = 3.3 V ± 0.3 V, V , V_SSQ = 0 V)

SS

(cont.)

HM5221605

-15

-17

-20

Parameter

Symbol Min Max

Min Max

Unit Notes

Data-in setup time

t_DS

4

—

4

—

4

—

ns

1

Data in hold time

t_DH

2

1

Address setup time

Address hold time

t_AS

4

1

t_AH

2

1

CKE setup time

t_CES

t_CESP

t_CEH

t_CEHP

4

1, 4

1, 5

1

CKE setup time for CKE function exit

CKE hold time

13

2

15

2

17

2

CKE hold time for CKE function exit

17

4

19

4

22

4

1, 6

1

Command (CS, RAS, CAS, WE, DQM) t_CS

setup time

Command (CS, RAS, CAS, WE, DQM) t_CH

2

—

2

—

2

—

ns

1

hold time

Ref/Active to Ref/Active command

period

t_RC

110

120

130

Active to precharge command period

Active to precharge on full page mode

t_RAS

70

—

30

10000 75

10000 80

80000 —

10000 ns

80000 ns

1

t_RASC

t_RCD

80000

—

Active command to column command

(same bank)

34

—

40

—

ns

Precharge to active command period

t_RP

30

1

—

5

34

1

—

5

40

1

—

5

ns

ms

1

The last data-in to Precharge lead time t_RWL

Active (a) to Active (b) command period t_RRD

Register set to active command

Transition time (rise to fall)

Refresh period

t_RSA

t_T

t_REF

—

8

—

8

—

8

Notes: 1. AC measurement assumes t_T= 1 ns. Reference level for timing of input signals is 1.40 V.

2. Access time is measured at 1.40 V. Load condition is C_L= 50 pF with current source.

3. t_HZ(max) defines the time at which the outputs achieves ± 200 mV. Load condition is C_L= 5 pF

with current source.

4. t_CESdefine CKE setup time to CLK rising edge except power down exit command and active

clock suspend exit command.

5. t_CESPdefine CKE setup time to CLK rising edge for power down exit command and active clock

suspend exit command.

6. t_CEHPdefine CLK rising edge to CKE hold time for self refresh exit command, power down exit

command and active clock suspend exit command.

40

HM5221605 Series

Test Conditions

•

Input and output timing reference levels: 1.4 V

Input waveform and output load: See following figures.

Output

I/O

2.8 V

80%

500 Ω

Input

20%

+1.4 V

V

SS

CL

t

T

Relationship Between Frequency and Minimum Latency

HM5221605

-17

Parameter

-15

-20

Frequency (MHz)

66

33

30

58

17

29

34

50

20

25

40

t

_CK(ns)

Symbol 15

Note

Active command to column command

(same bank)

t_RCD

t_RC

t_RAS

t_RP

2

7

5

2

4

8

1

4

3

1

2

4

2

7

5

2

4

8

1

4

3

1

2

4

2

6

4

2

4

7

1

3

2

1

2

4

1

Active command to active command

(same bank)

1,

= [t_RAS+ t_RP]

Active command to precharge command

(same bank)

1

Precharge command to active command

(same bank)

1

Last data input to precharge command

(same bank)

t_RWL

t_RRD

l_APW

l_SEC

1

Active command to active command

(different bank)

1

Last data in to active command

(auto precharge, same bank)

= [t_RWL+ t_RP]

Self refresh exit to command input

Precharge command to high impedance

(CAS latency = 1)

l_HZP

—

2

1

2

3

—

2

1

2

3

—

2

1

2

3

(CAS latency = 2)

(CAS latency = 3)

3

Last data out to active command

(auto precharge, same bank)

(CAS latency = 1)

l_APR

—

2

1

—

1

0

—

1

0

= [t_RP]

(CAS latency = 2,3)

= [t_RP] – 1

41

HM5221605 Series

HM5221605

-17

Parameter

-15

-20

Frequency (MHz)

66

33

30

58

17

29

34

50

20

25

40

t

_CK(ns)

Symbol 15

Note

Last data out to precharge (early precharge)

(CAS latency = 1)

l_EP

—

–1

–2

1

0

—

–1

–2

1

0

—

–1

–2

1

0

(CAS latency = 2)

l_EP

–1

–2

1

–1

–2

1

–1

–2

1

(CAS latency = 3)

l_EP

Column command to column command

Write command to data in latency

DQM to data in

l_CCD

l_WCD

l_DID

l_DOD

l_CLE

t_RSA

l_CDD

l_PEC

0

DQM to data out

2

CKE to CLK disable

1

Register set to active command

CS to command disable

Power down exit to command input

2

1

2

1

2

1

0

1

Burst stop to output valid data hold

(CAS latency = 1)

l_BSR

—

1

0

1

2

—

1

0

1

2

—

1

0

1

2

(CAS latency = 2)

(CAS latency = 3)

2

Burst stop to output high impedance

(CAS latency = 1)

l_BSH

l_BSW

—

2

1

2

3

1

—

2

1

2

3

1

—

2

1

2

3

1

(CAS latency = 2)

(CAS latency = 3)

3

Burst stop to write data ignore

1

Note: 1. t_RCDto t_RRDare recommended value.

42

HM5221605 Series

Timing Waveforms

Read Cycle

t

CK

t

CKH CKL

CLK

CKE

t

RC

V

IH

t

RAS

RP

t

RCD

t

CH

t

CS

CH

CS

t

CH

CS

RAS

t

CH

CS

CAS

t

CH

CS

CH

CS

t

CH

CS

WE

A9

t

AH

AS

t

AH

AS

A8

t

AH

AS

AH

AS

Address

t

CH

CS

DQMU/L

I/O(input)

t

AC

ACK

I/O(output)

t

AC

t

OH

t

OH

HZ

t

Burst length = 4

Bank0 Access

= V or V

LZ

Bank 0

Read

Bank 0

Active

Bank 0

Precharge

IH

IL

43

HM5221605 Series

Write Cycle

t

CK

t

CKH CKL

CLK

CKE

t

RC

V

IH

t

RAS

RP

t

RCD

t

CH

CS

t

CH

CS

t

CH

CS

RAS

t

CH

CS

t

CH

CS

CAS

WE

t

CH

CS

t

CH

AH

CH

AH

CS

AS

CS

AS

t

AH

AS

A9

A8

t

AH

AS

t

AH

AS

Address

t

CH

CS

DQMU/L

I/O(input)

I/O(output)

t

DH

t

DS

DH

t

DS

t

DH

DS

DH

DS

t

RWL

Bank 0

Precharge

Bank 0

Write

Bank 0

Active

Burst length = 4

Bank0 Access

= V or V

IH

IL

44

HM5221605 Series

Mode Register Set Cycle

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

CLK

CKE

CS

V

IH

RAS

CAS

WE

A9(BS)

code

C: b’

Address

DQMU/L

valid

C: b

R: b

b+3

b’+1 b’+2 b’+3

b’

I/O(output)

I/O(input)

b

High-Z

t

RCD

RP

RSA

Output mask

Precharge

If needed

Mode register

Set

Bank 1

Active

Bank 1

Read

t

= 3

RCD

CAS latency = 3

Burst length = 4

= V or V

IH

IL

Read Cycle/Write Cycle

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20

CLK

CKE

V

IH

Read cycle

RAS-CAS delay = 3

CAS latency = 3

Burst length = 4

CS

RAS

= V or V

IH

IL

CAS

WE

A9(BS)

Address

R:a

C:a

R:b

C:b

C:b'

C:b"

DQMU/L

I/O

a

a+1 a+2 a+3

b

b+1 b+2 b+3 b' b'+1 b" b"+1 b"+2 b"+3

(output)

High-Z

I/O

(input)

Bank 0

Active

Bank 0

Read

Bank 1

Active

Bank 1 Bank 0

Bank 1

Read

Bank 1

Read

Bank 1

Precharge

Read

Precharge

Write cycle

V

IH

CKE

RAS-CAS delay = 3

CAS latency = 3

Burst length = 4

CS

RAS

= V or V

IH

IL

CAS

WE

A9(BS)

Address

DQMU/L

R:a

C:a

a

R:b

C:b

C:b'

C:b"

High-Z

I/O

(output)

I/O

a+1 a+2 a+3

b

b+1 b+2 b+3 b'

b'+1 b" b"+1b"+2 b"+3

(input)

Bank 0

Active

Bank 0

Write

Bank 1

Active

Bank 1

Write

Bank 0

Precharge

Bank 1

Write

Bank 1

Write

Bank 1

Precharge

45

HM5221605 Series

Read/Single Write Cycle

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20

CLK

CKE

V

IH

CS

RAS

CAS

WE

A9(BS)

R:a

C:a

R:b

C:a' C:a

a

Address

DQMU/L

I/O

(input)

I/O

a

a+1 a+2 a+3

a

a+1 a+2 a+3

(output)

Bank 0

Active

Bank 0

Read

Bank 1

Active

Bank 0 Bank 0

Write Read

Bank 0

Precharge

Bank 1

Precharge

V

IH

CKE

CS

RAS

CAS

WE

A9(BS)

R:a

C:a

R:b

C:a

a

C:b C:c

Address

DQMU/L

I/O

b

c

(input)

I/O

a

a+1

a+3

(output)

Bank 0

Active

Bank 0

Read

Bank 0

Write

Bank 0 Bank 0

Write Write

Bank 0

Precharge

Bank 1

Active

Read/Single write

RAS-CAS delay = 3

CAS latency = 3

Burst length = 4

= V or V

IH

IL

46

HM5221605 Series

Read/Burst Write Cycle

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20

CLK

CKE

CS

RAS

CAS

WE

A9(BS)

Address

DQMU/L

R:a

C:a

R:b

C:a'

I/O

a

a+1 a+2 a+3

(input)

I/O

a

a+1 a+2 a+3

(output)

Bank 0

Active

Bank 0

Read

Bank 1

Active

Clock

suspend

Bank 0

Precharge

Bank 1

Precharge

Bank 0

Write

V

CKE

IH

CS

RAS

CAS

WE

A9(BS)

R:a

C:a

R:b

C:a

a

Address

DQMU/L

I/O

a+1 a+2 a+3

(input)

I/O

a

a+1

a+3

(output)

Bank 0

Active

Bank 0

Read

Bank 0

Write

Bank 0

Precharge

Bank 1

Active

Read/Burst write

RAS-CAS delay = 3

CAS latency = 3

Burst length = 4

= V or V

IH

IL

47

HM5221605 Series

Full Page Read/Write Cycle

0

1

2

3

4

5

6

7

8

9

260 261 262 263 264 265 266 267 268 269

CLK

CKE

V

IH

Read cycle

RAS-CAS delay = 3

CAS latency = 3

Burst length = full page

CS

RAS

= V or V

IH

IL

CAS

WE

A9(BS)

R:a

C:a

R:b

Address

DQMU/L

I/O

a

a+1

a+2 a+3

a-2

a-1

a

a+1 a+2

a+3

a+4

a+5

(output)

High-Z

I/O

(input)

Bank 0

Active

Bank 0

Read

Bank 1

Active

Bank 1

Precharge

Burst stop

V

IH

CKE

Write cycle

RAS-CAS delay = 3

CAS latency = 3

CS

Burst length = full page

RAS

= V or V

IH

IL

CAS

WE

A9(BS)

R:a

C:a

R:b

Address

DQMU/L

High-Z

I/O

(output)

I/O

a

a+1

a+2 a+3

Bank 1

a+4

a+5 a+6

a+1 a+2

a+3 a+4

a+5 a+6

Burst stop

(input)

Bank 0

Active

Bank 0

Write

Bank 1

Precharge

Active

Auto Refresh Cycle

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

CLK

CKE

CS

V

IH

RAS

CAS

WE

A9(BS)

Address

DQMU/L

C:a

A8=1

R:a

I/O(input)

a+1

a

High-Z

I/O(output)

t

RC

t

RP

RC

Refresh cycle and

Read cycle

Active

Bank 0

Read

Bank 0

Auto Refresh

Precharge

If needed

Auto Refresh

RAS-CAS delay = 2

CAS latency = 2

Burst length = 4

= V or V

IH

IL

48

HM5221605 Series

Self Refresh Cycle

CLK

CKE

CS

CKE Low

RAS

CAS

WE

A9(BS)

Address

A8=1

DQMU/L

I/O(input)

High-Z

I/O(output)

t

RC

RP

Auto refresh Self refresh cycle

RAS-CAS delay = 3

CAS latency = 3

Self refresh entry

command

Self refresh exit

ignore command

or No operation

Precharge command

If needed

Burst length = 4

= V or V

IH

IL

Clock Suspend Mode

t

CESP

5

CES

CEH

8

0

1

2

3

4

6

7

9

10 11 12 13 14 15 16 17 18 19 20

CLK

CKE

Read cycle

RAS-CAS delay = 2

CAS latency = 2

Burst length = 4

CS

RAS

= V or V

IH

IL

CAS

WE

A9(BS)

Address

R:a

C:a

R:b

C:b

DQMU/L

I/O

a

a+1 a+2

a+3

b

b+1 b+2 b+3

(output)

High-Z

I/O

(input)

Bank0 Active clock

Active suspend start

Active clock Bank0

suspend end Read

Bank1 Read suspend Read suspend

Bank0

Earliest Bank1

Precharge

Bank1

Active

start

end Read Precharge

CKE

Write cycle

RAS-CAS delay = 2

CAS latency = 2

Burst length = 4

CS

RAS

= V or V

IH

IL

CAS

WE

A9(BS)

Address

DQMU/L

R:a

C:a

a

R:b

a+1

C:b

High-Z

I/O

(output)

I/O

a+2

a+3

b

b+1 b+2 b+3

(input)

Bank0

Active clock Bank0 Bank1 Write suspend Write suspend Bank1

Earliest Bank1

Precharge

Bank0 Active clock

Active suspend start

Precharge

end Write

supend end Write Active

start

49

HM5221605 Series

Power Down Mode

CLK

CKE

CS

CKE Low

RAS

CAS

WE

A9(BS)

Address

A8=1

R: a

DQMU/L

I/O (input)

High-Z

I/O (output)

t

RP

Power down cycle

RAS-CAS delay = 3

CAS latency = 3

Burst length = 4

= V or V

Power down entry

Power down

mode exit

Active Bank 0

Precharge command

If needed

IH

IL

50

HM5221605 Series

Power Up Sequence (1)

17

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

18

19

CLK

V

IH

CKE

CS

RAS

CAS

WE

code

valid

Address

Valid

V

IH

DQMU/L

I/O

High-Z

t

RC

t

RSA

RC

RP

Bank active

If needed

Auto Refresh *

All banks

Precharge

Mode register

Set

Auto Refresh *

Note: Set 2 or more auto refresh commands.

= V or V

IH

IL

Power Up Sequence (2)

17

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

18

19

CLK

V

IH

CKE

CS

RAS

CAS

WE

code

valid

Address

Valid

V

IH

DQMU/L

I/O

High-Z

t

RP

t

RC

t

RC

RSA

Bank active

If needed

All banks

Precharge

Mode register

Set

Auto Refresh *

Note: Set 8 or more auto refresh commands.

= V or V

IH

IL

51

HM5221605 Series

Package Dimensions

HM5221605TT Series (TTP-50DA)

Unit: mm

20.95

21.35 Max

50

26

25

1

0.80

0.30 ± 0.10

0.25 ± 0.05

M

0.13

11.76 ± 0.20

0.94 Max

0° – 5°

0.50 ± 0.10

0.10

Hitachi Code

TTP-50DA

JEDEC

EIAJ

—

Dimension including the plating thickness

Base material dimension

Weight (reference value) 0.51 g

52

HM5221605 Series

When using this document, keep the following in mind:

1. This document may, wholly or partially, be subject to change without notice.

2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of

this document without Hitachi’s permission.

3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any

other reasons during operation of the user’s unit according to this document.

4. Circuitry and other examples described herein are meant merely to indicate the characteristics and

performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual

property claims or other problems that may result from applications based on the examples described

herein.

5. No license is granted by implication or otherwise under any patents or other rights of any third party or

Hitachi, Ltd.

6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL

APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company.

Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are

requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL

APPLICATIONS.

Hitachi, Ltd.

Semiconductor & IC Div.

Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan

Tel: Tokyo (03) 3270-2111

Fax: (03) 3270-5109

For further information write to:

Hitachi Semiconductor

(America) Inc.

2000 Sierra Point Parkway

Brisbane, CA. 94005-1897

U S A

Hitachi Europe GmbH

Continental Europe

Dornacher Straße 3

D-85622 Feldkirchen

München

Hitachi Europe Ltd.

Electronic Components Div.

Northern Europe Headquarters

Whitebrook Park

Lower Cookham Road

Maidenhead

Berkshire SL6 8YA

United Kingdom

Tel: 01628-585000

Fax: 01628-585160

Hitachi Asia Pte. Ltd.

16 Collyer Quay #20-00

Hitachi Tower

Singapore 049318

Tel: 535-2100

Tel: 800-285-1601

Fax:303-297-0447

Tel: 089-9 91 80-0

Fax: 089-9 29 30-00

Fax: 535-1533

Hitachi Asia (Hong Kong) Ltd.

Unit 706, North Tower,

World Finance Centre,

Harbour City, Canton Road

Tsim Sha Tsui, Kowloon

Hong Kong

Tel: 27359218

Fax: 27306071

53

HM5221605 Series

Revision Record

Rev. Date

Contents of Modification

Drawn by

Approved by

0.0

0.1

Nov. 18, 1993 Initial issue

S. Ishikawa T. Kizaki

M.Sakamoto T. Kizaki

Sep. 22, 1994 Clock frequency: 50/57/66 MHz to 50/58/66 MHz

Pin Functions: Change of description

Simplified State Diagram

Change of order and Simplified State Diagram

Addition of note

Command Operation: Addition of description

DQM Truth Table and CKE Truth Table:

Change of description

Function Truth Table: Addition of note2,3 and description

Mode Register Configuration: Change of description

Change of order for Burst Sequence

Operation of HM5221605 Series:

Change of description and figures

DC Characteristics: Addition of note2, 3, 4, 5, 6 and 7

I

_CC1max: 80/70/65 mA to 85/75/70mA

_CC2max: 25/22/20 mA to 33/30/26mA

_CC3max: 30/26/23 mA to 34/31/26 mA

_CC4(CL = 1)max: 55/50/45 mA to 65/60/50 mA

_CC4(CL = 2)max: 100/90/80 mA to 100/95/80 mA

Capacitance: Addition of note3

AC Characteristics: Deletion of note4 and 5

Relationship Between Frequency and Minimum Latency

t_RC: 8/5/7/4/6/3 to 8/5/7/4/7/4

l_SEC: 8/5/7/4/6/3 to 8/4/7/4/7/4

Addition of l_EP(CL = 3): -2/-2/-2/-2/-2/-2

Addition of note 1

Change of Timing Waveforms

Addition of Power UP Sequence

Change of name for Mode Register Write Cycle to Mode

Register Set Cycle

Change of name for Read/Write Cycle to Read/Burst

Write Cycle

Change of Package type: TTP-50D to TTP-50DA

1.0

Jun. 20, 1995 Operation of HM5221605 Series

M.Sakamoto T. Kizaki

Addition of figure for READ to WRITE Command

Interval(2)

Change of description for Power-up sequence

Absolute Maximum Ratings: Addition of note2

Relationship Between Frequency and Minimum Latency

t_RC: 8/5/7/4/7/4 to 8/5/8/4/7/4

l_SEC: 8/5/7/4/7/4 to 8/4/8/4/7/4

Addition of l_BSR(CL = 3): 2/2/2/2/2/2

Timing Waveforms

Addition of Power UP Sequence (2)

54

HM5221605 Series

Revision Record (cont)

Rev. Date

Contents of Modification

Drawn by

Approved by

2.0 Nov. 14, 1996 Change of Format

M.Sakamoto T. Kizaki

AC Characteristics

t_CKHmin: 6/7/8 ns to 4.5/7/8 ns

t_CKLmin: 6/7/8 ns to 4.5/7/8 ns

t_RPmin: 34/34/40 ns to 30/34/40 ns

Addition of t_CEHPmin 17/19/22 ns

Addition of notes5, 6

Change of note4

Relationship Between Frequency and Minimum Latency

t_RC: 8/5/8/4/7/4 to 7/4/7/4/6/3

t_RP: 3/2/2/1/2/1 to 2/1/2/1/2/1

l

_APW: 5/3/4/2/4/2 to 4/2/4/2/4/2

Deletion of note2: CL = CAS latency

3.0

Nov. 1997

Change of Subtitle

55


型号：	HM5221605TT-15
厂家：	ETC
描述：	x16 SDRAM X16 SDRAM\n 内存集成电路光电二极管动态存储器时钟
文件：	总55页 (文件大小：698K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HM5221605TT-15 [ETC]

相关型号：

HM5221605TT-17

HM5221605TT-20

HM5225165B

HM5225165B-75

HM5225165B-A6

HM5225165B-B6

HM5225165B/5805B/5405B-75/A6/B6

HM5225165BLTT-75

HM5225165BLTT-75

HM5225165BLTT-A6

HM5225165BLTT-A6

HM5225165BLTT-B6