HMS81C4308 [ETC]
[TV : OSD/ I?C] ; [电视: OSD / I C]\n型号: | HMS81C4308 |
厂家: | ETC |
描述: | [TV : OSD/ I?C]
|
文件: | 总100页 (文件大小:1667K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
HMS81C43xx / GMS87C4060
HMS81C43xx/GMS87C4060
CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
FOR TELEVISION
1. OVERVIEW
1.1 Description
The HMS81C43xx/GMS87C4060 is an advanced CMOS 8-bit microcontroller with 8~32K(60K) bytes of ROM. The device
is one of GMS800 family. The HYNIX’s HMS81C43xx/GMS87C4060 is a powerful microcontroller which provides a high-
ly flexible and cost effective solution to many TV applications. The HMS81C43xx/GMS87C4060 provides the following
standard features: 8~32K(60K) bytes of ROM, 256~512/1,536 bytes of RAM, 8-bit timer/counter .
Device name
ROM Size
RAM Size
Package
8~32K bytes
Mask ROM
256~512
bytes
HMS81C43xx
32 PDIP
60K bytes
EPROM
GMS87C4060
1,536 bytes
52 SDIP
1.2 GMS87C4060 (OTP) Features
• 60K Bytes On-chip Program Memory
- Timer/Counter : 8bit x 4ch (16bit x 2ch)
- Basic interval timer : 8bit x 1ch
- Watch Dog Timer
• 1,536 Bytes of On-chip Data RAM
(Included 256 bytes stack memory)
• Number of Interrupt sources : 18
• Instruction Cycle Time (ex:NOP)
- 0.5us at 8MHz
• On Screen Display
- Number of characters : 512 (6 characters are
reserved for IC test)
• 40 Programmable I/O pins
- 33 Input/Ooutput and 7 Output pins
- Character size : 12 dots(X) x 16 dots(Y)
- Character display size : Large, Medium, Small
- DIsplay capability : 24Characters x 16 Lines
- Character, Back ground color : 16kinds
- Special functions : Rounding, Outline, Sprite,
Shadow, Half Tone Background,...
• Serial I/O : 8bit x 1ch
2
• I C Bus interface
- Multimaster (2 Pairs interface pins)
• A/D Converter : 8bit x 6ch (TBD LSB)
• Pulse Width Modulation
- 14bit x 1ch
• Buzzer Driving port
- 500Hz ~ 250kHz @8MHz (Duty 50%)
-
8bit x 6ch
• Operating Range : 4.5V to 5.5V
• Timer
1.3 HMS81C43xx Family Features
• On-chip Program Memry and Data memry
HMS81C4332 ( 32K ROM, 512 RAM)
HMS81C4324 ( 24K ROM, 256 RAM)
HMS81C4316 ( 16K ROM, 256 RAM)
HMS81C4308 ( 8K ROM, 256 RAM)
(Included 64/256 bytes stack memory)
• Instruction Cycle Time (ex:NOP)
- 1.0us at 4MHz
• 21 Programmable I/O pins
- 19 Input/Output and 3 Output pins
2
• I C Bus interface
- Multimaster (2 Pairs interface pins)
November 2001 ver 1.2
1
HMS81C43xx / GMS87C4060
• A/D Converter : 8bit x 6ch (TBD LSB)
- Character size : 12 dots(X) x 16 dots(Y)
- Character display size : Large, Medium, Small
- DIsplay capability : 24Characters x 16 Lines
- Character, Back ground color : 8 kinds
- Special functions : Rounding, Outline,
Shadow, Half tone Background...
• Pulse Width Modulation
- 14bit x 1ch
-
8bit x 2ch
• Timer
- Timer/Counter : 8bit x 4ch (16bit x 2ch)
• Buzzer Driving port
- 250Hz ~ 125kHz @4MHz (Duty 50%)
- Basic interval timer : 8bit x 1ch
- Watch Dog Timer
• Operating Range : 4.5V to 5.5V
•
• Number of Interrupt sources : 18
• On Screen Display
- Number of characters : 256
1.4 Development Tools
The HMS81C43xx/GMS87C4060 is supported by a full-
HYNIX’s Macro Assembler /
Assembler / Linker
featured macro assembler / linker , OSD font editor, an in-
Linker
TM
circuit emulator CHOICE-Dr
.
Font Editor
Debugger
MS-Windows GUI version
MS-Windows GUI version
CHOICE-Dr.
(with EVA81C4xxx board)
In Circuit Emulators
2
N ovem ber 2001 ver 1.2
HMS81C43xx / GMS87C4060
2. BLOCK DIAGRAM
R10 / AN0
R11 / AN1
R12 / AN2
R13 / AN3
R14 / AN4
R15 / AN5
R16 / VD
R17 / HD
R50 / BUZZ
R51 / PWM8
R52 / INT0
R53
R54 / YM
R55 / YS
R56 / I
R,G,B
OSC1
OSC2
OSD
Display
Memory
OSD (On Screen Display) Controller
R1
R5
Data bus
Buzzer
8bit A/D
Convertor
Accumulator
& Index X,Y
Stack pointer
PSW
ALU
Data
Memory
PC
PWM
14bit x 1
8bit x 6
Program
Memory
Interrupt Controller
Vector Table
8-bit Basic
Interval
Timer
RESET
System controller
TEST
8-bit x 4
Timer/
Counter
Interrupt
Interval
M easure
System
Serial I/O
Interface
I2C
Interface
Clock Controller
Watchdog
Timer
Timing generator
XIN
Clock generator
XOUT
Data bus
VDD
VSS
Power
Supply
R0
R6
R4
R2
R40 / PWM0
R67 / INT1
R00
R01
R02
R03
R04
R05
R06
R07
R20 / INT2
R21 / Sclk
R22 / Sout
R23 / Sin
R24 / INT3
R25 / EC2
R26 / INT4
R27 / EC3
R41 / PWM1
R42 / PWM2
R43 / PWM3
R44 / SCL0
R45 / SCL1 / PWM4
R46 / SDA0
R47 / SDA1 / PWM5
November 2001 ver 1.2
3
HMS81C43xx / GMS87C4060
3. PIN ASSIGNMENT
1
2
3
4
5
6
7
8
R17/HD
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
R
G
B
R56
R16/VD
R15/AN5
R14/AN4
R13/AN3
R12/AN2
R11/AN1
R10/AN0
Vss
R55/YS
R54/YM
OSC1
OSC2
TEST
Vdd
RESET
R53
R52/INT0
R51/PWM8
R50/BUZZ
R26/INT4
9
10
11
12
13
14
15
16
Xin
Xout
R47/SDA1/PWM5
R46/SDA0
R45/SCL1/PWM4
R44/SCL0
R27/EC3
R27/EC3
R26/INT4
R25/EC2
R24/INT3
R23/Sin
R22/Sout
R21/Sclk
R20/INT2
R17/HD
R16/VD
RESET
Vss
1
2
3
4
5
6
7
8
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
R40/PWM0
R41/PWM1
R42/PWM2
R43/PWM3
R44/SCL0
R45/SCL1/PWM4
R46/SDA0
R47/SDA1/PWM5
R50/BUZZ
R51/PWM8
R52/INT0
R53
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Xout
Xin
Vss
Vdd
TEST
OSC1
R15/AN5
R14/AN4
R13/AN3
R12/AN2
R11/AN1
R10/AN0
R07
OSC2
R54/YM
R55/YS
R56/I
B
G
R
R00
R01
R02
R06
R05
R04
R03
R67/INT1
4
N ovem ber 2001 ver 1.2
HMS81C43xx / GMS87C4060
4. PACKAGE DIAGRAM
UNIT: inch
HYNIX
HMS81C4332
TYP 0.600 BSC
1.665
1.645
0.550
0.530
MIN 0.015
0.140
0.120
0.022
0.015
0 ~ 15°
0.1 BSC
0.065
0.045
November 2001 ver 1.2
5
HMS81C43xx / GMS87C4060
Figure 4-1 52pin Shrink DIP Package Diagram
52
27
0 ~ 15
HYNIX
GMS87C4060
26
1
0.25 0.05
45.97 0.13
0.76 0.13
UNIT: mm
0.47 0.13
1.02 0.25
1.778
0.25
6
N ovem ber 2001 ver 1.2
HMS81C43xx / GMS87C4060
5. PIN FUNCTION
V
V
R40~R47
: R40~R43 are 8-bit NMOS open drain output
: Supply voltage.
DD
and R45~R47 are bidirectional CMOS Input / NMOS open
drain output port. R4 pins 1 or 0 written to the Port Direc-
tion Register can be used as outputs or inputs.
: Circuit ground.
SS
TEST
: Used for shipping inspection of the IC. For normal
operation, it should not be connected .
In addition, R4 serves the functions of the various follow-
ing special features.
RESET
: Reset the MCU.
X
: Input to the inverting oscillator amplifier and input to
IN
Port pin
Alternate function
the internal main clock operating circuit.
PWM0 (Pulse Width Modulation output 0)
PWM1 (Pulse Width Modulation output 1)
PWM2 (Pulse Width Modulation output 2)
PWM3 (Pulse Width Modulation output 3)
R40
R41
R42
R43
R44
R45
X
: Output from the inverting oscillator amplifier.
OUT
OSC1
circuit.
: Input to the internal On Screen Display operating
2
SCL0 (I C Clock 0)
OSC2
: Output from the inverting OSC1 amplifier.
2
SCL1 (I C Clock 1)
PWM4 (Pulse Width Modulation output 4)
R00~R07
: R0 is an 8-bit CMOS bidirectional I/O port. R0
pins 1 or 0 written to the Port Direction Register can be
used as outputs or inputs.
2
R46
R47
SDA0 (I C Data 0)
2
SDA1 (I C Data 1)
PWM5 (Pulse Width Modulation output 5)
R10~R17
: R1 is an 8-bit CMOS bidirectional I/O port. R1
pins 1 or 0 written to the Port Direction Register can be
used as outputs or inputs.
R50~R56
: R50~R53 are 4-bit CMOS bidirectional I/O and
R54~R56 are CMOS output port. R5 pins 1 or 0 written to
the Port Direction Register can be used as outputs or in-
puts.
In addition, R1 serves the functions of the various follow-
ing special features.
In addition, R5 serves the functions of the various follow-
ing special features.
Port pin
Alternate function
R10
R11
R12
R13
R14
R15
R16
R17
AN0 (A/D converter input 0)
AN1 (A/D converter input 1)
AN2 (A/D converter input 2)
AN3 (A/D converter input 3)
AN4 (A/D converter input 4)
AN5 (A/D converter input 5)
VD (Vertical Sync. input)
Port pin
Alternate function
BUZZ (Buzzer output)
PWM8 (Pulse Width Modulation output 8)
INT0 (External interrupt input 0)
YM (Back ground)
R50
R51
R52
R54
R55
R56
YS (Edge)
I (Intencity)
HD (Horisontal Sync. input)
R20~R27
: R2 is a 8-bit CMOS bidirectional I/O port. Each
R67
: R67 is an 1-bit CMOS bidirectional I/O port. R67
pins 1 or 0 written to the their Port Direction Register can
be used as outputs or inputs.
pins 1 or 0 written to the Port Direction Register can be
used as outputs or inputs.
In addition, R2 serves the functions of the various follow-
ing special features.
In addition, R67 serves the functions of the various follow-
ing special features.
Port pin
Alternate function
Port pin
Alternate function
R20
R21
R22
R23
R24
R25
R26
R27
INT2 (External interrupt input 2)
Sclk (Serial communication clock)
Sout (Serial communication data out)
Sin (Serial communication data in)
INT3 (External interrupt input 3)
EC2 (Event counter input 2)
R67
INT1 (External interrupt input 1)
R,G,B
: R,G,B CMOS output port. Each pins controls Red,
Green,. Blue color control.
INT4 (External interrupt input 4)
EC3 (Event counter input 3)
November 2001 ver 1.2
7
HMS81C43xx / GMS87C4060
PIN NAME
Pin No.
In/Out
Function
V
V
39
12, 40
38
11
14
13
37
36
9
-
-
Supply voltage
Circuit ground
DD
SS
TEST
I
For test purposes. Should not be connected. (N.C.)
Reset signal input
RESET
I
X
I
Main oscillation input
IN
X
O
I
Main oscillation output
OUT
OSC1
On screen display oscillation input
OSC2
O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
On screen display osc. output
Horisontal Sync. input
Vertical Sync. input
Red signal output
Green signal output
Blue signal output
Intencity signal output
Edge signal output
Background signal output
8bit PWM
R17/HD
R16/VD
R
10
30
31
32
33
34
35
52
51
50
49
On screen display functions
G
B
R56/I
R55/YS
R54/YM
R40/PWM0
R41/PWM1
R42/PWM2
R43/PWM3
8bit PWM
8bit PWM
8bit PWM
PWM functions
R45/SCL1/
PWM4
2
47
45
I/O
I/O
Include I C Serial clock 1 (SCL1)
R47/SDA1/
PWM5
2
Include I C Serial data 1 (SDA1)
R51/PWM8
R44/SCL0
43
48
I/O
I/O
14bit PWM
2
I C Serial clock 0
2
I C functions
2
R46/SDA0
R23/Sin
46
5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I C Serial data 0
Serial data input
R22/Sout
R21/Sclk
R27/EC3
R25/EC2
R50/Buzzer
6
SCI functions
Serial data output
7
Serial communication clock
Event counter input 3
Event counter input 2
500Hz ~ 250KHz @8MHz
1
Timer event functions
Buzzer function
3
44
Table 5-1 Port Function Description
8
N ovem ber 2001 ver 1.2
HMS81C43xx / GMS87C4060
PIN NAME
R52/INT0
Pin No.
42
26
8
In/Out
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Function
External interrupt input 0
External interrupt input 1
External interrupt input 2
External interrupt input 3
External interrupt input 4
Analog input 0
R67/INT1
R20/INT2
R24/INT3
R26/INT4
R10/AN0
R11/AN1
R12/AN2
R13/AN3
R14/AN4
R15/AN5
R00
External interrupt functions
4
2
20
19
18
17
16
15
29
28
27
25
24
23
22
21
41
Analog input 1
Analog input 2
A/D conversion functions
Analog input 3
Analog input 4
Analog input 5
R01
R02
R03
R04
Digital I/O functions
R05
R06
R07
R53
Table 5-1 Port Function Description
November 2001 ver 1.2
9
HMS81C43xx / GMS87C4060
6. PORT STRUCTURES
RESET
OSC1, OSC2
VDD
VDD
Main frequency
clock
RESET
Noise
Canceler
OSC1
VDD
VSS
VSS
OSC2
OSDON
TEST
VSS
VDD
R00~07, R53
VDD
VSS
DB
DB
DB
Data Reg.
Dir. Reg.
Pin
X , X
IN
OUT
VSS
MUX
VDD
Main frequency
clock
RD
XIN
VSS
VDD
R10~15 (AN0~5)
VDD
XOUT
DB
DB
DB
Data Reg.
Dir. Reg.
VSS
VSS
Pin
VSS
MUX
RD
AN0~5
10
N ovem ber 2001 ver 1.2
HMS81C43xx / GMS87C4060
R16, 17, 20, 24, 25, 26, 27, 52, 67
R23/Sin
VDD
VDD
DB
Data Reg.
Dir. Reg.
DB
DB
DB
Data Reg.
Dir. Reg.
Selection
DB
Pin
Pin
VSS
VSS
MUX
M UX
DB
RD
RD
HD,VD,
EC2~3
INT0~INT4
Sin
R21/Sclk, R22/Sout
R40~43 (PWM0~3)
DB
Data Reg.
DB
Data Reg.
Dir. Reg.
Pin
VDD
M UX
M UX
PWM0~3
Selection
Sout, Sclk
Selection
VSS
Pin
DB
DB
R44, 45, 46, 47 (SCL, SDA, PWM)
VSS
M UX
DB
Data Reg.
M UX
SCL,SDA
RD
PWM4,PWM5
Sclk
Selection
Pin
Dir. Reg.
DB
DB
VSS
M UX
RD
SCL, SDA
November 2001 ver 1.2
11
HMS81C43xx / GMS87C4060
R50/BUZZ, R51/PWM8
DB
Data Reg.
VDD
M UX
Buzz, PWM8
Selection
Pin
Dir. Reg.
DB
DB
VSS
M UX
RD
R54/YM, R55/YS, R56/I
VDD
OSD ON or Data Reg Write.
DB
Data Reg.
Pin
M UX
YM, YS, I
Selection
VSS
R, G, B
VDD
R, G, B
i
Pin
OSD_ON
VSS
12
N ovem ber 2001 ver 1.2
HMS81C43xx / GMS87C4060
7. ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
Supply voltage........................................... -0.3 to +6.0 V
Storage Temperature ................................-40 to +125 °C
Maximum current (ΣI ) ...................................... 80 mA
OL
Maximum current (ΣI )...................................... 50 mA
OH
Voltage on any pin with respect to Ground (V
............................................................... -0.3 to V +0.3
)
SS
Note: Stresses above those listed under "Absolute Maxi-
mum Ratings" may cause permanent damage to the de-
vice. This is a stress rating only and functional operation of
the device at any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for ex-
tended periods may affect device reliability.
DD
Maximum current out of V pin ........................100 mA
SS
Maximum current into V pin ............................80 mA
DD
Maximum current sunk by (I per I/O Pin) ........20 mA
OL
Maximum output current sourced by (I per I/O Pin)
OH
.................................................................................8 mA
7.2 Recommended Operating Conditions
Specifications
Unit
Parameter
Symbol
Condition
Min.
4.5
4
Max.
5.5
8
f
=8MHz
=16MHz
XIN
V
Supply Voltage
V
DD
f
OSC
f
V
V
=4.5~5.5V
Operating Frequency
MHz
MHz
XIN
DD
On Screen Display Oper-
ating Frequency
f
=4.5~5.5V
8
16
OSC
DD
T
Operating Temperature
-10
70
C
°
OPR
7.3 DC Electrical Characteristics - HMS81C43xx
(T =-10~70°C, V =4.5~5.5V),
A
DD
Specifications
Typ.
Parameter
Symbol
Condition
Unit
Min.
Max.
TEST, RESET, Xin, OSC1, R17~16,
R27~20, R47~44, R52, R67
V
0.8 V
0.7 V
0
V
-
-
-
-
-
V
V
V
V
V
IH1
DD
DD
DD
High level input voltage
Low level input voltage
V
V
R0, R15~10, R53~50
IH2
DD
TEST, RESET, Xin, OSC1, R17~16,
R27~20, R47~44, R52, R67
V
0.12 V
IL1
DD
V
0.3 V
R0, R15~10, R53~50
0
IL2
DD
I
= -5mA
OH
V
V
- 1
- 1
-
DD
R0, R1, R2, R5, R67
V
High level output voltage
Low level output voltage
OH
I
= -1.2mA
OH
-
-
-
-
V
V
DD
-
R,G,B
I
OL
= 5mA
V
1.0
30
OL
R0, R1, R2, R4, R5, R67, R, G, B
Supply current in
ACTIVE mode
I
V
-
mA
DD
DD
November 2001 ver 1.2
13
HMS81C43xx / GMS87C4060
Specifications
Typ.
Parameter
Symbol
Condition
Unit
Min.
Max.
V
TEST
= 5.5v, V
= 0.4V
DD
PIN
I
pull-up lekage current
-1.5
-400
A
A
µ
µ
RUP
V
= 5.5V V
= V
DD
DD
,
PIN
High input leakage
current
I
All input, I/O pins except X , OSC1,
R47~40
-5
-5
-
-
5
5
IZH
IN
V
= 5.5V V
= 0V
PIN
DD
,
Low input leakage
current
I
All input, I/O pins except X , OSC1,
R47~44
A
A
µ
µ
IZL
IN
V
= 5.5V V = V , N-ch Tr. off
Open drain leakage
current
DD
,
OH
DD
I
-
-
-
10
-
LOZ
R47~40
RAM data retention
voltage
V
V
1.2
V
RAM
DD
V
V
V
= 4.5V
DD
,
= V
= V
= 2.25V
= 2.25V
SCL0
SDA0
SCL1
SDA1
2
I C port impedance
R
-
-
-
120
-
Ω
BS
(I/O Transistor off)
SCL0:SCl1 (R44:R45)
SDA0:SDA1 (R46:R47)
Vt+ ~
Vt-
TEST, RESET, Xin, OSC1, R17~16,
R27~20, R47~44, R52, R67
Hysterisis
1.0
V
14
N ovem ber 2001 ver 1.2
HMS81C43xx / GMS87C4060
7.4 A/D Comparator Characteristics
(T =-10~70°C, V =5.0V)
A
DD
Specifications
Unit
Parameter
Symbol
Pins
Min.
Typ.
Max.
V
V
V
Analog Input Voltage Range
Accuracy
AN0~AN5
-
-
-
V
AIN
SS
DD
N
-
LSB
ΤΒ∆
FS
7.5 AC Characteristics
(T =-10~70°C, V =5V±10%, V =0V)
A
DD
SS
Specifications
Parameter
Symbol
Pins
Unit
Min.
Typ.
Max.
8
f
X
IN
4
-
-
-
-
-
-
-
-
MHz
MHz
nS
XIN
Operating Frequency
f
OSC
8
16
OSC
t
X
62.5
125
MCPW
IN
External Clock Pulse Width
External Clock Transition Time
t
S
0.5
S
µ
SCPW
CLK
t
t
X
-
-
20
20
20
-
nS
nS
MRCP, MFCP
IN
t
t
S
SRCP, SFCP
CLK
t
ST
X , X
IN OUT
Oscillation Stabilizing Time
Interrupt Pulse Width
RESET Input Width
-
mS
1
t
INT0~4
RESET
2
t
t
IW
SYS
1
t
8
2
-
-
-
-
-
-
RST
SYS
Event Counter Input Pulse
Width
1
t
EC2, EC3
EC2, EC3
t
ECW
SYS
t
t
Event Counter Transition Time
20
nS
REC, FEC
1. tSYS is one of 2/fXIN main clock operation mode,
November 2001 ver 1.2
15
HMS81C43xx / GMS87C4060
tMCPW
tMCPW
1/fXIN
VDD-0.5V
X
S
IN
0.5V
0.5V
tMRCP
tSCPW
tMFCP
tSCPW
1/fSCLK
VDD-0.5V
CLK
tSRCP
tSFCP
tIW
tIW
INT0 ~ 4
0.8VDD
0.2VDD
tRST
RESET
0.2VDD
tECW
tECW
0.8VDD
EC2, EC3
0.2VDD
tREC
tFEC
Figure 7-1 Timing Chart
16
N ovem ber 2001 ver 1.2
HMS81C43xx / GMS87C4060
7.6 Typical Characteristics
This data will generate after evaluation.
Not available at this time.
November 2001 ver 1.2
17
HMS81C43xx / GMS87C4060
8. MEMORY ORGANIZATION
The GMS81C43xx/GMS87C4060 has separate address
spaces for Program memory, Data Memory and Display
memory. Program memory can only be read, not written
to. It can be up to 32K/60K bytes of Program memory.
Data memory can be read and written to up to 256~512/
1,536 bytes including the stack area. Font memory has pre-
pared 16K bytes for OSD.
8.1 Registers
This device has six registers that are the Program Counter
(PC), a Accumulator (A), two index registers (X, Y), the
Stack Pointer (SP), and the Program Status Word (PSW).
The Program Counter consists of 16-bit register.
(save or restore).
Generally, SP is automatically updated when a subroutine
call is executed or an interrupt is accepted. However, if it
is used in excess of the stack area permitted by the data
memory allocating configuration, the user-processed data
may be lost.
ACCUMULATOR
X REGISTER
A
X
The stack can be located at any position within 0100 to
H
01FF of the internal data memory. The SP is not initial-
H
Y
Y REGISTER
ized by hardware, requiring to write the initial value (the
location with which the use of the stack starts) by using the
SP
STACK POINTER
initialization routine. Normally, the initial value of "FF "
H
PCH
PCL
PROGRAM COUNTER
is used.
PROGRAM STATUS
WORD
PSW
Stack Address ( 0100H ~ 013F or 01FFH
)
15
8
7
0
01
SP
Figure 8-1 Configuration of Registers
Hardware fixed
Accumulator:
The Accumulator is the 8-bit general pur-
pose register, used for data operation such as transfer, tem-
porary saving, and conditional judgement, etc.
Caution:
The Accumulator can be used as a 16-bit register with Y
Register as shown below.
The Stack Pointer must be initialized by software be-
cause its value is undefined after RESET.
Y
Example: To initialize the SP for 81C4324 (256 RAM)
Y
A
LDX
TXSP
#03FH
; SP ← 3F
H
A
Two 8-bit Registers can be used as a "YA" 16-bit Register
Program Counter
: The Program Counter is a 16-bit wide
which consists of two 8-bit registers, PCH and PCL. This
counter indicates the address of the next instruction to be
executed. In reset state, the program counter has reset rou-
Figure 8-2 Configuration of YA 16-bit Register
X, Y Registers
: In the addressing mode which uses these
index registers, the register contents are added to the spec-
ified address, which becomes the actual address. These
modes are extremely effective for referencing subroutine
tables and memory tables. The index registers also have in-
crement, decrement, comparison and data transfer func-
tions, and they can be used as simple accumulators.
tine address (PC :0FF , PC :0FE ).
H
H
L
H
Program Status Word
: The Program Status Word (PSW)
contains several bits that reflect the current state of the
CPU. The PSW is described in Figure 8-3 . It contains the
Negative flag, the Overflow flag, the Break flag the Half
Carry (for BCD operation), the Interrupt enable flag, the
Zero flag, and the Carry flag.
Stack Pointer
: The Stack Pointer is an 8-bit register used
for occurrence interrupts and calling out subroutines. Stack
Pointer identifies the location in the stack to be accessed
[Carry flag C]
This flag stores any carry or borrow from the ALU of CPU
18
N ovem ber 2001 ver 1.2
HMS81C43xx / GMS87C4060
after an arithmetic operation and is also changed by the
Shift Instruction or Rotate Instruction.
MSB
LSB
C
N
V
G
B
H
I
Z
RESET VALUE : 00H
CARRY FLAG RECEIVES
PSW
NEGATIVE FLAG
CARRY OUT
OVERFLOW FLAG
ZERO FLAG
SELECT DIRECT PAGE
when G=1, page is addressed by RPR
INTERRUPT ENABLE FLAG
HALF CARRY FLAG RECEIVES
CARRY OUT FROM BIT 1 OF
BRK FLAG
ADDITION OPERLANDS
Figure 8-3 PSW (Program Status Word) Register
[Zero flag Z]
[Direct page flag G]
This flag is set when the result of an arithmetic operation
or data transfer is "0" and is cleared by any other result.
This flag assigns RAM page for direct addressing mode. In
the direct addressing mode, addressing area is from zero
page 00 to 0FF when this flag is "0". If it is set to "1",
addressing area is assigned by DPGR register (address
H
H
[Interrupt disable flag I]
This flag enables/disables all interrupts except interrupt
caused by Reset or software BRK instruction. All inter-
rupts are disabled when cleared to "0". This flag immedi-
ately becomes "0" when an interrupt is served. It is set by
the EI instruction and cleared by the DI instruction.
0F8 ). It is set by SETG instruction and cleared by CLRG.
H
[Overflow flag V]
This flag is set to "1" when an overflow occurs as the result
of an arithmetic operation involving signs. An overflow
occurs when the result of an addition or subtraction ex-
[Half carry flag H]
ceeds +127(7F ) or -128(80 ). The CLRV instruction
H
H
After operation, this is set when there is a carry from bit 3
of ALU or there is borrow from bit 4 of ALU. This bit can
not be set or cleared except CLRV instruction with Over-
flow flag (V).
clears the overflow flag. There is no set instruction. When
the BIT instruction is executed, bit 6 of memory is copied
to this flag.
[Negative flag N]
[Break flag B]
This flag is set to match the sign bit (bit 7) status of the re-
sult of a data or arithmetic operation. When the BIT in-
struction is executed, bit 7 of memory is copied to this flag.
This flag is set by software BRK instruction to distinguish
BRK from TCALL instruction with the same vector ad-
dress.
November 2001 ver 1.2
19
HMS81C43xx / GMS87C4060
At execution of
a CALL/TCALL/PCALL
At acceptance
of interrupt
At execution
of RET instruction
At execution
of RETI instruction
01FC
01FC
01FD
01FE
01FC
01FD
01FE
01FC
01FD
01FE
PSW
PSW
01FD
Push
Push
down
Pop
up
01FE
01FF
PCL
PCH
PCL
PCH
PCL
PCL
down
Pop
up
PCH
PCH
01FF
01FF
01FF
SP before
execution
01FF
01FD
01FF
01FC
01FD
01FF
01FC
01FF
SP after
execution
At execution
At execution
of PUSH instruction
PUSH A (X,Y,PSW)
of POP instruction
POP A (X,Y,PSW)
01FC
01FC
0100H
Stack
depth
01FD
01FE
01FD
01FE
Push
down
Pop
up
A
A
01FF
01FF
01FFH
SP before
01FF
01FE
01FE
01FF
execution
SP after
execution
Figure 8-4 Stack Operation
20
N ovem ber 2001 ver 1.2
HMS81C43xx / GMS87C4060
8.2 Program Memory
A 16-bit program counter is capable of addressing up to
64K bytes, but HMS81C43xx/GMS87C4060 has 8~32K/
60K bytes program memory space only physically imple-
Example: Usage of TCALL
LDA
#5
TCALL 0FH
;
;
;
1BYTE INST RU CT IO N
IN STEAD O F 2 BYTES
N O R M AL CALL
mented. Accessing a location above FFFF will cause a
H
:
:
wrap-around to 0000 .
H
;
;TABLE CALL ROUTINE
;
Figure 8-5 , shows a map of Program Memory. After reset,
the CPU begins execution from reset vector which is stored
FUNC_A: LDA
LRG0
in address FFFE and FFFF as shown in Figure 8-6 .
H
H
RET
;
As shown in Figure 8-5 , each area is assigned a fixed lo-
cation in Program Memory. Program Memory area con-
tains the user program.
FUNC_B: LDA
LRG1
1
2
RET
;
;TABLE CALL ADD. AREA
;
ORG
DW
DW
0FFC0H
FUNC_A
FUNC_B
;
TC ALL ADD R ESS AREA
87C4060:1000H
81C4332:8000H
81C4324:A000H
81C4316:C000H
The interrupt causes the CPU to jump to specific location,
where it commences the execution of the service routine.
The External interrupt 0, for example, is assigned to loca-
PROGRAM
MEMORY
81C4308:E000H
FEFFH
FF00H
tion 0FFFC . The interrupt service locations spaces 2-byte
H
interval: 0FFF8 and 0FFF9 for External Interrupt 1,
H
H
FFBFH
FFC0H
0FFFC and 0FFFD for External Interrupt 0, etc.
H
H
TCALL
AREA
PCALL
AREA
Any area from 0FF00 to 0FFFF , if it is not going to be
FFDFH
FFE0H
H
H
INTERRUPT
VECTOR AREA
used, its service location is available as general purpose
Program Memory.
FFFFH
Address
Vector Area Memory
I2C Bus Interface Interrupt Vector Area
Serial I/O Interrupt Vector Area
0FFE0H
E2
Figure 8-5 Program Memory Map
E4
Page Call (PCALL) area contains subroutine program to
reduce program byte length by using 2 bytes PCALL in-
stead of 3 bytes CALL instruction. If it is frequently called,
it is more useful to save program byte length.
Basic Interval Timer Interrupt Vector Area
Watchdog Timer Interrupt Vector Area
External Interrupt 3/4 Vector Area
E6
E8
EA
Timer/Counter 3 Interrupt Vector Area
Timer/Counter 1 Interrupt Vector Area
V-Sync Interrupt Vector Area
EC
EE
Table Call (TCALL) causes the CPU to jump to each
TCALL address, where it commences the execution of the
service routine. The Table Call service area spaces 2-byte
for every TCALL: 0FFC0 for TCALL15, 0FFC2 for
F0
1 Frame Timer Interrupt Vector Area
F2
F4
F6
F8
FA
FC
FE
Timer/Counter 2 Interrupt Vector Area
Timer/Counter 0 Interrupt Vector Area
External Interrupt 2 Vector Area
External Interrupt 1 Vector Area
H
H
TCALL14, etc., as shown in Figure 8-7 .
On Screen Display Interrupt Vector Area
External Interrupt 0 Vector Area
RESET Vector Area
NOTE:
"-" means reserved area.
Figure 8-6 Interrupt Vector Area
November 2001 ver 1.2
21
HMS81C43xx / GMS87C4060
Address
Program Memory
TCALL 15
TCALL 14
TCALL 13
TCALL 12
TCALL 11
TCALL 10
TCALL 9
0FFC0H
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
Address
0FF00H
PCALL Area Memory
PCALL Area
(192 Bytes)
TCALL 8
0FFBFH
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
TCALL 7
TCALL 6
TCALL 5
TCALL 4
TCALL 3
TCALL 2
TCALL 1
TCALL 0 / BRK *
NOTE:
* means that the BRK software interrupt is using
same address with TCALL0.
Figure 8-7 PCALL and TCALL Memory Area
PCALL→ rel
TCALL→ n
4F35
PCALL 35H
4A
TCALL 4
4A
01001010
4F
35
Reverse
þ
~
~
~
~
PC:
11111111
FH FH
11010110
DH 6H
Upper address is
assumed 0FFH.
~
~
~
~
Sub-routine
0D125H
0FF00H
Ã
0FF00H
À
0FF35H
0FFFFH
Sub-routine
0FFD6H
0FFD7H
25
D1
0FFFFH
22
N ovem ber 2001 ver 1.2
HMS81C43xx / GMS87C4060
Example: The usage software example of Vector address and the initialize part in HMS81C4324.
ORG
0FFE0H
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
I2C
SERIAL
BIT
; I2C
; Serial I/O
; Basic interval timer
; Watch dog timer
; Interrupt 3/4
; Timer 3
WATCHDOG
INT3_4
TIMER3
TIMER1
VSYNC
One_Frame
TIMER2
TIMER0
INT2
; Timer 1
; Vertical Sync.
; 1 Frame interrupt
; Timer 2
; Timer 0
; Interrupt 2
; Interrupt 1
; On Screen Display
; Interrupt 0
; Reset
INT1
OSD
INT0
RESET
ORG
0A000H
; Start Address of 24 kbytes Program Memory
;********************************************
MAIN PROGRAM
;
*
;********************************************
;
RESET:
DI
; Disable All Interrupts
LDX
LDA
#0
#0
; RAM Page0 Clear(!0000H->!00BFH)
RAM_CLR: STA
{X}+
#0C0H
RAM_CLR
CMPX
BNE
;
CALL
OSD_Stop
#03FH
; Stop OSD display
;
LDX
TXSP
; Stack Pointer Initialize
LDM
LDM
:
R0, #0
R0DD,#1000_0010B
; Normal Port 0
; Normal Port Direction
:
:
:
November 2001 ver 1.2
23
HMS81C43xx / GMS87C4060
8.3 Data Memory
Figure 8-8 shows the internal Data Memory space availa-
ble. Data Memory is divided into four groups, a user RAM,
control registers, Stack, and OSD memory.
Note: Write only registers can not be accessed by bit ma-
nipulation instruction. Do not use read-modify-write instruc-
tion. Use byte manipulation instruction.
0000H
Example; To write at CKCTLR
RAM (192 bytes)
Page0
LDM
CLCTLR,#09H ;Divide ratio ÷8
00C0H
Peripheral Reg. (64 bytes)
0100H
RAM (256 bytes)
Stack area
Stack Area
Page1
Page2
The stack provides the area where the return address is
saved before a jump is performed during the processing
routine at the execution of a subroutine call instruction or
the acceptance of an interrupt.
0200H
0300H
0400H
0500H
RAM (256 bytes)
RAM (256 bytes)
RAM (256 bytes)
Page3
Page4
When returning from the processing routine, executing the
subroutine return instruction [RET] restores the contents of
the program counter from the stack; executing the interrupt
return instruction [RETI] restores the contents of the pro-
gram counter and flags.
RAM (256 bytes)
RAM (64 bytes)
Page5
Page6
0600H
063FH
Empty area
The save/restore locations in the stack are determined by
the stack pointed (SP). The SP is automatically decreased
after the saving, and increased before the restoring. This
means the value of the SP indicates the stack location
number for the next save. Refer to Figure 8-4 on page 20.
0A00H
0AE0H
OSD RAM (192 bytes)
PageA
PageC
Peripheral Reg. (32 bytes)
Sprite RAM (96 bytes)
0C00H
0C5FH
Figure 8-8 Data Memory Map
User Memory
Addressing
Address
Symbol
R/W Reset Value
mode
The GMS87C4060 has 1,536 × 8 bits for the user memory
(RAM). HMS81C4332 has 512 x 8 bit for the user mem-
1
00C0H
00C1H
00C2H
00C3H
00C4H
00C5H
00C8H
00C9H
00CAH
00CBH
00CCH
00CDH
00CEH
00CFH
R0
R0DD
R1
R1DD
R2
R2DD
R4
R4DD
R5
R5DD
R6
R6DD
FUNC1
FUNC2
R/W
W
R/W
W
R/W
W
R/W
W
R/W
W
R/W
W
W
W
byte, bit
????????
00000000
????????
00000000
????????
00000000
????????
0000----
????????
----0000
?-------
0-------
-0000000
---00000
2
byte
Peripheral Reg. (64
ory (RAM) addressed 000H ~ 23FH except
byte, bit
byte
byte, bit
byte
byte, bit
byte
byte, bit
byte
bytes)
. HMS81C4308/16/24 has 256 x 8 bit RAM ad-
dressed 000H ~ 13FH except peripheral register
(0C0h~0FFh)
Control Registers
The control registers are used by the CPU and Peripheral
function blocks for controlling the desired operation of the
device. Therefore these registers contain control and status
bits for the interrupt system, the timer/ counters, analog to
digital converters and I/O ports. The basic control registers
byte, bit
byte
byte
byte
are in address range of 00C0 to 00FF . And OSD control
H
H
registers are assigned within 0AE0 ~ 0AFF .
Table 8-1Control registers
H
H
Note that unoccupied addresses may not be implemented
on the chip. Read accesses to these addresses will in gen-
eral return random data, and write accesses will have an in-
determinate effect.
More detailed informations of each register are explained
in each peripheral section.
24
N ovem ber 2001 ver 1.2
HMS81C43xx / GMS87C4060
1. "byte, bit" means that register can be addressed by not only bit
but byte manipulation instruction.
2. "byte" means that register can be addressed by only byte
manipulation instruction. On the other hand, do not use any
read-modify-write instruction such as bit manipulation for clear-
ing bit.
0D0H
0D1H
0D2H
0D3H
0D4H
0D5H
0D6H
TM0
TM2
R/W
R/W
R/W
R/W
R/W
R/W
R
byte
byte
-0000000
-0000000
????????
????????
????????
????????
????????
--010111
-0111111
00000000
11111111
0001000-
00000000
00000000
-0000001
????????
TDR0
TDR1
TDR2
TDR3
BITR
CKCTLR
WDTR
ICAR
ICDR
ICSR
ICCR1
ICCR2
SIOM
SIOR
byte, bit
byte, bit
byte, bit
byte, bit
byte
W
W
byte
byte
0D7H
0D8H
0D9H
0DAH
0DBH
0DCH
0DEH
0DFH
R/W
R/W
R/W
R/W
R/W
R/W
R/W
byte, bit
byte, bit
byte, bit
byte, bit
byte, bit
byte, bit
byte, bit
0E0H
0E1H
0E2H
0E3H
0E4H
0E5H
0E8H
0E9H
0EAH
0EBH
0EEH
0EFH
PWMR0
PWMR1
PWMR2
PWMR3
PWMR4
PWMR5
PWM8H
PWM8L
PWMCR1 R/W
PWMCR2 R/W
BUR
AIPS
W
W
W
W
W
W
R/W
R/W
byte
byte
byte
byte
byte
????????
????????
????????
????????
????????
????????
????????
--??????
00000000
--0-0000
????????
--000000
byte
byte, bit
byte, bit
byte, bit
byte, bit
byte
W
W
byte
0F0H
0F1H
0F2H
0F3H
0F4H
0F5H
0F6H
0F7H
0F9H
0FAH
0FBH
0FCH
0FDH
ADCM
ADR
R/W
R
W
R/W
R/W
R/W
R/W
R/W
R/W
R
byte, bit
byte
byte
byte, bit
byte, bit
byte, bit
byte, bit
byte, bit
byte, bit
byte
--011101
????????
--000000
--000000
0000000-
0000000-
00000000
00000000
0000-000
1----001
????????
----0000
????????
IEDS
IMOD
IENL
IRQL
IENH
IRQH
IDCR
IDFS
IDR
R
R/W
W
byte
byte, bit
byte
DPGR
TMR
0AE0H OSDcon1 R/W
0AE1H OSDcon2 R/W
byte, bit
byte, bit
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
00000000
-0000000
????????
01111010
10000111
---00000
????????
????????
????????
????????
????????
????????
????????
0AE2H OSDPOL
0AE3H FDWSET
0AE4H EDGEcol
W
W
W
R
W
W
W
W
W
W
W
0AE5H
0AE6H
OSDLN
LHPOS
0AE8H SPVPOS
0AE9H SPHPOS
0AF0H
0AF1H
0AF3H
0AF4H
L1ATTR
L1VPOS
L2ATTR
L2VPOS
Table 8-1Control registers
November 2001 ver 1.2
25
HMS81C43xx / GMS87C4060
8.4 Addressing Mode
The GMS800 series uses six addressing modes;
• Register addressing
(3) Direct Page Addressing → dp
In this mode, a address is specified within direct page.
Example; G=0
• Immediate addressing
• Direct page addressing
• Absolute addressing
E551: C535
LDA
35H;A ←RAM[35H]
• Indexed addressing
35H
data
• Register-indirect addressing
À
~
~
~
data
A
→
~
þ
0E550H
0E551H
C5
35
(1) Register Addressing
Register addressing accesses the A, X, Y, C and PSW.
(2) Immediate Addressing → #imm
In this mode, second byte (operand) is accessed as a data
immediately.
(4) Absolute Addressing → !abs
Example:
Absolute addressing sets corresponding memory data to
Data , i.e. second byte(Operand I) of command becomes
lower level address and third byte (Operand II) becomes
upper level address.
FE10: 0435
ADC
#35H
MEMORY
With 3 bytes command, it is possible to access to whole
memory area.
0FE10H
04
35
A+35H+C
A
→
ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX,
LDY, OR, SBC, STA, STX, STY
Example;
F100: 0735F0 ADC!0F035H
;A ←ROM[0F035H]
When G-flag is 1, then RAM address is defined by 16-bit
address which is composed of 8-bit direct page accessable
register (DPGR) and 8-bit immediate data.
Example: G=1, DPGR=0CH
0F035H
data
A
F100: E45535
LDM
35H,#55H
~
~
~
~
A+data+C
A
→
0F100H
0F101H
0F102H
07
35
F0
P
address: 0F035
data
0C35H
data
55H
←
~
~
~
~
þ
A
0F100H
E4
55
35
0F101H
0F102H
26
N ovem ber 2001 ver 1.2
HMS81C43xx / GMS87C4060
The operation within data memory (RAM)
ASL, BIT, DEC, INC, LSR, ROL, ROR
X indexed direct page, auto increment→ {X}+
In this mode, a address is specified within direct page by
the X register and the content of X is increased by 1.
Example; Addressing accesses the address 0135 regard-
H
less of G-flag and DPGR.
LDA, STA
F100: 983501 INC!0135H
;A ←ROM[135H]
Example; G=0, X=35
H
F100: DB
LDA
{X}+
135H
data
Ã
À
~
~
~
35H
~
data
À
data+1
data
→
data
36H
A
X
→
→
0F100H
0F101H
0F102H
98
35
01
~
~
~
~
þ
þ
address: 0135
0F100H
DB
(5) Indexed Addressing
X indexed direct page (8 bit offset) → dp+X
X indexed direct page (no offset) → {X}
This address value is the second byte (Operand) of com-
mand plus the data of -register. And it assigns the mem-
ory in Direct page.
In this mode, a address is specified by the X register.
ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA
Example; X=15 , G=1, DPGR=03
H
H
ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA
STY, XMA, ASL, DEC, INC, LSR, ROL, ROR
E550: D4
LDA
{X};ACC←RAM[X].
Example; G=0, X=0F5
H
E550: C645
LDA
45H+X
315H
data
À
data
A
→
~
~
~
~
3AH
data
þ
Ã
À
D4
0E550H
data
A
→
~
~
~
~
0E550H
0E551H
C6
45
þ
45H+0F5H=13AH
November 2001 ver 1.2
27
HMS81C43xx / GMS87C4060
FA00: 3F35
JMP
[35H]
Y indexed direct page (8 bit offset) → dp+Y
This address value is the second byte (Operand) of com-
mand plus the data of Y-register, which assigns Memory in
Direct page.
35H
36H
0A
E3
This is same with above (2). Use Y register instead of X.
À jump to address 0E30A
H
Y indexed absolute → !abs+Y
~
~
~
~
Sets the value of 16-bit absolute address plus Y-register
data as Memory. This addressing mode can specify mem-
ory in whole area.
þ
0E30AH
0FA00H
NEXT
~
~
~
~
Example; Y=55
H
3F
35
F100: D500FA
LDA
!0FA00H+Y
0F100H
0F101H
0F102H
D5
þ
00
X indexed indirect → [dp+X]
FA
0FA00H+55H=0FA55H
Processes memory data as Data, assigned by 16-bit pair
memory w hich is deter mined by pair data
[dp+X+1][dp+X] Operand plus X-register data in Direct
page.
~
~
~
~
À
data
0FA55H
data
A
→
Ã
ADC, AND, CMP, EOR, LDA, OR, SBC, STA
Example; G=0, X=10
H
FA00: 1625
ADC
[25H+X]
(6) Indirect Addressing
Direct page indirect → [dp]
35H
36H
05
E0
Assigns data address to use for accomplishing command
which sets memory data(or pair memory) by Operand.
Also index can be used with Index register X,Y.
À 0E005
~
~
H
~
~
25 + X(10) = 35H
þ
0E005H
0FA00H
data
JMP, CALL
~
~
~
~
Example; G=0
16
25
A + data + C
A
→
Ã
28
N ovem ber 2001 ver 1.2
HMS81C43xx / GMS87C4060
Y indexed indirect → [dp]+Y
Absolute indirect → [!abs]
Processes momory data as Data, assigned by the data
[dp+1][dp] of 16-bit pair memory paired by Operand in Di-
rect page plus Y-register data.
The program jumps to address specified by 16-bit absolute
address.
JMP
ADC, AND, CMP, EOR, LDA, OR, SBC, STA
Example; G=0
Example; G=0, Y=10
H
FA00: 1F25E0
JMP
[!0C025H]
FA00: 1725
ADC
[25H]+Y
PROGRAM MEMORY
0E025H
0E026H
25
25H
26H
05
E0
E7
jump to
address 0E30AH
À
0E005H + Y(10) = 0E015H
À
~
~
~
~
~
~
~
~
0E725H
0FA00H
NEXT
þ
0E015H
data
þ
~
~
~
~
~
~
~
~
1F
0FA00H
17
25
25
A + data + C
A
→
Ã
E0
November 2001 ver 1.2
29
HMS81C43xx / GMS87C4060
9. I/O PORTS
The GMS87C4060 has digital ports (R0, R1, R2, R4, R5
and R6) and OSD ports (R,G,B), but HMS81C43xx has
R1, R2, R4, R5 and OSD ports (R,G,B)
function for the peripheral features on the device. In gen-
eral, in a initial reset state, R ports are used as a general
purpose digital port.
These ports pins may be multiplexed with an alternate
9.1 Registers for Port
Port Data Registers
ister) during initial setting as shown in Figure 9-1 .
The Port Data Registers in I/O buffer in each R ports are
represented as a Type D flip-flop, which will clock in a val-
ue from the internal bus in response to a "write to data reg-
ister" signal from the CPU. The Q output of the flip-flop is
placed on the internal bus in response to a "read data reg-
ister" signal from the CPU. The level of the port pin itself
is placed on the internal bus in response to "read data reg-
ister" signal from the CPU. Some instructions that read a
port activating the "read register" signal, and others acti-
vating the "read pin" signal
All the port direction registers in the HMS81C43xx/
GMS87C4060 have 0 written to them by reset function. On
the other hand, its initial status is input.
WRITE "55H" TO PORT R0 DIRECTION REGISTER
0C0H
0C1H
BIT
R0 DATA
0
7
1
6
0
5
1
4
0
3
1
2
0
1
1
0
R0 DIRECTION
~
~
Port Direction Registers
~
~
0C8H
0C9H
R4 DATA
I
O
6
I
O
4
I
O
2
I
O
0
PORT
All pins have data direction registers which can define
these ports as output or input. A "1" in the port direction
register configure the corresponding port pin as output.
Conversely, write "0" to the corresponding bit to specify it
as input pin. For example, to use the even numbered bit of
R0 as output ports and the odd numbered bits as input
7
5
3
1
R4 DIRECTION
I : INPUT PORT
O : OUTPUT PORT
Figure 9-1 Example of port I/O assignment
ports, write "55 " to address 0C1 (R0 port direction reg-
H
H
30
N ovem ber 2001 ver 1.2
HMS81C43xx / GMS87C4060
9.2 I/O Ports Configuration
R0 Ports
The control registers for R1 are shown below.
R0 is an 8-bit CMOS bidirectional I/O port (address
ADDRESS : 00C2H
RESET VALUE : Undefined
R1 Data Register
0C0 ). Each I/O pin can independently used as an input or
H
RW
RW
R16
RW
RW
RW
RW
RW
RW
an output through the R0DD register (address 0C1 ).
H
R17
R12
R11
R10
R15
R14
R13
R1
The control registers for R0 are shown below.
ADDRESS : 00C3H
RESET VALUE : 0000 0000b
R1 Direction Register
ADDRESS : 00C0H
R0 Data Register
W
W
W
W
W
W
W
W
RESET VALUE : Undefined
RW
R07
RW
R06
RW
RW
RW
RW
RW
RW
R1DD
R05
R04
R03
R02
R01
R00
R0
Port Direction
0: Input
1: Output
ADDRESS : 00C1H
RESET VALUE : 0000 0000b
R0 Direction Register
W
W
W
W
W
W
W
W
ADDRESS : 00F0H
RESET VALUE : --01 1101b
A/D Convertor mode Register
R0DD
RW
RW
RW
R
RW
RW
Port Direction
0: Input
ADEN ADS2 ADS1 ADS0 ADST ADSF
ADCM
1: Output
A/D Enable
0: Disable
1: Enable
A/D Status
0: Busy
1: Finish
A/D Port select
000: AN0
001: AN1
010: AN2
011: AN3
100: AN4
In addition, Port R0 is only digital I/O. After reset, R0DD
value is "0", R0 acts as normal digital input port.
A/D Start
0: Ignore
1: A/D start
101: AN5
110: AN6
111: No Analog port
R1 Ports
ADDRESS : 00EFH
Analog input pin selector Register
R1 is an 8-bit CMOS bidirectional I/O port (address
RESET VALUE : --00 0000b
W
W
W
W
W
W
0C2 ). Each I/O pin can independently used as an input or
H
AIPS
an output through the R1DD register (address 0C3 ).
R1 port have secondary functions as following table.
H
Port Property
0: Digital I/O
1: Analog Input
Port Pin
Alternate Function
AN0 (A/D input 0)
AN1 (A/D input 1)
AN2 (A/D input 2)
AN3 (A/D input 3)
AN4 (A/D input 4)
AN5 (A/D input 5)
VD (Vertical Sync. input)
HD (Horizontal Sync. input)
ADDRESS : 00CFH
RESET VALUE : ---0 0000b
Port function select Register 2
R10
R11
R12
R13
R14
R15
R16
R17
W
W
W
W
W
VDS YMS YSS
IS
HDS
FUNC2
R16/VD select
0: R16 I/O
1: VD Input
R17/HD select
0: R17 I/O
1: HD Input
Port R1 is multiplexed with various special features.The
control registers controls the selection of alternate func-
tion. After reset, R1 port acts as normal digital input port.
The way to select alternate function such as A/D input or
HD,VD will be shown in each peripheral section.
November 2001 ver 1.2
31
HMS81C43xx / GMS87C4060
R2 Port
R4 Port
R2 is an 8-bit CMOS bidirectional I/O port (address
R4 is consrutced with 4-bit Open drain Output port and 4-
0C4 ). Each I/O pin can independently used as an input or
bit CMOS bidirectional I/O port (address 0C8 ). Each I/O
H
H
an output through the R2DD register (address 00C5 ).
pin can independently used as an input or an output
H
through the R4DD register (address 0C9 ).
H
The control registers for R2 are shown below.
The control registers for R4 are shown below.
ADDRESS : 00C4H
R2 Data Register
ADDRESS : 00C8H
R4 Data Register
RESET VALUE : Undefined
RESET VALUE : Undefined
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R27
R22
R21
R20
R26
R25
R24
R23
R2
R47
R46
R45
R44
R43
R42
R41
R40
R4
ADDRESS : 00C5H
RESET VALUE : 0000 0000b
ADDRESS : 00C9H
R2 Direction Register
R4 Direction Register
RESET VALUE : 0000 ----b
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
R2DD
R4DD
Port Direction
0: Input
Port Direction
0: Input
1: Output
1: Output
ADDRESS : 00DEH
ADDRESS : 00DBH
Serial I/O mode Register
I2C Control Register 1
RESET VALUE : -000 0001b
RESET VALUE : 00-0 0000b
RW
RW
RW
RW
RW
RW
R
RW
RW
RW
RW
RW
RW
RW
IOSW SM1 SM0 SCK1 SCK0 SIOST SIOSF
BSW1 BSW0
ALS
ESO BC2
BC1
BC0
SIOM
Serial I/O
ICCR1
Seriial Status
0: Serial In
1: Serial Out
0: Busy
1: Finish
Bit count
000b (8bit)
001b~111b (1~7bit)
Clock select
00: PS3
01: PS4
10: PS5
11: External
I2C enable
0: Disable
1: Enable
Serial Start
0: Ignore
1: Serial start
Slave address identification
0: Accept (Addressing format)
1: Decline (Free data format)
SM1 SM0 Mode
R21 R22 R23
R21 R22 R23
Sclk Sout R23
Sclk R22 Sin
R21 R22 R23
0
1
0
1
-
0
0
1
1
R44 R45
R46
R47
BSW0
BSW1
Send
Receive
-
0
0
1
1
0
1
0
1
R44 R45/PWM4 R46
R47/PWM5
SCL0 R45/PWM4 SDA0 R47/PWM5
R44 SCL1
SCL SCL
R46
SDA1
SDA SDA
ADDRESS : 00CEH
RESET VALUE : -000 0000b
Port function select Register 1
W
W
W
W
W
W
W
ADDRESS : 00EAH
PWM control Register 1
EC3S EC2S
INT3S INT2S INT1S INT0S
INT4S
RESET VALUE : 0000 0000b
FUNC1
R27/EC3
RW
RW
RW
RW
RW
RW
RW
RW
R20/INT2
0: R20
1: INT2
EN5
EN4
EN3
EN1
EN0
EN8 CNT
EN2
PWMCR1
0: R27
1: EC3
R24/INT3
0: R24
1: INT3
14/8bit PWM count
0: Count start
1: Count stop
R25/EC2
R26/INT4
0: R26
1: INT4
0: R25
1: EC2
EN5,4,3,2,1 : R47,45,43,42,41,40
0: R4x acts normal digital port
1: R4x acts PWM output port
ADDRESS : 00F2H
RESET VALUE : --00 0000b
R51/PWM8 select
0: R51
Ext. interrupt edge selection Register
1: PWM8
W
W
W
W
W
W
IED2H IED2L IED1H IED1L IED0H IED0L
IEDS
00: Ignore edge
INT2
01: Falling edge
10: Rising edge
11: Falling/Rising edge
32
N ovem ber 2001 ver 1.2
HMS81C43xx / GMS87C4060
R5 Port
R6 Port
R6 is an 1-bit CMOS bidirectional I/O port (address
0CC ). Each I/O pin can independently used as an input or
R5 is an 7-bit port (address 0CA ). Each I/O pin can inde-
pendently used as an input or an output through the R5DD
H
H
register (address 0CB ).
an output through the R6DD register (address 0CD ).
H
H
The control registers for R5 are shown below
The control registers for R6 are shown below
ADDRESS : 00CAH
R5 Data Register
ADDRESS : 00CCH
R6 Data Register
RESET VALUE : Undefined
RESET VALUE : Undefined
RW
RW
RW
RW
RW
RW
RW
RW
R52
R51
R56
R55
R54
R53
R50
R67
R5
R6
ADDRESS : 00CBH
RESET VALUE : ---- 0000b
ADDRESS : 00CDH
R6 Direction Register
R5 Direction Register
R5DD
RESET VALUE : 0--- ----b
W
W
W
W
W
R6DD
Port Direction
0: Input
1: Output
Port Direction
0: Input
1: Output
ADDRESS : 00CEH
ADDRESS : 00CEH
Port function select Register 1
Port function select Register 1
RESET VALUE : -000 0000b
RESET VALUE : -000 0000b
W
W
W
W
W
W
W
W
W
W
W
W
W
W
EC3S EC2S INT4S INT3S INT2S INT1S INT0S
FUNC1
EC3S EC2S INT4S INT3S INT2S INT1S INT0S
FUNC1
R52/INT0
0: R52
1: INT0
R67/INT1
0: R67
1: INT1
ADDRESS : 00CFH
Port function select Register 2
ADDRESS : 00F2H
RESET VALUE : --00 0000b
RESET VALUE : ---0 0000b
Ext. interrupt edge selection Register
W
W
W
W
W
W
W
W
W
W
W
VDS YMS YSS
IS
HDS
FUNC2
IED2H IED2L IED1H IED1L IED0H IED0L
IEDS
R54/YM
0: R56
R55/YS
0: R55
R56/I
0: R56
INT1
00: Ignore edge
01: Falling edge
10: Rising edge
1: YM Output 1: YS Output 1: I Output
11: Falling/Rising edge
ADDRESS : 00EBH
RESET VALUE : --0- 0000b
PWM control Register 2
RW
BUZS
RW
RW
RW
RW
POL2 POL1 EN7 EN6
PWMCR2
R50/BUZZ
0: R50
1: BUZZ
ADDRESS : 00F2H
RESET VALUE : --00 0000b
Ext. interrupt edge selection Register
W
W
W
W
W
W
IED2H IED2L IED1H IED1L IED0H IED0L
IEDS
00: Ignore edge
01: Falling edge
INT2
10: Rising edge
11: Falling/Rising edge
November 2001 ver 1.2
33
HMS81C43xx / GMS87C4060
10. CLOCK GENERATOR
As shown in Figure 10-1 , the clock generator produces the
basic clock pulses which provide the system clock to be
supplied to the CPU and the peripheral hardware. It con-
tains two oscillators: a main-frequency clock oscillator and
a sub-frequency clock oscillator. The system clock can
also be obtained from the external oscillator.
Minimum instruction cycle time
Main clock
(ex:NOP ; f 4clock is needed)
ex
3.6MHz
4MHz
1,111nS
1,000nS
500nS
8MHz
The clock generator produces the system clocks forming
clock pulse, which are supplied to the CPU and the periph-
eral hardware.
To the peripheral block, the clock among the not-divided
original clocks, divided by 2, 4,..., up to 1024 can be pro-
vided. Peripheral clock is enabled or disabled by bit 4 of
the peripheral clock enable register (ENPCK).
Internal system clock
Clock pulse Generator
fEX
OSC
Circuit
PRESCALER
ENPCK
[0D6H]
WDT
ENPCK BTCL BTS2 BTS1 BTS0
CKCTLR
ON
Clock control register
Peripheral clock
Figure 10-1 Block Diagram of Clock Generator
Note: On the initial reset, all peripherals are run because
peripheral clock is supplied to each function block. If you
want to see more details, see Clock Control Register
(CKCTLR).
ADDRESS : 00D6H
Clock control register
RESET VALUE : --01 0111b
W
W
W
W
W
W
WDT
ON
ENPCK BTCL BTS2 BTS1 BTS0
CKCTLR
Watch-dog
timer select
B.I.T Clock
ADDRESS : 00FDH
Test mode register
B.I.T set
0: Normal 6bit timer
1: Watch-dog timer
RESET VALUE : 0000 0000b
0: Free run
1: B.I.T clear
Peri. Clock
0: Stop
W
W
W
W
W
W
W
W
1: Supply
TMR
0000 0110b Normal operation mode
34
N ovem ber 2001 ver 1.2
HMS81C43xx / GMS87C4060
11. TIMER
11.1 Basic Interval Timer
The HMS81C43xx/GMS87C4060 has one 8-bit Basic In-
terval Timer that is free-run and can not be stopped. Block
diagram is shown in Figure 11-1 .
generated. The Basic Interval Timer is controlled by the
clock control register (CKCTLR) shown in Figure 11-2 .
Source clock can be selected by lower 3 bits of CKCTLR.
The Basic Interval Timer generates the time base for
watchdog timer counting, and etc. It also provides a Basic
interval timer interrupt (BITIF). As the count overflow
BITR and CKCTLR are located at same address, and ad-
dress 00D6 is read as a BITR and written to CKCTLR..
H
from FF to 00 , this overflow causes the interrupt to be
H
H
fex 24
÷
PS4
PS5
PS6
PS7
PS8
PS9
fex 25
÷
8-bit up-counter
BITR
fex 26
÷
source
clock
overflow
fex 27
÷
BITIF
MUX
fex 28
Basic Interval Timer Interrupt
÷
fex 29
÷
[0D6H]
fex 210
Watchdog timer clock (WDTCK)
÷
PS10
PS11
clear
BTCL
fex 211
÷
3
BITCK
Select Input clock
Clock control register
[0D6H]
WDT
ENPCK BTCL BTS2 BTS1 BTS0
CKCTLR
ON
Internal bus line
Figure 11-1 Block Diagram of Basic Interval Timer
Interrupt
(overflow) Period
Source clock
BTS2~0
At f =8MHz
Pre-Scaler output
ex
4
f
ex
f
ex
f
ex
f
ex
f
ex
f
ex
f
ex
f
ex
2
÷
2
÷
2
÷
2
÷
2
÷
2
÷
2
÷
2
÷
000
001
010
011
100
101
110
111
PS4
PS5
PS6
PS7
PS8
PS9
PS10
PS11
0.512 mS
1.024
5
6
2.048
7
4.096
8
8.192
9
16.384
32.768
65.536
10
11
Table 11-1 Basic Interval Timer Interrupt Time
November 2001 ver 1.2
35
HMS81C43xx / GMS87C4060
W
W
W
W
W
W
ADDRESS : 00D6H
WDT
ON
ENPCK BTCL BTS2 BTS1 BTS0
CKCTLR
RESET VALUE : --01 0111b
Watch-dog
timer select
0: Normal 6bit timer
1: Watch-dog timer
B.I.T Clock
B.I.T set
0: Free run
Peri. Clock
0: Stop
1: Supply
1: Clear 8-bit counter (BITR) to "0". This bit becomes 0
automatically after 1 machine cycle
:
Caution
Both register are in same address,
when write, to be a CKCTLR,
when read, to be a BITR.
R
R
R
R
R
R
R
R
ADDRESS: 00D6H
INITIAL VALUE: Undefined
BITR
8-BIT BINARY COUNTER
Figure 11-2 BITR: Basic Interval Timer Mode Register
11.2 Timer 0, 1
Timer 0, 1 consists of prescaler, multiplexer, 8-bit compare
data register, 8-bit count register, Control register, and
Comparator as shown in Figure 11-3 .
The control registers for Timer 0,1 are shown below.
ADDRESS : 00D0H
Timer mode register 0
RESET VALUE : -000 0000b
RW
RW
RW
RW
RW
RW
RW
These Timers can run separated 8bit timer or combined
16bit timer. These timers are operated by internal clock.
T1ST T1SL1 T1SL0 T0ST T0CN T0SL1 T0SL0
TM0
Timer 0 input clock
Timer 1 start
0: Count Hold
1: Count Clear and Start
00: PS2 (fex / 22)
01: PS4 (fex / 24)
10: PS6 (fex / 26)
11: PS8 (fex / 28)
The contents of TDR1 are compared with the contents of
up-counter T1. If a match is found, a timer/counter 1 inter-
rupt (T1IF) is generated, and the counter is cleared. Count-
ing up is resumed after the counter is cleared.
Timer 1 input clock
00: Timer 0 overflow (16bit mode)
Timer 0 control
0: Count Hold
1: Count Continue
01: PS2 (fex / 22)
10: PS4 (fex / 24)
11: PS6 (fex / 26)
Timer 0 start
0: Count Hold
1: Count Clear and Start
Note: You can read Timer 0, Timer 1 value from TDR0 or
TDR1. But if you write data to TDR0 or TDR1, it changes
Timer 0 or Timer 1 modulo data, not Timer value.
ADDRESS : 00D2H
RESET VALUE : Undefined
Timer 0 data register
RW
RW
RW
RW
RW
RW
RW
RW
The content of TDR0, TDR1 must be initialized (by soft-
TDR0
ware) with the value between 01 and FF ,not to 00 .
H
H
H
Or not, Timer 0 or Timer 1 can not count up forever.
ADDRESS : 00D3H
Timer 1 data register
RESET VALUE : Undefined
RW
RW
RW
RW
RW
RW
RW
RW
TDR1
36
N ovem ber 2001 ver 1.2
HMS81C43xx / GMS87C4060
.
Internal bus line
TM0
TDR0
TDR1
T0CN
8bit Comparator
T0IF
8bit Comparator
T1IF
Timer 0
Clock
Timer 1
PS2
PS4
PS6
PS8
MUX
MUX
Clear
Clock
Clear
T0ST
NC
PS2
PS4
PS6
T1ST
Figure 11-3 Simplified Block Diagram of 8bit Timer0, 1
TDR0
enable
disable
clear & start
stop
TIME
Timer 0 (T0IF)
Interrupt
Occur interrupt
Occur interrupt
T0ST
T0ST = 1
T0ST = 0
Start & Stop
T0CN
T0CN = 1
Control count
T0CN = 0
Figure 11-4 Count Example of Timer
November 2001 ver 1.2
37
HMS81C43xx / GMS87C4060
Internal bus line
TM0
TDR0
TDR1
0
0
T0CN
16bit Comparator
T1IF
Timer 0
Clock
Timer 1
Clock
PS2
PS4
PS6
PS8
MUX
Clear
Clear
T0ST
Figure 11-5 Simplified Block Diagram of 16bit Timer0, 1
11.3 Timer / Event Counter 2, 3
Timer 2, 3 consists of prescaler, multiplexer, 8-bit compare
data register, 8-bit count register, Control register, and
Comparator as shown in Figure 11-5 .
The control registers for Timer 2,3 are shown below
ADDRESS : 00D1H
RESET VALUE : -000 0000b
Timer mode register 2
RW
RW
RW
RW
RW
RW
RW
These Timers have two operating modes. One is the timer
mode which is operated by internal clock, other is event
counter mode which is operated by external clock from pin
R25/EC2, R27/EC3.
T3ST T3SL1
T2ST T2CN T2SL1 T2SL0
T3SL0
TM2
Timer 2 input clock
Timer 3 start
0: Count Hold
00: PS2 (fex / 22)
01: PS4 (fex / 24)
10: PS6 (fex / 26)
11: PS8 (fex / 28)
1: Count Clear and Start
Timer 3 input clock
00: Timer 2 overflow (16bit mode)
01: PS2 (fex / 22)
These Timers can run separated 8bit timer or combined
16bit timer.
Timer 2 control
0: Count Hold
1: Count Continue
10: PS4 (fex / 24)
11: PS6 (fex / 26)
Timer 2 start
0: Count Hold
1: Count Clear and Start
Note: You can read Timer 2, Timer 3 value from TDR2 or
TDR3. But if you write data to TDR2 or TDR3, it changes
Timer 2 or Timer 3 modulo data, not Timer value.
ADDRESS : 00D4H
RESET VALUE : Undefined
Timer 2 data register
RW
RW
RW
RW
RW
RW
W
RW
RW
RW
The content of TDR2, TDR3 must be initialized (by soft-
TDR2
ware) with the value between 01 and FF ,not to 00 .
H
H
H
Or not, Timer 2 or Timer 3 can not count up forever.
ADDRESS : 00D5H
Timer 3 data register
RESET VALUE : Undefined
RW
RW
RW
RW
RW
RW
RW
TDR3
ADDRESS : 00CEH
RESET VALUE : -000 0000b
Port function select Register 1
W
W
W
W
W
W
EC3S EC2S INT4S INT3S INT2S INT1S INT0S
FUNC1
R25/EC2
0: R25
1: EC2
R27/EC3
0: R27
1: EC3
38
N ovem ber 2001 ver 1.2
HMS81C43xx / GMS87C4060
.
Internal bus line
TM2
TDR2
TDR3
T2CN
8bit Comparator
T2IF
8bit Comparator
T3IF
Timer 2
Clock
Timer 3
EC2
PS2
PS4
PS6
MUX
MUX
Clear
Clock
Clear
T2ST
NC
EC3
PS2
PS4
T3ST
Figure 11-6 Simplified Block Diagram of 8bit Timer/Event Counter 2,3
TDR2
enable
disable
clear & start
stop
TIME
Timer 2 (T2IF)
Interrupt
Occur interrupt
Occur interrupt
T2ST
Start & Stop
T2ST = 1
T2ST = 0
T2CN
T2CN = 1
Control count
T2CN = 0
Figure 11-7 Count Example of Timer / Event counter
November 2001 ver 1.2
39
HMS81C43xx / GMS87C4060
Internal bus line
TM2
TDR2
TDR3
0
0
T0CN
16bit Comparator
T3IF
Timer 2
Clock
Timer 3
Clock
EC2
PS4
PS6
PS8
MUX
Clear
Clear
T0ST
Figure 11-8 Simplified Block Diagram of 16bit Timer/Event Counter 2,3
n interrupt (TnIF) is generated and the up-counter is
Timer Mode
cleared to 0. Counting up is resumed after the up-counter
is cleared.
In the timer mode, the internal clock is used for counting
up. Thus, you can think of it as counting internal clock in-
put. The contents of TDRn (n=0~3) are compared with the
contents of up-counter, Timer n. If match is found, a timer
As the value of TDRn is changeable by software, time in-
terval is set as you want
Start count
Source clock
N-2
N-1
N
1
4
0
3
0
1
2
3
2
Up-counter
TDRn (n=0~3)
N
Match
Detect
Counter
Clear
TnIF (n=0~3) interrupt
Figure 11-9 Timer Mode Timing Chart
Event counter Mode
put.
In event timer mode, counting up is started by an external
trigger. This trigger means falling edge of the ECn (n=2~3)
pin input. Source clock is used as an internal clock selected
with TM2. The contents of TDRn are compared with the
contents of the up-counter. If a match is found, an TnIF in-
The maximum frequency applied to the ECn pin is f /2
[Hz] in main clock mode.
ex
In order to use event counter function, the bit EC2S, EC3
of the Port Function Select Register1 FUNC1(address
0CE ) is required to be set to "1".
H
terrupt is generated, and the counter is cleared to 00 . The
H
counter is restarted by the falling edge of the ECn pin in-
After reset, the value of TDRn is undefined, it should be
40
N ovem ber 2001 ver 1.2
HMS81C43xx / GMS87C4060
initialized to between 01 ~FF not to 00
H
H
H
Start count
ECn (n=2~3) pin
1
1
2
Up-counter
0
2
N-1
N
0
TDRn (n=2~3)
N
TnIF (n=2~3) interrupt
Figure 11-10 Event Counter Mode Timing Chart
The interval period of Timer is calculated as below equa-
tion.
-------
=
×
×
TDR2
TDR2=n
n
n-1
n-2
PCP
8
7
6
5
4
3
2
1
0
TIME
Interrupt period
= PCP x n
Timer 2 (T2IF)
Interrupt
Occur interrupt
Occur interrupt
Occur interrupt
Figure 11-11 Count Example of Timer / Event counter
November 2001 ver 1.2
41
HMS81C43xx / GMS87C4060
TDR2
enable
disable
clear & start
stop
TIME
Timer 2 (T2IF)
Interrupt
Occur interrupt
Occur interrupt
T2ST
Start & Stop
T2ST = 1
T2ST = 0
T2CN
T2CN = 1
Control count
T2CN = 0
Figure 11-12 Count Operation of Timer / Event counter
42
N ovem ber 2001 ver 1.2
HMS81C43xx / GMS87C4060
12. A/D Converter
The A/D convertor circuit is shown in Figure 12-1 .
alog input. The ADCM register control A/D converter’s
activity. The ADR register stores A/D converted 8bit re-
sult. The more details are shown Figure 12-2 .
The A/D convertor circuit consists of the comparator and
control register AIPS(00EF ), ADCM(00F0 ),
H
H
ADR(00F1 ). The AIPS register select normal port or an-
H
ADEN ADS2 ADS1 ADS0 ADST ADSF
ADCM [F0H]
ADR [F1H]
IFA
Control circuit
port
select
AN0
Comparator
AN1
S/H
Succesive
Approximation
Circuit
AN2
MUX
AN3
+
−
Vref
AN4
AN5
Register ladder
Figure 12-1 Block Diagram of A/D convertor circuit
;
1 : analog port
AIPS,#00??????b
Control
LDM
; Set ADEN, xxx is analog port number
The HMS81C43xx/GMS87C4060 contains a A/D con-
verter module which has six analog inputs.
LDM
ADCM,#001xxx00b
; or “SET1 ADEN”
; Set ADST, xxx is analog port number
1. First of all, you have to select analog input pin by set the
ADCM and AIPS.
LDM
ADCM,#001xxx10b
; or “SET1 ADST”
:
:
2. Set ADEN (A/D enable bit : ADCM bit5).
3. Set ADST (A/D start bit : ADCM bit1). We recommend
you do not set ADEN and ADST at once, it makes worse
A/D converted result.
5. After A/D conversion is completed, ADSF bit and inter-
rupt flag IFA will be set. (A/D conversion takes 36 ma-
chine cycle : 9uS when f =8MHz).
ex
4. ADST bit will be cleared automatically 1cycle after you
set this.
Note:
Make sure AIPS bits, if you using a port which is set
digital input by AIPS, analog voltage will be flow into MCU
internal logic not A/D converter. Sometimes device or port
is damaged permanently.
Example:
:
; Set AIPS, change ? to what you want
;
0 : digital port
November 2001 ver 1.2
43
HMS81C43xx / GMS87C4060
ADDRESS : 00F0H
RESET VALUE : --01 1101b
A/D Convertor mode Register
RW
RW
RW
RW
RW
R
ADEN ADS2 ADS1 ADS0 ADST ADSF
ADCM
A/D Enable
0: Disable
1: Enable
A/D Status
0: Busy
1: Finish
A/D Port select
000: AN0
001: AN1
010: AN2
011: AN3
100: AN4
A/D Start
0: Ignore
1: A/D start
101: AN5
11x: No Analog port
ADDRESS : 00F1H
RESET VALUE : Undefined
A/D Result Register
R
R
R
R
R
R
R
R
ADR
8bit result is stored
ADDRESS : 00EFH
RESET VALUE : --00 0000b
Analog input pin selector Register
W
W
W
W
W
W
AIPS
Port Property
0: Digital I/O
1: Analog Input
Figure 12-2 A/D convertor Registers
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HMS81C43xx / GMS87C4060
13. Serial I/O
The Serial I/O circuit is shown in Figure 13-1 .
data or data which will be transfered. The SIOM register
controls serial communication mode, speed, start, etc.
The Serial I/O circuit consists of the octal counter, SI-
OR(DF ), SIOM(DE ). The SIOR register stores received
The more details about registers are shown Figure 13-2 .
H
H
IOSW SM1 SM0 SCK1 SCK0 SIOST SIOSF
D7
D6
D5
D4
D3
D2
D1
D0
SIOM [DEH]
SIOR [DFH]
PS3
PS4
IFSIO
Control
Circuit
Octal counter
MUX
PS5
Exclk
Sclk
Sout
1
MUX
Sin
0
Figure 13-1 Block Diagram of Serial I/O circuit
2. You have to select serial communication clock by set the
SCK1~0.
Control
The HMS81C43xx/GMS87C4060 contains a Synchronous
type Serial I/O module.
Ex: Frequency
SCK1 SCK0
Selected Clock
1. You have to select serial I/O pins by set the SM1~0.
(f =8MHz)
ex
0
0
1
1
0
1
0
1
PS3
PS4
1uS
2uS
Port select
SM1 SM0
Function
R21
R21
Sclk
Sclk
R21
R22
R22
Sout
R22
R22
R23
R23
R23
Sin
PS5
4uS
0
0
1
1
0
1
0
1
-
Send
Receive
-
External clock
User define
3. If you want to send data, write it to SIOR. Or not skip
this.
R23
4. Start serial communication by set SIOST(Serial I/O
start, SIOM bit1).
Note:
Sout pin can handle serial data output or serial data
. After serial communication is completed, SIOSF bit and
5
input. You can input serial data to Sout pin when IOSW bit
is 1. But Sin pin is dedicated serial data input pin.
interrupt flag IFSIO will be set.
November 2001 ver 1.2
45
HMS81C43xx / GMS87C4060
ADDRESS : 0DEH
RESET VALUE : -000 0001b
Serial I/O mode Register
RW
RW
RW
RW
RW
RW
R
Serial I/O Interrupt
Service routine
IOSW SM1 SM0 SCK1 SCK0 SIOST SIOSF
SIOM
Serial Status
0: Busy
Clock Select
Input select
0: Sin
1: Sout
1: Finish
No
SIOSF=1?
Yes
Serial COMM. Start
0: Ignore
1: COMM. start
Send / Receive
Abnormal operation
SE=0
ADDRESS : 0DFH
RESET VALUE : Undefined
Serial I/O data Register
// SE : Interrupt enable bit
RW
D7
RW
D6
RW
D5
RW
D4
RW
D3
RW
RW
RW
SIOR
D2
D1
D0
Write SIOM
// SR : Interrupt request flag
No
SR=0?
Yes
Figure 13-2 Serial I/O Registers
Overrun error
Normal operation
Figure 13-3 Example for serial I/O check by S/W
Input clock
Sclk
SIOST
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
Sout
Sin
IFSIO
Figure 13-4 Serial I/O Timing Chart
46
N ovem ber 2001 ver 1.2
HMS81C43xx / GMS87C4060
14. Pulse Width Modulation (PWM)
The PWM circuit is shown in Figure 14-1 , Figure .
The PWM circuit consists of the counter, comparator, Data
register.
Example
(f =8MHz)
ex
The PWM control registers are PWMR7~0, PWMCR2~1,
PWM8H, PWM8L.
14bit PWM
8bit PWM
Resolution
Input Clock
Frame cycle
0.5uS
2MHz
4uS
The more details about registers are shown Figure 14-2 .
250KHz
1,024uS
8,192uS
PWMCR2 [EBH]
PWMCR1 [EAH]
CNTB
PWM5
PWM4
PWMR5 [E5H]
PWMR4 [E4H]
PWMR3 [E3H]
PWM3
PWM2
PWMR2 [E2H]
PWMR1 [E1H]
PWM1
PWMR0 [E0H]
8bit comparator
PWM0
PS5
IF1Frame
8bit counter
Figure 14-1 8bit register (PWM7~0) circuit
PWMCR2 [EBH]
CNTB
PWMCR1 [EAH]
PWMR8H 8bit [E8H]
PWMR8L 6bit [E9H]
PWM8
14bit comparator
MSB
LSB
PS2
14bit counter
Figure 14-2 14bit register (PWM8) circuit
November 2001 ver 1.2
47
HMS81C43xx / GMS87C4060
8bit PWM Control
5. CNTB controls all PWM counter enable.
If CNTB=0, Counter is enabled.
The HMS81C43xx/GMS87C4060 contains a one 14bit
PWM and six 8bit PWM module.
14bit PWM Control
1. 8bit PWM0~5 is wholy same internal circuit, but
PWM0~5 output port is NMOS open drain.
1. 14bit PWM’s operation concept is not the same as 8bit
PWM.
2. Al l PWM polarity has the same by POL2’s value.
1 PWM frame contains 64 sub PWMs.
PWM8H : Set sub PWM’s basic Pulse Width.
PWM8L : Number of sub PWM which is added 1 clock.
3. Calulate Frame cycle and Pulse width is as following.
13
PWM Frame Cycle = 2 / f (Sec)
ex
5
PWM Width = (PWMRn+1) * 2 / f (n=0~5)
2. PWM polarity is selected by POL1’s value.
If POL1=0, Positive Polarity.
ex
Pulse Duty (%) = (PWMRn +1) / 256 *100(%) (n=0~5)
3. Calulate Frame cycle and Pulse width is as following.
16
Main PWM Frame Cycle = 2 / f (Sec).
ex
Positive Polarity (POL2=0)
Negative Polarity (POL2=1)
Sub PWM Frame Cycle = Main Frame Cycle / 64.
4. Table 14-1, “PWM8L and Sub frame matching table,”
on page 48 show PWM8L function.
1
2
1
2
Sub frame number which is
added 1 clock
Pulse
count
Bit value
1. Frame cycle
2. Pulse Width
if Bit0=1 32
1
2
4
8
if Bit1=1 16, 48
Figure 14-3 Wave form example for 8bit PWM
if Bit2=1 8, 24, 40, 56
if Bit3=1 4, 12, 20, 28, 36, 44, 52, 60
4. PWM output is enabled during ENn(n=0~5) bit (See
PWMCR1~2) contains 1.
2, 6, 10, 14, 18, 22, 26, 30, 34,
if Bit4=1
16
38, 42, 46, 50, 54
1, 3, 5, 7, 9, 11, 13, 15, 17, 19,
21, 23, 25, 27, 29, 31, 33, 35, 37,
39, 41, 43, 45, 47, 49, 51, 53, 55,
57, 59, 61, 63
ADDRESS : 0E0~E5H
PWM Data Register
RESET VALUE : Undefined
if Bit5=1
32
W
W
W
W
W
W
W
W
D7
D6
D5
D4
D3
D2
D1
D0
PWMR0~5
ADDRESS : 0EAH
Table 14-1 PWM8L and Sub frame matching table
PWM control Register 1
RESET VALUE : 0000 0000b
RW
RW
RW
RW
RW
RW
RW
RW
EN5
EN4 EN3 EN2
EN1
EN0 EN8 CNTB
PWMCR1
EN5,4,3,2,1 : R47,45,43,42,41,40
0: R4x acts normal digital port
1: R4x acts PWM output port
Main PWM Frame
14bit Counter enable
0: Counter run
1: Counter stop
0
1
2
61 62 63
.....
ADDRESS : 0EBH
RESET VALUE : --0- 00--b
PWM control Register 2
RW
RW
RW
Sub PWM Frame
BUZS
POL2 POL1
PWMCR2
Sub PWM Frame
which is added
1 clock
8bit PWM Polarity
0: Positive (PWM from Rising edge)
1: Negative (PWM from Rising edge)
1 clock width : PS2
Figure 14-4 8bit PWM Registers
Figure 14-5 Wave form example for 14bit PWM
48
N ovem ber 2001 ver 1.2
HMS81C43xx / GMS87C4060
5. PWM output is enabled during EN8 bit contains 1.
ADDRESS : 0E8H
RESET VALUE : Undefined
6. CNTB controls PWM counter enable.
If CNTB=0, Counter is enabled.
PWM Width Data Register
RW
RW
RW
D7
RW
D6
RW
D5
RW
D4
RW
D3
RW
PWM8H
D2
D1
D0
ADDRESS : 0E9H
PWM Sub-pulse count Register
RESET VALUE : Undefined
RW
D5
RW
D4
RW
D3
RW
RW
RW
D2
D1
D0
PWM8L
ADDRESS : 0EAH
PWM control Register 1
RESET VALUE : 0000 0000b
RW
RW
RW
RW
RW
RW
RW
RW
EN5
EN4
EN3
EN1
EN0
EN8 CNTB
EN2
PWMCR1
14bit PWM enable
0: R51
1: PWM8
14bit Counter enable
0: Counter run
1: Counter stop
ADDRESS : 0EBH
RESET VALUE : --0- 00--b
RW
PWM control Register 2
RW
RW
POL2 POL1
BUZS
PWMCR2
14bit PWM Polarity
0: Positive (PWM from Rising edge)
1: Negative (PWM from Rising edge)
Figure 14-6 14bit PWM Registers
November 2001 ver 1.2
49
HMS81C43xx / GMS87C4060
15. Interrupt interval measurement circuit
The Interrupt interval measurement circuit is shown in Fig-
ure 15-1 .
tor, 8bit counter, measured result storing register, FIFO
(9bit, 6level) interrupt, Control register, etc.
The Interrupt interval measurement circuit consists of the
input multiplexer, sampling clock multiplexer, Edge detec-
The more details about registers are shown Figure 15-2 .
FCLR IMS
I34H I34L
ISEL IDCK IDST
DPOL
FOE FFUL FEMP
IDCR [F9H]
PS8
IDFS [FAH]
1
MUX
0
8bit counter
PS9
Clear
Overflow
8
4
INTV
INT3
1
MUX
Edge detector
0
FCLR
INT4
MUX
0
FIFO
(9bit, 6level)
1
D7
D6
D5
D4
D3
D2
D1
D0
IDR [FBH]
Figure 15-1 Block Diagram of Interrupt interval measurement circuit
edge is detected. After data was written, timer is cleard au-
tomatically and it counts continue.
Control
The HMS81C43xx/GMS87C4060 contains a Interrupt in-
terval measurement module.
. You can select interrupt occuring point by set Interrupt
5
Mode Select bit (IMS), every edge what you selected or
FIFO 4 level is filled.
1. Select interrupt input pin what you want to measure by
set the FUNC1 [00CE ].
H
6. If input signal’s interval is larger than maximum counter
2. Set IDCR [00F9 ] : FIFO clear, interrupt mode, inter-
rupt edge select, external interrupt select between INT3
and INT4, sampling clock select.
H
value (0FF ), counter occurring an interrupt and count
H
again from 00 .
H
7. See Figure 15-4 FIFO operating mechanism.
3. Set IDCR [00F9 ] : set IDST to start measuring.
H
4. Counter value is stored to IDR [00FB ] when selected
H
50
N ovem ber 2001 ver 1.2
HMS81C43xx / GMS87C4060
Interrupt interval determination
control Register
ADDRESS : 00F9H
RESET VALUE : 0000 -000b
RW
RW
RW
RW
RW
RW
RW
FCLR IMS
I34H I34L
ISEL IDCK IDST
IDCR
Interrupt input
Counter control
0: stop
See Figure 15-3
1: Clear & count
Int. occuring time
0: Every selected
edge by I34H/L
1: Every FIFO 4level
is filled
Sampling clock select
0: PS9
1: PS8
is filled
FIFO clear
0: Ignored
External Interrupt select
0: INT3
Detecting
edge
1: Clear and return to 0
1: INT4
Item
Symbol I34H
I34L
Interrupt interval determination
ADDRESS : 00FAH
FIFO status Register
RESET VALUE : 1--- -001b
Rising
edge
1
0
0
1
R
R
R
R
DPOL
FOE FFUL FEMP
Frame Cycle
IDFS
Falling
edge
FIFO Empty flag
0: Data filled
1: Empty
Data polarity
0: Data is stored every Falling edge
1: Data is stored every Rising edge
1
1
1
1
Both edge
Both edge
FIFO Full flag
0: Not full
1: Full
FIFO overrun error flag
0: No Error
1: Error detected
Pulse width
Interrupt interval determination
FIFO Data Register
ADDRESS : 00FBH
Figure 15-3 Setting for measurement
RESET VALUE : Undefined
R
R
R
R
R
R
R
R
IDR
D7
D6
D5
D4
D3
D2
D1
D0
ADDRESS : 00CEH
RESET VALUE : -000 0000b
Port function select Register 1
W
W
W
W
W
W
W
EC3S EC2S INT4S INT3S INT2S INT1S INT0S
FUNC1
R26/INT4
0: R26
R24/INT3
0: R24
1: INT4
1: INT3
Figure 15-2 Int. interval measurement Registers
1) FIFO storing mechanism
FEMP=1, FFUL=0
FEMP=0, FFUL=0
FEMP=0, FFUL=0
Data 1
FEMP=0, FFUL=1
Data 1
FEMP=0, FFUL=1
Data 1
Data 1
Data 2
Data 3
Data 2
Data 2
Data 3
Data 4
Data 5
Data 4
Data 5
Data 6
Data 7
Data in
Data in
Data in
Data in
Data 6 will be erased.
FOE=1 (Over run error)
2) FIFO reading mechanism
Read out
Read out
FEMP=0
Data 2
FEMP=1
FEMP=0
Data 1
Data 2
Figure 15-4 Example for FIFO operating mechanism
November 2001 ver 1.2
51
HMS81C43xx / GMS87C4060
16. Buzzer driver
The Buzzer driver circuit is shown in Figure 16-1 .
register controls source clock and output frequency.
The more details about registers are shown Figure 16-2 .
The Buzzer driver circuit consists of the 6bit counter, 6bit
comparator, Buzzer data register BUR(00EE ). The BUR
H
BUR write
BUCK BUCK
BU5 BU4
BU3
BU2
BU1 BU0
BUR [EEH]
-1
-0
6
BUZZ
6bit Comparator
Output
Generator
clear
PS4
6
00
PS5
PS6
PS7
6bit counter
01
10
11
clear
MUX
BUZS
POL2 POL1 EN7
EN6
PWMCR2 [EBH]
Figure 16-1 Block Diagram of Buzzer driver circuit
Control
3. Set BUZS bit for output enable.
The HMS81C43xx/GMS87C4060 contains a Buzzer driv-
er module.
4. Output waveform is rectagle clock which has 50% duty.
5. You can use this clock for the other purposes.
1. Select an input clock among PS4~7 by set the
BUCK1~0 of BUR.
ADDRESS : 0EEH
RESET VALUE : ???? ????b
Buzzer data Register
BUCK1
BUCK0
Clock source
PS4
W
W
W
W
W
W
W
W
BUCK BUCK
-1 -0
BU5 BU4 BU3
BU2
BU1 BU0
BUR
0
0
1
1
0
1
0
1
Input select
Clock Select
PS5
PS6
ADDRESS : 0EBH
RESET VALUE : --0- 00--b
RW
PWM control Register 2
RW
BUZS
RW
PS7
POL2 POL1
PWMCR2
R50/Buzz select
0: R50
1: Buzz output
2. Select output frequency by change the BU5~0.
Output frequency = 1 / (PSx * BUy *2) Hz.
x=4~7, y=5~0
See example Table 16-1 and Table 16-2.
Figure 16-2 Buzzer driver Registers
Note: Do not select 00 to BU5~0. It means counter stop.
H
N ovem ber 2001 ver 1.2
52
HMS81C43xx / GMS87C4060
BUR5~0
Output frequency (KHz)
PS5 PS6
62.5
BUR5~0
Output frequency (KHz)
Dec Hex
PS4
PS7
31.25
Dec Hex
PS4
PS5
PS6
PS7
1
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
250
125
125
62.5
1
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
375
187.5
125
93.75
75
62.5
187.5
93.75
46.875
23.438
15.625
11.719
9.375
7.813
6.696
5.895
5.208
4.688
4.261
3.906
3.606
3.348
3.125
2.930
2.757
2.604
2.467
2.344
2.232
2.131
2.038
1.953
1.875
1.803
1.736
1.674
1.616
1.563
1.512
1.465
1.420
1.379
1.339
1.302
1.267
1.234
1.202
1.172
1.143
1.116
1.09
2
31.25
20.833
15.625
12.5
10.461
8.928
7.813
6.944
6.25
15.625
10.436
7.813
6.25
2
93.75
62.5
46.875
31.35
23.436
18.75
15.625
13.393
11.719
10.417
9.375
8.523
7.813
7.211
6.696
6.25
3
83.333
62.5
42.666
31.25
25
20.888
17.858
15.625
13.888
12.5
11.364
10.417
9.615
8.929
8.333
7.813
7.353
6.944
6.579
6.25
3
4
4
46.875
37.5
5
50
5
6
41.666
35.714
31.25
27.728
25
5.208
4.464
3.907
3.472
3.125
2.841
2.604
2.404
2.242
2.083
1.953
1.838
1.736
1.644
1.562
1.438
1.420
1.359
1.302
1.25
1.202
1.158
1.116
1.078
1.042
1.008
0.976
0.947
0.919
0.893
0.868
0.845
0.822
0.801
0.781
0.762
0.744
0.727
0.710
0.694
0.679
0.665
0.651
0.638
0.625
0.613
0.601
0.590
0.579
0.568
0.558
0.548
0.539
0.530
0.521
0.512
0.504
0.496
6
31.25
26.786
23.436
20.833
18.75
17.045
15.625
14.423
13.393
12.5
7
7
53.572
46.875
41.666
37.5
34.09
31.25
28.846
26.786
25
23.436
22.058
20.833
19.736
18.75
17.858
17.045
16.304
15.625
15
14.424
13.888
13.393
12.932
12.5
12.096
11.718
11.364
11.03
10.714
10.416
10.136
9.868
9.616
9.375
9.146
8.929
8.72
8.523
8.334
8.152
7.978
7.813
7.654
7.5
7.352
7.212
7.076
6.944
6.818
6.696
6.578
6.466
6.356
6.25
8
8
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
22.728
20.834
19.23
17.858
16.666
15.626
14.706
13.888
13.158
12.5
11.904
11.364
10.87
10.416
10
9.616
9.26
5.682
5.209
4.808
4.484
4.166
3.906
3.676
3.472
3.289
3.125
2.976
2.841
2.718
2.604
2.5
2.404
2.315
2.232
2.155
2.084
2.016
1.953
1.894
1.838
1.786
1.736
1.689
1.645
1.602
1.563
1.524
1.488
1.453
1.421
1.389
1.359
1.33
11.719
11.029
10.417
9.868
9.375
8.929
8.523
8.152
7.813
7.5
7.212
6.944
6.696
6.466
6.25
6.048
5.859
5.682
5.515
5.357
5.208
5.068
4.934
4.808
4.688
4.573
4.464
4.36
5.859
5.515
5.208
4.934
4.688
4.464
4.261
4.076
3.906
3.75
3.606
3.472
3.348
3.233
3.125
3.024
2.930
2.841
2.757
2.679
2.604
2.534
2.467
2.404
2.344
2.287
2.232
2.18
5.952
5.682
5.435
5.208
5
4.808
4.63
8.928
8.62
4.464
4.31
8.334
8.064
7.812
7.576
7.352
7.124
6.944
6.756
6.578
6.41
4.167
4.032
3.906
3.788
3.676
3.571
3.472
3.378
3.289
3.205
3.125
3.049
2.976
2.907
2.841
2.778
2.717
2.66
6.25
6.098
5.952
5.814
5.682
5.556
5.434
5.32
4.261
4.167
4.076
3.989
3.906
3.827
3.75
3.676
3.606
3.538
3.472
3.409
3.348
3.289
3.233
3.178
3.125
3.074
3.024
2.976
2.131
2.083
2.038
1.995
1.953
1.913
1.875
1.838
1.802
1.769
1.736
1.705
1.674
1.645
1.616
1.589
1.563
1.537
1.512
1.488
1.065
1.042
1.019
0.997
0.977
0.957
0.938
0.919
0.901
0.884
0.868
0.852
0.837
0.822
0.808
0.795
0.781
0.768
0.756
0.744
5.208
5.102
5
4.902
4.808
4.716
4.63
4.546
4.464
4.386
4.31
4.238
4.166
4.098
4.032
3.968
2.604
2.551
2.5
1.302
1.276
1.25
2.451
2.404
2.358
2.315
2.273
2.232
2.193
2.155
2.119
2.083
2.049
2.016
1.984
1.225
1.202
1.179
1.157
1.136
1.116
1.096
1.078
1.059
1.042
1.025
1.008
0.992
6.148
6.048
5.952
Table 16-1 . Example for f =8MHz
Table 16-2 . Example for f =12MHz
ex
ex
November 2001 ver 1.2
53
HMS81C43xx / GMS87C4060
17. On Screen Display (OSD)
The On Screen Display circuit is shown in Figure 17-1 .
The OSD circuit consists of the Position attribute register,
Line register, Full screen screen control register, sprite
control register, sprite position reigster, I/O polarity regis-
ter, sprite RAM, font ROM, VRAM, etc. The more details
about registers are shown Figure 17-2.
The HMS81C43xx/GMS87C4060 can support 512 OSD
chacters, but the last 6 characters (number 506 ~ 511,
1FA ~ 1FF ) are reserved for IC test and its pattern is
H
H
fixed by manufacturer. So you can use 506 characters for
your own.
Line 1,2 Attribute,
Position register
Full screen control
register
Line register
Sprite control register
OSDCON2 [AE1H]
Sprite position register I/O polarity register
L1ATTR [AF0H]
L1VPOS [AF1H]
OSDLN [AE5H]
OSDCON1 [AE0H]
SPVPOS [AE8H]
SPHPOS [AE9H]
OSDPOL [AE2H]
Horizontal position register
LHPOS [AE6H]
Field detection register
FDWSET [AE3H]
L2ATTR [AF3H]
L2VPOS [AF4H]
Color Mode Register
COLMOD [0AEFH]
Edge color register
EDGECOL [AE4H]
Mesh Control Register
MESHCON [0AEBH]
OSD Control
Circuit
Sprite Control
Circuit
VRAM
Sprite RAM
Font ROM
R
G
Output
Control
Circuit
B
Sprite Control
Circuit
OSD, Sprite Generation Circuit
I
YS
YM
HSYNC
VSYNC
OSC1
Synchronization
Circuit
OSC2
Figure 17-1 Block Diagram of On Screen Display circuit
N ovem ber 2001 ver 1.2
54
HMS81C43xx / GMS87C4060
Character(foreground)
- 16 color with half intensity
- Color selecting: VRAM n-character bit19~16(see VRAM)
Background
- 16 color with half intensity
- Color selecting :VRAM n-character bit23-20(see VRAM)
Characte(foreground) Outline
- Controled by LnATTR register(see LnATTR)
- 16 color with half intensity
- Color selecting : EDGECOL register(see EDGECOL)
Character Shadow
- Controlled by LnATTR register(see LnATTR) and
VRAM n-character bit11-10(see VRAM)
- Color selecting : EDGECOL(see EDGECOL)
- 16 color with half intensity
Background Shadow
- Controlled by VRAM n-character bit15-12
- Color selecting : EDGECOL register(see EDGECOL)
- 16 color with half intensity
(No Character Outline Case)
Figure 17-2 OSD Character Font Example
November 2001 ver 1.2
55
HMS81C43xx / GMS87C4060
M
0
0
0
0
0
0
0
0
0
0
0
0
0
1
I
B
0
0
1
1
1
1
0
0
0
0
1
1
1
0
G
1
1
0
0
1
1
0
0
1
1
0
0
1
0
R
0
1
0
1
0
1
0
1
0
1
0
1
1
0
Color
GREEN
0
0
0
0
0
0
1
1
1
1
1
1
1
0
ADDRESS : 0AE0H
RESET VALUE : 0000 0000b
Full screen control Register
RED+GREEN
RW
RW
RW
RW
RW
RW
RW
RW
BLUE
FULM FULI FULB FULG FULR DLINE DDCLKSTOCK
OSDCON1
STOP OSD clock
0: Release
1: Stop
BLUE+RED
Full screen background
: Half blank
FULLM
FULLI : Half intensity
: Blue
BLUE+GREEN
Double dot clock mode
0: Normal
1: Double
FULLB
FULLG : Green
: Red
RED+GREEN+BLUE (WHITE)
BLACK
FULLR
Double scan line mode
0: Normal
1: Double
Half intensity RED
Half intensity GREEN
Half intencity RED+GREEN
Half intensity BLUE
Half intensity GREEN+BLUE
Half intensity WHITE
Half BLANK
ADDRESS : 0AE1H
Sprite OSD control Register
RESET VALUE : 0000 0000b
RW
RW
RW
RW
RW
RW
RW
RW
DUSP
CL
PRO OSD
OSDCON2
OBGW ONL2 ONL1 DUSP ENSP
SD
ON
Double sprite
dot clock
(Sprite size)
0: x1, x2
OSD, Sprite
0: All Off
1: All On
OSD line 2
0: Off
1: On
Priority
0: Sprite > OSD
1: OSD > Sprite
1: x2, x4
OSD line 1
0: Off
1: On
Sprite enable
0: Disable
1: Enable
Background width
per 1 character
0: 12dots
Table 17-1 Full Screen Back ground color selection
Sprite size
0: Normal
1: Double
1: 14dots
OSDCON2
bit 0: OSDON
Figure 17-3 OSD Control Registers - 1
OSDCON1
It controls OSD, Sprite, Full screen background at once. It
does not affect anything to Vsync interrupt and OSD inter-
rupt, etc.
bit 0: STOCK
bit 1: PROSD
It controls OSD LC oscillation. If oscillation is stoped,
IC’s power consumption is decreased.
It controls screen output priority between sprite and OSD.
If its value is 1, OSD hide sprite pattern in overapped area.
bit 1: DDCLK
bit 2: ENSP
If you set this bit to 1, OSD input clock is doubled from LC
oscillation. It makes OSD horisontal image size as dou-
bled.
It enables sprite display.
bit 3: DUSP
bit 2: DLINE
It doubles sprite’s horizontal & vertical size during this
value is 1.
If you set this bit to 1, OSD vertical scan counter input
clock is doubled from normal state. It makes OSD vertical
image size as doubled.
bit 4: ONL1
It enables OSD line 1 display. If it is enabled, OSD inter-
rupt is activated.
bit 7~3: FULLM, I, B, G, R
It controls back ground color as below.
bit 5: ONL2
It enables OSD line 2 display. If it is enabled, OSD inter-
rupt is activated.
M
0
I
B
0
0
G
0
R
0
1
Color
Transparent (Normal TV)
RED
0
0
bit 6: OBGW
0
0
It controls character’s width. Default width is 12dots. If its
value is set, 2 dots (background color) are added both left
Table 17-1 Full Screen Back ground color selection
N ovem ber 2001 ver 1.2
56
HMS81C43xx / GMS87C4060
and right side of character.
bit 7: DUSPCL
It controls HS, VS, I, YM, YS, B, G, R port’s polarity. If
its value is 1, polarity is active high.
It controls sprite’s dot clock and scan line speed. It does not
affect to OSD. Sprite size is controlled as below.
FDWSET
FDWSET (Field Detection Window Seting) register de-
tects the begin of VSync(Vertical Sync.) signal and distin-
guishs its current field is Even field or Odd field.
DUSPCL
DUSP
Size
Normal
0
0
1
1
0
1
0
1
12x16
24x32
-
x 2
Not used
x 4
Ex1: VSync(Odd)
Ex2: VSync(Even)
48x64
Table 17-2 Sprite pattern size
FMIN
HSync
FMAX
ADDRESS : 0AE2H
RESET VALUE : Undefined
I/O Polarity ( initial ) Register
W
W
W
W
W
W
W
W
POL POL
HS VS
POL
YM
POL
YS
OSDPOL
POLI
POLB POLG POLR
Figure 17-5 FDWSET detection region
POLHS : Hsync. input
POLVS : Vsync. input
OSD display enable,
include the edge color.
0: Off
The region of FMIN[2:0] ~ FMAX[3:0] is field detection
window.
POLI
: Half intensity output
POLYM : Half blank output
1: On
POLB
POLG
POLR
: Blue output
: Green output
: Red output
FMAX[3:0] can divide the region between HSync(Hori-
zontal Sync.) by 16. You can assume there is 4 bit horizon-
tal counter, for example HCOUNT[3:0] which count 0~15.
0: Active Low
1: Active High
ADDRESS : 0AE3H
Field detection Register
If the start of VSync is detected at the window, next field
is even. Else if VSync is detected another region of the
window, next field is odd.
RESET VALUE : 0111 1010b
W
W
W
W
W
W
W
W
FPOL
FDWSET
FM AX3 ~ 0
FM IN2 ~ 0
Field detection
Maximum pointer
Field detection
Minimum pointer
It means start of VSync is detected during FMIN[2:0] <
HCOUNT[3:0] < FMAX[3:0] and FPOL value is 0, it dis-
tinguish odd field.
Field detection polarity
0: Detect Odd field
Masking range : Min.~Max.
1: Detect Even field
Detecting range : Min.~Max.
And, start of VSync is detected during FMIN[2:0] <
HCOUNT[3:0] < FMAX[3:0] and FPOL value is 1, it dis-
tinguish even field.
FMIN[2:0], FMAX[3:0] are compared with the horizontal
counter in OSD block.
Figure 17-4 OSD Registers - 2
OSDPOL
bit7~0 : POL HS, VS, I, YM, YS, B, G, R
November 2001 ver 1.2
57
HMS81C43xx / GMS87C4060
Figure 17-7 OSD Registers - 4
Background shadow / edge
color Register
ADDRESS : 0AE4H
RESET VALUE : Undefined
L1ATTR
W
W
W
W
W
W
W
W
bit 0 : LIV8
EDG EDG EDG EDG EDG EDG
2I 2B 2G 2R 1I 1B
EDG EDG
EDGECOL
1G
1R
It is equivalent with L1VPOS’s bit 8. See more details in
L1VPOS.
Edge 2 color
Edge 1 color
EDGnI : Half Intensity
EDGnB : Blue
EDGnG : Green
EDGnR : Red
n : 1 ~ 2
bit 1: FSC1
It selects character outline and shadow color. If it is 1, it se-
lect EDGE2 color in EDGECOL register. Or not, it select
EDGE1 color. According to EDGECOL register and this
bit character and shadow colors are selected simulteneous-
ly
ADDRESS : 0AE5H
OSD line Register
OSDLN
RESET VALUE : ---0 0000b
R
R
R
R
R
Current displayed OSD line number
( 00000 ~ 11111b : 0 ~ 63 )
bit 3~2: CSZ11~CSZ10
OSD line horizontal
position Register
ADDRESS : 0AE6H
RESET VALUE : Undefined
It controls OSD character’s size ( x1, x2, x3). You can use
this register and DDCLK, DLINE bit, horizontal / vertical
size can be controlled (x2, x4, x6).
W
W
W
W
W
W
W
W
LHPOS
D6
D5
D4
D3
D2
D1
D0
D7
OSD line’s horizontal position (00 ~ FFH)
bit 4: ENSH1
ADDRESS : 0AE8H
Sprite vertical
RESET VALUE : Undefiend
position Register
It enables line 1’s character(foreground) shadow.
bit 5: ENOL1
W
W
W
W
W
W
W
W
SPVPOS
D6
D5
D4
D3
D2
D1
D0
D7
Sprite’s vertical position (00 ~ FFH)
It enables line 1’s character(foreground) outline.
bit 6: WDSL1
Sprite horisontal
position Register
ADDRESS : 0AE9H
RESET VALUE : Undefined
W
W
W
W
W
W
W
W
SPHPOS
It shows thickness of line 1’s shadow and outline.
D7
D6
D5
D4
D3
D2
D1
D0
Sprite’s horisontal position (00 ~ FFH)
WDSL ENOL
ENSH
outline, shadow
No outline, No shadow
Thin shadow
0
0
0
0
0
1
0
1
0
Figure 17-6 OSD Registers - 3
Thin outline
Thin outline
Thick shadow
0
1
1
ADDRESS : 0AF0H
RESET VALUE : Undefined
OSD line 1’s
1
1
1
0
0
1
0
1
0
No outline, No shadow
Thick shadow
attribute Register
W
W
W
W
W
W
W
W
OBGH WDSL ENOL ENSH CSZ CSZ
11
FSC1 L1V8
L1ATTR
1
1
1
1
10
Vertical position
L1VPOS’s bit8
Character
background
height
0: 16dots
1: 18dots
Thick outline
Character size
00: Normal
01: 2 times
10: 3 times
11: Reserved
Foreground shadow
out line color
0: Edge 1’s color
1: Edge 2’s color
Thick outline
Thick shadow
1
1
1
Shadow / Outline
width
0: 1dot
1: Propotional
to character
size
Character Shodow
Table 17-3 Character Outline, Shadow table
control
0: Disable
1: Enable
charcater outline
control
0: Disable
1: Enable
bit 7: OBGH1
ADDRESS : 0AF1H
RESET VALUE : Undefined
It controls character’s height. Default height is 16dots. If
its value is set, 2 dots (background color) are added both
top and bottom side of character.
OSD line 1’s
vertical position Register
W
W
W
W
W
W
W
W
L1V7 L1V6 L1V5 L1V4 L1V3 L1V2 L1V1 L1V0
L1VPOS
OSD line 1’s vertical position (include L1V8 : 000 ~ 1FFH)
N ovem ber 2001 ver 1.2
58
HMS81C43xx / GMS87C4060
L2VPOS
It shows OSD line 2’s vertical position. Its function is the
same as L1VPOS.
L1VPOS
It shows OSD line 1’s vertical position in 9bit format
(LIV8 + L1VPOS, 000 ~ 1FF ).
COLMOD
H
It controls OSD output mode-RGB direct half intencity.
OSD line 2’s
attribute Register
ADDRESS : 0AF3H
Color Output Mode
Register
ADDRESS : 0AEFH
RESET VALUE : Undifined
(see Note)
RESET VALUE : Undefined
W
W
W
W
W
W
W
W
OBGH WDSL ENOL ENSH CSZ CSZ
21 20
FSC2 L2V8
L2ATTR
W
2
2
2
2
Vertical position
L2VPOS’s bit8
C16EN
Character
background
height
0: 16dots
1: 18dots
COLMOD
Character size
00: Normal
01: 2 times
10: 3 times
11: Reserved
Foreground shadow
out line color
0: Edge 1’s color
1: Edge 2’s color
Fill with ‘0’
RGB Half intensity enable
1: Enable
0: Enable
Shadow / Outline
width
0: 1dot
1: Propotional
to character
size
Shodow control
0: Disable
1: Enable
Out line control
0: Disable
Figure 17-10 OSD Register - 7
bit 0: C16EN
1: Enable
OSD line 2’s
vertical position Register
ADDRESS : 0AF4H
RESET VALUE : Undefined
W
W
W
W
W
W
W
W
It enables RGB port half intencity output. When this bit is
set, RGB port generates half intencity output. Half intenci-
ty output is 3.5V voltage level output of RGB port. When
you use this bit, you must fill all the other bit with ‘0’.
L2V7 L2V6 L2V5 L2V4 L2V3 L2V2 L2V1 L2V0
L2VPOS
OSD line 2’s vertical position (include L2V8 : 000 ~ 1FFH)
Figure 17-8 OSD Registers - 5
Note: When you do not use RGB direct half intncsity out-
OSD line 2’s
attribute Register
put , please initialize this register as 00h.
ADDRESS : 0AF3H
RESET VALUE : Undefined
W
W
W
W
W
W
W
W
OBGH WDSL ENOL ENSH CSZ CSZ
21 20
FSC2 L2V8
L2ATTR
2
2
2
2
MESHCON
Vertical position
L2VPOS’s bit8
Character
background
height
0: 16dots
1: 18dots
Character size
00: Normal
01: 2 times
10: 3 times
11: Reserved
It controls OSD mesh mode color.
Foreground shadow
out line color
0: Edge 1’s color
1: Edge 2’s color
Mesh Mode Color
Register
ADDRESS : 0AEBH
RESET VALUE : See Note
Shadow / Outline
width
Shodow control
0: Disable
1: Enable
0: 1dot
Out line control
0: Disable
1: Propotional
to character
size
MESHCON
1: Enable
OSD line 2’s
vertical position Register
ADDRESS : 0AF4H
RESET VALUE : Undefined
W
W
W
W
W
W
W
W
L2V7 L2V6 L2V5 L2V4 L2V3 L2V2 L2V1 L2V0
L2VPOS
Figure 17-11 OSD Register - 8
OSD line 2’s vertical position (include L2V8 : 000 ~ 1FFH)
Note: Please initialize this register as 00h. Though this
register is for mesh mode color, it is not used currently.
Figure 17-9 OSD Register - 6
VRAM
L2ATTR
VRAM contains 1 OSD line, 24 character’s attributes.
It controls OSD line 2’s attributes. Its function is the same
as L1ATTR.
Each character’s attribute is constructed with 3 bytes, it
contains color data for background, shadow, outline, char-
acter and character number ( 000 ~ 1FF , 512 characters
H
H
November 2001 ver 1.2
59
HMS81C43xx / GMS87C4060
), etc.
Bit No.
Name
Function
Select color of left and top side
BSCUL shadow of the background
0: Edge1, 1: Edge2 color
Line Character
Address (bit 23~0)
10
No.
No.
Hexa decimal
1
A40
A41
A42
:
A20
A21
A22
:
A00
A01
A02
:
9
ENRND Enable character’s rounding
2
Character font number
CG8~0
8~0
( among 000 ~ 1FF
)
H
3
1
:
Table 17-5 VRAM (bit15~0) function
22
23
24
1
A55
A56
A57
AC0
AC1
AC2
:
A35
A36
A37
AA0
AA1
AA2
:
A15
A16
A17
A80
A81
A82
:
Note: if (BSL = 1) & (BSCUL = 0) & (LnATTR,ENSHn = 1),
then the right bottom shadow of font character is shifted to
1 dot right side. This shadow effect will continue until that
(BSR) of adjacent character attribution become (BSR = 1).
2
3
Bit No. &
Name
Output ( Polarity :
Through)
2
:
Character
color
19 18 17 16
22
23
24
AD5
AD6
AD7
AB5
AB6
AB7
A95
A96
A97
Y
M
Y
I
B
G
R
I
B
G
R
S
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
Clear
Red
Table 17-4 VRAM memory map
Green
Yellow
Blue
Bit No.
Name
Function
Magenta
Cyan
Enable right side background
shadow.
cf
. If BSL=1 and BSCUL=1 and
LnATTR.ENSHn=1, character’s
right bottom shadow is shifted to
right side by 1dot unit.
It acts continued until current
character’s right side chacter’s
BSR is set to 1.
White
15
BSR
Black
Half-I,Red
Half-I,Green
Enable left side background
shadow.
Half-I,
Yellow
14
13
12
BSL
BSD
BSU
1
1
1
0
1
1
1
0
0
1
0
1
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
1
0
1
Enable bottom side background
shadow.
Half-I,Blue
Half-I,
Magenta
Enable top side background
shadow.
1
1
1
1
1
1
0
1
0
0
1
1
0
0
1
1
1
1
0
1
Half-I,Cyan
Half-I,White
Select color of right and bottom
side shadow of the background
0: Edge1, 1: Edge2 color
11
BSCDR
Table 17-6 VRAM (bit19~16) function
Table 17-5 VRAM (bit15~0) function
N ovem ber 2001 ver 1.2
60
HMS81C43xx / GMS87C4060
this memory can not be accessed by user program.
Bit No. &
Name
Address range
Charact
Output ( Polarity :
Through)
er code
Back
ground
color
Upper 4bit
Lower 8bit
23 22 21 20
000
001
002
:
12000 ~ 1200F
10000 ~ 1000F
H
H
H
H
H
H
H
H
H
H
H
Y
M
Y
I
B
G
R
I
B
G
R
12010 ~ 1201F
10010 ~ 1001F
S
0
1
1
1
1
1
1
1
H
H
12020 ~ 1202F
10020 ~ 1002F
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Clear
Red
H
H
:
:
Green
Yellow
Blue
(12000H + xyz0H) ~ (10000H + xyz0H) ~
xyz
:
H
(12000H + xyzFH)
(10000H + xyzFH)
:
:
1FD
13FD0 ~ 13FDF
11FD0 ~ 11FDF
H
H
H
H
H
H
H
H
H
H
H
Magenta
Cyan
1FE
13FE0 ~ 13FEF
11FE0 ~ 11FEF
H
H
1FF
13FF0 ~ 13FFF
11FF0 ~ 11FFF
H
H
White
Half
blanking
Table 17-8 Font ROM memory map
1
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
1
0
0
0
0
0
1
1
1
1
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
5. A character’s address and dot position in font ROM is
described in Figure 17-12 .
Half-I,Green
Half-I,
Yellow
Half-I,Blue
Address Data
Address Data
Half-I,
Magenta
MSB
LSB
12530H 00H
12531H 07H
12532H 08H
08H
12534H 08H
09H
10530H 00H
10531H FEH
10532H 01H
1
1
1
1
1
1
0
1
1
1
0
1
0
0
0
1
1
1
1
1
0
1
1
1
0
1
1
1
0
1
Half-I,Cyan
Half-I,White
Black
61H
10534H F1H
F9H
10535H
12533H
10533H
12535H
12536H 0BH
12537H 08H
12538H 08H
12539H 08H
1253AH 08H
1253BH 08H
1253CH 08H
1253DH 08H
1253EH 07H
1253FH 00H
10536H FDH
10537H 61H
10538H 61H
10539H 61H
1053AH 61H
1053BH 61H
1053CH 61H
1053DH 01H
1053EH FEH
1053FH 00H
Table 17-7 VRAM (bit 23 ~ 20) function
Font ROM
The HMS81C43xx/GMS87C4060 OSD character size is
fixed as 12dots (Horisontal) * 16dots (Vertical).
1. Each horisontal data (12dots) needs 2byte ROM.
2. One character is constructed with 16 horisontal data to
vertically. As a result, one character needs 32bytes (2 * 16
bytes).
Figure 17-12 Example for a character (53 )
H
Sprite RAM
3. HMS81C4332/GMS87C4060 contains 256/512 charac-
ters.
The HMS81C43xx/GMS87C4060 contains a 32bytes
(12dot * 16dot) sprite RAM.
Total Font ROM memory size is calulated as 16,384bytes
( 32bytes / character * 512 character )
1. In view point, sprite is similar to character font but it is
not using font ROM.
4. Font ROM memory is located from 10000 ~ 13FFF ,
H
H
2. You can selct color by dot unit.
3. Using above 1 and 2, you can make any of patterns what
you want by software. For example, arrow cursor or some-
November 2001 ver 1.2
61
HMS81C43xx / GMS87C4060
thing.
4. Sprite position is controlled by sprite position register
B
0
0
0
0
1
1
1
1
G
0
0
1
1
0
0
1
1
R
0
1
0
1
0
1
0
1
Color
Clear
Red
SPVPOS[0AE8 ] and SPHPOS[0AE9 ].
H
H
5. Sprite RAM is located 0C00~0CF5 . One sprite RAM
H
byte contains 2 dot’s color data. See more details in Table
17-9 ~ Table 17-11.
Green
Yellow
Blue
Row number
Column
number
MSB
~
~
~
~
~
LSB
Black
Cyan
White
00
01
02
:
0C05
0C00
H
H
H
H
H
0C15
0C25
:
0C10
0C20
:
H
H
H
H
Table 17-11 Sprite RAM Color Table
0n
(n=0~F)
H
0Cn5
0Cn0
~
H
H
Test Font
HMS81C43xx use first OSD font as test purpose(see
Fig17-13). When you design OSD characte font, you incert
following font to Font ROM 00h. If you like to use this font
originally, please contact us
:
:
~
~
~
:
0E
0C05
0C05
0C00
0C00
H
H
H
H
H
0F
H
Table 17-9 Sprite RAM address map
MSB
LSB
address data
address data
1200H
1201H
1202H
1203H
1204H
1205H
1206H
1207H
1208H
1209H
120AH
120BH
120CH
120DH
120EH
120FH
00H
00H
00H
01H
03H
07H
06H
06H
06H
06H
06H
06H
07H
03H
01H
00H
1000H
1001H
1002H
1003H
1004H
1005H
1006H
1007H
1008H
1009H
100AH
100BH
100CH
100DH
100EH
100FH
00H
00H
00H
F8H
FCH
0EH
06H
06H
06H
06H
06H
06H
0EH
FCH
F8H
00H
Odd dot color
Even dot color
bit No.
7
6
5
4
3
2
1
0
Function
-
B
G
R
-
B
G
R
Table 17-10 A sprite RAM’s contents
Figure 17-13 Test Font Pattern
N ovem ber 2001 ver 1.2
62
HMS81C43xx / GMS87C4060
2
18. I C Bus Interface
2
2
The I C Bus interface circuit is shown in Figure 18-1 .
This multi-master I C Bus interface circuit consists of the
2
2
2
I C address register, the I C data shift register, the I C
clock control register, the I C control register, the I C sta-
tus register and other control circuits.
2
The multi-master I C Bus interface is a serial communica-
tions circuit, conforming to the Phlips I C Bus data trans-
fer format. This interface, offering both arbitration lost
detection and a synchronous functions, is useful for the
multi-master serial communications.
2
2
2
The more details about registers are shown Figure 18-2 ~
Figure 18-6 .
SAD6 SDA5 SDA4 SDA3 SDA2 SDA1 SDA0 R/W
ICAR [D8H]
Address
comparator
Interrupt
IFI2CR
Generation
Circuit
D7
D6
D5
D4
D3
D2
D1
D0
ICDR [D9H]
SDA
Data
Control
Circuit
Noise
Elimination
Circuit
MST TRX
BB
PIN
AL
AAS AD0
LRB
ICSR [00DAH]
BB
Circuit
AL
Circuit
ALS
ESO
BSEL1~0
BC 2~0
ICCR1 [00DBH]
SCL
Clock
Control
Circuit
Bit counter
ACLK ACK
1
CCR3~0
ICCR2 [DCH]
Noise
Elimination
Circuit
External clock
Clock division
2
Figure 18-1 Block Diagram of multi-master I C circuit
Control
ITEM
Function
2
The HMS81C43xx/GMS87C4060 contains two I C Bus
interface modules. It supports multi-master function, so it
contains arbitration lost detection, synchronization func-
tion,etc.
66.6KHz ~ 500KHz (f =12MHz)
SCL clock
frequency
ex
44.4KHz ~ 333.3KHz (f =8MHz)
ex
2
I C address register
It contains slave address (7bit) which is used during slave
mode and Read/Write bit.
ITEM
Function
2
Philips I C standard
7bit addressing format
Format
Bit 7 ~ 0 : Slave address 6~0
Master transmitter
Communication Master receiver
Note: Bit 7~0 (SAD6~0) store slave address. The address
data transmitted from the master is compared with the con-
tents of these bits.
mode
Slave transmitter
Slave receiver
November 2001 ver 1.2
63
HMS81C43xx / GMS87C4060
The more details about its bits are shown Table 18-1.
ADDRESS : 00D8H
RESET VALUE : 0000 0000b
Bit
No.
Name
Function
RW
RW
RW
RW
RW
RW
RW
R
SDA5 SDA4 SDA3 SDA2 SDA1 SDA0 R/W
SAD6
ICAR
00: Slave / Receiver mode
01: Slave / Transmitter mode
10: Master / Receiver mode
11: Master / Transmitter mode
MST is cleared when
Slave address
2
Figure 18-2 I C address Register
- After reset.
- After the arbitration lost is occured and
1 byte data transmission is finished.
2
7
6
MST - After stop condition is detected.
I C data shift register [ICDR]
TRX
- When start condition is disabled by
start condition duplication preventation
function.
2
The I C data shift register is an 8bit shift register to store
received data and write transmit data.
TRX is cleared when
- After reset.
- When arbitration lost or stop condition
is occured .
- When MST is ‘0’, and start condition
or ACK non-return mode is detected.
When transmit data is written into this register, it is trans-
fered to the outside from bit7 in synchronization with the
SCL clock, and each time one-bit data is output, the data of
this register are shifted one bit to the left. When data is re-
ceived, it is input to this register from bit0 in synchroniza-
tion with the SCL clock, and each time one-bit data is
input, the data of this register are shifted one bit to the left.
BB(Bus busy)bit is 1 during bus is busy.
This bit can be written by S/W. its value
is ‘1’ by start condition, and cleared by
stop condition.
5
BB
2
The I C data shift register is in a write enable status only
2
when the ESO bit of the I C control register (address
PIN(Pending Interrupt Not)bit is inter-
rupt request bit.
00DC ) is “1”. The bit counter is reset by a write instruc-
H
2
tion to the I C data shift register. Reading data from the
2
2
If I C interrupt request is issued, its
I C data shift register is always enabled regardless of the
value is 0.
ESO bit value.
PIN is cleared when
- After 1 byte trasmission / receive is fin-
ished.
PIN is set when
- After reset.
ADDRESS : 00D9H
RESET VALUE : 0000 0000b
RW
RW
RW
D7
RW
D6
RW
D5
RW
D4
RW
D3
RW
4
PIN
D2
D1
D0
ICDR
Shift left 1-bit each SCL
- After write instruction is excuted into
2
I C data shift register ICDR.
- When PIN bit low, the output of SCL is
pulled down, So if you want to release
SCL, you must perform write instruction
CDR.
Figure 18-3 Data shift register
2
I C status register
2
2
The I C status register controls the I C Bus interface sta-
tus. The low-order 4bits are read only bits and the high-or-
der 4bits can be read out and written to.
Arbitration lost detection flag.
If arbitration lost is detected, AL=1, or 0.
3
2
AL
Slave address comparison flag.
It shows compared result with received
2
AAS
address data and I C address register
(ICAR).
It is 1, when two of data is same.
Table 18-1 Bit function
N ovem ber 2001 ver 1.2
64
HMS81C43xx / GMS87C4060
Bit
No.
Name
Function
ADDRESS : 00DBH
RESET VALUE : 00-0 0000b
General call detection flag.
If general call is detected, AD0=1, or
not 0.
RW
RW
RW
RW
RW
RW
RW
BSEL BSEL
1
ALS ESO BC2 BC1
BC0
ICCR1
0
1
0
AD0
* General call : If received address is all
‘0’ . it is called general call.
2
Figure 18-5 I C control Register 1
Last received bit.
it is used for receive confirmation. If
ACK is returned, LRB=0, or not 1.
LRB
2
I C control register 2
Table 18-1 Bit function
It controls SCL mode, SCL frequency, etc.
It contains 8bit data to transmit to external device when tr-
asmitter mode, or received 8bit data from external device
when receive mode.
ADDRESS : 00DAH
RESET VALUE : 0001 0000b
RW
R
R
R
RW
RW
BB
RW
PIN
R
MST TRX
AL
AAS
AD0 LRB
ICSR
Bit
No.
2
Name
ACLK
ACK
Function
Figure 18-4 I C status Register
Select acknowledge clock (ACK) mode.
0: No acknowledge clock mode.
acknowledge clock is not generated
after data was transmismitted.
1: acknowledge clock mode.
2
I C control register 1
It controls communication data format.
7
acknowledge clock is generated after
data was transmismitted.
Bit
No.
Name
Function
If acknowledge clock is returned, this bit
is 0. Or not 1.
6
5
2
I C connection control.
00: No connection
01: SCL1, SDA1
10: SCL2, SDA2
1
7
6
BSEL1
BSEL0
Not used.
(fixed)
11: SCL1, SDA1, SCL2, SDA2
Table 18-3 Bit function
Data format selection.
0: Addressing format
1: Free data format
4
3
ALS
2
I C Bus interface use enable flag
ESO
0: Disabled
1: Enabled
2
1
0
BC2
BC1
BC0
Bit counter.
000 : 8bit
b
001 ~111 : 1~7bit
b
b
Table 18-2 Bit function
November 2001 ver 1.2
65
HMS81C43xx / GMS87C4060
Figure 18-7 Interrupt request signal generation timing
Bit
No.
Name
Function
SCL Frequency selection
SCL frequency = f / (12 * CCR)
ex
START condition generation
f
= 12MHz
f
= 8MHz
ex
Value
ex
2
When the ESO bit of the I C control register (00DB ) is
H
2
“1”, writing to the I C status register will generate START
condition. Refer to Figure 18-8 for the START condition
generation timing diagram.
0000 Not allowed
0001 Not allowed
0010 500.0KHz
0011 333.3KHz
0100 250.0KHz
0101 200.0KHz
0110 166.6KHz
0111 142.9KHz
1000 125.0KHz
1001 111.1KHz
1010 100.0KHz
1011 90.0KHz
1100 83.3KHz
1101 76.4KHz
1110 71.4KHz
1111 66.6KHz
Not allowed
Not allowed
333.3KHz
222.2KHz
166.6KHz
133.3KHz
111.1KHz
95.2KHz
83.3KHz
74.1KHz
66.6KHz
60.6KHz
55.5KHz
51.3KHz
47.6KHz
44.4KHz
3
2
1
0
CCR3
CCR2
CCR1
CCR0
ICSR write signal
(I2C status reg.)
SCL
tSETUP
tHOLD
SDA
tBB
BB (Bus busy) flag
Table 18-3 Bit function
tSETUP : Setup time
tHOLD : Hold time
tBB
: Set time for BB
ADDRESS : 00DCH
RESET VALUE : 000- 0000b
Figure 18-8 START condition generation timing
RESTART condition generation
RW
ACLK
RW
RW
RW
RW
RW
ACK
1
CCR2
CCR3
CCR1 CCR0
ICCR2
2
Figure 18-6 I C control Register 2
RESTART condition’s setting sequence is as followings.
2
1. Write 020 to I C status register (ICSR, 00DA )
H
H
2
2. Write slave address to I C data shift register (ICDR,
00D9 )
SCL
PIN
H
2
3. Write 0F0 to I C status register (ICSR, 00DA )
H
H
I2C Request
STOP condition generation
Writing ‘C0h’ to ICSR will generate a stop condition,
N ovem ber 2001 ver 1.2
66
HMS81C43xx / GMS87C4060
w h e n E S O ( I C C R b i t 3 ) i s ‘ 1 ’
START / STOP condition detect
ICSR write signal
(I2C status reg.)
START / STOP condition is detected when Table 18-4 is
satisfied.
SCL
tSETUP
tHOLD
SDA
tBB
SCL release time
BB (Bus busy) flag
SCL
tSETUP
tHOLD
tSETUP : Setup time
tHOLD : Hold time
SDA (START)
SDA (STOP)
tBB
: Set time for BB
tSETUP : Setup time
tHOLD : Hold time
Figure 18-9 STOP condition generating timing diagram
START / STOP condition generation time is shown Table
18-4.
Figure 18-10 START / STOP condition detection timing
START / STOP detection time is showed Table 18-5.
ITEM
Timing SPEC.
Setup time
ITEM
SCL release time
Setup time
Timing SPEC.
3.3uS (n=20cycles)
( t
)
SETUP
> 2.0uS (n=12cycles)
> 1.0uS (n=6cycles)
> 1.0uS (n=6cycles)
Hold time
( t
3.3uS (n=20cycles)
3.0uS (n=18cycles)
)
HOLD
Set/Reset time for
BB flag ( t
Hold time
)
BB
Table 18-5 Example time ( f =12MHz )
ex
Table 18-4 Example time ( f =12MHz )
ex
November 2001 ver 1.2
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HMS81C43xx / GMS87C4060
Address data communication
not compared but it determines next data operation. i.e,
transmitting or receiving data
The first transmitted data from master is compared with
2
I C address register (ICAR, 00D8 ). At this time R/W is
H
Master -> Slave (with 7bit address)
ACK
/ACK
ACK
START Slave addr.
7bit
ACK Data
Data
STOP
R/W
(“0”)
Slave -> Master (with 7bit address)
Data block from master to slave
Data block from slave to master
ACK
START Slave addr.
7bit
ACK Data
Data
STOP
ACK
R/W
(“1”)
Figure 18-11 Address data communication format
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HMS81C43xx / GMS87C4060
19. INTERRUPTS
The HMS81C43xx/GMS87C4060 interrupt circuits con-
sist of Interrupt enable register (IENH, IENL), Interrupt re-
quest flags of IRQH, IRQL, Priority circuit and Master
enable flag ("I" flag of PSW). 16 interrupt sources are pro-
vided. The configuration of interrupt circuit is shown in
Figure 19-2 .
Interrupt Mode Register
It controls interrupt priority. It takes only one specified in-
terrupt.
Of course, interrupt’s priority is fixed by H/W, but some-
times user want to get specified interrupt even if higher
priority interrupt was occured. Higher priority interrupt is
processed the next time.
Below table shows the Interrupt priority
It contains 2bit data to enable priority selection and 4bit
data to select specified interrupt.
Reset/Interrupt
Hardware Reset
External Interrupt 0
OSD Interrupt
Symbol
Priority
RESET
INT0
OSD
-
1
2
Bit No. Name
Value
Function
External Interrupt 1
External Interrupt 2
Timer/Counter 0
Timer/Counter 2
1 Frame Interrupt
VSync Interrupt
INT1
INT2
3
4
5
6
7
8
9
10
11
12
13
14
15
00
01
1X
Mode 0: H/W priority
Mode 1: S/W priority
Interrupt is disabled, even
if IE is set.
5,4
IM1~0
Timer 0
Timer 2
1Frame
VSync
Timer 1
Timer 3
INTV(INT3/4)
WDT
0000 INT0
0001 OSD
0010 INT1
0011 INT2
0100 Timer 0
0101 Timer 2
0110 1Frame
0111 VSync
1000 Timer 1
1001 Timer 3
1010 INTV(INT3/4)
1011 WDT
1100 BIT
Timer/Counter 1
Timer/Counter 3
Interrupt interval measure
Watchdog Timer
Basic Interval Timer
Serial I/O Interrupt
BIT
SIO
I2C
3~0
IP3~0
2
I C Interrupt
The External Interrupts can each be transition-activated (1-
to-0 or 0-to-1 transition).
When an external interrupt is generated, the flag that gen-
erated it is cleared by the hardware when the service rou-
tine is vectored to only if the interrupt was transition-
activated.
1101 SIO
1110 I2C
1111 Not used
Table 19-1 Bit function
The Timer/Counter Interrupts are generated by
TnIF(n=0~3), which is set by a match in their respective
timer/counter register.
ADDRESS : 00F3H
RESET VALUE : Undefined
The Basic Interval Timer Interrupt is generated by BITIF
which are set by a overflow in the timer register.
RW
IM1
RW
IM0
RW
IP3
RW
RW
RW
IP1
IP2
IP0
IMOD
The interrupts are controlled by the interrupt master enable
flag I-flag (bit 2 of PSW), the interrupt enable register
(IENH, IENL) and the interrupt request flags (in
IRQH,IRQL) except Power-on reset and software BRK in-
terrupt.
Figure 19-1 Interrupt Mode Register
November 2001 ver 1.2
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HMS81C43xx / GMS87C4060
Internal bus line
Interrupt Enable
Register (Higher byte)
IMOD [00F3H]
Bit5
IENH [00F6H]
IRQH
[0F7H]
INT0
IFOSD
INT1
INT0
OSD
RESET
BRK
INT1
INT2
T0
INT2
Timer 0
To CPU
Timer 2
1 Frame
IFVSync
T2
1Frame
VSync
I Flag
T1
T3
Timer 1
Timer 3
Interrupt Master
Enable Flag
I-flag is in PSW, it is cleared by "DI", set by
"EI" instruction. W hen it goes interrupt service,
INTV
WDT
BIT
Intr. interval
I-flag is cleared by hardware, thus any other
interrupt are inhibited. When interrupt service is
completed by "RETI" instruction, I-flag is set to
"1" by hardware.
IFWDT
IFBIT
SR
IFS
I2C
Interrupt
Vector
Address
Generator
IFI2C
IRQL
[00F5H]
Interrupt Enable
Register (Lower byte)
IENL [00F4H]
Internal bus line
Figure 19-2 Block Diagram of Interrupt
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HMS81C43xx / GMS87C4060
Interrupt enable registers are shown in Figure 19-4 . These
registers are composed of interrupt enable flags of each in-
terrupt source, these flags determines whether an interrupt
will be accepted or not. When enable flag is "0", a corre-
sponding interrupt source is prohibited. Note that PSW
contains also a master enable bit, I-flag, which disables all
interrupts at once.
R/W R/W R/W R/W R/W R/W R/W R/W
ADDRESS: 00F7H
INITIAL VALUE: 0000 0000b
INT1
T2 1Frame
INT2
T0
INT0 OSD
MSB
VSync
LSB
IRQH
VSync interrupt request flag
1 Frame interrupt request flag
Timer / Counter 2 interrupt request flag
Timer / Counter 0 interrupt request flag
External interrupt 2 interrupt request flag
External interrupt 1 interrupt request flag
On screen display interrupt request flag
External interrupt 0 interrupt request flag
R/W R/W R/W R/W
T1 T3
MSB
R/W R/W R/W
BIT SR I2C
ADDRESS: 00F5H
INITIAL VALUE: 0000 000-b
IRQL
INTV WDT
LSB
I2C interrupt request flag
Serial I/O interrupt request flag
Basic interval timer interrupt request flag
Watch-dog timer interrupt request flag
Interrupt interval measurement interrupt request flag (INT3/4)
Timer / Counter 3 interrupt request flag
Timer / Counter 1 interrupt request flag
Figure 19-3 Interrupt Request Flags
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HMS81C43xx / GMS87C4060
R/W R/W R/W R/W R/W R/W R/W R/W
INT1 T2 1Frame
ADDRESS: 00F6H
INITIAL VALUE: 0000 0000b
INT2
T0
INT0 OSD
MSB
VSync
LSB
IENH
VSync interrupt enable flag
1Frame interrupt enable flag
Timer / Counter 2 interrupt enable flag
Timer / Counter 0 interrupt enable flag
External interrupt 2 interrupt enable flag
External interrupt 1 interrupt enable flag
On screen display interrupt enable flag
External interrupt 0 interrupt enable flag
R/W R/W R/W R/W
T1 T3
MSB
R/W R/W R/W
BIT SR I2C
ADDRESS: 00F4H
INITIAL VALUE: 0000 000-b
IENL
INTV WDT
LSB
I2C interrupt enable flag
Serial I/O interrupt enable flag
Basic interval timer interrupt enable flag
Watch-dog timer interrupt enable flag
Interrupt interval measurement interrupt enable flag (INT3/4)
Timer / Counter 3 interrupt enable flag
Timer / Counter 1 interrupt enable flag
Figure 19-4 Interrupt Enable Flags
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HMS81C43xx / GMS87C4060
19.1 Interrupt Sequence
An interrupt request is held until the interrupt is accepted
or the interrupt latch is cleared to "0" by a reset or an in-
2. Interrupt request flag for the interrupt source accepted
is cleared to "0".
struction. Interrupt acceptance sequence requires 8 f (2
ex
3. The contents of the program counter (return address)
and the program status word are saved (pushed) onto
the stack area. The stack pointer decrements 3 times.
µs at f
=4MHz) after the completion of the current in-
MAIN
struction execution. The interrupt service task terminates
upon execution of an interrupt return instruction [RETI].
4. The entry address of the interrupt service program is
read from the vector table address, and the entry ad-
dress is loaded to the program counter.
Interrupt acceptance
5. The instruction stored at the entry address of the inter-
rupt service program is executed.
1. The interrupt master enable flag (I-flag) is cleared to
"0" to temporarily disable the acceptance of any fol-
lowing maskable interrupts. When a non-maskable in-
terrupt is accepted, the acceptance of any following
interrupts is temporarily disabled.
System clock
Instruction Fetch
SP-2
PSW
V.L.
V.H.
New PC
OP code
SP
SP-1
PC
Address Bus
Data Bus
Not used
V.L.
ADL
ADH
PCH
PCL
Internal Read
Internal Write
Interrupt Processing Step
Interrupt Service Task
V.L. and V.H. are vector addresses.
ADL and ADH are start addresses of interrupt service routine as vector contents.
Figure 19-5 Interrupt Service routine Entering Timing
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HMS81C43xx / GMS87C4060
General-purpose register save/restore using push and pop
instructions;
Basic Interval Timer
Vector Table Address
Entry Address
012H
0E3H
0FFE6H
0FFE7H
0EH
2EH
0E312H
0E313H
main task
acceptance of
interrupt
interrupt
service task
saving
registers
Correspondence between vector table address for BIT interrupt
and the entry address of the interrupt service program.
restoring
registers
A maskable interrupt is not accepted until the I-flag is set
to "1" even if a maskable interrupt of higher priority than
that of the current interrupt being serviced.
interrupt return
When nested interrupt service is necessary, the I-flag is set
to "1" in the interrupt service program. In this case, accept-
able interrupt sources are selectively enabled by the indi-
vidual interrupt enable flags.
19.2 BRK Interrupt
Software interrupt can be invoked by BRK instruction,
which is the lowest priority order.
Interrupt vector address of BRK is shared with the vector
of TCALL 0 (Refer to Program Memory Section). When
BRK interrupt is generated, B-flag of PSW is set to distin-
guish BRK from TCALL 0.
Saving/Restoring General-purpose Register
During interrupt acceptance processing, the program
counter and the program status word are automatically
saved on the stack, but not the accumulator and other reg-
isters. These registers are saved by the program if neces-
sary. Also, when nesting multiple interrupt services, it is
necessary to avoid using the same data memory area for
saving registers.
Each processing step is determined by B-flag as shown in
Figure 19-6 .
=0
The following method is used to save/restore the general-
purpose registers.
B-FLAG
=1
BRK or
TCALL0
BRK
INTERRUPT
ROUTINE
Example: Register save using push and pop instructions
TCALL0
ROUTINE
INTxx: PUSH
A
;SAVE ACC.
;SAVE X REG.
;SAVE DPGR
; Direct page
; accessable reg.
;
PUSH
LDA
X
RETI
RET
DPGR
PUSH
A
:
interrupt processing
:
Figure 19-6 Execution of BRK/TCALL0
POP
STA
POP
POP
RETI
A
DPGR
;RESTORE DPGR
;RESTORE X REG.
;RESTORE ACC.
;RETURN
X
A
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HMS81C43xx / GMS87C4060
19.3 Multi Interrupt
If two requests of different priority levels are received si-
multaneously, the request of higher priority level is ser-
viced. If requests of the same priority level are received
simultaneously, an internal polling sequence determines
by hardware which request is serviced.
However, multiple processing through software for special
features is possible. Generally when an interrupt is accept-
ed, the I-flag is cleared to disable any further interrupt. But
as user set I-flag in interrupt routine, some further interrupt
can be serviced even if certain interrupt is in progress.
Example: Even though Timer1 interrupt is in progress,
INT0 interrupt serviced without any suspend.
Main Program
service
TIMER 1
service
TIMER1: PUSH
A
PUSH
PUSH
LDM
LDM
EI
X
INT0
service
Y
IENH,#80H
IENL,#0
;Enable INT0 only
;Disable other
;Enable Interrupt
enable INT0
disable other
EI
:
:
:
Occur
Occur
INT0
TIMER1 interrupt
:
:
:
enable INT0
enable other
LDM
LDM
POP
POP
POP
RETI
IENH,#FFH
;Enable all interrupts
IENL,#FEH
Y
X
A
In this example, the INT0 interrupt can be serviced without any
pending, even TIMER1 is in progress.
Because of re-setting the interrupt enable registers IENH,IENL
and master enable "EI" in the TIMER1 routine.
Figure 19-7 Execution of Multi Interrupt
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HMS81C43xx / GMS87C4060
19.4 External Interrupt
The external interrupt on INT0, INT1... pins are edge trig-
gered depending the edge selection register.
INT0, INT1 and INT2 are multiplexed with general I/O
ports. To use external interrupt pin, the bit of port function
register FUNC1 should be set to "1" correspondingly.
Refer to “6. PORT STRUCTURES” on page 10.
The edge detection of external interrupt has three transition
activated mode: rising edge, falling edge, both edge.
Response Time
The INT0, INT1 and INT2 edge are latched into INT0IF,
INT1IF and INT2IF at every machine cycle. The values
are not actually polled by the circuitry until the next ma-
chine cycle. If a request is active and conditions are right
for it to be acknowledged, a hardware subroutine call to the
requested service routine will be the next instruction to be
executed. For example, the DIV instruction takes twelve
machine cycles. Thus, a minimum of twelve complete ma-
chine cycles elapse between activation of an external inter-
rupt request and the beginning of execution of the first
instruction of the service routine
INT0 pin
INT1 pin
INT0IF
INT1IF
INT0 INTERRUPT
INT1 INTERRUPT
INT2 pin
INT2IF
INT2 INTERRUPT
IEDS
[00F2H]
Figure 19-8 External Interrupt Block Diagram
System clock
Instruction Fetch
Last instruction execution (0~12cycle)
Interrupt request sampling
Enter interrupt service routine (8cycle)
1cycle
Interrupt overhaed (9~21cycle)
Figure 19-9 Interrupt Response Timing Diagram ( Interrupt overhead )
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HMS81C43xx / GMS87C4060
20. WATCHDOG TIMER
The watchdog timer rapidly detects the CPU malfunction
such as endless looping caused by noise or the like, and re-
sumes the CPU to the normal state.
When the watchdog timer is not being used for malfunc-
tion detection, it can be used as a timer to generate an in-
terrupt at fixed intervals.
The watchdog timer signal for detecting malfunction can
be selected either a reset CPU or a interrupt request.
6-bit up-counter
Clock source
WDT
(BIT overflow : IFBIT)
clear
comparator
IFWDT
Watchdog Timer interrupt
6-bit compare data
6
to reset CPU
enable
WDTCL[bit6]
WDTR[bit5~0]
WDTON[bit5]
CKCTLR
WDTR
Watchdog Timer Register
Clock control Register
[00D7H]
[00D6H]
Figure 20-1 Block Diagram of Watchdog Timer
Watchdog Timer Control
ADDRESS : 00D6H
Figure 20-2 shows the watchdog timer control register.
The watchdog timer is automatically disabled after reset.
RESET VALUE : 0000 0000b
W
W
W
W
W
R
WDT ENP
BTCL BTS2 BTS1 BTS0
CKTCLR
ON
CK
The CPU malfunction is detected as setting the detection
time, selecting output, and clearing the binary counter. Re-
peatedly clearing the binary counter within the setting de-
tection time.
Watchdog timer On/Off control
0: Normal 6bit timer, Watchdog off
1: Watchdog timer
ADDRESS : 00D7H
RESET VALUE : -011 1111b
If the malfunction occurs for any cause, the watchdog tim-
er output will become active at the rising overflow from
the binary counters unless the binary counter are cleared.
At this time, when WDTON=1 a reset is generated, which
drives the RESET pin low to reset the internal hardware.
When WDTON=0, a watchdog timer interrupt (IFWDT) is
generated.
W
W
W
W
W
W
W
WDT
CL
WDTR
Slave address
Watchdog timer Clear
0: Watchdog timer free run
1: Watchdog timer clear and free run
Automatically cleared this bit after 1cycle
Figure 20-2 Watchdog timer register
November 2001 ver 1.2
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HMS81C43xx / GMS87C4060
Example: Sets the watchdog timer detection time
LDM WDTR,#01??????b
;Clear Counter and set value(??????b)
;You have to set WDTR first, for prevent unpredictable interrupt
;when you set WDTON bit.
LDM CKCTLR,#00111???b
;Select clock source(???b) and WDTON=1
LDM WDTR,#01??????b
;Clear counter
;Clear counter
;Clear counter
Within WDT
detection time
:
:
:
:
LDM WDTR,#01??????b
Within WDT
detection time
:
:
:
:
LDM WDTR,#01??????b
Enable and Disable Watchdog
Watchdog timer is enabled by setting WDTON (bit 5 in
CKTCLR) to "1". WDTON is initialized to "0" during re-
set, WDTON should be set to "1" to operate after reset is
released.
Example: 6-bit timer interrupt setting up.
LDX
TXSP
LDM
LDM
:
#03FH
;SP← 3F
CKTCLR,#000?????b ;WDTON←0
WDTR,#01??????b ;WDTCL←0
Example: Enables watchdog timer reset
:
:
LDM
:
CKTCLR,#001?????b ;WDTON←1
Refer table and see BIT timer ().
:
Watchdog
timer input IFWDT cycle
clock
CKCTLR
BTS2~0
BIT input
clock
The watchdog timer is disabled by clearing bit 5 (WD-
TON) of CKTCLR.
000
PS4 (2uS)
PS5 (4uS)
512uS
1,024uS
2,048uS
4,096uS
8,192uS
16,384uS
32,768uS
65,536uS
32,256uS
64,512uS
b
001
b
Watchdog Timer Interrupt
010
PS6 (8uS)
129,024uS
258,048uS
516,096uS
1,032,192uS
2,064,384uS
4,128,768uS
b
The watchdog timer can also be used as a simple 6-bit tim-
er by clearing bit 5 (WDTON) of CKTCLR. The interval
of watchdog timer interrupt is decided by Basic Interval
Timer.
011
PS7 (16uS)
PS8 (32uS)
PS9 (64uS)
PS10 (128uS)
PS11 (256uS)
b
100
b
101
b
Interval equation is shown as below.
110
b
=
×
111
b
Table 20-1 Watchdog timer MAX. cycle (Ex:f =8MHz)
ex
The stack pointer (SP) should be initialized before using
the watchdog timer output as an interrupt source.
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HMS81C43xx / GMS87C4060
Source clock
BIT overflow
3
3
0
2
0
1
2
1
Binary-counter
Counter
Clear
3
n
WDTR
Match
Detect
IFWDT interrupt
WDTR ← "0100_0011b"
WDT reset
reset
Figure 20-3 Watchdog timer Timing
Minimizing Current Consumption
that if unspecified voltage, i.e. if unfirmed voltage level is
applied to input pin, there can be little current (max. 1mA
at around 2V) flow.
It should be set properly that current flow through port
doesn't exist.
If it is not appropriate to set as an input mode, then set to
output mode considering there is no current flow. Setting
to High or Low is decided considering its relationship with
external circuit. For example, if there is external pull-up re-
sistor then it is set to output mode, i.e. to High, and if there
is external pull-down register, it is set to low. See Figure
20-4 .
First conseider the setting to input mode. Be sure that there
is no current flow after considering its relationship with
external circuit. In input mode, the pin impedance viewing
from external MCU is very high that the current doesn’t
flow.
But input voltage level should be V or V . Be careful
SS
DD
November 2001 ver 1.2
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HMS81C43xx / GMS87C4060
OUTPUT PIN
ON
INPUT PIN
VDD
VDD
ON
internal
pull-up
OPEN
VDD
OFF
O
OFF
O
i
i
VDD
GND
VDD
GND
ON
X
X
OFF
OPEN
Weak pull-up current flows
O
O
In the left case, much current flows from port to GND.
VDD
INPUT PIN
OUTPUT PIN
VDD
VDD
L
i=0
L
ON
OFF
ON
OPEN
O
i
i=0
OFF
i
GND
GND
Very weak current flows
i=0
GND
X
X
O
In the left case, Tr. base current flows from port to GND.
To avoid power consumption, low output to the port .
O
When port is configured as an input, input level should
be closed to 0V or 5V to avoid power consumption.
Figure 20-4 Application example of Port under Power Consumption
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HMS81C43xx / GMS87C4060
21. OSCILLATOR CIRCUIT
The HMS81C43xx/GMS87C4060 has two oscillation cir-
for OSD(On Screen display) frequency, respectively, of a
inverting amplifier which can be configured for use as an
on-chip oscillator, as shown in Figure 21-1 .
cuits internally. X and X
are input and output for
OUT
IN
main frequency and OSC1 and OSC2 are input and output
Recommend
C1
C1 & C2 (pF)
fc (MHz)
XOUT
4
6
30
5
C2
fc (MHz)
XIN
8
VSS
Crystal Oscillator
Recommend
fc (MHz) C1 & C2 (pF)
C1
C2
For selection L,C value,
you have to tune the
frequency to appropriate
range which is dependent
to your target set.
L (uH)
100
OSC2
L1
5
20
10
5
8
12
15
15
15
OSC1
VSS
16
20
LC Oscillator
Open
XOUT
XIN
External Clock
External Oscillator
Figure 21-1 Oscillation Circuit
Oscillation components have their own characteristics, so
user should consult the component manufacturers for ap-
propriate values of external components.
In addition, see Figure 21-2 for the layout of the crystal.
Note: Minimize the wiring length. Do not allow wiring to in-
tersect with other signal conductors. Do not allow wiring to
come near changing high current. Set the potential of the
grounding position of the oscillator capacitor to that of VSS.
Do not ground to any ground pattern where high current is
present. Do not fetch signals from the oscillator.
XOUT
XIN
Figure 21-2 Layout example of Oscillator PCB circuit
November 2001 ver 1.2
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HMS81C43xx / GMS87C4060
22. RESET
The HMS81C43xx/GMS87C4060 have two types of reset
generation procedures; one is an external reset input, other
is a watch-dog timer reset. Table 22-1 shows on-chip hard-
ware initialization by reset action.
On-chip Hardware
Initial Value
On-chip Hardware
Peripheral clock
Initial Value
(FFFF ) - (FFFE )
Program counter
PC
DPGR
G
Off
Disable
H
H
00
H
RAM page register
G-flag of PSW
Watchdog timer
Control registers
0
Refer to Table 8-1 on page 22
Table 22-1 Initializing Internal Status by Reset Action
22.1 External Reset Input
The reset input is the RESET pin, which is the input to a
Schmitt Trigger. A reset in accomplished by holding the
RESET pin low for at least 8 oscillator periods, within the
operating voltage range and oscillation stable, a reset is ap-
plied and the internal state is initialized. After reset, 64ms
(at 4 MHz) add with 7 oscillator periods are required to
start execution as shown in Figure 22-2 .
A connecting for simple power-on-reset is shown in Figure
22-1 .
VDD
RESET
Internal RAM is not affected by reset. When V is turned
DD
+
on, the RAM content is indeterminate. Therefore, this
RAM should be initialized before reading or testing it.
−
MCU
GND
When the RESET pin input goes high, the reset operation
is released and the program execution starts at the vector
address stored at addresses FFFE - FFFF .
H
H
Figure 22-1 Simple Power-on-Reset Circuit
1
2
3
4
5
6
7
Oscillator
(XIN pin)
RESET
Fetch
ADDRESS
BUS
FFFE FFFF Start
?
?
?
?
?
?
DATA
BUS
OP
ADH
?
?
FE
ADL
MAIN PROGRAM
RESET Process Step
1
Stabilization Time
tST = 62.5mS at 4.19MHz
tST
=
x 256
fMAIN ÷1024
Figure 22-2 Timing Diagram after RESET
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HMS81C43xx / GMS87C4060
22.2 Watchdog Timer Reset
Refer to “20. WATCHDOG TIMER” on page 77.
November 2001 ver 1.2
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HMS81C43xx / GMS87C4060
23. OTP Programming
23.1 GMS87C4060 OTP Programming
You can burn out GMS87C4060 OTP through the general
Gang programmer using Intel 27010/C010 mode. In Dev-
leopment tool package auxiliary, GMS87C4060-to-27010/
C010 conversion socket is included. GMS87C4060 have
two ROM memory areas. One is Program ROM memory
and the other is Font ROM memory. Program ROM area is
from 1000h to FFFFh Font ROM area is from 10000h to
13FFFh. When you acquire new OTP, actually, the OTP is
not fully blank. The OPT have six test pattern in the OSD
Font ROM memory(see figure23-1). The test pattern are
written at 11FA0h ~ 11FFFh and 13FA0h ~ 13FFFh.
file(***.OTP) and the other is font OTP file(***.FNT).
You can make each file through ASMLINKER.exe and
OSDFONT.exe respectively. All OTP file is Motolora S-
format. You can burn the program file and font file respec-
tively or together. To burn program file and font file re-
spectively, refer following procedure
1. Make program OTP file and font OTP file repec-
tively.
2. Check whether six test pattern is included in font
OTP file(see below Six Text Pattern)
3. Burn program OTP file(Set chip target address
1000h ~ FFFFh)
Note: DO NOT write any data in this area(11FA0h ~
11FFFh, 13FA0h ~ 13FFFh)
4. Burn font OTP file(Set chip target address 10000h
~13FFFh)
Blank Check
If you run blank check function of ROM writer, ROM
writer inform blank error because of test pattern. To avoid
this situation, you must run the blank check function sep-
eretely. For example, check OTP address rage of 1000h ~
11F9Fh at first. And then check OPT address range of
12000h ~ 13F9Fh. If you have ROM writer without partial
blank check function, please do not run blank check func-
tion.
Note: When you program the OTP file, DO NOT check the
blank. Because there are already written data(Six test pat-
tern / 11FA0h ~ 11FFFh, 13FA0h~13FFFh) It will occur
blank error
To burn program file and font file together, refer following
procedure
1. Add program OTP file and font OTP file
1000H
2. Check whether six test pattern is included in font
OTP file(see below Six Text Pattern)
3. Burn OTP file(Set chip target address 1000h ~
13FFFh)
Program
Memory
About other details, refer ROM wirter manual.
Six Test Pattern
FFFFH
OSD Font
Memory
When you make font file through OSDFONT.exe, please
confirm whether six test pattern is included or not in char-
acter address 1FAh ~ 1FFh, To include six test patern, refer
following procedure.
13FFFH
1. Make Font file and save it to your PC
2. Reopen the font file and save it to your HDD once
again.
Figure 23-1 GMS87C4060 OTP Memory Map
Program Writing
3. Then six test pattern will be included automatically.
(Character address 1FAh ~ 1FFh)
There are two kind of OTP file. One is program OTP
N ovem ber 2001 ver 1.2
84
HMS81C43xx / GMS87C4060
23.2 .Device configuration data
A15
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
1
2
3
4
5
6
7
8
CEB
A14
A13
A12
A11
A10
A9
A8
A7
A6
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
PGMB
OEB
GND
VCC
VPP
A5
A4
A3
A2
A1
A0
O7
O6
O5
O4
O0
O1
O2
O3
A16
Figure 23-2 Figure Pin Configuration in OTP Programming Mode
GMS87C4060
Intel 27010
Mode
Program
Verify
VPP
CEB
Low
Low
OEB
High*2
Low
PGMB
Low*1
High
VPP
CEB
OEB
High
Low
PGMB
Low
12.75V
12.75V
12.75V
12.75V
Low
Low
High
Optional
Ver ify
5V
Low
Low
Low
Low
High
Low
X
Low
X
5V
Low
Low
Low
Low
High
Low
X
Low
X
Gang
12.75V
12.75V
12.75V
Write *3
Gang
12.75V,
5V
Verify *4
Figure 23-3 Figure Mode Table
November 2001 ver 1.2
85
HMS81C43xx / GMS87C4060
*1: Low = Input Low Voltage = V (<0.8V)
*4: In Gang Verify mode, the VPP pin can be sset to both
normal high(5V), aand 12.75V and chip slecection is pos-
sible using the CEB pin
IL
*2: High = Input High Value = VIL(>2.0V)
*3: In Gang Write Mode, All OTPs are programmed sim-
ulaneously. So all signals of OTPs are in the same condi-
tion
SYMBOL
Parameter
Address Setup Time
OEB Setup Time
Data Setup Time
Address Hold Time
Data Hold Time
OEB High to Output Float Delay
Vpp Setup Time
CEB Setup Time
PGMB initial program pulse width
Limits
Typ Max
Conditions
Min
2
2
2
0
2
0
2
2
Unit
µs
µs
µs
µs
µs
ns
µs
µs
µs
tAS
tOES
tDS
tAH
tDH
tDFP
tVPS
tCES
tPW
130
105
Note1
95
100
Quick pulse
programming
tOE
tACC
tOH
Data Valid from OEB
100
150
0
ns
ns
ns
Address to output delay
output hold from addresses CEB or
OEB whichever occurrs first
CEB to output delay
0
tCE
tCS
100
100
ns
ns
chip selection interval
(@Gang verify)
*Note1: Output Float is defined as the point where data is no longer driven
Figure 23-4 Figure AC Programming Characteristics
N ovem ber 2001 ver 1.2
86
HMS81C43xx / GMS87C4060
Intel 27010
GMS87C4060
Pin Name
VPP
A16
A15
A12
A7
Pin Number
Pin Name
TEST_N
R67
R27
R24
R17
R16
R15
R14
R13
R12
R11
R10
R00
R01
R02
VSS
R03
R04
R05
R06
R07
R41
R22
R53
R23
R21
R20
R25
R26
Pin Number
1
2
3
4
5
6
7
8
38
26
1
4
9
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
O3
O4
O5
O6
O7
10
15
16
17
18
19
20
29
28
27
12, 40
25
24
23
22
21
51
6
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CEB
A10
OEB
A11
A9
41
5
7
8
3
A8
A13
A14
N.C.
PGMB
VCC
2
R52
VDD
42
39
Figure 23-5 Pin Mapping Table between Intel 27010/C010 and GMS87C4060
November 2001 ver 1.2
87
HMS81C43xx / GMS87C4060
Pin Name
RESET_N
Xout
Xin
R
G
B
R56
R55
R54
OSC2
OSC1
R47
Pin Number
Connect to
GND
Not Connect
GND
Not Connect
Not Connect
Not Connect
Not Connect
Not Connect
Not Connect
Not Connect
GND
11
13
14
30
31
32
33
34
35
36
37
45
46
47
48
49
50
52
44
43
GND
GND
GND
GND
R46
R45
R44
R43
R42
R40
R50
R51
Not Connect
Not Connect
GND
VDD
VDD
Figure 23-6 Connection of Other Pins of GMS87C4060 in OTP Mode
23.3 Timing Chart
Program
Address Stable
Verify
Optinal Verify
Address Valid
VIH
Address
VIL
tAS
tAH
VIH
High Z
Valid ouput
Data in Stable
tDH
Data out Valid
Data
VIL
tDFP
tDS
12.5V
tVPS
VPP
5V
VIH
Don’t care
Don’t care
CEB
VIL
tCES
VIH
PGMB
Don’t care
tOE
VIL
tOES
tOE
tPW
VIH
OEB
VIL
Figure 23-7 Figure Programming Timing Chart
N ovem ber 2001 ver 1.2
88
HMS81C43xx / GMS87C4060
Optinal Verify
VIH
VIL
VIH
Address
Address Stable
.....
Data
Data
Data
(n-1)th OTP
Data
OEB
VIL
VIH
0th OTP
1st OTP
VIL
tACC
VIH
VIL
CEB[0]
tCS
tACC
VIH
VIL
CEB[1]
tACC
VIH
VIL
CEB[n-1]
1) When you verify the data in the same address of many OTPs.
When you select OTPs using CEB, and can verify the data inthe same address.
(PGMB : Don’t care , Vpp : VIH or 12.5V )
VIH
OEB
VIL
tACC
VIH
CEB[0]
tCS
VIL
tACC
VIH
CEB[1]
VIL
tACC
VIH
CEB[n-1]
VIL
VIH
OEB
VIL
tACC
VIH
CEB[0]
VIL
VIH
Addr1
tACC
Addr2
tACC
Addr0
tACC
Data0
Addr3
tACC
Address
Data
VIL
VIH
VIL
Data3
Data1
Data2
2) When you verify the data in s single OTP throughout the ROM address
Figure 23-8 AC Wave Form in Gang Verify Mode
November 2001 ver 1.2
89
HMS81C43xx / GMS87C4060
24. Assemble mnemonics
24.1 Instruction Map
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
SET1
dp.bit
BBS
A.bit,rel
BBS
dp.bit,rel
ADC
#imm
ADC
dp
ADC
dp+X
ADC
!abs
ASL
A
ASL TCALL
BIT
dp
POP PUSH
SETA1
.bit
000
001
NOP
BRK
dp
0
A
A
SBC
#imm
SBC
dp
SBC
!abs
ROL
A
ROL TCALL CLRA1 COM
POP
BRA
rel
SBC
dp+X
PUSH
//
//
//
//
//
//
CLRC
X
dp
2
.bit
dp
X
CMP
#imm
CMP
dp
CMP
dp+X
CMP
!abs
LSR
A
LSR TCALL NOT1 TST
POP PUSH PCALL
010 CLRG
dp
4
M.bit
dp
Y
Y
Upage
OR1
OR
#imm
OR
dp
OR
dp+X
OR
!abs
ROR
A
ROR TCALL
POP PUSH
CMPX
dp
//
//
//
//
//
//
//
//
//
011
100
101
DI
RET
dp
6
PSW
PSW
OR1B
AND1
AND
#imm
AND
dp
AND
dp+X
AND
!abs
INC
A
INC TCALL
CMPY CBNE
INC
X
CLRV
SETC
TXSP
dp
8
dp
dp+X
AND1B
EOR1
EOR
#imm
EOR
dp
EOR
dp+X
EOR
!abs
DEC
A
DEC TCALL
DBNE XMA
DEC
X
TSPX
dp
10
dp
dp+X
EOR1B
LDC
LDA
#imm
LDA
dp
LDA
dp+X
LDA
!abs
LDY TCALL
LDX
dp
LDX
dp+Y
//
//
//
//
//
//
110
111
SETG
EI
TXA
TAX
XCN
XAS
DAS
dp
12
LDCB
LDM
dp,#imm
STA
dp
STA
dp+X
STA
!abs
STY TCALL STC
STX
dp
STX
dp+Y
dp
14
M.bit
10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
BPL
rel
CLR1 BBC
BBC
dp.bit,rel
ADC
{X}
ADC
!abs+Y
ADC
[dp+X]
ADC
[dp]+Y
ASL
!abs
ASL TCALL
BIT ADDW LDX
JMP
[!abs]
JMP
!abs
000
001
010
011
100
101
110
111
dp.bit
A.bit,rel
dp+X
1
!abs
dp
#imm
BVC
rel
SBC
{X}
SBC
!abs+Y
SBC
[dp]+Y
ROL
!abs
ROL TCALL CALL TEST SUBW
JMP
[dp]
SBC
[dp+X]
LDY
//
//
//
//
//
//
//
//
//
#imm
dp+X
3
!abs
!abs
dp
BCC
rel
CMP
{X}
CMP
!abs+Y
CMP
[dp+X]
CMP
[dp]+Y
LSR
!abs
LSR TCALL
TCLR1 CMPW CMPX CALL
//
//
//
//
//
//
//
//
//
//
//
//
MUL
dp+X
5
!abs
dp
#imm
[dp]
BNE
rel
OR
{X}
OR
!abs+Y
OR
[dp+X]
OR
[dp]+Y
ROR
!abs
ROR TCALL DBNE
LDYA CMPY
CMPX
RETI
!abs
dp+X
7
Y
dp
#imm
BMI
rel
AND
{X}
AND
!abs+Y
AND
[dp+X]
AND
[dp]+Y
INC
!abs
INC TCALL
CMPY INCW
INC
DIV
TAY
TYA
DAA
NOP
dp+X
9
!abs
dp
Y
BVS
rel
EOR
{X}
EOR
!abs+Y
EOR
[dp+X]
EOR
[dp]+Y
DEC
!abs
DEC TCALL XMA
XMA DECW DEC
dp+X
11
{X}
dp
dp
Y
BCS
rel
LDA
{X}
LDA
!abs+Y
LDA
[dp+X]
LDA
[dp]+Y
LDY
!abs
LDY TCALL LDA
LDX STYA
XAY
dp+X
13
{X}+
!abs
dp
BEQ
rel
STA
{X}
STA
!abs+Y
STA
[dp+X]
STA
[dp]+Y
STY
!abs
STY TCALL STA
STX CBNE
XYX
dp+X
15
{X}+
!abs
dp
N ovem ber 2001 ver 1.2
90
HMS81C43xx / GMS87C4060
24.2 Alphabetic order table of instruction
OP
BYTE
NO.
CYCLE
NO
FLAG
NO.
MNENONIC
ADC #imm
OPERATION
CODE
NVGBHIZC
1
04
05
06
07
15
16
17
14
1D
84
85
86
87
95
96
97
94
8B
8B
08
09
19
18
y2
y3
x2
x3
2
2
2
3
3
2
2
1
2
2
2
2
3
3
2
2
1
3
3
1
2
2
3
2
3
2
3
2
3
Add with carry.
2
ADC dp
A ← A + (M) + C
3
ADC dp + X
ADC !abs
4
4
4
NV - - H - ZC
5
ADC !abs+Y
ADC [dp+X]
ADC [dp]+Y
ADC {X}
5
6
6
7
6
8
3
9
ADDW dp
AND #imm
AND dp
5
16-bits add without carry : YA ← YA + (dp+1)(dp)
NV - - H - ZC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
2
Logical AND
3
A ← A ^ (M)
AND dp + X
AND !abs
4
4
N - - - - - Z -
AND !abs+Y
AND [dp+X]
AND [dp] + Y
AND {X}
5
6
6
3
AND1 M.bit
AND1B M.bit
4
Bit AND C-flag : C ← C ^ (M.bit)
Bit AND C-flag and NOT : C ← C ^ ~(M.bit)
Arithmetic shift left
- - - - - - - C
- - - - - - - C
4
ASL
A
2
ASL dp
4
C
7 6 5 4 3 2 1 0
← ← ← ← ← ← ← ← ← ← "0"
N - - - - - ZC
- - - - - - - -
ASL dp + X
ASL !abs
5
5
BBC A.bit,rel
BBC dp.bit,rel
BBS A.bit,rel
BBS dp.bit,rel
4/6
5/7
4/6
5/7
Branch if bit clear :
if(bit) = 0, then PC ← PC + rel
Branch if bit clear :
- - - - - - - -
if(bit) = 1, then PC ← PC + rel
Branch if carry bit clear :
if(C) = 0, then PC ← PC + rel
28
BCC rel
50
2
2/4
MM - - - - Z -
29
30
31
32
33
34
35
36
37
BCS rel
BEQ rel
BIT dp
BIT !abs
BMI rel
BNE rel
BPL rel
BRA rel
BRK
D0
F0
0C
1C
90
70
10
2F
0F
2
2
2
3
2
2
2
2
1
2/4
2/4
4
Branch if carry bit set : If (C) =1, then PC ← PC + rel
Branch if equal : if (Z) = 1, then PC ← PC + rel
Bit test A with memory :
- - - - - - - -
- - - - - - - -
MM - - - - Z -
Z ← A ^ M, N ← (M7), V ← (M6)
5
2/4
2/4
2/4
4
Branch if munus : if (N) = 1, then PC ← PC + rel
Branch if not equal : if (Z) = 0, then PC ← PC + rel
Branch if not minus : if (N) = 0, then PC ← PC + rel
Branch always : PC ← PC + rel
- - - - - - - -
- - - - - - - -
- - - - - - - -
- - - - - - - -
8
Software interrupt:
B ← “1”, M(SP) ← (PCH), SP ← SP - 1,
M(s) ← (PCL), SP ← S - 1, M(SP) ← PSW,
SP ← SP - 1, PCL ← (0FFDEH), PCH ← (0FFDFH)
Branch if overflow bit clear :
- - - 1 - 0 - -
38
39
BVC rel
BVS rel
30
B0
2
2
2/4
2/4
- - - - - - - -
- - - - - - - -
If (V) = 0, then PC ← PC + rel
Branch if overflow bit set :
If (V) = 1, then PC ← PC + rel
40
41
CALL !abs
CALL [dp]
3B
5F
3
2
8
8
Subroutine call
M(SP) ← (PCH), SP ← SP-1, M(SP) ← (PCL), SP←SP-1
if !abs, PC ← abs ; if [dp], PCL ← (dp), PCH ← (dp+1)
Compare and branch if not equal ;
If A ≠ (M), then PC ← PC + rel.
- - - - - - - -
- - - - - - - -
42
43
44
45
46
47
CBNE dp,rel
CBNE dp + X, rel
CLR1 dp.bit
CLR1A A.bit
CLRC
FD
8D
y1
3
3
2
2
1
1
5/7
6/8
4
Clear bit : (M.bit) ← “0”
- - - - - - - -
- - - - - - - -
- - - - - - - 0
- - 0 - - - - -
2B
20
40
2
Clear A.bit : (A.bit) ← “0”
2
Clear C-flag : C ← “0”
CLRG
2
Clear G-flag : G ← “0”
November 2001 ver 1.2
91
HMS81C43xx / GMS87C4060
OP
BYTE
CYCLE
NO
FLAG
NO.
MNENONIC
CLRV
OPERATION
CODE
NO.
NVGBHIZC
48
49
50
51
52
53
54
55
56
57
80
44
45
46
47
55
56
57
54
5D
1
2
2
2
3
3
2
2
1
2
2
2
3
4
4
5
6
6
3
4
Clear V-flag : V ← “0”
- 0 - - 0 - - -
CMP #imm
CMP dp
Compare accumulator contents with memory contents
A - (M)
CMP dp + X
CMP !abs
N - - - - - ZC
CMP !abs + Y
CMP [dp + X]
CMP [dp] + Y
CMP {X}
CMPW dp
Compare YA contents with memory pair contents :
YA - (dp+1)(dp)
N - - - - - ZC
N - - - - - ZC
N - - - - - ZC
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
CMPX #imm
CMPX dp
CMPX !abs
CMPY #imm
CMPY dp
CMPY !abs
COM dp
5E
6C
7C
7E
8C
9C
2C
DF
CF
AC
7B
A8
A9
B9
B8
AF
BE
BD
60
9B
E0
A4
A5
A6
A7
B5
96
97
94
AB
AB
88
89
99
98
8F
9E
9D
1B
1F
3F
2
2
3
2
2
3
2
1
1
3
2
1
2
2
3
1
1
2
1
1
1
2
2
2
3
3
2
2
1
3
3
1
2
2
3
1
1
2
3
3
2
2
3
Compare X contents with memory contents
X - (M)
4
2
Compare Y contents with memory contents
Y - (M)
3
4
4
1’s complement : (dp) ← ~(dp)
Decimal adjust for addition
Decimal adjust for substraction
Decrement and branch if not equal :
if (M) ≠ 0, then PC ← PC + rel.
Decrement
N - - - - - Z -
N - - - - - ZC
N - - - - - ZC
DAA
3
DAS
3
DBNE dp,rel
DBNE Y,rel
5/7
4/6
2
- - - - - - - -
DEC
A
DEC dp
4
M ← M - 1
DEC dp + X
DEC !abs
5
N - - - - - Z -
5
DEC
DEC
X
Y
2
2
DECW dp
DI
6
Decrement memory pair : (dp+1)(dp) ← {(dp+1)(dp)} - 1
Disable interrupts : I ← “0”
N - - - - - Z -
- - - - - 0 - -
NV - - H - Z -
- - - - - 1 - -
3
DIV
12
3
Divide : YA / X ← Q:A, R:Y
EI
Enable interrupts
Exclusive OR
A ← A (M)
: I ← “1”
EOR #imm
EOR dp
2
3
EOR dp + X
EOR !abs
EOR !abs + Y
EOR [ dp + X]
EOR [dp] + Y
EOR {X}
EOR1 M.bit
EOR1B M.bit
4
4
N - - - - - Z -
5
6
6
3
5
Bit exclusive-OR C-flag : C ← C (M.bit)
Bit exclusive-OR C-flag and NOT : C ← C
Increment
- - - - - - - C
- - - - - - - C
N - - - - - ZC
5
(M.bit)
INC
A
2
INC dp
4
(M) ← (M) + 1
INC dp + X
INC !abs
5
5
N - - - - - Z -
INC
INC
X
Y
2
2
INCW dp
JMP !abs
JMP [!abs]
JMP [dp]
6
Increment memory pair : (dp+1)(dp) ← {(dp+1)(dp)} + 1
Unconditional jump
N - - - - - Z -
- - - - - - - -
3
5
PC ← jump address
4
N ovem ber 2001 ver 1.2
92
HMS81C43xx / GMS87C4060
OP
CODE
BYTE
NO.
CYCLE
NO
FLAG
NVGBHIZC
NO.
MNENONIC
LDA #imm
OPERATION
99
C4
C5
C6
C7
D5
D6
D7
D4
DB
CB
CB
E4
1E
CC
CD
DC
3E
C9
D9
D8
7D
48
2
2
2
3
3
2
2
1
1
3
3
3
2
2
2
3
2
2
2
3
2
1
2
2
2
3
4
4
5
6
6
3
4
4
4
5
2
3
4
4
2
3
4
4
5
2
4
5
Load accumulator
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
LDA dp
A ← (M)
LDA dp + X
LDA !abs
LDA !abs + Y
LDA [dp + X]
LDA [dp]+Y
LDA {X}
N - - - - - Z -
LDA {X}+
LDC M.bit
LDCB M.bit
LDM dp,#imm
LDX #imm
LDX dp
X-register auto-increment : A ← (M), X ← X + 1
Load C-flag : C ← (M.bit)
- - - - - - - C
- - - - - - - C
- - - - - - - -
Load C-flag with NOT : C ← ~(M.bit)
Load memory with immediate data : (M) ← imm
Load X-register
X ← (M)
N - - - - - Z -
LDX dp + Y
LDX !abs
LDY #imm
LDY dp
Load X-register
Y ← (M)
N - - - - - Z -
N - - - - - Z -
LDY dp + Y
LDY !abs
LDYA dp
Load YA
: YA ← (dp+1)(dp)
LSR
A
Logical shift right
LSR dp
49
7 6 5 4 3 2 1 0
"0"→ → → → → → → → → →
C
N - - - - - ZC
LSR dp + X
59
123
LSR !abs
58
3
5
124
125
126
127
128
129
130
131
132
133
134
135
136
137
MUL
5B
00,FF
4B
64
1
1
3
2
2
2
3
3
2
2
1
3
3
2
9
2
5
2
3
4
4
5
6
6
3
5
5
6
Multiply
:
YA ← Y x A
N - - - - - Z -
- - - - - - - -
- - - - - - - -
NOP
No operation
NOT1 M.bit
OR #imm
OR dp
Bit complement : (M.bit) ← ~(M.bit)
Logical OR
65
A ← A V (M)
OR dp + X
OR !abs
OR !abs + Y
OR [dp +X}
OR [dp] + Y
OR {X}
66
67
N - - - - - Z -
75
76
77
74
OR1 M.bit
OR1B M.bit
PCALL
6B
6B
4F
Bit OR C-flag : C ← C V (M.bit)
Bit OR C-flag and NOT : C ← C V ~(M.bit)
U-page call : M(SP) ← (PCH), SP ← SP -1,
M(SP) ← (PCL), SP ← SP -1,
PCL ← (upage), PCH ←"OFFH"
Pop from stack
- - - - - - - C
- - - - - - - C
- - - - - - - -
138
139
140
141
142
143
144
145
146
POP
POP
POP
A
X
Y
0D
2D
4D
6D
0E
2E
4E
6E
6F
1
1
1
1
1
1
1
1
1
4
4
4
4
4
4
4
4
5
SP ← SP + 1, Reg. ← M(SP)
- - - - - - - -
(restored)
POP PSW
PUSH
PUSH
PUSH
A
X
Y
Push to stack
M(SP) ← Reg. SP ← SP - 1
- - - - - - - -
PUSH PSW
RET
Return from subroutine :
- - - - - - - -
(restored)
SP ← SP+1, PCL ← M(SP), SP ← SP+1, PCH ← M(SP)
Return from interrupt :
147
RETI
7F
1
6
SP ← SP+1, PSW ← M(SP), SP ← SP+1,PCL ← M(SP),
SP ← SP+1, PCH ← M(SP)
November 2001 ver 1.2
93
HMS81C43xx / GMS87C4060
OP
BYTE
CYCLE
NO
FLAG
NO.
MNENONIC
OPERATION
Rotate left through carry
CODE
NO.
NVGBHIZC
148
149
150
151
152
153
154
ROL
A
28
29
39
38
68
69
79
1
2
2
3
1
2
2
2
4
5
5
2
4
5
ROL dp
N - - - - - ZC
N - - - - - ZC
C
7 6 5 4 3 2 1 0
ROL dp + X
ROL !abs
← ← ← ← ← ← ← ← ←
ROR
A
Rotate right through carry
ROR dp
7 6 5 4 3 2 1 0
→ → → → → → → → →
C
ROR dp + X
155
ROR !abs
78
3
5
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
SBC #imm
SBC dp
24
25
26
27
35
36
37
34
x1
2
2
2
3
3
2
2
1
2
2
1
1
2
2
3
3
2
2
1
1
3
2
2
3
2
2
3
2
2
1
1
1
2
3
4
4
5
6
6
3
4
2
2
2
3
4
4
5
6
6
3
4
6
4
5
5
4
5
5
5
5
2
2
8
Substract with carry
A ← A - (M) - ~(C)
SBC dp + X
SBC !abs
SBC !abs + Y
SBC [dp + X]
SBC [dp] + Y
SBC {X}
NV - - HZC
SET1 dp.bit
SETA1 A.bit
SETC
Set bit : (M.bit) ← “1”
Set A.bit : (A.bit) ← “1”
Set C-flag : C ← “1”
Set G-flag : G ← “1”
Store accumulator contents in memory
(M) ← A
- - - - - - - -
- - - - - - - -
- - - - - - - 1
- - 1 - - - - -
0B
A0
C0
E5
E6
E7
F5
F6
F7
F4
FB
EB
EC
ED
FC
E9
F9
F8
DD
3D
E8
9F
nA
SETG
STA dp
STA dp + X
STA !abs
STA !abs + Y
STA [dp + X]
STA [dp] + Y
STA {X}
- - - - - - - -
STA {X}+
STC M.bit
STX dp
X-register auto-increment : (M) ← A, X ← X + 1
Store C-flag : (M.bit) ← C
- - - - - - - -
- - - - - - - -
Store X-register contents in memory
(M) ← X
STX dp + Y
STX !abs
STY dp
Store Y-register contents in memory
STY dp + X
STY !abs
STYA dp
SUBW dp
TAX
(M) ← Y
- - - - - - - -
Store YA : (dp+1)(dp) ← YA
- - - - - - - -
NV - - H - ZC
N - - - - - Z -
N - - - - - Z -
16-bits substract without carry : YA ← YA - (dp+1)(dp)
Transfer accumulator contents to X-register : X ← A
Transfer accumulator contents to Y-register : Y ← A
Table call :
TAY
TCALL
n
M(SP) ← (PCH), SP ← SP -1,
- - - - - - - -
M(SP) ← (PCL), SP ← SP -1
PCL ← (Table vector L), PCH ← (Table vector H)
Test and clear bits with A :
188
189
TCLR1 !abs
TSET1 !abs
5C
3C
3
3
6
6
N - - - - - Z -
N - - - - - Z -
A - (M), (M) ← (M) ^ ~(A)
Test and set bits with A :
A - (M), (M) ← (M) V (A)
190
191
192
193
194
195
196
TSPX
TST dp
TXA
AE
4C
C8
8E
BF
EE
DE
1
2
1
1
1
1
1
2
3
2
2
2
4
4
Transfer stack-pointer contents to X-register : X ← SP
Test memory contents for negative or zero : (dp) - 00H
Transfer X-register contents to accumulator : A ← X
Transfer X-register contents to stack-pointer : SP ← X
Transfer Y-register contents to accumulator : A ← Y
Exchange X-register contents with accumulator : X fA
Exchange Y-register contents with accumulator : Y fA
N - - - - - Z -
N - - - - - Z -
N - - - - - Z -
N - - - - - Z -
N - - - - - Z -
- - - - - - - -
TXSP
TYA
XAX
XAY
- - - - - - - -
N ovem ber 2001 ver 1.2
94
HMS81C43xx / GMS87C4060
OP
BYTE
NO.
CYCLE
NO
FLAG
NO.
MNENONIC
XCN
OPERATION
CODE
NVGBHIZC
197
CE
1
5
Exchange nibbles within the accumulator:
N - - - - - Z -
N - - - - - Z -
A
7 ~ A4 f A3 ~ A0
198
199
200
201
XMA dp
XMA dp + X
XMA {X}
XYX
BC
AD
BB
FE
2
2
1
1
5
6
5
4
Exchange memory contents with accumulator
(M) f A
Exchange X-register contents with Y-register : X f Y
- - - - - - - -
24.3 Instruction Table by Function
1. Arithmetic/Logic Operation
OP
CODE
BYTE
NO.
CYCLE
NO
FLAG
NVGBHIZC
NO.
MNENONIC
ADC #imm
OPERATION
1
04
05
06
07
15
16
17
14
84
85
86
87
95
96
97
94
08
09
19
18
44
45
46
47
55
56
57
54
5E
6C
7C
7E
8C
9C
2C
DF
CF
A8
A9
B9
B8
AF
BE
2
2
2
3
3
2
2
1
2
2
2
3
3
2
2
1
1
2
2
3
2
2
2
3
3
2
2
1
2
2
3
2
2
3
2
1
1
1
2
2
3
1
1
2
3
4
4
5
6
6
3
2
3
4
4
5
6
6
3
2
4
5
5
2
3
4
4
5
6
6
3
2
3
4
2
3
4
4
3
3
2
4
5
5
2
2
Add with carry.
2
ADC dp
A ← A + (M) + C
3
ADC dp + X
ADC !abs
ADC !abs+Y
ADC [dp+X]
ADC [dp]+Y
ADC {X}
4
NV - - H - ZC
5
6
7
8
9
AND #imm
AND dp
Logical AND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
A ← A ^ (M)
AND dp + X
AND !abs
AND !abs+Y
AND [dp+X]
AND [dp] + Y
AND {X}
N - - - - - Z -
N - - - - - ZC
N - - - - - ZC
ASL
A
Arithmetic shift left
ASL dp
C
7 6 5 4 3 2 1 0
ASL dp + X
ASL !abs
CMP #imm
CMP dp
← ← ← ← ← ← ← ← ← ← "0"
Compare accumulator contents with memory contents
A - (M)
CMP dp + X
CMP !abs
CMP !abs + Y
CMP [dp + X]
CMP [dp] + Y
CMP {X}
CMPX #imm
CMPX dp
CMPX !abs
CMPY #imm
CMPY dp
CMPY !abs
COM dp
Compare X contents with memory contents
X - (M)
N - - - - - ZC
N - - - - - ZC
Compare Y contents with memory contents
Y - (M)
1’s complement : (dp) ← ~(dp)
Decimal adjust for addition
Decimal adjust for substraction
Decrement
N - - - - - Z -
N - - - - - ZC
N - - - - - ZC
DAA
DAS
DEC
A
DEC dp
M ← M - 1
DEC dp + X
DEC !abs
N - - - - - Z -
DEC
DEC
X
Y
November 2001 ver 1.2
95
HMS81C43xx / GMS87C4060
OP
CODE
BYTE
NO.
CYCLE
NO
FLAG
NO.
MNENONIC
OPERATION
Divide : YA / X ← Q:A, R:Y
NVGBHIZC
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
DIV
9B
A4
A5
A6
A7
B5
96
97
94
88
89
99
98
8F
9E
48
49
59
1
2
2
2
3
3
2
2
1
1
2
2
3
1
1
1
2
2
12
2
3
4
4
5
6
6
3
2
4
5
5
2
2
2
4
5
NV - - H - Z -
EOR #imm
EOR dp
Exclusive OR
A ← A (M)
EOR dp + X
EOR !abs
N - - - - - Z -
EOR !abs + Y
EOR [ dp + X]
EOR [dp] + Y
EOR {X}
INC
A
Increment
N - - - - - ZC
N - - - - - Z -
INC dp
(M) ← (M) + 1
INC dp + X
INC !abs
INC
INC
LSR
X
Y
A
Logical shift right
LSR dp
7 6 5 4 3 2 1 0
"0"→ → → → → → → → → →
C
N - - - - - ZC
N - - - - - Z -
LSR dp + X
62
LSR !abs
58
3
5
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
MUL
5B
64
65
66
67
75
76
77
74
28
29
39
38
68
69
79
1
2
2
2
3
3
2
2
1
1
2
2
3
1
2
2
9
2
3
4
4
5
6
6
3
2
4
5
5
2
4
5
Multiply
: YA ← Y x A
OR #imm
OR dp
Logical OR
A ← A V (M)
OR dp + X
OR !abs
OR !abs + Y
OR [dp +X}
OR [dp] + Y
OR {X}
N - - - - - Z -
ROL
A
Rotate left through carry
ROL dp
N - - - - - ZC
N - - - - - ZC
C
7 6 5 4 3 2 1 0
← ← ← ← ← ← ← ← ←
ROL dp + X
ROL !abs
ROR
A
Rotate right through carry
ROR dp
7 6 5 4 3 2 1 0
→ → → → → → → → →
C
ROR dp + X
79
ROR !abs
78
3
5
80
81
82
83
84
85
86
87
88
89
SBC #imm
SBC dp
24
25
26
27
35
36
37
34
4C
CE
2
2
2
3
3
2
2
1
2
1
2
3
4
4
5
6
6
3
3
5
Substract with carry
A ← A - (M) - ~(C)
SBC dp + X
SBC !abs
SBC !abs + Y
SBC [dp + X]
SBC [dp] + Y
SBC {X}
NV - - HZC
Test memory contents for negative or zero : (dp) - 00H
Exchange nibbles within the accumulator:
A7 ~ A4 f A3 ~ A0
TST dp
N - - - - - Z -
N - - - - - Z -
XCN
N ovem ber 2001 ver 1.2
96
HMS81C43xx / GMS87C4060
2. Register / Memory Operation
OP
CODE
BYTE
NO.
CYCLE
NO
FLAG
NVGBHIZC
NO.
MNENONIC
LDA #imm
OPERATION
1
C4
C5
C6
C7
D5
D6
D7
D4
DB
E4
1E
CC
CD
DC
3E
C9
D9
D8
E5
E6
E7
F5
2
2
2
3
3
2
2
1
1
3
2
2
2
3
2
2
2
3
2
2
3
3
2
2
1
1
2
2
3
2
2
3
1
1
1
1
1
1
1
1
2
2
1
1
2
3
4
4
5
6
6
3
4
5
2
3
4
4
2
3
4
4
3
4
4
5
6
6
3
4
4
5
5
4
5
5
2
2
2
2
2
2
4
4
5
6
5
4
Load accumulator
2
LDA dp
A ← (M)
3
LDA dp + X
LDA !abs
LDA !abs + Y
LDA [dp + X]
LDA [dp]+Y
LDA {X}
LDA {X}+
LDM dp,#imm
LDX #imm
LDX dp
4
5
N - - - - - Z -
6
7
8
9
X-register auto-increment : A ← (M), X ← X + 1
Load memory with immediate data : (M) ← imm
Load X-register
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
- - - - - - - -
X ← (M)
N - - - - - Z -
LDX dp + Y
LDX !abs
LDY #imm
LDY dp
Load X-register
Y ← (M)
N - - - - - Z -
LDY dp + Y
LDY !abs
STA dp
Store accumulator contents in memory
STA dp + X
STA !abs
STA !abs + Y
STA [dp + X]
STA [dp] + Y
STA {X}
STA {X}+
STX dp
(M) ← A
- - - - - - - -
F6
F7
F4
FB
EC
ED
FC
E9
F9
X-register auto-increment : (M) ← A, X ← X + 1
Store X-register contents in memory
(M) ← X
STX dp + Y
STX !abs
STY dp
- - - - - - - -
- - - - - - - -
Store Y-register contents in memory
STY dp + X
STY !abs
TAX
(M) ← Y
F8
E8
9F
Transfer accumulator contents to X-register : X ← A
Transfer accumulator contents to Y-register : Y ← A
Transfer stack-pointer contents to X-register : X ← SP
Transfer X-register contents to accumulator : A ← X
Transfer X-register contents to stack-pointer : SP ← X
Transfer Y-register contents to accumulator : A ← Y
Exchange X-register contents with accumulator : X fA
Exchange Y-register contents with accumulator : Y fA
Exchange memory contents with accumulator
N - - - - - Z -
N - - - - - Z -
N - - - - - Z -
N - - - - - Z -
N - - - - - Z -
N - - - - - Z -
- - - - - - - -
TAY
TSPX
AE
C8
8E
BF
EE
DE
BC
AD
BB
FE
TXA
TXSP
TYA
XAX
XAY
- - - - - - - -
XMA dp
XMA dp + X
XMA {X}
XYX
(M) f A
N - - - - - Z -
- - - - - - - -
Exchange X-register contents with Y-register : X f Y
3. 16-Bit Operation
OP
BYTE
NO.
CYCLE
NO
FLAG
NO.
MNENONIC
ADDW dp
OPERATION
CODE
NVGBHIZC
1
2
1D
5D
2
2
5
4
16-bits add without carry : YA ← YA + (dp+1)(dp)
Compare YA contents with memory pair contents :
YA - (dp+1)(dp)
NV - - H - ZC
N - - - - - ZC
CMPW dp
3
4
DECW dp
INCW dp
BD
9D
2
2
6
6
Decrement memory pair : (dp+1)(dp) ← {(dp+1)(dp)} - 1
Increment memory pair : (dp+1)(dp) ← {(dp+1)(dp)} + 1
N - - - - - Z -
N - - - - - Z -
November 2001 ver 1.2
97
HMS81C43xx / GMS87C4060
OP
BYTE
CYCLE
NO
FLAG
NO.
MNENONIC
LDYA dp
OPERATION
YA ← (dp+1)(dp)
CODE
NO.
NVGBHIZC
5
6
7
7D
DD
3D
2
2
2
5
5
5
Load YA
:
N - - - - - Z -
- - - - - - - -
STYA dp
SUBW dp
Store YA : (dp+1)(dp) ← YA
16-bits substract without carry : YA ← YA - (dp+1)(dp)
NV - - H - ZC
4. Bit Manipulation
OP
BYTE
NO.
CYCLE
NO
FLAG
NO.
MNENONIC
AND1 M.bit
OPERATION
CODE
NVGBHIZC
1
2
8B
8B
0C
1C
y1
3
3
2
3
2
2
1
1
1
3
3
3
3
3
3
3
2
2
1
1
3
3
4
4
4
5
4
2
2
2
2
5
5
4
4
5
5
5
4
2
2
2
6
6
Bit AND C-flag : C ← C ^ (M.bit)
Bit AND C-flag and NOT : C ← C ^ ~(M.bit)
Bit test A with memory :
- - - - - - - C
- - - - - - - C
AND1B M.bit
BIT dp
3
MM - - - - Z -
Z ← A ^ M, N ← (M7), V ← (M6)
Clear bit : (M.bit) ← “0”
4
BIT !abs
5
CLR1 dp.bit
CLR1A A.bit
CLRC
- - - - - - - -
- - - - - - - -
- - - - - - - 0
- - 0 - - - - -
- 0 - - 0 - - -
- - - - - - - C
- - - - - - - C
- - - - - - - C
- - - - - - - C
- - - - - - - -
- - - - - - - C
- - - - - - - C
- - - - - - - -
- - - - - - - -
- - - - - - - 1
- - 1 - - - - -
- - - - - - - -
6
2B
20
40
80
AB
AB
CB
CB
4B
6B
6B
x1
Clear A.bit : (A.bit) ← “0”
7
Clear C-flag : C ← “0”
8
CLRG
Clear G-flag : G ← “0”
9
CLRV
Clear V-flag : V ← “0”
10
11
12
13
14
15
16
17
18
19
20
21
22
EOR1 M.bit
EOR1B M.bit
LDC M.bit
LDCB M.bit
NOT1 M.bit
OR1 M.bit
OR1B M.bit
SET1 dp.bit
SETA1 A.bit
SETC
Bit exclusive-OR C-flag : C ← C (M.bit)
Bit exclusive-OR C-flag and NOT : C ← C
Load C-flag : C ← (M.bit)
Load C-flag with NOT : C ← ~(M.bit)
Bit complement : (M.bit) ← ~(M.bit)
Bit OR C-flag : C ← C V (M.bit)
Bit OR C-flag and NOT : C ← C V ~(M.bit)
Set bit : (M.bit) ← “1”
(M.bit)
0B
A0
C0
EB
5C
Set A.bit : (A.bit) ← “1”
Set C-flag : C ← “1”
SETG
Set G-flag : G ← “1”
STC M.bit
TCLR1 !abs
Store C-flag : (M.bit) ← C
Test and clear bits with A :
N - - - - - Z -
N - - - - - Z -
A - (M), (M) ← (M) ^ ~(A)
23
TSET1 !abs
3C
3
6
Test and set bits with A :
A - (M), (M) ← (M) V (A)
5. Branch / Jump Operation
OP
CODE
BYTE
NO.
CYCLE
NO
FLAG
NVGBHIZC
NO.
MNENONIC
OPERATION
1
2
3
4
BBC A.bit,rel
BBC dp.bit,rel
BBS A.bit,rel
BBS dp.bit,rel
y2
y3
x2
x3
2
4/6
5/7
4/6
5/7
Branch if bit clear :
- - - - - - - -
3
if(bit) = 0, then PC ← PC + rel
Branch if bit clear :
2
- - - - - - - -
3
if(bit) = 1, then PC ← PC + rel
Branch if carry bit clear :
if(C) = 0, then PC ← PC + rel
5
BCC rel
50
2
2/4
MM - - - - Z -
6
7
BCS rel
BEQ rel
BMI rel
BNE rel
BPL rel
BRA rel
BVC rel
D0
F0
90
70
10
2F
30
2
2
2
2
2
2
2
2/4
2/4
2/4
2/4
2/4
4
Branch if carry bit set : If (C) =1, then PC ← PC + rel
Branch if equal : if (Z) = 1, then PC ← PC + rel
Branch if munus : if (N) = 1, then PC ← PC + rel
Branch if not equal : if (Z) = 0, then PC ← PC + rel
Branch if not minus : if (N) = 0, then PC ← PC + rel
Branch always : PC ← PC + rel
- - - - - - - -
- - - - - - - -
- - - - - - - -
- - - - - - - -
- - - - - - - -
- - - - - - - -
8
9
10
11
12
2/4
Branch if overflow bit clear :
- - - - - - - -
- - - - - - - -
If (V) = 0, then PC ← PC + rel
13
BVS rel
B0
2
2/4
Branch if overflow bit set :
If (V) = 1, then PC ← PC + rel
N ovem ber 2001 ver 1.2
98
HMS81C43xx / GMS87C4060
OP
BYTE
NO.
CYCLE
NO
FLAG
NO.
MNENONIC
CALL !abs
OPERATION
CODE
NVGBHIZC
14
15
3B
5F
3
2
8
8
Subroutine call
M(SP) ← (PCH), SP ← SP-1, M(SP) ← (PCL), SP←SP-1
if !abs, PC ← abs ; if [dp], PCL ← (dp), PCH ← (dp+1)
Compare and branch if not equal ;
If A ≠ (M), then PC ← PC + rel.
CALL [dp]
- - - - - - - -
16
17
18
19
20
21
22
23
CBNE dp,rel
CBNE dp + X, rel
DBNE dp,rel
DBNE Y,rel
JMP !abs
FD
8D
AC
7B
1B
1F
3F
4F
3
3
3
2
3
3
2
2
5/7
6/8
5/7
4/6
3
- - - - - - - -
- - - - - - - -
Decrement and branch if not equal :
if (M) ≠ 0, then PC ← PC + rel.
Unconditional jump
JMP [!abs]
JMP [dp]
5
PC ← jump address
- - - - - - - -
- - - - - - - -
4
U-page call : M(SP) ← (PCH), SP ← SP -1,
M(SP) ← (PCL), SP ← SP -1,
PCL ← (upage), PCH ←"OFFH"
Table call :
PCALL
6
24
TCALL
n
nA
1
8
M(SP) ← (PCH), SP ← SP -1,
M(SP) ← (PCL), SP ← SP -1
PCL ← (Table vector L), PCH ← (Table vector H)
- - - - - - - -
6. Control Operation & etc.
OP
BYTE
NO.
CYCLE
NO
FLAG
NVGBHIZC
NO.
MNENONIC
BRK
OPERATION
CODE
1
0F
1
8
Software interrupt:
B ← “1”, M(SP) ← (PCH), SP ← SP - 1,
M(s) ← (PCL), SP ← S - 1, M(SP) ← PSW,
SP ← SP - 1, PCL ← (0FFDEH), PCH ← (0FFDFH)
Disable interrupts : I ← “0”
- - - 1 - 0 - -
2
3
DI
60
E0
FF
0D
2D
4D
6D
0E
2E
4E
6E
6F
1
1
1
1
1
1
1
1
1
1
1
1
3
3
2
4
4
4
4
4
4
4
4
5
- - - - - 0 - -
- - - - - 1 - -
- - - - - - - -
EI
Enable interrupts
No operation
: I ← “1”
4
NOP
POP
POP
POP
5
A
X
Y
Pop from stack
6
SP ← SP + 1, Reg. ← M(SP)
- - - - - - - -
(restored)
7
8
POP PSW
9
PUSH
PUSH
PUSH
A
X
Y
Push to stack
10
11
12
13
M(SP) ← Reg. SP ← SP - 1
- - - - - - - -
PUSH PSW
RET
Return from subroutine :
- - - - - - - -
(restored)
SP ← SP+1, PCL ← M(SP), SP ← SP+1, PCH ← M(SP)
Return from interrupt :
14
RETI
7F
1
6
SP ← SP+1, PSW ← M(SP), SP ← SP+1,PCL ← M(SP),
SP ← SP+1, PCH ← M(SP)
November 2001 ver 1.2
99
HMS81C43xx / GMS87C4060
N ovem ber 2001 ver 1.2
100
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